From: Marc Zyngier <maz@kernel.org>
To: Raghavendra Rao Ananta <rananta@google.com>
Cc: Oliver Upton <oliver.upton@linux.dev>,
Alexandru Elisei <alexandru.elisei@arm.com>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Shaoqin Huang <shahuang@redhat.com>,
Jing Zhang <jingzhangos@google.com>,
Reiji Watanabe <reijiw@google.com>,
Colton Lewis <coltonlewis@google.com>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Subject: Re: [PATCH v8 05/13] KVM: arm64: Add {get,set}_user for PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR}
Date: Mon, 23 Oct 2023 13:31:15 +0100 [thread overview]
Message-ID: <86zg094j1o.wl-maz@kernel.org> (raw)
In-Reply-To: <20231020214053.2144305-6-rananta@google.com>
On Fri, 20 Oct 2023 22:40:45 +0100,
Raghavendra Rao Ananta <rananta@google.com> wrote:
>
> For unimplemented counters, the bits in PM{C,I}NTEN{SET,CLR} and
> PMOVS{SET,CLR} registers are expected to RAZ. To honor this,
> explicitly implement the {get,set}_user functions for these
> registers to mask out unimplemented counters for userspace reads
> and writes.
>
> Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
> ---
> arch/arm64/kvm/sys_regs.c | 91 ++++++++++++++++++++++++++++++++++++---
> 1 file changed, 85 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index faf97878dfbbb..2e5d497596ef8 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -987,6 +987,45 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
> return true;
> }
>
> +static void set_pmreg_for_valid_counters(struct kvm_vcpu *vcpu,
> + u64 reg, u64 val, bool set)
> +{
> + struct kvm *kvm = vcpu->kvm;
> +
> + mutex_lock(&kvm->arch.config_lock);
> +
> + /* Make the register immutable once the VM has started running */
> + if (kvm_vm_has_ran_once(kvm)) {
> + mutex_unlock(&kvm->arch.config_lock);
> + return;
> + }
> +
> + val &= kvm_pmu_valid_counter_mask(vcpu);
> + mutex_unlock(&kvm->arch.config_lock);
> +
> + if (set)
> + __vcpu_sys_reg(vcpu, reg) |= val;
> + else
> + __vcpu_sys_reg(vcpu, reg) &= ~val;
> +}
> +
> +static int get_pmcnten(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
> + u64 *val)
> +{
> + u64 mask = kvm_pmu_valid_counter_mask(vcpu);
> +
> + *val = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
> + return 0;
> +}
> +
> +static int set_pmcnten(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
> + u64 val)
> +{
> + /* r->Op2 & 0x1: true for PMCNTENSET_EL0, else PMCNTENCLR_EL0 */
> + set_pmreg_for_valid_counters(vcpu, PMCNTENSET_EL0, val, r->Op2 & 0x1);
> + return 0;
> +}
Huh, this is really ugly. Why the explosion of pointless helpers when
the whole design of the sysreg infrastructure to have *common* helpers
for registers that behave the same way?
I'd expect something like the hack below instead.
M.
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index a2c5f210b3d6..8f560a2496f2 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -987,42 +987,46 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
return true;
}
-static void set_pmreg_for_valid_counters(struct kvm_vcpu *vcpu,
- u64 reg, u64 val, bool set)
+static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val)
{
struct kvm *kvm = vcpu->kvm;
+ bool set;
mutex_lock(&kvm->arch.config_lock);
/* Make the register immutable once the VM has started running */
if (kvm_vm_has_ran_once(kvm)) {
mutex_unlock(&kvm->arch.config_lock);
- return;
+ return 0;
}
val &= kvm_pmu_valid_counter_mask(vcpu);
mutex_unlock(&kvm->arch.config_lock);
+ switch(r->reg) {
+ case PMOVSSET_EL0:
+ /* CRm[1] being set indicates a SET register, and CLR otherwise */
+ set = r->CRm & 2;
+ break;
+ default:
+ /* Op2[0] being set indicates a SET register, and CLR otherwise */
+ set = r->Op2 & 1;
+ break;
+ }
+
if (set)
- __vcpu_sys_reg(vcpu, reg) |= val;
+ __vcpu_sys_reg(vcpu, r->reg) |= val;
else
- __vcpu_sys_reg(vcpu, reg) &= ~val;
-}
-
-static int get_pmcnten(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
- u64 *val)
-{
- u64 mask = kvm_pmu_valid_counter_mask(vcpu);
+ __vcpu_sys_reg(vcpu, r->reg) &= ~val;
- *val = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
return 0;
}
-static int set_pmcnten(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
- u64 val)
+static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val)
{
- /* r->Op2 & 0x1: true for PMCNTENSET_EL0, else PMCNTENCLR_EL0 */
- set_pmreg_for_valid_counters(vcpu, PMCNTENSET_EL0, val, r->Op2 & 0x1);
+ u64 mask = kvm_pmu_valid_counter_mask(vcpu);
+
+ *val = __vcpu_sys_reg(vcpu, r->reg) & mask;
return 0;
}
@@ -1054,23 +1058,6 @@ static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
return true;
}
-static int get_pminten(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
- u64 *val)
-{
- u64 mask = kvm_pmu_valid_counter_mask(vcpu);
-
- *val = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
- return 0;
-}
-
-static int set_pminten(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
- u64 val)
-{
- /* r->Op2 & 0x1: true for PMINTENSET_EL1, else PMINTENCLR_EL1 */
- set_pmreg_for_valid_counters(vcpu, PMINTENSET_EL1, val, r->Op2 & 0x1);
- return 0;
-}
-
static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
@@ -1095,23 +1082,6 @@ static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
return true;
}
-static int set_pmovs(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
- u64 val)
-{
- /* r->CRm & 0x2: true for PMOVSSET_EL0, else PMOVSCLR_EL0 */
- set_pmreg_for_valid_counters(vcpu, PMOVSSET_EL0, val, r->CRm & 0x2);
- return 0;
-}
-
-static int get_pmovs(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
- u64 *val)
-{
- u64 mask = kvm_pmu_valid_counter_mask(vcpu);
-
- *val = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
- return 0;
-}
-
static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
@@ -2311,10 +2281,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
{ PMU_SYS_REG(PMINTENSET_EL1),
.access = access_pminten, .reg = PMINTENSET_EL1,
- .get_user = get_pminten, .set_user = set_pminten },
+ .get_user = get_pmreg, .set_user = set_pmreg },
{ PMU_SYS_REG(PMINTENCLR_EL1),
.access = access_pminten, .reg = PMINTENSET_EL1,
- .get_user = get_pminten, .set_user = set_pminten },
+ .get_user = get_pmreg, .set_user = set_pmreg },
{ SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },
{ SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
@@ -2366,13 +2336,13 @@ static const struct sys_reg_desc sys_reg_descs[] = {
.reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr },
{ PMU_SYS_REG(PMCNTENSET_EL0),
.access = access_pmcnten, .reg = PMCNTENSET_EL0,
- .get_user = get_pmcnten, .set_user = set_pmcnten },
+ .get_user = get_pmreg, .set_user = set_pmreg },
{ PMU_SYS_REG(PMCNTENCLR_EL0),
.access = access_pmcnten, .reg = PMCNTENSET_EL0,
- .get_user = get_pmcnten, .set_user = set_pmcnten },
+ .get_user = get_pmreg, .set_user = set_pmreg },
{ PMU_SYS_REG(PMOVSCLR_EL0),
.access = access_pmovs, .reg = PMOVSSET_EL0,
- .get_user = get_pmovs, .set_user = set_pmovs },
+ .get_user = get_pmreg, .set_user = set_pmreg },
/*
* PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was
* previously (and pointlessly) advertised in the past...
@@ -2401,7 +2371,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
.reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
{ PMU_SYS_REG(PMOVSSET_EL0),
.access = access_pmovs, .reg = PMOVSSET_EL0,
- .get_user = get_pmovs, .set_user = set_pmovs },
+ .get_user = get_pmreg, .set_user = set_pmreg },
{ SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
{ SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
--
Without deviation from the norm, progress is not possible.
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Raghavendra Rao Ananta <rananta@google.com>
Cc: Oliver Upton <oliver.upton@linux.dev>,
Alexandru Elisei <alexandru.elisei@arm.com>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Shaoqin Huang <shahuang@redhat.com>,
Jing Zhang <jingzhangos@google.com>,
Reiji Watanabe <reijiw@google.com>,
Colton Lewis <coltonlewis@google.com>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Subject: Re: [PATCH v8 05/13] KVM: arm64: Add {get,set}_user for PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR}
Date: Mon, 23 Oct 2023 13:31:15 +0100 [thread overview]
Message-ID: <86zg094j1o.wl-maz@kernel.org> (raw)
In-Reply-To: <20231020214053.2144305-6-rananta@google.com>
On Fri, 20 Oct 2023 22:40:45 +0100,
Raghavendra Rao Ananta <rananta@google.com> wrote:
>
> For unimplemented counters, the bits in PM{C,I}NTEN{SET,CLR} and
> PMOVS{SET,CLR} registers are expected to RAZ. To honor this,
> explicitly implement the {get,set}_user functions for these
> registers to mask out unimplemented counters for userspace reads
> and writes.
>
> Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
> ---
> arch/arm64/kvm/sys_regs.c | 91 ++++++++++++++++++++++++++++++++++++---
> 1 file changed, 85 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index faf97878dfbbb..2e5d497596ef8 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -987,6 +987,45 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
> return true;
> }
>
> +static void set_pmreg_for_valid_counters(struct kvm_vcpu *vcpu,
> + u64 reg, u64 val, bool set)
> +{
> + struct kvm *kvm = vcpu->kvm;
> +
> + mutex_lock(&kvm->arch.config_lock);
> +
> + /* Make the register immutable once the VM has started running */
> + if (kvm_vm_has_ran_once(kvm)) {
> + mutex_unlock(&kvm->arch.config_lock);
> + return;
> + }
> +
> + val &= kvm_pmu_valid_counter_mask(vcpu);
> + mutex_unlock(&kvm->arch.config_lock);
> +
> + if (set)
> + __vcpu_sys_reg(vcpu, reg) |= val;
> + else
> + __vcpu_sys_reg(vcpu, reg) &= ~val;
> +}
> +
> +static int get_pmcnten(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
> + u64 *val)
> +{
> + u64 mask = kvm_pmu_valid_counter_mask(vcpu);
> +
> + *val = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
> + return 0;
> +}
> +
> +static int set_pmcnten(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
> + u64 val)
> +{
> + /* r->Op2 & 0x1: true for PMCNTENSET_EL0, else PMCNTENCLR_EL0 */
> + set_pmreg_for_valid_counters(vcpu, PMCNTENSET_EL0, val, r->Op2 & 0x1);
> + return 0;
> +}
Huh, this is really ugly. Why the explosion of pointless helpers when
the whole design of the sysreg infrastructure to have *common* helpers
for registers that behave the same way?
I'd expect something like the hack below instead.
M.
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index a2c5f210b3d6..8f560a2496f2 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -987,42 +987,46 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
return true;
}
-static void set_pmreg_for_valid_counters(struct kvm_vcpu *vcpu,
- u64 reg, u64 val, bool set)
+static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val)
{
struct kvm *kvm = vcpu->kvm;
+ bool set;
mutex_lock(&kvm->arch.config_lock);
/* Make the register immutable once the VM has started running */
if (kvm_vm_has_ran_once(kvm)) {
mutex_unlock(&kvm->arch.config_lock);
- return;
+ return 0;
}
val &= kvm_pmu_valid_counter_mask(vcpu);
mutex_unlock(&kvm->arch.config_lock);
+ switch(r->reg) {
+ case PMOVSSET_EL0:
+ /* CRm[1] being set indicates a SET register, and CLR otherwise */
+ set = r->CRm & 2;
+ break;
+ default:
+ /* Op2[0] being set indicates a SET register, and CLR otherwise */
+ set = r->Op2 & 1;
+ break;
+ }
+
if (set)
- __vcpu_sys_reg(vcpu, reg) |= val;
+ __vcpu_sys_reg(vcpu, r->reg) |= val;
else
- __vcpu_sys_reg(vcpu, reg) &= ~val;
-}
-
-static int get_pmcnten(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
- u64 *val)
-{
- u64 mask = kvm_pmu_valid_counter_mask(vcpu);
+ __vcpu_sys_reg(vcpu, r->reg) &= ~val;
- *val = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
return 0;
}
-static int set_pmcnten(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
- u64 val)
+static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val)
{
- /* r->Op2 & 0x1: true for PMCNTENSET_EL0, else PMCNTENCLR_EL0 */
- set_pmreg_for_valid_counters(vcpu, PMCNTENSET_EL0, val, r->Op2 & 0x1);
+ u64 mask = kvm_pmu_valid_counter_mask(vcpu);
+
+ *val = __vcpu_sys_reg(vcpu, r->reg) & mask;
return 0;
}
@@ -1054,23 +1058,6 @@ static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
return true;
}
-static int get_pminten(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
- u64 *val)
-{
- u64 mask = kvm_pmu_valid_counter_mask(vcpu);
-
- *val = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
- return 0;
-}
-
-static int set_pminten(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
- u64 val)
-{
- /* r->Op2 & 0x1: true for PMINTENSET_EL1, else PMINTENCLR_EL1 */
- set_pmreg_for_valid_counters(vcpu, PMINTENSET_EL1, val, r->Op2 & 0x1);
- return 0;
-}
-
static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
@@ -1095,23 +1082,6 @@ static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
return true;
}
-static int set_pmovs(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
- u64 val)
-{
- /* r->CRm & 0x2: true for PMOVSSET_EL0, else PMOVSCLR_EL0 */
- set_pmreg_for_valid_counters(vcpu, PMOVSSET_EL0, val, r->CRm & 0x2);
- return 0;
-}
-
-static int get_pmovs(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
- u64 *val)
-{
- u64 mask = kvm_pmu_valid_counter_mask(vcpu);
-
- *val = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
- return 0;
-}
-
static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
@@ -2311,10 +2281,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
{ PMU_SYS_REG(PMINTENSET_EL1),
.access = access_pminten, .reg = PMINTENSET_EL1,
- .get_user = get_pminten, .set_user = set_pminten },
+ .get_user = get_pmreg, .set_user = set_pmreg },
{ PMU_SYS_REG(PMINTENCLR_EL1),
.access = access_pminten, .reg = PMINTENSET_EL1,
- .get_user = get_pminten, .set_user = set_pminten },
+ .get_user = get_pmreg, .set_user = set_pmreg },
{ SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },
{ SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
@@ -2366,13 +2336,13 @@ static const struct sys_reg_desc sys_reg_descs[] = {
.reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr },
{ PMU_SYS_REG(PMCNTENSET_EL0),
.access = access_pmcnten, .reg = PMCNTENSET_EL0,
- .get_user = get_pmcnten, .set_user = set_pmcnten },
+ .get_user = get_pmreg, .set_user = set_pmreg },
{ PMU_SYS_REG(PMCNTENCLR_EL0),
.access = access_pmcnten, .reg = PMCNTENSET_EL0,
- .get_user = get_pmcnten, .set_user = set_pmcnten },
+ .get_user = get_pmreg, .set_user = set_pmreg },
{ PMU_SYS_REG(PMOVSCLR_EL0),
.access = access_pmovs, .reg = PMOVSSET_EL0,
- .get_user = get_pmovs, .set_user = set_pmovs },
+ .get_user = get_pmreg, .set_user = set_pmreg },
/*
* PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was
* previously (and pointlessly) advertised in the past...
@@ -2401,7 +2371,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
.reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
{ PMU_SYS_REG(PMOVSSET_EL0),
.access = access_pmovs, .reg = PMOVSSET_EL0,
- .get_user = get_pmovs, .set_user = set_pmovs },
+ .get_user = get_pmreg, .set_user = set_pmreg },
{ SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
{ SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
--
Without deviation from the norm, progress is not possible.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-10-23 12:31 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-20 21:40 [PATCH v8 00/13] KVM: arm64: PMU: Allow userspace to limit the number of PMCs on vCPU Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-20 21:40 ` [PATCH v8 01/13] KVM: arm64: PMU: Introduce helpers to set the guest's PMU Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-23 15:24 ` Sebastian Ott
2023-10-23 15:24 ` Sebastian Ott
2023-10-20 21:40 ` [PATCH v8 02/13] KVM: arm64: PMU: Set the default PMU for the guest before vCPU reset Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-23 10:40 ` Marc Zyngier
2023-10-23 10:40 ` Marc Zyngier
2023-10-23 18:24 ` Oliver Upton
2023-10-23 18:24 ` Oliver Upton
2023-10-23 15:25 ` Sebastian Ott
2023-10-23 15:25 ` Sebastian Ott
2023-10-20 21:40 ` [PATCH v8 03/13] KVM: arm64: PMU: Add a helper to read a vCPU's PMCR_EL0 Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-23 16:18 ` Sebastian Ott
2023-10-23 16:18 ` Sebastian Ott
2023-10-20 21:40 ` [PATCH v8 04/13] KVM: arm64: PMU: Set PMCR_EL0.N for vCPU based on the associated PMU Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-23 11:50 ` Marc Zyngier
2023-10-23 11:50 ` Marc Zyngier
2023-10-23 16:20 ` Sebastian Ott
2023-10-23 16:20 ` Sebastian Ott
2023-10-24 9:22 ` Oliver Upton
2023-10-24 9:22 ` Oliver Upton
2023-10-20 21:40 ` [PATCH v8 05/13] KVM: arm64: Add {get,set}_user for PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR} Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-23 12:31 ` Marc Zyngier [this message]
2023-10-23 12:31 ` Marc Zyngier
2023-10-23 17:28 ` Raghavendra Rao Ananta
2023-10-23 17:28 ` Raghavendra Rao Ananta
2023-10-24 8:59 ` Oliver Upton
2023-10-24 8:59 ` Oliver Upton
2023-10-20 21:40 ` [PATCH v8 06/13] KVM: arm64: Sanitize PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR} before first run Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-23 12:42 ` Marc Zyngier
2023-10-23 12:42 ` Marc Zyngier
2023-10-23 17:42 ` Raghavendra Rao Ananta
2023-10-23 17:42 ` Raghavendra Rao Ananta
2023-10-23 18:07 ` Marc Zyngier
2023-10-23 18:07 ` Marc Zyngier
2023-10-24 19:56 ` kernel test robot
2023-10-20 21:40 ` [PATCH v8 07/13] KVM: arm64: PMU: Allow userspace to limit PMCR_EL0.N for the guest Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-23 13:00 ` Marc Zyngier
2023-10-23 13:00 ` Marc Zyngier
2023-10-23 17:53 ` Raghavendra Rao Ananta
2023-10-23 17:53 ` Raghavendra Rao Ananta
2023-10-24 18:37 ` Oliver Upton
2023-10-24 18:37 ` Oliver Upton
2023-10-20 21:40 ` [PATCH v8 08/13] tools: Import arm_pmuv3.h Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-20 21:40 ` [PATCH v8 09/13] KVM: selftests: aarch64: Introduce vpmu_counter_access test Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-20 21:40 ` [PATCH v8 10/13] KVM: selftests: aarch64: vPMU register test for implemented counters Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-20 21:40 ` [PATCH v8 11/13] KVM: selftests: aarch64: vPMU register test for unimplemented counters Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-24 18:29 ` Oliver Upton
2023-10-24 18:29 ` Oliver Upton
2023-10-20 21:40 ` [PATCH v8 12/13] KVM: selftests: aarch64: vPMU test for validating user accesses Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-20 21:40 ` [PATCH v8 13/13] KVM: selftests: aarch64: vPMU test for immutability Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-24 10:36 ` Oliver Upton
2023-10-24 10:36 ` Oliver Upton
2023-10-23 13:09 ` [PATCH v8 00/13] KVM: arm64: PMU: Allow userspace to limit the number of PMCs on vCPU Marc Zyngier
2023-10-23 13:09 ` Marc Zyngier
2023-10-23 17:58 ` Raghavendra Rao Ananta
2023-10-23 17:58 ` Raghavendra Rao Ananta
2023-10-23 18:19 ` Marc Zyngier
2023-10-23 18:19 ` Marc Zyngier
2023-10-23 18:35 ` Marc Zyngier
2023-10-23 18:35 ` Marc Zyngier
2023-10-24 19:21 ` Oliver Upton
2023-10-24 19:21 ` Oliver Upton
2023-10-25 0:01 ` Oliver Upton
2023-10-25 0:01 ` Oliver Upton
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=86zg094j1o.wl-maz@kernel.org \
--to=maz@kernel.org \
--cc=alexandru.elisei@arm.com \
--cc=coltonlewis@google.com \
--cc=james.morse@arm.com \
--cc=jingzhangos@google.com \
--cc=kvm@vger.kernel.org \
--cc=kvmarm@lists.linux.dev \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=oliver.upton@linux.dev \
--cc=pbonzini@redhat.com \
--cc=rananta@google.com \
--cc=reijiw@google.com \
--cc=shahuang@redhat.com \
--cc=suzuki.poulose@arm.com \
--cc=yuzenghui@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.