From: Marc Zyngier <maz@kernel.org>
To: Raghavendra Rao Ananta <rananta@google.com>
Cc: Oliver Upton <oliver.upton@linux.dev>,
Alexandru Elisei <alexandru.elisei@arm.com>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Shaoqin Huang <shahuang@redhat.com>,
Jing Zhang <jingzhangos@google.com>,
Reiji Watanabe <reijiw@google.com>,
Colton Lewis <coltonlewis@google.com>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Subject: Re: [PATCH v8 06/13] KVM: arm64: Sanitize PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR} before first run
Date: Mon, 23 Oct 2023 19:07:13 +0100 [thread overview]
Message-ID: <86ttqh43hq.wl-maz@kernel.org> (raw)
In-Reply-To: <CAJHc60xijk_QpxK-eDzdY2g2OXXaQ3En=fBfBe45hAjuJMFNUw@mail.gmail.com>
On Mon, 23 Oct 2023 18:42:43 +0100,
Raghavendra Rao Ananta <rananta@google.com> wrote:
>
> On Mon, Oct 23, 2023 at 5:42 AM Marc Zyngier <maz@kernel.org> wrote:
> >
> > On Fri, 20 Oct 2023 22:40:46 +0100,
> > Raghavendra Rao Ananta <rananta@google.com> wrote:
> > >
> > > For unimplemented counters, the registers PM{C,I}NTEN{SET,CLR}
> > > and PMOVS{SET,CLR} are expected to have the corresponding bits RAZ.
> > > Hence to ensure correct KVM's PMU emulation, mask out the bits in
> > > these registers for these unimplemented counters before the first
> > > vCPU run.
> > >
> > > Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
> > > ---
> > > arch/arm64/kvm/arm.c | 2 +-
> > > arch/arm64/kvm/pmu-emul.c | 11 +++++++++++
> > > include/kvm/arm_pmu.h | 2 ++
> > > 3 files changed, 14 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
> > > index e3074a9e23a8b..3c0bb80483fb1 100644
> > > --- a/arch/arm64/kvm/arm.c
> > > +++ b/arch/arm64/kvm/arm.c
> > > @@ -857,7 +857,7 @@ static int check_vcpu_requests(struct kvm_vcpu *vcpu)
> > > }
> > >
> > > if (kvm_check_request(KVM_REQ_RELOAD_PMU, vcpu))
> > > - kvm_pmu_handle_pmcr(vcpu, kvm_vcpu_read_pmcr(vcpu));
> > > + kvm_vcpu_handle_request_reload_pmu(vcpu);
> >
> > Please rename this to kvm_vcpu_reload_pmu(). That's long enough. But
> > see below.
> >
> Sounds good.
>
> > >
> > > if (kvm_check_request(KVM_REQ_RESYNC_PMU_EL0, vcpu))
> > > kvm_vcpu_pmu_restore_guest(vcpu);
> > > diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
> > > index 9e24581206c24..31e4933293b76 100644
> > > --- a/arch/arm64/kvm/pmu-emul.c
> > > +++ b/arch/arm64/kvm/pmu-emul.c
> > > @@ -788,6 +788,17 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1)
> > > return val & mask;
> > > }
> > >
> > > +void kvm_vcpu_handle_request_reload_pmu(struct kvm_vcpu *vcpu)
> > > +{
> > > + u64 mask = kvm_pmu_valid_counter_mask(vcpu);
> > > +
> > > + kvm_pmu_handle_pmcr(vcpu, kvm_vcpu_read_pmcr(vcpu));
> > > +
> > > + __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= mask;
> > > + __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= mask;
> > > + __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= mask;
> > > +}
> >
> > Why is this done on a vcpu request? Why can't it be done upfront, when
> > we're requesting the reload? Or when assigning the PMU? Or when
> > setting PMCR_EL0?
> >
> The idea was to do this only once, after userspace has configured the
> PMCR.N (and has no option to change it), but before we run the guest
> for the first time. So, I guess this can be done when we are
> requesting the reload, if you prefer.
Well, I'm trying to limit the proliferation of these one-off "helpers"
that make the code hard to follow. So it isn't "what I prefer", but
what makes the code easier to understand without having to follow a
maze of pointless abstraction.
> When assigning the PMU, it could be too early to sanitize as the
> userspace would not have configured the PMCR.N yet.
> It can probably be done when userspace configures PMCR.N, but since
> this field is per-guest, we may have to apply the setting for all the
> vCPUs during the ioctl, which may get a little ugly.
Right. So it has to happen at the point where userspace cannot write
to PMCR_EL0 anymore, for which any of the options I mentioned is too
early. What you have is thus correct. But it would have helped if that
rationale was captured in the commit message.
M.
--
Without deviation from the norm, progress is not possible.
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Raghavendra Rao Ananta <rananta@google.com>
Cc: Oliver Upton <oliver.upton@linux.dev>,
Alexandru Elisei <alexandru.elisei@arm.com>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Shaoqin Huang <shahuang@redhat.com>,
Jing Zhang <jingzhangos@google.com>,
Reiji Watanabe <reijiw@google.com>,
Colton Lewis <coltonlewis@google.com>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Subject: Re: [PATCH v8 06/13] KVM: arm64: Sanitize PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR} before first run
Date: Mon, 23 Oct 2023 19:07:13 +0100 [thread overview]
Message-ID: <86ttqh43hq.wl-maz@kernel.org> (raw)
In-Reply-To: <CAJHc60xijk_QpxK-eDzdY2g2OXXaQ3En=fBfBe45hAjuJMFNUw@mail.gmail.com>
On Mon, 23 Oct 2023 18:42:43 +0100,
Raghavendra Rao Ananta <rananta@google.com> wrote:
>
> On Mon, Oct 23, 2023 at 5:42 AM Marc Zyngier <maz@kernel.org> wrote:
> >
> > On Fri, 20 Oct 2023 22:40:46 +0100,
> > Raghavendra Rao Ananta <rananta@google.com> wrote:
> > >
> > > For unimplemented counters, the registers PM{C,I}NTEN{SET,CLR}
> > > and PMOVS{SET,CLR} are expected to have the corresponding bits RAZ.
> > > Hence to ensure correct KVM's PMU emulation, mask out the bits in
> > > these registers for these unimplemented counters before the first
> > > vCPU run.
> > >
> > > Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
> > > ---
> > > arch/arm64/kvm/arm.c | 2 +-
> > > arch/arm64/kvm/pmu-emul.c | 11 +++++++++++
> > > include/kvm/arm_pmu.h | 2 ++
> > > 3 files changed, 14 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
> > > index e3074a9e23a8b..3c0bb80483fb1 100644
> > > --- a/arch/arm64/kvm/arm.c
> > > +++ b/arch/arm64/kvm/arm.c
> > > @@ -857,7 +857,7 @@ static int check_vcpu_requests(struct kvm_vcpu *vcpu)
> > > }
> > >
> > > if (kvm_check_request(KVM_REQ_RELOAD_PMU, vcpu))
> > > - kvm_pmu_handle_pmcr(vcpu, kvm_vcpu_read_pmcr(vcpu));
> > > + kvm_vcpu_handle_request_reload_pmu(vcpu);
> >
> > Please rename this to kvm_vcpu_reload_pmu(). That's long enough. But
> > see below.
> >
> Sounds good.
>
> > >
> > > if (kvm_check_request(KVM_REQ_RESYNC_PMU_EL0, vcpu))
> > > kvm_vcpu_pmu_restore_guest(vcpu);
> > > diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
> > > index 9e24581206c24..31e4933293b76 100644
> > > --- a/arch/arm64/kvm/pmu-emul.c
> > > +++ b/arch/arm64/kvm/pmu-emul.c
> > > @@ -788,6 +788,17 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1)
> > > return val & mask;
> > > }
> > >
> > > +void kvm_vcpu_handle_request_reload_pmu(struct kvm_vcpu *vcpu)
> > > +{
> > > + u64 mask = kvm_pmu_valid_counter_mask(vcpu);
> > > +
> > > + kvm_pmu_handle_pmcr(vcpu, kvm_vcpu_read_pmcr(vcpu));
> > > +
> > > + __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= mask;
> > > + __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= mask;
> > > + __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= mask;
> > > +}
> >
> > Why is this done on a vcpu request? Why can't it be done upfront, when
> > we're requesting the reload? Or when assigning the PMU? Or when
> > setting PMCR_EL0?
> >
> The idea was to do this only once, after userspace has configured the
> PMCR.N (and has no option to change it), but before we run the guest
> for the first time. So, I guess this can be done when we are
> requesting the reload, if you prefer.
Well, I'm trying to limit the proliferation of these one-off "helpers"
that make the code hard to follow. So it isn't "what I prefer", but
what makes the code easier to understand without having to follow a
maze of pointless abstraction.
> When assigning the PMU, it could be too early to sanitize as the
> userspace would not have configured the PMCR.N yet.
> It can probably be done when userspace configures PMCR.N, but since
> this field is per-guest, we may have to apply the setting for all the
> vCPUs during the ioctl, which may get a little ugly.
Right. So it has to happen at the point where userspace cannot write
to PMCR_EL0 anymore, for which any of the options I mentioned is too
early. What you have is thus correct. But it would have helped if that
rationale was captured in the commit message.
M.
--
Without deviation from the norm, progress is not possible.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-10-23 18:07 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-20 21:40 [PATCH v8 00/13] KVM: arm64: PMU: Allow userspace to limit the number of PMCs on vCPU Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-20 21:40 ` [PATCH v8 01/13] KVM: arm64: PMU: Introduce helpers to set the guest's PMU Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-23 15:24 ` Sebastian Ott
2023-10-23 15:24 ` Sebastian Ott
2023-10-20 21:40 ` [PATCH v8 02/13] KVM: arm64: PMU: Set the default PMU for the guest before vCPU reset Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-23 10:40 ` Marc Zyngier
2023-10-23 10:40 ` Marc Zyngier
2023-10-23 18:24 ` Oliver Upton
2023-10-23 18:24 ` Oliver Upton
2023-10-23 15:25 ` Sebastian Ott
2023-10-23 15:25 ` Sebastian Ott
2023-10-20 21:40 ` [PATCH v8 03/13] KVM: arm64: PMU: Add a helper to read a vCPU's PMCR_EL0 Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-23 16:18 ` Sebastian Ott
2023-10-23 16:18 ` Sebastian Ott
2023-10-20 21:40 ` [PATCH v8 04/13] KVM: arm64: PMU: Set PMCR_EL0.N for vCPU based on the associated PMU Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-23 11:50 ` Marc Zyngier
2023-10-23 11:50 ` Marc Zyngier
2023-10-23 16:20 ` Sebastian Ott
2023-10-23 16:20 ` Sebastian Ott
2023-10-24 9:22 ` Oliver Upton
2023-10-24 9:22 ` Oliver Upton
2023-10-20 21:40 ` [PATCH v8 05/13] KVM: arm64: Add {get,set}_user for PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR} Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-23 12:31 ` Marc Zyngier
2023-10-23 12:31 ` Marc Zyngier
2023-10-23 17:28 ` Raghavendra Rao Ananta
2023-10-23 17:28 ` Raghavendra Rao Ananta
2023-10-24 8:59 ` Oliver Upton
2023-10-24 8:59 ` Oliver Upton
2023-10-20 21:40 ` [PATCH v8 06/13] KVM: arm64: Sanitize PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR} before first run Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-23 12:42 ` Marc Zyngier
2023-10-23 12:42 ` Marc Zyngier
2023-10-23 17:42 ` Raghavendra Rao Ananta
2023-10-23 17:42 ` Raghavendra Rao Ananta
2023-10-23 18:07 ` Marc Zyngier [this message]
2023-10-23 18:07 ` Marc Zyngier
2023-10-24 19:56 ` kernel test robot
2023-10-20 21:40 ` [PATCH v8 07/13] KVM: arm64: PMU: Allow userspace to limit PMCR_EL0.N for the guest Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-23 13:00 ` Marc Zyngier
2023-10-23 13:00 ` Marc Zyngier
2023-10-23 17:53 ` Raghavendra Rao Ananta
2023-10-23 17:53 ` Raghavendra Rao Ananta
2023-10-24 18:37 ` Oliver Upton
2023-10-24 18:37 ` Oliver Upton
2023-10-20 21:40 ` [PATCH v8 08/13] tools: Import arm_pmuv3.h Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-20 21:40 ` [PATCH v8 09/13] KVM: selftests: aarch64: Introduce vpmu_counter_access test Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-20 21:40 ` [PATCH v8 10/13] KVM: selftests: aarch64: vPMU register test for implemented counters Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-20 21:40 ` [PATCH v8 11/13] KVM: selftests: aarch64: vPMU register test for unimplemented counters Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-24 18:29 ` Oliver Upton
2023-10-24 18:29 ` Oliver Upton
2023-10-20 21:40 ` [PATCH v8 12/13] KVM: selftests: aarch64: vPMU test for validating user accesses Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-20 21:40 ` [PATCH v8 13/13] KVM: selftests: aarch64: vPMU test for immutability Raghavendra Rao Ananta
2023-10-20 21:40 ` Raghavendra Rao Ananta
2023-10-24 10:36 ` Oliver Upton
2023-10-24 10:36 ` Oliver Upton
2023-10-23 13:09 ` [PATCH v8 00/13] KVM: arm64: PMU: Allow userspace to limit the number of PMCs on vCPU Marc Zyngier
2023-10-23 13:09 ` Marc Zyngier
2023-10-23 17:58 ` Raghavendra Rao Ananta
2023-10-23 17:58 ` Raghavendra Rao Ananta
2023-10-23 18:19 ` Marc Zyngier
2023-10-23 18:19 ` Marc Zyngier
2023-10-23 18:35 ` Marc Zyngier
2023-10-23 18:35 ` Marc Zyngier
2023-10-24 19:21 ` Oliver Upton
2023-10-24 19:21 ` Oliver Upton
2023-10-25 0:01 ` Oliver Upton
2023-10-25 0:01 ` Oliver Upton
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