* Re: [Mesa-dev] [PATCH 1/2] i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions. [not found] <1429679612-18584-1-git-send-email-kenneth@whitecape.org> @ 2015-05-06 13:38 ` Daniel Vetter 2015-05-06 13:45 ` Chris Wilson 0 siblings, 1 reply; 4+ messages in thread From: Daniel Vetter @ 2015-05-06 13:38 UTC (permalink / raw) To: Kenneth Graunke; +Cc: Intel Graphics Development On Tue, Apr 21, 2015 at 10:13:31PM -0700, Kenneth Graunke wrote: > The BLT engine on Gen8+ requires linear surfaces to be cacheline > aligned. This restriction was added as part of converting the BLT to > use 48-bit addressing. > > intel_emit_linear_blit needs to handle blits that are not cacheline > aligned, as we use it for arbitrary glBufferSubData calls and subrange > mappings. > > Since intel_emit_linear_blit uses 1 byte per pixel, we can use the src/dst > pixel X offset field to represent the unaligned portion, and subtract > that from the address so it's cacheline aligned. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521 > Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> > Cc: mesa-stable@lists.freedesktop.org s/cacheline/page/ afaik, and nope it's not documented. Chris&Mika learned that the hard way. Adding them to correct me in case I make a mess again. -Daniel > --- > src/mesa/drivers/dri/i965/intel_blit.c | 22 ++++++++++++++-------- > 1 file changed, 14 insertions(+), 8 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c > index 4993f60..98d414c 100644 > --- a/src/mesa/drivers/dri/i965/intel_blit.c > +++ b/src/mesa/drivers/dri/i965/intel_blit.c > @@ -524,6 +524,7 @@ intel_emit_linear_blit(struct brw_context *brw, > { > struct gl_context *ctx = &brw->ctx; > GLuint pitch, height; > + int16_t src_x, dst_x; > bool ok; > > /* The pitch given to the GPU must be DWORD aligned, and > @@ -532,11 +533,13 @@ intel_emit_linear_blit(struct brw_context *brw, > */ > pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 1), 4); > height = (pitch == 0) ? 1 : size / pitch; > + src_x = src_offset % 64; > + dst_x = dst_offset % 64; > ok = intelEmitCopyBlit(brw, 1, > - pitch, src_bo, src_offset, I915_TILING_NONE, > - pitch, dst_bo, dst_offset, I915_TILING_NONE, > - 0, 0, /* src x/y */ > - 0, 0, /* dst x/y */ > + pitch, src_bo, src_offset - src_x, I915_TILING_NONE, > + pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE, > + src_x, 0, /* src x/y */ > + dst_x, 0, /* dst x/y */ > pitch, height, /* w, h */ > GL_COPY); > if (!ok) > @@ -544,15 +547,18 @@ intel_emit_linear_blit(struct brw_context *brw, > > src_offset += pitch * height; > dst_offset += pitch * height; > + src_x = src_offset % 64; > + dst_x = dst_offset % 64; > size -= pitch * height; > assert (size < (1 << 15)); > pitch = ALIGN(size, 4); > + > if (size != 0) { > ok = intelEmitCopyBlit(brw, 1, > - pitch, src_bo, src_offset, I915_TILING_NONE, > - pitch, dst_bo, dst_offset, I915_TILING_NONE, > - 0, 0, /* src x/y */ > - 0, 0, /* dst x/y */ > + pitch, src_bo, src_offset - src_x, I915_TILING_NONE, > + pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE, > + src_x, 0, /* src x/y */ > + dst_x, 0, /* dst x/y */ > size, 1, /* w, h */ > GL_COPY); > if (!ok) > -- > 2.3.5 > > _______________________________________________ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-dev -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Mesa-dev] [PATCH 1/2] i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions. 2015-05-06 13:38 ` [Mesa-dev] [PATCH 1/2] i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions Daniel Vetter @ 2015-05-06 13:45 ` Chris Wilson 2015-05-06 17:25 ` Mika Kuoppala 0 siblings, 1 reply; 4+ messages in thread From: Chris Wilson @ 2015-05-06 13:45 UTC (permalink / raw) To: Daniel Vetter; +Cc: Intel Graphics Development On Wed, May 06, 2015 at 03:38:44PM +0200, Daniel Vetter wrote: > On Tue, Apr 21, 2015 at 10:13:31PM -0700, Kenneth Graunke wrote: > > The BLT engine on Gen8+ requires linear surfaces to be cacheline > > aligned. This restriction was added as part of converting the BLT to > > use 48-bit addressing. > > > > intel_emit_linear_blit needs to handle blits that are not cacheline > > aligned, as we use it for arbitrary glBufferSubData calls and subrange > > mappings. > > > > Since intel_emit_linear_blit uses 1 byte per pixel, we can use the src/dst > > pixel X offset field to represent the unaligned portion, and subtract > > that from the address so it's cacheline aligned. > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521 > > Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> > > Cc: mesa-stable@lists.freedesktop.org > > s/cacheline/page/ afaik, and nope it's not documented. Chris&Mika learned > that the hard way. Adding them to correct me in case I make a mess again. It's cacheline. Issue: if the 1st pixel in XY_SRC_COPY is not CL aligned when SRC or DST are linear that will cause failure. https://vthsd.fm.intel.com/hsd/bdwgfx/bug_de/default.aspx?bug_de_id=1912704 -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Mesa-dev] [PATCH 1/2] i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions. 2015-05-06 13:45 ` Chris Wilson @ 2015-05-06 17:25 ` Mika Kuoppala 2015-05-06 17:41 ` Kenneth Graunke 0 siblings, 1 reply; 4+ messages in thread From: Mika Kuoppala @ 2015-05-06 17:25 UTC (permalink / raw) To: Chris Wilson, Daniel Vetter; +Cc: Intel Graphics Development Chris Wilson <chris@chris-wilson.co.uk> writes: > On Wed, May 06, 2015 at 03:38:44PM +0200, Daniel Vetter wrote: >> On Tue, Apr 21, 2015 at 10:13:31PM -0700, Kenneth Graunke wrote: >> > The BLT engine on Gen8+ requires linear surfaces to be cacheline >> > aligned. This restriction was added as part of converting the BLT to >> > use 48-bit addressing. >> > >> > intel_emit_linear_blit needs to handle blits that are not cacheline >> > aligned, as we use it for arbitrary glBufferSubData calls and subrange >> > mappings. >> > >> > Since intel_emit_linear_blit uses 1 byte per pixel, we can use the src/dst >> > pixel X offset field to represent the unaligned portion, and subtract >> > that from the address so it's cacheline aligned. >> > >> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521 >> > Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> >> > Cc: mesa-stable@lists.freedesktop.org >> >> s/cacheline/page/ afaik, and nope it's not documented. Chris&Mika learned >> that the hard way. Adding them to correct me in case I make a mess again. > > It's cacheline. > > Issue: if the 1st pixel in XY_SRC_COPY is not CL aligned when SRC or > DST are linear that will cause failure. > > https://vthsd.fm.intel.com/hsd/bdwgfx/bug_de/default.aspx?bug_de_id=1912704 > -Chris > FWIF, I ended up doing it like this in igt: http://lists.freedesktop.org/archives/intel-gfx/2015-January/059191.html And I think the documentation was updated on the restrictions. -Mika _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Mesa-dev] [PATCH 1/2] i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions. 2015-05-06 17:25 ` Mika Kuoppala @ 2015-05-06 17:41 ` Kenneth Graunke 0 siblings, 0 replies; 4+ messages in thread From: Kenneth Graunke @ 2015-05-06 17:41 UTC (permalink / raw) To: Mika Kuoppala; +Cc: Intel Graphics Development [-- Attachment #1.1: Type: text/plain, Size: 1905 bytes --] On Wednesday, May 06, 2015 08:25:28 PM Mika Kuoppala wrote: > Chris Wilson <chris@chris-wilson.co.uk> writes: > > > On Wed, May 06, 2015 at 03:38:44PM +0200, Daniel Vetter wrote: > >> On Tue, Apr 21, 2015 at 10:13:31PM -0700, Kenneth Graunke wrote: > >> > The BLT engine on Gen8+ requires linear surfaces to be cacheline > >> > aligned. This restriction was added as part of converting the BLT to > >> > use 48-bit addressing. > >> > > >> > intel_emit_linear_blit needs to handle blits that are not cacheline > >> > aligned, as we use it for arbitrary glBufferSubData calls and subrange > >> > mappings. > >> > > >> > Since intel_emit_linear_blit uses 1 byte per pixel, we can use the src/dst > >> > pixel X offset field to represent the unaligned portion, and subtract > >> > that from the address so it's cacheline aligned. > >> > > >> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521 > >> > Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> > >> > Cc: mesa-stable@lists.freedesktop.org > >> > >> s/cacheline/page/ afaik, and nope it's not documented. Chris&Mika learned > >> that the hard way. Adding them to correct me in case I make a mess again. > > > > It's cacheline. > > > > Issue: if the 1st pixel in XY_SRC_COPY is not CL aligned when SRC or > > DST are linear that will cause failure. > > > > https://vthsd.fm.intel.com/hsd/bdwgfx/bug_de/default.aspx?bug_de_id=1912704 > > -Chris > > > > FWIF, I ended up doing it like this in igt: > > http://lists.freedesktop.org/archives/intel-gfx/2015-January/059191.html > > And I think the documentation was updated on the restrictions. > > -Mika Yeah, I saw the updated documentation, remembered that Chris warned me about this a while back (I think I just said "ugh" and promptly forgot about it), and finally fixed Mesa. It's all upstream and working now. Huge thanks for tracking this down and getting it documented! [-- Attachment #1.2: This is a digitally signed message part. --] [-- Type: application/pgp-signature, Size: 819 bytes --] [-- Attachment #2: Type: text/plain, Size: 159 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2015-05-06 17:41 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
[not found] <1429679612-18584-1-git-send-email-kenneth@whitecape.org>
2015-05-06 13:38 ` [Mesa-dev] [PATCH 1/2] i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions Daniel Vetter
2015-05-06 13:45 ` Chris Wilson
2015-05-06 17:25 ` Mika Kuoppala
2015-05-06 17:41 ` Kenneth Graunke
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.