* [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE
@ 2023-05-30 18:55 Anusha Srivatsa
2023-05-30 18:55 ` [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step Anusha Srivatsa
` (9 more replies)
0 siblings, 10 replies; 16+ messages in thread
From: Anusha Srivatsa @ 2023-05-30 18:55 UTC (permalink / raw)
To: intel-gfx
Replace all occurences of ADL -> ALDERLAKE in
platform and subplatform defines. This way there is a
consistent pattern to how platforms are referred. While
the change is minor and could be combined to have lesser patches,
splitting to per subpaltform for easier cherrypicks, if needed.
Anusha Srivatsa (5):
drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step
drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines
drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines
drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines
drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines
drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++----
.../gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 16 ++++++++--------
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
drivers/gpu/drm/i915/intel_step.c | 6 +++---
10 files changed, 24 insertions(+), 24 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread* [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step 2023-05-30 18:55 [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE Anusha Srivatsa @ 2023-05-30 18:55 ` Anusha Srivatsa 2023-06-05 15:13 ` Jani Nikula 2023-05-30 18:55 ` [Intel-gfx] [PATCH 2/5] drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines Anusha Srivatsa ` (8 subsequent siblings) 9 siblings, 1 reply; 16+ messages in thread From: Anusha Srivatsa @ 2023-05-30 18:55 UTC (permalink / raw) To: intel-gfx Driver refers to the platfrom Alderlake P as ADLP in places and ALDERLAKE_P in some. Making the consistent change to avoid confusion of the right naming convention for the platform. Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> --- drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++---- drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++-- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 6bed75f1541a..013678caaca8 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -3541,7 +3541,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) } else if (IS_ALDERLAKE_P(dev_priv)) { dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; /* Wa_22011320316:adl-p[a0] */ - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; else if (IS_ADLP_RPLU(dev_priv)) dev_priv->display.cdclk.table = rplu_cdclk_table; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 6b2d8a1e2aa9..81f3ce5a0a1e 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3781,7 +3781,7 @@ static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct inte { u32 val; - if (!IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0) || + if (!IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0) || pll->info->id != DPLL_ID_ICL_DPLL0) return; /* diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index ea0389c5f656..c25457dae315 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -639,7 +639,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) } /* Wa_22012278275:adl-p */ - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { static const u8 map[] = { 2, /* 5 lines */ 1, /* 6 lines */ @@ -807,7 +807,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, return; /* Wa_16011303918:adl-p */ - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) return; /* @@ -975,7 +975,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n"); return false; } @@ -1033,7 +1033,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, /* Wa_16011303918:adl-p */ if (crtc_state->vrr.enable && - IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { + IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, not compatible with HW stepping + VRR\n"); return false; diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 36070d86550f..2019e0a87bd3 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2174,7 +2174,7 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915, return false; /* Wa_22011186057 */ - if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) + if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) return false; if (DISPLAY_VER(i915) >= 11) @@ -2200,7 +2200,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915, return false; /* Wa_22011186057 */ - if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) + if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) return false; /* Wa_14013215631 */ diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f1205ed3ba71..1a50b8b2f00d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -669,11 +669,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, (IS_ALDERLAKE_S(__i915) && \ IS_GRAPHICS_STEP(__i915, since, until)) -#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \ +#define IS_ALDERLAKE_P_DISPLAY_STEP(__i915, since, until) \ (IS_ALDERLAKE_P(__i915) && \ IS_DISPLAY_STEP(__i915, since, until)) -#define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \ +#define IS_ALDERLAKE_P_GRAPHICS_STEP(__i915, since, until) \ (IS_ALDERLAKE_P(__i915) && \ IS_GRAPHICS_STEP(__i915, since, until)) -- 2.25.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step 2023-05-30 18:55 ` [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step Anusha Srivatsa @ 2023-06-05 15:13 ` Jani Nikula 2023-06-05 18:20 ` Srivatsa, Anusha 0 siblings, 1 reply; 16+ messages in thread From: Jani Nikula @ 2023-06-05 15:13 UTC (permalink / raw) To: Anusha Srivatsa, intel-gfx On Tue, 30 May 2023, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote: > Driver refers to the platfrom Alderlake P as ADLP in places > and ALDERLAKE_P in some. Making the consistent change > to avoid confusion of the right naming convention for > the platform. $ git grep "#define IS_.*_DISPLAY_STEP" -- drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_drv.h:#define IS_KBL_DISPLAY_STEP(i915, since, until) \ drivers/gpu/drm/i915/i915_drv.h:#define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \ drivers/gpu/drm/i915/i915_drv.h:#define IS_TGL_DISPLAY_STEP(__i915, since, until) \ drivers/gpu/drm/i915/i915_drv.h:#define IS_RKL_DISPLAY_STEP(p, since, until) \ drivers/gpu/drm/i915/i915_drv.h:#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \ drivers/gpu/drm/i915/i915_drv.h:#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \ drivers/gpu/drm/i915/i915_drv.h:#define IS_MTL_DISPLAY_STEP(__i915, since, until) \ drivers/gpu/drm/i915/i915_drv.h:#define IS_DG2_DISPLAY_STEP(__i915, since, until) \ They all use the acronym. Do you suggest to rename all of them, or just ADL-P? BR, Jani. > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- > drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++---- > drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++-- > drivers/gpu/drm/i915/i915_drv.h | 4 ++-- > 5 files changed, 10 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 6bed75f1541a..013678caaca8 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -3541,7 +3541,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) > } else if (IS_ALDERLAKE_P(dev_priv)) { > dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; > /* Wa_22011320316:adl-p[a0] */ > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) > + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) > dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; > else if (IS_ADLP_RPLU(dev_priv)) > dev_priv->display.cdclk.table = rplu_cdclk_table; > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > index 6b2d8a1e2aa9..81f3ce5a0a1e 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > @@ -3781,7 +3781,7 @@ static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct inte > { > u32 val; > > - if (!IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0) || > + if (!IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0) || > pll->info->id != DPLL_ID_ICL_DPLL0) > return; > /* > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index ea0389c5f656..c25457dae315 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -639,7 +639,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > } > > /* Wa_22012278275:adl-p */ > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { > + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { > static const u8 map[] = { > 2, /* 5 lines */ > 1, /* 6 lines */ > @@ -807,7 +807,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, > return; > > /* Wa_16011303918:adl-p */ > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) > + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) > return; > > /* > @@ -975,7 +975,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > return false; > } > > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { > + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { > drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n"); > return false; > } > @@ -1033,7 +1033,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > > /* Wa_16011303918:adl-p */ > if (crtc_state->vrr.enable && > - IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { > + IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { > drm_dbg_kms(&dev_priv->drm, > "PSR2 not enabled, not compatible with HW stepping + VRR\n"); > return false; > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c > index 36070d86550f..2019e0a87bd3 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > @@ -2174,7 +2174,7 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915, > return false; > > /* Wa_22011186057 */ > - if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) > + if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) > return false; > > if (DISPLAY_VER(i915) >= 11) > @@ -2200,7 +2200,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915, > return false; > > /* Wa_22011186057 */ > - if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) > + if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) > return false; > > /* Wa_14013215631 */ > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index f1205ed3ba71..1a50b8b2f00d 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -669,11 +669,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > (IS_ALDERLAKE_S(__i915) && \ > IS_GRAPHICS_STEP(__i915, since, until)) > > -#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \ > +#define IS_ALDERLAKE_P_DISPLAY_STEP(__i915, since, until) \ > (IS_ALDERLAKE_P(__i915) && \ > IS_DISPLAY_STEP(__i915, since, until)) > > -#define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \ > +#define IS_ALDERLAKE_P_GRAPHICS_STEP(__i915, since, until) \ > (IS_ALDERLAKE_P(__i915) && \ > IS_GRAPHICS_STEP(__i915, since, until)) -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step 2023-06-05 15:13 ` Jani Nikula @ 2023-06-05 18:20 ` Srivatsa, Anusha 2023-06-05 18:29 ` Jani Nikula 0 siblings, 1 reply; 16+ messages in thread From: Srivatsa, Anusha @ 2023-06-05 18:20 UTC (permalink / raw) To: Jani Nikula, intel-gfx@lists.freedesktop.org > -----Original Message----- > From: Jani Nikula <jani.nikula@linux.intel.com> > Sent: Monday, June 5, 2023 8:14 AM > To: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel- > gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for > display and graphics step > > On Tue, 30 May 2023, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote: > > Driver refers to the platfrom Alderlake P as ADLP in places and > > ALDERLAKE_P in some. Making the consistent change to avoid confusion > > of the right naming convention for the platform. > > $ git grep "#define IS_.*_DISPLAY_STEP" -- drivers/gpu/drm/i915/i915_drv.h > drivers/gpu/drm/i915/i915_drv.h:#define IS_KBL_DISPLAY_STEP(i915, since, > until) \ drivers/gpu/drm/i915/i915_drv.h:#define IS_JSL_EHL_DISPLAY_STEP(p, > since, until) \ drivers/gpu/drm/i915/i915_drv.h:#define > IS_TGL_DISPLAY_STEP(__i915, since, until) \ > drivers/gpu/drm/i915/i915_drv.h:#define IS_RKL_DISPLAY_STEP(p, since, until) \ > drivers/gpu/drm/i915/i915_drv.h:#define IS_ADLS_DISPLAY_STEP(__i915, since, > until) \ drivers/gpu/drm/i915/i915_drv.h:#define > IS_ADLP_DISPLAY_STEP(__i915, since, until) \ > drivers/gpu/drm/i915/i915_drv.h:#define IS_MTL_DISPLAY_STEP(__i915, since, > until) \ drivers/gpu/drm/i915/i915_drv.h:#define IS_DG2_DISPLAY_STEP(__i915, > since, until) \ > > They all use the acronym. Do you suggest to rename all of them, or just ADL-P? Got the idea after looking at subplatform defines in i915_drv.h: #define IS_METEORLAKE_M(i915) \ IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M) #define IS_METEORLAKE_P(i915) \ IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P) #define IS_DG2_G10(i915) \ IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) #define IS_DG2_G11(i915) \ IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11) #define IS_DG2_G12(i915) \ IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12) #define IS_ADLS_RPLS(i915) \ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) #define IS_ADLP_N(i915) \ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) #define IS_ADLP_RPLP(i915) \ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) #define IS_ADLP_RPLU(i915) \ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU) We are using the same platform name for platform and sub-platform defines for Meteor Lake and DG2, but somehow for flavors of Alder Lake, the sub-platform has acronym. The idea was that developers should not think if the full name or acronym has to be used. And that resulted in the series. But now that you have pointed out the above other such occurrences, I am leaning towards having them changed as well. That is for a platform defined as TIGERLAKE, All of its steppings etc should have TIGERLAKE_(TIGERLAKE_MEDIA_,TIGERLAKE_DISPLAY_, TIGERLAKE_GRAPHICS_ ) etc instead of having TIGERLAKE in some places and TGL in its stepping or sub-platform defines. This was the naming is uniform and consistent. Anusha > BR, > Jani. > > > > > > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- > > drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++---- > > drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++-- > > drivers/gpu/drm/i915/i915_drv.h | 4 ++-- > > 5 files changed, 10 insertions(+), 10 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > > b/drivers/gpu/drm/i915/display/intel_cdclk.c > > index 6bed75f1541a..013678caaca8 100644 > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > > @@ -3541,7 +3541,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private > *dev_priv) > > } else if (IS_ALDERLAKE_P(dev_priv)) { > > dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; > > /* Wa_22011320316:adl-p[a0] */ > > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) > > + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, > STEP_B0)) > > dev_priv->display.cdclk.table = > adlp_a_step_cdclk_table; > > else if (IS_ADLP_RPLU(dev_priv)) > > dev_priv->display.cdclk.table = rplu_cdclk_table; diff -- > git > > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > index 6b2d8a1e2aa9..81f3ce5a0a1e 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > @@ -3781,7 +3781,7 @@ static void adlp_cmtg_clock_gating_wa(struct > > drm_i915_private *i915, struct inte { > > u32 val; > > > > - if (!IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0) || > > + if (!IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0) || > > pll->info->id != DPLL_ID_ICL_DPLL0) > > return; > > /* > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index ea0389c5f656..c25457dae315 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -639,7 +639,7 @@ static void hsw_activate_psr2(struct intel_dp > *intel_dp) > > } > > > > /* Wa_22012278275:adl-p */ > > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { > > + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { > > static const u8 map[] = { > > 2, /* 5 lines */ > > 1, /* 6 lines */ > > @@ -807,7 +807,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp > *intel_dp, > > return; > > > > /* Wa_16011303918:adl-p */ > > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) > > + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) > > return; > > > > /* > > @@ -975,7 +975,7 @@ static bool intel_psr2_config_valid(struct intel_dp > *intel_dp, > > return false; > > } > > > > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { > > + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { > > drm_dbg_kms(&dev_priv->drm, "PSR2 not completely > functional in this stepping\n"); > > return false; > > } > > @@ -1033,7 +1033,7 @@ static bool intel_psr2_config_valid(struct > > intel_dp *intel_dp, > > > > /* Wa_16011303918:adl-p */ > > if (crtc_state->vrr.enable && > > - IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { > > + IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { > > drm_dbg_kms(&dev_priv->drm, > > "PSR2 not enabled, not compatible with HW stepping > + VRR\n"); > > return false; > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c > > b/drivers/gpu/drm/i915/display/skl_universal_plane.c > > index 36070d86550f..2019e0a87bd3 100644 > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > > @@ -2174,7 +2174,7 @@ static bool skl_plane_has_rc_ccs(struct > drm_i915_private *i915, > > return false; > > > > /* Wa_22011186057 */ > > - if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) > > + if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) > > return false; > > > > if (DISPLAY_VER(i915) >= 11) > > @@ -2200,7 +2200,7 @@ static bool gen12_plane_has_mc_ccs(struct > drm_i915_private *i915, > > return false; > > > > /* Wa_22011186057 */ > > - if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) > > + if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) > > return false; > > > > /* Wa_14013215631 */ > > diff --git a/drivers/gpu/drm/i915/i915_drv.h > > b/drivers/gpu/drm/i915/i915_drv.h index f1205ed3ba71..1a50b8b2f00d > > 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -669,11 +669,11 @@ IS_SUBPLATFORM(const struct drm_i915_private > *i915, > > (IS_ALDERLAKE_S(__i915) && \ > > IS_GRAPHICS_STEP(__i915, since, until)) > > > > -#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \ > > +#define IS_ALDERLAKE_P_DISPLAY_STEP(__i915, since, until) \ > > (IS_ALDERLAKE_P(__i915) && \ > > IS_DISPLAY_STEP(__i915, since, until)) > > > > -#define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \ > > +#define IS_ALDERLAKE_P_GRAPHICS_STEP(__i915, since, until) \ > > (IS_ALDERLAKE_P(__i915) && \ > > IS_GRAPHICS_STEP(__i915, since, until)) > > -- > Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step 2023-06-05 18:20 ` Srivatsa, Anusha @ 2023-06-05 18:29 ` Jani Nikula 2023-06-05 20:40 ` Srivatsa, Anusha 0 siblings, 1 reply; 16+ messages in thread From: Jani Nikula @ 2023-06-05 18:29 UTC (permalink / raw) To: Srivatsa, Anusha, intel-gfx@lists.freedesktop.org On Mon, 05 Jun 2023, "Srivatsa, Anusha" <anusha.srivatsa@intel.com> wrote: >> -----Original Message----- >> From: Jani Nikula <jani.nikula@linux.intel.com> >> Sent: Monday, June 5, 2023 8:14 AM >> To: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel- >> gfx@lists.freedesktop.org >> Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for >> display and graphics step >> >> On Tue, 30 May 2023, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote: >> > Driver refers to the platfrom Alderlake P as ADLP in places and >> > ALDERLAKE_P in some. Making the consistent change to avoid confusion >> > of the right naming convention for the platform. >> >> $ git grep "#define IS_.*_DISPLAY_STEP" -- drivers/gpu/drm/i915/i915_drv.h >> drivers/gpu/drm/i915/i915_drv.h:#define IS_KBL_DISPLAY_STEP(i915, since, >> until) \ drivers/gpu/drm/i915/i915_drv.h:#define IS_JSL_EHL_DISPLAY_STEP(p, >> since, until) \ drivers/gpu/drm/i915/i915_drv.h:#define >> IS_TGL_DISPLAY_STEP(__i915, since, until) \ >> drivers/gpu/drm/i915/i915_drv.h:#define IS_RKL_DISPLAY_STEP(p, since, until) \ >> drivers/gpu/drm/i915/i915_drv.h:#define IS_ADLS_DISPLAY_STEP(__i915, since, >> until) \ drivers/gpu/drm/i915/i915_drv.h:#define >> IS_ADLP_DISPLAY_STEP(__i915, since, until) \ >> drivers/gpu/drm/i915/i915_drv.h:#define IS_MTL_DISPLAY_STEP(__i915, since, >> until) \ drivers/gpu/drm/i915/i915_drv.h:#define IS_DG2_DISPLAY_STEP(__i915, >> since, until) \ >> >> They all use the acronym. Do you suggest to rename all of them, or just ADL-P? > > Got the idea after looking at subplatform defines in i915_drv.h: > > #define IS_METEORLAKE_M(i915) \ > IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M) > #define IS_METEORLAKE_P(i915) \ > IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P) > #define IS_DG2_G10(i915) \ > IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) > #define IS_DG2_G11(i915) \ > IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11) > #define IS_DG2_G12(i915) \ > IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12) > #define IS_ADLS_RPLS(i915) \ > IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) > #define IS_ADLP_N(i915) \ > IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) > #define IS_ADLP_RPLP(i915) \ > IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) > #define IS_ADLP_RPLU(i915) \ > IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU) > > We are using the same platform name for platform and sub-platform defines for Meteor Lake and DG2, but somehow for flavors of Alder Lake, the sub-platform has acronym. The idea was that developers should not think if the full name or acronym has to be used. And that resulted in the series. But now that you have pointed out the above other such occurrences, I am leaning towards having them changed as well. That is for a platform defined as TIGERLAKE, All of its steppings etc should have TIGERLAKE_(TIGERLAKE_MEDIA_,TIGERLAKE_DISPLAY_, TIGERLAKE_GRAPHICS_ ) etc instead of having TIGERLAKE in some places and TGL in its stepping or sub-platform defines. > > This was the naming is uniform and consistent. One could also make the case for switching all of them use the acronym instead for brevity. BR, Jani. > > Anusha >> BR, >> Jani. >> >> >> >> > >> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >> > --- >> > drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- >> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- >> > drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++---- >> > drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++-- >> > drivers/gpu/drm/i915/i915_drv.h | 4 ++-- >> > 5 files changed, 10 insertions(+), 10 deletions(-) >> > >> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c >> > b/drivers/gpu/drm/i915/display/intel_cdclk.c >> > index 6bed75f1541a..013678caaca8 100644 >> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c >> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c >> > @@ -3541,7 +3541,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private >> *dev_priv) >> > } else if (IS_ALDERLAKE_P(dev_priv)) { >> > dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; >> > /* Wa_22011320316:adl-p[a0] */ >> > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) >> > + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, >> STEP_B0)) >> > dev_priv->display.cdclk.table = >> adlp_a_step_cdclk_table; >> > else if (IS_ADLP_RPLU(dev_priv)) >> > dev_priv->display.cdclk.table = rplu_cdclk_table; diff -- >> git >> > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c >> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c >> > index 6b2d8a1e2aa9..81f3ce5a0a1e 100644 >> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c >> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c >> > @@ -3781,7 +3781,7 @@ static void adlp_cmtg_clock_gating_wa(struct >> > drm_i915_private *i915, struct inte { >> > u32 val; >> > >> > - if (!IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0) || >> > + if (!IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0) || >> > pll->info->id != DPLL_ID_ICL_DPLL0) >> > return; >> > /* >> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c >> > b/drivers/gpu/drm/i915/display/intel_psr.c >> > index ea0389c5f656..c25457dae315 100644 >> > --- a/drivers/gpu/drm/i915/display/intel_psr.c >> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c >> > @@ -639,7 +639,7 @@ static void hsw_activate_psr2(struct intel_dp >> *intel_dp) >> > } >> > >> > /* Wa_22012278275:adl-p */ >> > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { >> > + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { >> > static const u8 map[] = { >> > 2, /* 5 lines */ >> > 1, /* 6 lines */ >> > @@ -807,7 +807,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp >> *intel_dp, >> > return; >> > >> > /* Wa_16011303918:adl-p */ >> > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) >> > + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) >> > return; >> > >> > /* >> > @@ -975,7 +975,7 @@ static bool intel_psr2_config_valid(struct intel_dp >> *intel_dp, >> > return false; >> > } >> > >> > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { >> > + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { >> > drm_dbg_kms(&dev_priv->drm, "PSR2 not completely >> functional in this stepping\n"); >> > return false; >> > } >> > @@ -1033,7 +1033,7 @@ static bool intel_psr2_config_valid(struct >> > intel_dp *intel_dp, >> > >> > /* Wa_16011303918:adl-p */ >> > if (crtc_state->vrr.enable && >> > - IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { >> > + IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { >> > drm_dbg_kms(&dev_priv->drm, >> > "PSR2 not enabled, not compatible with HW stepping >> + VRR\n"); >> > return false; >> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c >> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c >> > index 36070d86550f..2019e0a87bd3 100644 >> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c >> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c >> > @@ -2174,7 +2174,7 @@ static bool skl_plane_has_rc_ccs(struct >> drm_i915_private *i915, >> > return false; >> > >> > /* Wa_22011186057 */ >> > - if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) >> > + if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) >> > return false; >> > >> > if (DISPLAY_VER(i915) >= 11) >> > @@ -2200,7 +2200,7 @@ static bool gen12_plane_has_mc_ccs(struct >> drm_i915_private *i915, >> > return false; >> > >> > /* Wa_22011186057 */ >> > - if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) >> > + if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) >> > return false; >> > >> > /* Wa_14013215631 */ >> > diff --git a/drivers/gpu/drm/i915/i915_drv.h >> > b/drivers/gpu/drm/i915/i915_drv.h index f1205ed3ba71..1a50b8b2f00d >> > 100644 >> > --- a/drivers/gpu/drm/i915/i915_drv.h >> > +++ b/drivers/gpu/drm/i915/i915_drv.h >> > @@ -669,11 +669,11 @@ IS_SUBPLATFORM(const struct drm_i915_private >> *i915, >> > (IS_ALDERLAKE_S(__i915) && \ >> > IS_GRAPHICS_STEP(__i915, since, until)) >> > >> > -#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \ >> > +#define IS_ALDERLAKE_P_DISPLAY_STEP(__i915, since, until) \ >> > (IS_ALDERLAKE_P(__i915) && \ >> > IS_DISPLAY_STEP(__i915, since, until)) >> > >> > -#define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \ >> > +#define IS_ALDERLAKE_P_GRAPHICS_STEP(__i915, since, until) \ >> > (IS_ALDERLAKE_P(__i915) && \ >> > IS_GRAPHICS_STEP(__i915, since, until)) >> >> -- >> Jani Nikula, Intel Open Source Graphics Center -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step 2023-06-05 18:29 ` Jani Nikula @ 2023-06-05 20:40 ` Srivatsa, Anusha 0 siblings, 0 replies; 16+ messages in thread From: Srivatsa, Anusha @ 2023-06-05 20:40 UTC (permalink / raw) To: Jani Nikula, intel-gfx@lists.freedesktop.org +Tvrtko +Joonas > -----Original Message----- > From: Jani Nikula <jani.nikula@linux.intel.com> > Sent: Monday, June 5, 2023 11:29 AM > To: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel- > gfx@lists.freedesktop.org > Subject: RE: [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for > display and graphics step > > On Mon, 05 Jun 2023, "Srivatsa, Anusha" <anusha.srivatsa@intel.com> wrote: > >> -----Original Message----- > >> From: Jani Nikula <jani.nikula@linux.intel.com> > >> Sent: Monday, June 5, 2023 8:14 AM > >> To: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel- > >> gfx@lists.freedesktop.org > >> Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915/adlp: > >> s/ADLP/ALDERLAKE_P for display and graphics step > >> > >> On Tue, 30 May 2023, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote: > >> > Driver refers to the platfrom Alderlake P as ADLP in places and > >> > ALDERLAKE_P in some. Making the consistent change to avoid > >> > confusion of the right naming convention for the platform. > >> > >> $ git grep "#define IS_.*_DISPLAY_STEP" -- > >> drivers/gpu/drm/i915/i915_drv.h > >> drivers/gpu/drm/i915/i915_drv.h:#define IS_KBL_DISPLAY_STEP(i915, > >> since, > >> until) \ drivers/gpu/drm/i915/i915_drv.h:#define > >> IS_JSL_EHL_DISPLAY_STEP(p, since, until) \ > >> drivers/gpu/drm/i915/i915_drv.h:#define > >> IS_TGL_DISPLAY_STEP(__i915, since, until) \ > >> drivers/gpu/drm/i915/i915_drv.h:#define IS_RKL_DISPLAY_STEP(p, since, > >> until) \ drivers/gpu/drm/i915/i915_drv.h:#define > >> IS_ADLS_DISPLAY_STEP(__i915, since, > >> until) \ drivers/gpu/drm/i915/i915_drv.h:#define > >> IS_ADLP_DISPLAY_STEP(__i915, since, until) \ > >> drivers/gpu/drm/i915/i915_drv.h:#define IS_MTL_DISPLAY_STEP(__i915, > >> since, > >> until) \ drivers/gpu/drm/i915/i915_drv.h:#define > >> IS_DG2_DISPLAY_STEP(__i915, since, until) \ > >> > >> They all use the acronym. Do you suggest to rename all of them, or just ADL- > P? > > > > Got the idea after looking at subplatform defines in i915_drv.h: > > > > #define IS_METEORLAKE_M(i915) \ > > IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M) > > #define IS_METEORLAKE_P(i915) \ > > IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P) > > #define IS_DG2_G10(i915) \ > > IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) #define > > IS_DG2_G11(i915) \ > > IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11) #define > > IS_DG2_G12(i915) \ > > IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12) #define > > IS_ADLS_RPLS(i915) \ > > IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, > INTEL_SUBPLATFORM_RPL) > > #define IS_ADLP_N(i915) \ > > IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) > > #define IS_ADLP_RPLP(i915) \ > > IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, > INTEL_SUBPLATFORM_RPL) > > #define IS_ADLP_RPLU(i915) \ > > IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, > > INTEL_SUBPLATFORM_RPLU) > > > > We are using the same platform name for platform and sub-platform defines > for Meteor Lake and DG2, but somehow for flavors of Alder Lake, the sub- > platform has acronym. The idea was that developers should not think if the full > name or acronym has to be used. And that resulted in the series. But now that > you have pointed out the above other such occurrences, I am leaning towards > having them changed as well. That is for a platform defined as TIGERLAKE, All of > its steppings etc should have > TIGERLAKE_(TIGERLAKE_MEDIA_,TIGERLAKE_DISPLAY_, TIGERLAKE_GRAPHICS_ > ) etc instead of having TIGERLAKE in some places and TGL in its stepping or sub- > platform defines. > > > > This was the naming is uniform and consistent. > > One could also make the case for switching all of them use the acronym instead > for brevity. That works too. Anusha > BR, > Jani. > > > > > > Anusha > >> BR, > >> Jani. > >> > >> > >> > >> > > >> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > >> > --- > >> > drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- > >> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- > >> > drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++---- > >> > drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++-- > >> > drivers/gpu/drm/i915/i915_drv.h | 4 ++-- > >> > 5 files changed, 10 insertions(+), 10 deletions(-) > >> > > >> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > >> > b/drivers/gpu/drm/i915/display/intel_cdclk.c > >> > index 6bed75f1541a..013678caaca8 100644 > >> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > >> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > >> > @@ -3541,7 +3541,7 @@ void intel_init_cdclk_hooks(struct > >> > drm_i915_private > >> *dev_priv) > >> > } else if (IS_ALDERLAKE_P(dev_priv)) { > >> > dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; > >> > /* Wa_22011320316:adl-p[a0] */ > >> > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) > >> > + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, > >> STEP_B0)) > >> > dev_priv->display.cdclk.table = > >> adlp_a_step_cdclk_table; > >> > else if (IS_ADLP_RPLU(dev_priv)) > >> > dev_priv->display.cdclk.table = rplu_cdclk_table; diff -- > >> git > >> > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > >> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > >> > index 6b2d8a1e2aa9..81f3ce5a0a1e 100644 > >> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > >> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > >> > @@ -3781,7 +3781,7 @@ static void adlp_cmtg_clock_gating_wa(struct > >> > drm_i915_private *i915, struct inte { > >> > u32 val; > >> > > >> > - if (!IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0) || > >> > + if (!IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0) || > >> > pll->info->id != DPLL_ID_ICL_DPLL0) > >> > return; > >> > /* > >> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > >> > b/drivers/gpu/drm/i915/display/intel_psr.c > >> > index ea0389c5f656..c25457dae315 100644 > >> > --- a/drivers/gpu/drm/i915/display/intel_psr.c > >> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > >> > @@ -639,7 +639,7 @@ static void hsw_activate_psr2(struct intel_dp > >> *intel_dp) > >> > } > >> > > >> > /* Wa_22012278275:adl-p */ > >> > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { > >> > + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { > >> > static const u8 map[] = { > >> > 2, /* 5 lines */ > >> > 1, /* 6 lines */ > >> > @@ -807,7 +807,7 @@ tgl_dc3co_exitline_compute_config(struct > >> > intel_dp > >> *intel_dp, > >> > return; > >> > > >> > /* Wa_16011303918:adl-p */ > >> > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) > >> > + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) > >> > return; > >> > > >> > /* > >> > @@ -975,7 +975,7 @@ static bool intel_psr2_config_valid(struct > >> > intel_dp > >> *intel_dp, > >> > return false; > >> > } > >> > > >> > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { > >> > + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { > >> > drm_dbg_kms(&dev_priv->drm, "PSR2 not completely > >> functional in this stepping\n"); > >> > return false; > >> > } > >> > @@ -1033,7 +1033,7 @@ static bool intel_psr2_config_valid(struct > >> > intel_dp *intel_dp, > >> > > >> > /* Wa_16011303918:adl-p */ > >> > if (crtc_state->vrr.enable && > >> > - IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { > >> > + IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { > >> > drm_dbg_kms(&dev_priv->drm, > >> > "PSR2 not enabled, not compatible with HW stepping > >> + VRR\n"); > >> > return false; > >> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c > >> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c > >> > index 36070d86550f..2019e0a87bd3 100644 > >> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > >> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > >> > @@ -2174,7 +2174,7 @@ static bool skl_plane_has_rc_ccs(struct > >> drm_i915_private *i915, > >> > return false; > >> > > >> > /* Wa_22011186057 */ > >> > - if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) > >> > + if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) > >> > return false; > >> > > >> > if (DISPLAY_VER(i915) >= 11) > >> > @@ -2200,7 +2200,7 @@ static bool gen12_plane_has_mc_ccs(struct > >> drm_i915_private *i915, > >> > return false; > >> > > >> > /* Wa_22011186057 */ > >> > - if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) > >> > + if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) > >> > return false; > >> > > >> > /* Wa_14013215631 */ > >> > diff --git a/drivers/gpu/drm/i915/i915_drv.h > >> > b/drivers/gpu/drm/i915/i915_drv.h index f1205ed3ba71..1a50b8b2f00d > >> > 100644 > >> > --- a/drivers/gpu/drm/i915/i915_drv.h > >> > +++ b/drivers/gpu/drm/i915/i915_drv.h > >> > @@ -669,11 +669,11 @@ IS_SUBPLATFORM(const struct drm_i915_private > >> *i915, > >> > (IS_ALDERLAKE_S(__i915) && \ > >> > IS_GRAPHICS_STEP(__i915, since, until)) > >> > > >> > -#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \ > >> > +#define IS_ALDERLAKE_P_DISPLAY_STEP(__i915, since, until) \ > >> > (IS_ALDERLAKE_P(__i915) && \ > >> > IS_DISPLAY_STEP(__i915, since, until)) > >> > > >> > -#define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \ > >> > +#define IS_ALDERLAKE_P_GRAPHICS_STEP(__i915, since, until) \ > >> > (IS_ALDERLAKE_P(__i915) && \ > >> > IS_GRAPHICS_STEP(__i915, since, until)) > >> > >> -- > >> Jani Nikula, Intel Open Source Graphics Center > > -- > Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 2/5] drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines 2023-05-30 18:55 [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE Anusha Srivatsa 2023-05-30 18:55 ` [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step Anusha Srivatsa @ 2023-05-30 18:55 ` Anusha Srivatsa 2023-06-05 15:16 ` Jani Nikula 2023-05-30 18:55 ` [Intel-gfx] [PATCH 3/5] drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines Anusha Srivatsa ` (7 subsequent siblings) 9 siblings, 1 reply; 16+ messages in thread From: Anusha Srivatsa @ 2023-05-30 18:55 UTC (permalink / raw) To: intel-gfx Follow consistent naming convention. Replace ADLP with ALDERLAKE_P. Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_step.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 1a50b8b2f00d..43414cdc137c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -581,7 +581,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) #define IS_ADLP_N(i915) \ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) -#define IS_ADLP_RPLP(i915) \ +#define IS_ALDERLAKE_P_RPLP(i915) \ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) #define IS_ADLP_RPLU(i915) \ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU) diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c index 8a9ff6227e53..10d86c525beb 100644 --- a/drivers/gpu/drm/i915/intel_step.c +++ b/drivers/gpu/drm/i915/intel_step.c @@ -195,7 +195,7 @@ void intel_step_init(struct drm_i915_private *i915) } else if (IS_ADLP_N(i915)) { revids = adlp_n_revids; size = ARRAY_SIZE(adlp_n_revids); - } else if (IS_ADLP_RPLP(i915)) { + } else if (IS_ALDERLAKE_P_RPLP(i915)) { revids = adlp_rplp_revids; size = ARRAY_SIZE(adlp_rplp_revids); } else if (IS_ALDERLAKE_P(i915)) { -- 2.25.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 2/5] drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines 2023-05-30 18:55 ` [Intel-gfx] [PATCH 2/5] drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines Anusha Srivatsa @ 2023-06-05 15:16 ` Jani Nikula 0 siblings, 0 replies; 16+ messages in thread From: Jani Nikula @ 2023-06-05 15:16 UTC (permalink / raw) To: Anusha Srivatsa, intel-gfx On Tue, 30 May 2023, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote: > Follow consistent naming convention. Replace ADLP with > ALDERLAKE_P. Here too the consistent naming convention for all macros using IS_SUBPLATFORM() is to use the acronym. The IS_METEORLAKE_M() and IS_METEORLAKE_P() macros are the outliers. Again, do you suggest we rename all of them, or just ADL-P? The former is a lot of churn, and the latter is not consistent. BR, Jani. > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 2 +- > drivers/gpu/drm/i915/intel_step.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 1a50b8b2f00d..43414cdc137c 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -581,7 +581,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) > #define IS_ADLP_N(i915) \ > IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) > -#define IS_ADLP_RPLP(i915) \ > +#define IS_ALDERLAKE_P_RPLP(i915) \ > IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) > #define IS_ADLP_RPLU(i915) \ > IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU) > diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c > index 8a9ff6227e53..10d86c525beb 100644 > --- a/drivers/gpu/drm/i915/intel_step.c > +++ b/drivers/gpu/drm/i915/intel_step.c > @@ -195,7 +195,7 @@ void intel_step_init(struct drm_i915_private *i915) > } else if (IS_ADLP_N(i915)) { > revids = adlp_n_revids; > size = ARRAY_SIZE(adlp_n_revids); > - } else if (IS_ADLP_RPLP(i915)) { > + } else if (IS_ALDERLAKE_P_RPLP(i915)) { > revids = adlp_rplp_revids; > size = ARRAY_SIZE(adlp_rplp_revids); > } else if (IS_ALDERLAKE_P(i915)) { -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 3/5] drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines 2023-05-30 18:55 [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE Anusha Srivatsa 2023-05-30 18:55 ` [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step Anusha Srivatsa 2023-05-30 18:55 ` [Intel-gfx] [PATCH 2/5] drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines Anusha Srivatsa @ 2023-05-30 18:55 ` Anusha Srivatsa 2023-05-30 18:55 ` [Intel-gfx] [PATCH 4/5] drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines Anusha Srivatsa ` (6 subsequent siblings) 9 siblings, 0 replies; 16+ messages in thread From: Anusha Srivatsa @ 2023-05-30 18:55 UTC (permalink / raw) To: intel-gfx Follow consistent naming convention. Replace ADLP with ALDERLAKE_P Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> --- drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 013678caaca8..4420de5ffe9c 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -3543,7 +3543,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) /* Wa_22011320316:adl-p[a0] */ if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; - else if (IS_ADLP_RPLU(dev_priv)) + else if (IS_ALDERLAKE_P_RPLU(dev_priv)) dev_priv->display.cdclk.table = rplu_cdclk_table; else dev_priv->display.cdclk.table = adlp_cdclk_table; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 43414cdc137c..d400cecb318b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -583,7 +583,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) #define IS_ALDERLAKE_P_RPLP(i915) \ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) -#define IS_ADLP_RPLU(i915) \ +#define IS_ALDERLAKE_P_RPLU(i915) \ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU) #define IS_HSW_EARLY_SDV(i915) (IS_HASWELL(i915) && \ (INTEL_DEVID(i915) & 0xFF00) == 0x0C00) -- 2.25.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 4/5] drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines 2023-05-30 18:55 [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE Anusha Srivatsa ` (2 preceding siblings ...) 2023-05-30 18:55 ` [Intel-gfx] [PATCH 3/5] drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines Anusha Srivatsa @ 2023-05-30 18:55 ` Anusha Srivatsa 2023-05-30 18:55 ` [Intel-gfx] [PATCH 5/5] drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines Anusha Srivatsa ` (5 subsequent siblings) 9 siblings, 0 replies; 16+ messages in thread From: Anusha Srivatsa @ 2023-05-30 18:55 UTC (permalink / raw) To: intel-gfx Follow consistent naming convention. Replace ADLP with ALDERLAKE_P Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_step.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c index 852bea0208ce..cc9569af7f0c 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c @@ -94,7 +94,7 @@ static int guc_hwconfig_fill_buffer(struct intel_guc *guc, struct intel_hwconfig static bool has_table(struct drm_i915_private *i915) { - if (IS_ALDERLAKE_P(i915) && !IS_ADLP_N(i915)) + if (IS_ALDERLAKE_P(i915) && !IS_ALDERLAKE_P_N(i915)) return true; if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) return true; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index dc5c96c503a9..0989003a10ed 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -276,7 +276,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct intel_uc_fw *uc_fw) * ADL-S, otherwise the GuC might attempt to fetch a config table that * does not exist. */ - if (IS_ADLP_N(i915)) + if (IS_ALDERLAKE_P_N(i915)) p = INTEL_ALDERLAKE_S; GEM_BUG_ON(uc_fw->type >= ARRAY_SIZE(blobs_all)); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d400cecb318b..4ef336f6f24b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -579,7 +579,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12) #define IS_ADLS_RPLS(i915) \ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) -#define IS_ADLP_N(i915) \ +#define IS_ALDERLAKE_P_N(i915) \ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) #define IS_ALDERLAKE_P_RPLP(i915) \ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c index 10d86c525beb..0afe113b295a 100644 --- a/drivers/gpu/drm/i915/intel_step.c +++ b/drivers/gpu/drm/i915/intel_step.c @@ -192,7 +192,7 @@ void intel_step_init(struct drm_i915_private *i915) } else if (IS_XEHPSDV(i915)) { revids = xehpsdv_revids; size = ARRAY_SIZE(xehpsdv_revids); - } else if (IS_ADLP_N(i915)) { + } else if (IS_ALDERLAKE_P_N(i915)) { revids = adlp_n_revids; size = ARRAY_SIZE(adlp_n_revids); } else if (IS_ALDERLAKE_P_RPLP(i915)) { -- 2.25.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 5/5] drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines 2023-05-30 18:55 [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE Anusha Srivatsa ` (3 preceding siblings ...) 2023-05-30 18:55 ` [Intel-gfx] [PATCH 4/5] drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines Anusha Srivatsa @ 2023-05-30 18:55 ` Anusha Srivatsa 2023-05-31 16:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for s/ADL/ALDERLAKE Patchwork ` (4 subsequent siblings) 9 siblings, 0 replies; 16+ messages in thread From: Anusha Srivatsa @ 2023-05-30 18:55 UTC (permalink / raw) To: intel-gfx Driver refers to the platfrom Alderlake S as ADLS in places and ALDERLAKE_S in some. Making the consistent change to avoid confusion of the right naming convention for the platform. Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 6 +++--- drivers/gpu/drm/i915/intel_device_info.c | 2 +- drivers/gpu/drm/i915/intel_step.c | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c index c8b9cbb7ba3a..2bd908953e18 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c @@ -43,7 +43,7 @@ static void uc_expand_default_options(struct intel_uc *uc) } /* Intermediate platforms are HuC authentication only */ - if (IS_ALDERLAKE_S(i915) && !IS_ADLS_RPLS(i915)) { + if (IS_ALDERLAKE_S(i915) && !IS_ALDERLAKE_S_RPLS(i915)) { i915->params.enable_guc = ENABLE_GUC_LOAD_HUC; return; } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4ef336f6f24b..3ef2eb9fde02 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -577,7 +577,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11) #define IS_DG2_G12(i915) \ IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12) -#define IS_ADLS_RPLS(i915) \ +#define IS_ALDERLAKE_S_RPLS(i915) \ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) #define IS_ALDERLAKE_P_N(i915) \ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) @@ -661,11 +661,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_RKL_DISPLAY_STEP(p, since, until) \ (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until)) -#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \ +#define IS_ALDERLAKE_S_DISPLAY_STEP(__i915, since, until) \ (IS_ALDERLAKE_S(__i915) && \ IS_DISPLAY_STEP(__i915, since, until)) -#define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \ +#define IS_ALDERLAKE_S_GRAPHICS_STEP(__i915, since, until) \ (IS_ALDERLAKE_S(__i915) && \ IS_GRAPHICS_STEP(__i915, since, until)) diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 2f79d232b04a..559697c65664 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -416,7 +416,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) enum pipe pipe; /* Wa_14011765242: adl-s A0,A1 */ - if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2)) + if (IS_ALDERLAKE_S_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2)) for_each_pipe(dev_priv, pipe) display_runtime->num_scalers[pipe] = 0; else if (DISPLAY_VER(dev_priv) >= 11) { diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c index 0afe113b295a..15c23c8982b9 100644 --- a/drivers/gpu/drm/i915/intel_step.c +++ b/drivers/gpu/drm/i915/intel_step.c @@ -201,7 +201,7 @@ void intel_step_init(struct drm_i915_private *i915) } else if (IS_ALDERLAKE_P(i915)) { revids = adlp_revids; size = ARRAY_SIZE(adlp_revids); - } else if (IS_ADLS_RPLS(i915)) { + } else if (IS_ALDERLAKE_S_RPLS(i915)) { revids = adls_rpls_revids; size = ARRAY_SIZE(adls_rpls_revids); } else if (IS_ALDERLAKE_S(i915)) { -- 2.25.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for s/ADL/ALDERLAKE 2023-05-30 18:55 [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE Anusha Srivatsa ` (4 preceding siblings ...) 2023-05-30 18:55 ` [Intel-gfx] [PATCH 5/5] drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines Anusha Srivatsa @ 2023-05-31 16:26 ` Patchwork 2023-05-31 16:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork ` (3 subsequent siblings) 9 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2023-05-31 16:26 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: intel-gfx == Series Details == Series: s/ADL/ALDERLAKE URL : https://patchwork.freedesktop.org/series/118596/ State : warning == Summary == Error: dim checkpatch failed 4fc3d4f72d67 drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step -:7: WARNING:TYPO_SPELLING: 'platfrom' may be misspelled - perhaps 'platform'? #7: Driver refers to the platfrom Alderlake P as ADLP in places ^^^^^^^^ -:111: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #111: FILE: drivers/gpu/drm/i915/i915_drv.h:672: +#define IS_ALDERLAKE_P_DISPLAY_STEP(__i915, since, until) \ (IS_ALDERLAKE_P(__i915) && \ IS_DISPLAY_STEP(__i915, since, until)) -:116: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #116: FILE: drivers/gpu/drm/i915/i915_drv.h:676: +#define IS_ALDERLAKE_P_GRAPHICS_STEP(__i915, since, until) \ (IS_ALDERLAKE_P(__i915) && \ IS_GRAPHICS_STEP(__i915, since, until)) total: 0 errors, 1 warnings, 2 checks, 77 lines checked 6da159fe5a5e drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines eeff70227232 drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines e941cc927ade drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines fcf47d823462 drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines -:7: WARNING:TYPO_SPELLING: 'platfrom' may be misspelled - perhaps 'platform'? #7: Driver refers to the platfrom Alderlake S as ADLS in places ^^^^^^^^ -:45: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #45: FILE: drivers/gpu/drm/i915/i915_drv.h:664: +#define IS_ALDERLAKE_S_DISPLAY_STEP(__i915, since, until) \ (IS_ALDERLAKE_S(__i915) && \ IS_DISPLAY_STEP(__i915, since, until)) -:50: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #50: FILE: drivers/gpu/drm/i915/i915_drv.h:668: +#define IS_ALDERLAKE_S_GRAPHICS_STEP(__i915, since, until) \ (IS_ALDERLAKE_S(__i915) && \ IS_GRAPHICS_STEP(__i915, since, until)) total: 0 errors, 1 warnings, 2 checks, 45 lines checked ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for s/ADL/ALDERLAKE 2023-05-30 18:55 [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE Anusha Srivatsa ` (5 preceding siblings ...) 2023-05-31 16:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for s/ADL/ALDERLAKE Patchwork @ 2023-05-31 16:26 ` Patchwork 2023-05-31 16:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork ` (2 subsequent siblings) 9 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2023-05-31 16:26 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: intel-gfx == Series Details == Series: s/ADL/ALDERLAKE URL : https://patchwork.freedesktop.org/series/118596/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for s/ADL/ALDERLAKE 2023-05-30 18:55 [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE Anusha Srivatsa ` (6 preceding siblings ...) 2023-05-31 16:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork @ 2023-05-31 16:40 ` Patchwork 2023-06-02 4:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2023-06-05 15:19 ` [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE Jani Nikula 9 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2023-05-31 16:40 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 9181 bytes --] == Series Details == Series: s/ADL/ALDERLAKE URL : https://patchwork.freedesktop.org/series/118596/ State : success == Summary == CI Bug Log - changes from CI_DRM_13207 -> Patchwork_118596v1 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/index.html Participating hosts (36 -> 36) ------------------------------ No changes in participating hosts Known issues ------------ Here are the changes found in Patchwork_118596v1 that come from known issues: ### CI changes ### #### Possible fixes #### * boot: - fi-kbl-8809g: [FAIL][1] ([i915#8293] / [i915#8298]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/fi-kbl-8809g/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/fi-kbl-8809g/boot.html ### IGT changes ### #### Issues hit #### * igt@core_hotunplug@unbind-rebind: - fi-kbl-8809g: NOTRUN -> [ABORT][3] ([i915#8298] / [i915#8299] / [i915#8397]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/fi-kbl-8809g/igt@core_hotunplug@unbind-rebind.html * igt@dmabuf@all-tests@dma_fence: - fi-kbl-guc: [PASS][4] -> [DMESG-FAIL][5] ([i915#8189]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/fi-kbl-guc/igt@dmabuf@all-tests@dma_fence.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/fi-kbl-guc/igt@dmabuf@all-tests@dma_fence.html * igt@dmabuf@all-tests@sanitycheck: - fi-kbl-guc: [PASS][6] -> [ABORT][7] ([i915#8423]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/fi-kbl-guc/igt@dmabuf@all-tests@sanitycheck.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/fi-kbl-guc/igt@dmabuf@all-tests@sanitycheck.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html * igt@i915_selftest@live@requests: - bat-rpls-2: [PASS][9] -> [ABORT][10] ([i915#7913] / [i915#7982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/bat-rpls-2/igt@i915_selftest@live@requests.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/bat-rpls-2/igt@i915_selftest@live@requests.html * igt@i915_suspend@basic-s3-without-i915: - bat-rpls-1: NOTRUN -> [ABORT][11] ([i915#6687] / [i915#7978]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/bat-rpls-1/igt@i915_suspend@basic-s3-without-i915.html * igt@kms_addfb_basic@too-high: - fi-kbl-8809g: NOTRUN -> [FAIL][12] ([i915#8296]) +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/fi-kbl-8809g/igt@kms_addfb_basic@too-high.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-adlp-9: NOTRUN -> [SKIP][13] ([i915#7828]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/bat-adlp-9/igt@kms_chamelium_hpd@common-hpd-after-suspend.html * igt@kms_force_connector_basic@force-connector-state: - fi-kbl-8809g: NOTRUN -> [DMESG-FAIL][14] ([i915#8299]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/fi-kbl-8809g/igt@kms_force_connector_basic@force-connector-state.html * igt@kms_force_connector_basic@force-edid: - fi-kbl-8809g: NOTRUN -> [CRASH][15] ([i915#8299]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/fi-kbl-8809g/igt@kms_force_connector_basic@force-edid.html * igt@kms_psr@cursor_plane_move: - fi-kbl-8809g: NOTRUN -> [SKIP][16] ([fdo#109271]) +59 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html * igt@kms_setmode@basic-clone-single-crtc: - fi-kbl-8809g: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4579]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/fi-kbl-8809g/igt@kms_setmode@basic-clone-single-crtc.html #### Possible fixes #### * igt@i915_module_load@load: - {bat-adlp-11}: [ABORT][18] ([i915#4423] / [i915#8189]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/bat-adlp-11/igt@i915_module_load@load.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/bat-adlp-11/igt@i915_module_load@load.html * igt@i915_selftest@live@requests: - {bat-mtlp-8}: [DMESG-FAIL][20] ([i915#8497]) -> [PASS][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/bat-mtlp-8/igt@i915_selftest@live@requests.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/bat-mtlp-8/igt@i915_selftest@live@requests.html - bat-rpls-1: [ABORT][22] ([i915#7911] / [i915#7920] / [i915#7982]) -> [PASS][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/bat-rpls-1/igt@i915_selftest@live@requests.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/bat-rpls-1/igt@i915_selftest@live@requests.html * igt@i915_selftest@live@workarounds: - bat-adlp-9: [INCOMPLETE][24] ([i915#4983] / [i915#7677] / [i915#7913]) -> [PASS][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/bat-adlp-9/igt@i915_selftest@live@workarounds.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/bat-adlp-9/igt@i915_selftest@live@workarounds.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1: - bat-dg2-8: [FAIL][26] ([i915#7932]) -> [PASS][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#4093]: https://gitlab.freedesktop.org/drm/intel/issues/4093 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423 [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687 [i915#6868]: https://gitlab.freedesktop.org/drm/intel/issues/6868 [i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059 [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456 [i915#7677]: https://gitlab.freedesktop.org/drm/intel/issues/7677 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920 [i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932 [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978 [i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982 [i915#8189]: https://gitlab.freedesktop.org/drm/intel/issues/8189 [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293 [i915#8296]: https://gitlab.freedesktop.org/drm/intel/issues/8296 [i915#8298]: https://gitlab.freedesktop.org/drm/intel/issues/8298 [i915#8299]: https://gitlab.freedesktop.org/drm/intel/issues/8299 [i915#8397]: https://gitlab.freedesktop.org/drm/intel/issues/8397 [i915#8423]: https://gitlab.freedesktop.org/drm/intel/issues/8423 [i915#8497]: https://gitlab.freedesktop.org/drm/intel/issues/8497 Build changes ------------- * Linux: CI_DRM_13207 -> Patchwork_118596v1 CI-20190529: 20190529 CI_DRM_13207: e4b4b268de5e5b01c28b3d24b43453eaec2da37e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7314: ab70dfcdecf93a17fcaddb774855f726325fa0dd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_118596v1: e4b4b268de5e5b01c28b3d24b43453eaec2da37e @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits b6e0bf5a57a4 drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines a694eb706fe5 drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines f381d9c4c96b drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines a60b929fdf1a drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines 31a133055191 drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/index.html [-- Attachment #2: Type: text/html, Size: 10092 bytes --] ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for s/ADL/ALDERLAKE 2023-05-30 18:55 [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE Anusha Srivatsa ` (7 preceding siblings ...) 2023-05-31 16:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2023-06-02 4:35 ` Patchwork 2023-06-05 15:19 ` [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE Jani Nikula 9 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2023-06-02 4:35 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 16463 bytes --] == Series Details == Series: s/ADL/ALDERLAKE URL : https://patchwork.freedesktop.org/series/118596/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13207_full -> Patchwork_118596v1_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_118596v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_118596v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (7 -> 7) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_118596v1_full: ### IGT changes ### #### Possible regressions #### * igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs: - shard-apl: [PASS][1] -> [DMESG-WARN][2] +11 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-apl3/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-apl2/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs.html #### Warnings #### * igt@kms_ccs@pipe-a-bad-rotation-90-yf_tiled_ccs: - shard-snb: [SKIP][3] ([fdo#109271]) -> [ABORT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-snb2/igt@kms_ccs@pipe-a-bad-rotation-90-yf_tiled_ccs.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-snb6/igt@kms_ccs@pipe-a-bad-rotation-90-yf_tiled_ccs.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@gem_exec_balancer@noheartbeat: - {shard-dg1}: NOTRUN -> [SKIP][5] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-dg1-19/igt@gem_exec_balancer@noheartbeat.html Known issues ------------ Here are the changes found in Patchwork_118596v1_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][6] -> [FAIL][7] ([i915#2846]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-glk3/igt@gem_exec_fair@basic-deadline.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-glk6/igt@gem_exec_fair@basic-deadline.html * igt@gem_lmem_swapping@parallel-random-engines: - shard-glk: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-glk5/igt@gem_lmem_swapping@parallel-random-engines.html * igt@gem_pwrite@basic-exhaustion: - shard-glk: NOTRUN -> [WARN][9] ([i915#2658]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-glk5/igt@gem_pwrite@basic-exhaustion.html * igt@gem_spin_batch@spin-each: - shard-apl: [PASS][10] -> [FAIL][11] ([i915#2898]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-apl6/igt@gem_spin_batch@spin-each.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-apl3/igt@gem_spin_batch@spin-each.html * igt@gem_userptr_blits@vma-merge: - shard-glk: NOTRUN -> [FAIL][12] ([i915#3318]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-glk5/igt@gem_userptr_blits@vma-merge.html * igt@kms_atomic@plane-invalid-params: - shard-snb: [PASS][13] -> [SKIP][14] ([fdo#109271]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-snb6/igt@kms_atomic@plane-invalid-params.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-snb2/igt@kms_atomic@plane-invalid-params.html * igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs: - shard-snb: NOTRUN -> [SKIP][15] ([fdo#109271]) +19 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-snb4/igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs.html * igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc: - shard-glk: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3886]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-glk1/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html * igt@kms_content_protection@lic: - shard-glk: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4579]) +8 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-glk5/igt@kms_content_protection@lic.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-apl: [PASS][18] -> [FAIL][19] ([i915#2346]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-glk: NOTRUN -> [FAIL][20] ([i915#4767]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-glk1/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt: - shard-glk: NOTRUN -> [SKIP][21] ([fdo#109271]) +116 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-glk3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html * igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-vga-1: - shard-snb: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#4579]) +9 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-snb7/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-vga-1.html * igt@kms_psr2_sf@overlay-plane-update-continuous-sf: - shard-glk: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#658]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-glk5/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html * igt@kms_setmode@basic@pipe-a-hdmi-a-1: - shard-snb: NOTRUN -> [FAIL][24] ([i915#5465]) +1 similar issue [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-snb1/igt@kms_setmode@basic@pipe-a-hdmi-a-1.html * igt@perf_pmu@module-unload: - shard-apl: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-apl3/igt@perf_pmu@module-unload.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-apl2/igt@perf_pmu@module-unload.html #### Possible fixes #### * igt@gem_ctx_exec@basic-nohangcheck: - {shard-tglu}: [FAIL][27] ([i915#6268]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-tglu-9/igt@gem_ctx_exec@basic-nohangcheck.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-tglu-8/igt@gem_ctx_exec@basic-nohangcheck.html * igt@gen9_exec_parse@allowed-single: - shard-glk: [ABORT][29] ([i915#5566]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-glk2/igt@gen9_exec_parse@allowed-single.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-glk5/igt@gen9_exec_parse@allowed-single.html * igt@i915_pm_rc6_residency@rc6-idle@rcs0: - {shard-dg1}: [FAIL][31] ([i915#3591]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html * igt@i915_pm_rpm@dpms-non-lpsp: - {shard-rkl}: [SKIP][33] ([i915#1397]) -> [PASS][34] +2 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-rkl-7/igt@i915_pm_rpm@dpms-non-lpsp.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-rkl-6/igt@i915_pm_rpm@dpms-non-lpsp.html * igt@i915_suspend@basic-s3-without-i915: - shard-glk: [INCOMPLETE][35] ([i915#4817]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-glk7/igt@i915_suspend@basic-s3-without-i915.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-glk3/igt@i915_suspend@basic-s3-without-i915.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip: - {shard-rkl}: [FAIL][37] ([i915#3743]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-rkl-7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-rkl-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html #### Warnings #### * igt@kms_hdmi_inject@inject-audio: - shard-snb: [SKIP][39] ([fdo#109271]) -> [FAIL][40] ([IGT#3]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13207/shard-snb6/igt@kms_hdmi_inject@inject-audio.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/shard-snb2/igt@kms_hdmi_inject@inject-audio.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 [i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681 [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705 [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846 [i915#2898]: https://gitlab.freedesktop.org/drm/intel/issues/2898 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742 [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743 [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565 [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767 [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771 [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 [i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816 [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817 [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833 [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852 [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860 [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880 [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881 [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 [i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465 [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566 [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268 [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461 [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561 [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711 [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975 [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213 [i915#8304]: https://gitlab.freedesktop.org/drm/intel/issues/8304 [i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411 [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414 [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555 Build changes ------------- * Linux: CI_DRM_13207 -> Patchwork_118596v1 CI-20190529: 20190529 CI_DRM_13207: e4b4b268de5e5b01c28b3d24b43453eaec2da37e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7314: ab70dfcdecf93a17fcaddb774855f726325fa0dd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_118596v1: e4b4b268de5e5b01c28b3d24b43453eaec2da37e @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118596v1/index.html [-- Attachment #2: Type: text/html, Size: 13500 bytes --] ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE 2023-05-30 18:55 [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE Anusha Srivatsa ` (8 preceding siblings ...) 2023-06-02 4:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork @ 2023-06-05 15:19 ` Jani Nikula 9 siblings, 0 replies; 16+ messages in thread From: Jani Nikula @ 2023-06-05 15:19 UTC (permalink / raw) To: Anusha Srivatsa, intel-gfx On Tue, 30 May 2023, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote: > Replace all occurences of ADL -> ALDERLAKE in > platform and subplatform defines. This way there is a > consistent pattern to how platforms are referred. While > the change is minor and could be combined to have lesser patches, > splitting to per subpaltform for easier cherrypicks, if needed. Cc: Joonas, Tvrtko Commented on a couple of patches. I'm not necessarily opposed to switching from acronyms to full names, but this series alone does not improve consistency. Quite the opposite actually. It's a lot of churn to rename everything. Do we really want that? BR, Jani. > > Anusha Srivatsa (5): > drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step > drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines > drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines > drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines > drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines > > drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++-- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- > drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++---- > .../gpu/drm/i915/display/skl_universal_plane.c | 4 ++-- > drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 2 +- > drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +- > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +- > drivers/gpu/drm/i915/i915_drv.h | 16 ++++++++-------- > drivers/gpu/drm/i915/intel_device_info.c | 2 +- > drivers/gpu/drm/i915/intel_step.c | 6 +++--- > 10 files changed, 24 insertions(+), 24 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2023-06-05 20:40 UTC | newest] Thread overview: 16+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-05-30 18:55 [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE Anusha Srivatsa 2023-05-30 18:55 ` [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step Anusha Srivatsa 2023-06-05 15:13 ` Jani Nikula 2023-06-05 18:20 ` Srivatsa, Anusha 2023-06-05 18:29 ` Jani Nikula 2023-06-05 20:40 ` Srivatsa, Anusha 2023-05-30 18:55 ` [Intel-gfx] [PATCH 2/5] drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines Anusha Srivatsa 2023-06-05 15:16 ` Jani Nikula 2023-05-30 18:55 ` [Intel-gfx] [PATCH 3/5] drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines Anusha Srivatsa 2023-05-30 18:55 ` [Intel-gfx] [PATCH 4/5] drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines Anusha Srivatsa 2023-05-30 18:55 ` [Intel-gfx] [PATCH 5/5] drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines Anusha Srivatsa 2023-05-31 16:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for s/ADL/ALDERLAKE Patchwork 2023-05-31 16:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2023-05-31 16:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2023-06-02 4:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2023-06-05 15:19 ` [Intel-gfx] [PATCH 0/5] s/ADL/ALDERLAKE Jani Nikula
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