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From: Thomas Gleixner <tglx@kernel.org>
To: Andrew Jones <andrew.jones@oss.qualcomm.com>,
	linux-riscv@lists.infradead.org, iommu@lists.linux.dev
Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev,
	tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com,
	joro@8bytes.org, will@kernel.org, robin.murphy@arm.com,
	pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org,
	kevin.tian@intel.com, fangyu.yu@linux.alibaba.com
Subject: Re: [PATCH v6 11/16] irqchip/riscv-imsic: Support IOMMU MSI address lists
Date: Thu, 15 Oct 2026 23:32:26 +0200	[thread overview]
Message-ID: <87y0byd505.ffs@fw13> (raw)
In-Reply-To: <20260925151659.419512-12-andrew.jones@oss.qualcomm.com>

On Fri, Sep 25 2026 at 17:16, Andrew Jones wrote:
> RISC-V IOMMU host interrupt remapping maps every possible host IMSIC
> target into one contiguous IOVA range. MSI message composition therefore
> needs each target's position within that range.
>
> Prepare the complete IMSIC address list while allocating an IRQ. The
> list is guaranteed to exist after IMSIC state initialization. The IOMMU
> backend maps the pages and caches the contiguous base IOVA in the MSI
> descriptor when translation is needed.
>
> When the descriptor has an IOMMU MSI mapping, use the selected logical
> CPU directly as the page index within the IOVA range. Use the same path
> for initial composition and affinity updates. A zero iommu_msi_shift
> means no MSI address translation is required, so keep physical messages.
>
> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> Tested-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>

Acked-by: Thomas Gleixner <tglx@kernel.org>

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linux-riscv mailing list
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WARNING: multiple messages have this Message-ID (diff)
From: Thomas Gleixner <tglx@kernel.org>
To: Andrew Jones <andrew.jones@oss.qualcomm.com>,
	linux-riscv@lists.infradead.org, iommu@lists.linux.dev
Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev,
	tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com,
	joro@8bytes.org, will@kernel.org, robin.murphy@arm.com,
	pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org,
	kevin.tian@intel.com, fangyu.yu@linux.alibaba.com
Subject: Re: [PATCH v6 11/16] irqchip/riscv-imsic: Support IOMMU MSI address lists
Date: Thu, 15 Oct 2026 23:32:26 +0200	[thread overview]
Message-ID: <87y0byd505.ffs@fw13> (raw)
In-Reply-To: <20260925151659.419512-12-andrew.jones@oss.qualcomm.com>

On Fri, Sep 25 2026 at 17:16, Andrew Jones wrote:
> RISC-V IOMMU host interrupt remapping maps every possible host IMSIC
> target into one contiguous IOVA range. MSI message composition therefore
> needs each target's position within that range.
>
> Prepare the complete IMSIC address list while allocating an IRQ. The
> list is guaranteed to exist after IMSIC state initialization. The IOMMU
> backend maps the pages and caches the contiguous base IOVA in the MSI
> descriptor when translation is needed.
>
> When the descriptor has an IOMMU MSI mapping, use the selected logical
> CPU directly as the page index within the IOVA range. Use the same path
> for initial composition and affinity updates. A zero iommu_msi_shift
> means no MSI address translation is required, so keep physical messages.
>
> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> Tested-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>

Acked-by: Thomas Gleixner <tglx@kernel.org>

  parent reply	other threads:[~2026-10-15 21:32 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-25 15:16 [PATCH v6 00/16] iommu/riscv: Enable MSI remapping, IOMMU_DMA and VFIO Andrew Jones
2026-09-25 15:16 ` Andrew Jones
2026-09-25 15:16 ` [PATCH v6 01/16] iommu/dma: Prepare MSI physical address lists Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-10-02 16:21   ` Robin Murphy
2026-10-02 16:21     ` Robin Murphy
2026-10-03 12:03     ` Andrew Jones
2026-10-03 12:03       ` Andrew Jones
2026-10-03 12:10       ` Jason Gunthorpe
2026-10-03 12:10         ` Jason Gunthorpe
2026-09-25 15:16 ` [PATCH v6 02/16] iommufd: Convert struct iommufd_sw_msi_maps to a growable bitmap Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-10-15 19:35   ` Jason Gunthorpe
2026-10-15 19:35     ` Jason Gunthorpe
2026-09-25 15:16 ` [PATCH v6 03/16] iommufd: Split software MSI map lookup and allocation Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-25 15:16 ` [PATCH v6 04/16] iommufd: Bound software MSI mappings to the reserved range Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-25 15:16 ` [PATCH v6 05/16] iommufd: Prepare software MSI maps for address lists Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-25 15:16 ` [PATCH v6 06/16] iommufd: Install software MSI map ranges atomically Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-25 15:16 ` [PATCH v6 07/16] iommufd: Prepare software MSI installation for address lists Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-28 10:23   ` Andrew Jones
2026-09-28 10:23     ` Andrew Jones
2026-09-25 15:16 ` [PATCH v6 08/16] iommu/dma: Introduce iommu_dma_prepare_msi_list() Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-25 15:16 ` [PATCH v6 09/16] iommu/riscv: Reserve an MSI IOVA window for iommufd Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-10-15 19:35   ` Jason Gunthorpe
2026-10-15 19:35     ` Jason Gunthorpe
2026-10-15 19:51     ` Nicolin Chen
2026-10-15 19:51       ` Nicolin Chen
2026-09-25 15:16 ` [PATCH v6 10/16] irqchip/riscv-imsic: Add MSI address list Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-25 15:51   ` Anup Patel
2026-09-25 15:51     ` Anup Patel
2026-10-15 21:33     ` Thomas Gleixner
2026-10-15 21:33       ` Thomas Gleixner
2026-09-28  3:27   ` Nutty.Liu
2026-09-28  3:27     ` Nutty.Liu
2026-09-28 10:20   ` Andrew Jones
2026-09-28 10:20     ` Andrew Jones
2026-10-15 21:32   ` Thomas Gleixner
2026-10-15 21:32     ` Thomas Gleixner
2026-09-25 15:16 ` [PATCH v6 11/16] irqchip/riscv-imsic: Support IOMMU MSI address lists Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-25 15:52   ` Anup Patel
2026-09-25 15:52     ` Anup Patel
2026-09-28  3:18   ` Nutty.Liu
2026-09-28  3:18     ` Nutty.Liu
2026-10-15 21:32   ` Thomas Gleixner [this message]
2026-10-15 21:32     ` Thomas Gleixner
2026-09-25 15:16 ` [PATCH v6 12/16] iommu/dma: Enable IOMMU_DMA for 64-bit RISC-V Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-28  3:17   ` Nutty.Liu
2026-09-28  3:17     ` Nutty.Liu
2026-09-25 15:16 ` [PATCH v6 13/16] vfio: enable IOMMU_TYPE1 for RISC-V Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-25 15:16 ` [PATCH v6 14/16] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-25 15:51   ` Anup Patel
2026-09-25 15:51     ` Anup Patel
2026-09-25 15:16 ` [PATCH v6 15/16] riscv: defconfig: Enable IOMMUFD and VFIO Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-28  3:17   ` Nutty.Liu
2026-09-28  3:17     ` Nutty.Liu
2026-09-25 15:16 ` [PATCH v6 16/16] selftests/vfio: Allow building on RISC-V Andrew Jones
2026-09-25 15:16   ` Andrew Jones
2026-09-28  3:16   ` Nutty.Liu
2026-09-28  3:16     ` Nutty.Liu
2026-09-28 10:24 ` [PATCH v6 00/16] iommu/riscv: Enable MSI remapping, IOMMU_DMA and VFIO Andrew Jones
2026-09-28 10:24   ` Andrew Jones
2026-10-15 19:35 ` Jason Gunthorpe
2026-10-15 19:35   ` Jason Gunthorpe

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