From: "Alex Bennée" <alex.bennee@linaro.org>
To: Mark Rutland <mark.rutland@arm.com>
Cc: kvm@vger.kernel.org, marc.zyngier@arm.com,
andre.przywara@arm.com, qemu-devel@nongnu.org,
qemu-arm@nongnu.org, pbonzini@redhat.com,
kvmarm@lists.cs.columbia.edu
Subject: Re: [kvm-unit-tests PATCH v2 03/10] arm/arm64: smp: support more than 8 cpus
Date: Mon, 06 Jun 2016 18:28:57 +0100 [thread overview]
Message-ID: <87ziqygrae.fsf@linaro.org> (raw)
In-Reply-To: <20160606163238.GB23505@leverpostej>
Mark Rutland <mark.rutland@arm.com> writes:
> On Mon, Jun 06, 2016 at 05:22:49PM +0100, Alex Bennée wrote:
>> Andrew Jones <drjones@redhat.com> writes:
>> > +#define MPIDR_LEVEL_SHIFT(level) \
>> > + (((1 << level) >> 1) << 3)
>> > +#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
>> > + ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & 0xff)
>>
>> Doesn't Aff3 break this little macro? It sits at 32:39 with a gap for
>> MT, RES0, U, RES1 for bits 25:31
>
> It works, it's just a little bit magic:
Ahh the magic was too subtle for my eyes, perhaps a comment for the
wary.
>
> (gdb) p (((1 << 0) >> 1) << 3)
> $1 = 0
> (gdb) p (((1 << 1) >> 1) << 3)
> $2 = 8
> (gdb) p (((1 << 2) >> 1) << 3)
> $3 = 16
> (gdb) p (((1 << 3) >> 1) << 3)
> $4 = 32
> (gdb)
>
> We do the same in arch/arm64/include/asm/cputype.h since b058450f38c337d1
> ("arm64: kernel: add MPIDR_EL1 accessors macros").
I see the truth of it ;-)
>
> Thanks,
> Mark.
--
Alex Bennée
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WARNING: multiple messages have this Message-ID (diff)
From: "Alex Bennée" <alex.bennee@linaro.org>
To: Mark Rutland <mark.rutland@arm.com>
Cc: Andrew Jones <drjones@redhat.com>,
kvm@vger.kernel.org, marc.zyngier@arm.com,
andre.przywara@arm.com, qemu-devel@nongnu.org,
qemu-arm@nongnu.org, pbonzini@redhat.com,
kvmarm@lists.cs.columbia.edu
Subject: Re: [kvm-unit-tests PATCH v2 03/10] arm/arm64: smp: support more than 8 cpus
Date: Mon, 06 Jun 2016 18:28:57 +0100 [thread overview]
Message-ID: <87ziqygrae.fsf@linaro.org> (raw)
In-Reply-To: <20160606163238.GB23505@leverpostej>
Mark Rutland <mark.rutland@arm.com> writes:
> On Mon, Jun 06, 2016 at 05:22:49PM +0100, Alex Bennée wrote:
>> Andrew Jones <drjones@redhat.com> writes:
>> > +#define MPIDR_LEVEL_SHIFT(level) \
>> > + (((1 << level) >> 1) << 3)
>> > +#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
>> > + ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & 0xff)
>>
>> Doesn't Aff3 break this little macro? It sits at 32:39 with a gap for
>> MT, RES0, U, RES1 for bits 25:31
>
> It works, it's just a little bit magic:
Ahh the magic was too subtle for my eyes, perhaps a comment for the
wary.
>
> (gdb) p (((1 << 0) >> 1) << 3)
> $1 = 0
> (gdb) p (((1 << 1) >> 1) << 3)
> $2 = 8
> (gdb) p (((1 << 2) >> 1) << 3)
> $3 = 16
> (gdb) p (((1 << 3) >> 1) << 3)
> $4 = 32
> (gdb)
>
> We do the same in arch/arm64/include/asm/cputype.h since b058450f38c337d1
> ("arm64: kernel: add MPIDR_EL1 accessors macros").
I see the truth of it ;-)
>
> Thanks,
> Mark.
--
Alex Bennée
WARNING: multiple messages have this Message-ID (diff)
From: "Alex Bennée" <alex.bennee@linaro.org>
To: Mark Rutland <mark.rutland@arm.com>
Cc: Andrew Jones <drjones@redhat.com>,
kvm@vger.kernel.org, marc.zyngier@arm.com,
andre.przywara@arm.com, qemu-devel@nongnu.org,
qemu-arm@nongnu.org, pbonzini@redhat.com,
kvmarm@lists.cs.columbia.edu
Subject: Re: [Qemu-devel] [kvm-unit-tests PATCH v2 03/10] arm/arm64: smp: support more than 8 cpus
Date: Mon, 06 Jun 2016 18:28:57 +0100 [thread overview]
Message-ID: <87ziqygrae.fsf@linaro.org> (raw)
In-Reply-To: <20160606163238.GB23505@leverpostej>
Mark Rutland <mark.rutland@arm.com> writes:
> On Mon, Jun 06, 2016 at 05:22:49PM +0100, Alex Bennée wrote:
>> Andrew Jones <drjones@redhat.com> writes:
>> > +#define MPIDR_LEVEL_SHIFT(level) \
>> > + (((1 << level) >> 1) << 3)
>> > +#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
>> > + ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & 0xff)
>>
>> Doesn't Aff3 break this little macro? It sits at 32:39 with a gap for
>> MT, RES0, U, RES1 for bits 25:31
>
> It works, it's just a little bit magic:
Ahh the magic was too subtle for my eyes, perhaps a comment for the
wary.
>
> (gdb) p (((1 << 0) >> 1) << 3)
> $1 = 0
> (gdb) p (((1 << 1) >> 1) << 3)
> $2 = 8
> (gdb) p (((1 << 2) >> 1) << 3)
> $3 = 16
> (gdb) p (((1 << 3) >> 1) << 3)
> $4 = 32
> (gdb)
>
> We do the same in arch/arm64/include/asm/cputype.h since b058450f38c337d1
> ("arm64: kernel: add MPIDR_EL1 accessors macros").
I see the truth of it ;-)
>
> Thanks,
> Mark.
--
Alex Bennée
next prev parent reply other threads:[~2016-06-06 17:24 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-04 18:15 [kvm-unit-tests PATCH v2 00/10] arm/arm64: add gic framework Andrew Jones
2016-06-04 18:15 ` [Qemu-devel] " Andrew Jones
2016-06-04 18:15 ` Andrew Jones
2016-06-04 18:15 ` [kvm-unit-tests PATCH v2 01/10] lib: xstr: allow multiple args Andrew Jones
2016-06-04 18:15 ` [Qemu-devel] " Andrew Jones
2016-06-06 10:49 ` Alex Bennée
2016-06-06 10:49 ` [Qemu-devel] " Alex Bennée
2016-06-06 12:12 ` Andrew Jones
2016-06-06 12:12 ` [Qemu-devel] " Andrew Jones
2016-06-06 14:52 ` Alex Bennée
2016-06-06 14:52 ` [Qemu-devel] " Alex Bennée
2016-06-04 18:15 ` [kvm-unit-tests PATCH v2 02/10] arm64: fix get_"sysreg32" and make MPIDR 64bit Andrew Jones
2016-06-04 18:15 ` [Qemu-devel] " Andrew Jones
2016-06-04 18:15 ` Andrew Jones
2016-06-06 12:47 ` Alex Bennée
2016-06-06 12:47 ` [Qemu-devel] " Alex Bennée
2016-06-04 18:15 ` [kvm-unit-tests PATCH v2 03/10] arm/arm64: smp: support more than 8 cpus Andrew Jones
2016-06-04 18:15 ` [Qemu-devel] " Andrew Jones
2016-06-04 18:15 ` Andrew Jones
2016-06-06 16:22 ` Alex Bennée
2016-06-06 16:22 ` [Qemu-devel] " Alex Bennée
2016-06-06 16:31 ` Andrew Jones
2016-06-06 16:31 ` [Qemu-devel] " Andrew Jones
2016-06-06 17:32 ` Alex Bennée
2016-06-06 17:32 ` [Qemu-devel] " Alex Bennée
2016-06-06 16:32 ` Mark Rutland
2016-06-06 16:32 ` [Qemu-devel] " Mark Rutland
2016-06-06 16:32 ` Mark Rutland
2016-06-06 17:28 ` Alex Bennée [this message]
2016-06-06 17:28 ` [Qemu-devel] " Alex Bennée
2016-06-06 17:28 ` Alex Bennée
2016-06-04 18:15 ` [kvm-unit-tests PATCH v2 04/10] arm/arm64: add some delay routines Andrew Jones
2016-06-04 18:15 ` [Qemu-devel] " Andrew Jones
2016-06-04 18:15 ` Andrew Jones
2016-06-06 17:39 ` Alex Bennée
2016-06-06 17:39 ` [Qemu-devel] " Alex Bennée
2016-06-06 17:39 ` Alex Bennée
2016-06-06 17:48 ` Andrew Jones
2016-06-06 17:48 ` [Qemu-devel] " Andrew Jones
2016-06-04 18:16 ` [kvm-unit-tests PATCH v2 05/10] arm/arm64: irq enable/disable Andrew Jones
2016-06-04 18:16 ` [Qemu-devel] " Andrew Jones
2016-06-07 16:22 ` Alex Bennée
2016-06-07 16:22 ` [Qemu-devel] " Alex Bennée
2016-06-07 16:22 ` Alex Bennée
2016-06-04 18:16 ` [kvm-unit-tests PATCH v2 06/10] arm/arm64: add initial gicv2 support Andrew Jones
2016-06-04 18:16 ` [Qemu-devel] " Andrew Jones
2016-06-04 18:16 ` [kvm-unit-tests PATCH v2 07/10] arm/arm64: add initial gicv3 support Andrew Jones
2016-06-04 18:16 ` [Qemu-devel] " Andrew Jones
2016-06-04 18:16 ` Andrew Jones
2016-06-04 18:16 ` [kvm-unit-tests PATCH v2 08/10] arm/arm64: gicv2: add an IPI test Andrew Jones
2016-06-04 18:16 ` [Qemu-devel] " Andrew Jones
2016-06-04 18:16 ` Andrew Jones
2016-06-04 18:16 ` [kvm-unit-tests PATCH v2 09/10] arm/arm64: gicv3: " Andrew Jones
2016-06-04 18:16 ` [Qemu-devel] " Andrew Jones
2016-06-04 18:16 ` [kvm-unit-tests PATCH v2 10/10] arm/arm64: gic: don't just use zero Andrew Jones
2016-06-04 18:16 ` [Qemu-devel] " Andrew Jones
2016-06-04 18:45 ` [kvm-unit-tests PATCH v2 00/10] arm/arm64: add gic framework Alex Bennée
2016-06-04 18:45 ` [Qemu-devel] " Alex Bennée
2016-06-07 17:13 ` Alex Bennée
2016-06-07 17:13 ` [Qemu-devel] " Alex Bennée
2016-06-08 10:00 ` Andrew Jones
2016-06-08 10:00 ` Andrew Jones
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