Re: [PATCH v3 5/5] tests/intel/xe_exec_reset: Add long-spin-comp-reuse-many-preempt-threads

["K V P, Satyanarayana" <satyanarayana.k.v.p@intel.com>]

On 06-10-2025 14:47, Matthew Brost wrote:
> On Wed, Oct 01, 2025 at 05:16:19PM +0530, K V P, Satyanarayana wrote:
>>
>>
>> On 24-09-2025 02:43, Matthew Brost wrote:
>>> Add long-spin-comp-reuse-many-preempt-threads which verifies compressed
>>> memory can be used during this test. Useful to test VF migration.
>>>
>>> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>>> ---
>>>    lib/xe/xe_legacy.c          | 38 +++++++++++++++++++++++++++++--------
>>>    tests/intel/xe_exec_reset.c |  8 ++++++++
>>>    2 files changed, 38 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/lib/xe/xe_legacy.c b/lib/xe/xe_legacy.c
>>> index cb53a8cfc8..74432a4b3a 100644
>>> --- a/lib/xe/xe_legacy.c
>>> +++ b/lib/xe/xe_legacy.c
>>> @@ -9,9 +9,11 @@
>>>    #include "xe/xe_ioctl.h"
>>>    #include "xe/xe_legacy.h"
>>>    #include "xe/xe_spin.h"
>>> +#include "intel_pat.h"
>>>    /* Batch buffer element count, in number of dwords(u32) */
>>>    #define BATCH_DW_COUNT			16
>>> +#define COMPRESSION			(0x1 << 13)
>>>    #define SYSTEM				(0x1 << 12)
>>>    #define LONG_SPIN_REUSE_QUEUE		(0x1 << 11)
>>>    #define LONG_SPIN			(0x1 << 8)
>>> @@ -72,6 +74,9 @@ xe_legacy_test_mode(int fd, struct drm_xe_engine_class_instance *eci,
>>>    	igt_assert_lte(n_exec_queues, MAX_N_EXECQUEUES);
>>> +	if (flags & COMPRESSION)
>>> +		igt_require(intel_gen(intel_get_drm_devid(fd)) >= 20);
>>> +
>>>    	if (flags & CLOSE_FD)
>>>    		fd = drm_open_driver(DRIVER_XE);
>>> @@ -79,11 +84,20 @@ xe_legacy_test_mode(int fd, struct drm_xe_engine_class_instance *eci,
>>>    	bo_size = sizeof(*data) * (n_execs + extra_execs);
>>>    	bo_size = xe_bb_size(fd, bo_size);
>>> -	bo = xe_bo_create(fd, vm, bo_size,
>>> -			  flags & SYSTEM ?
>>> -			  system_memory(fd) :
>>> -			  vram_if_possible(fd, eci->gt_id),
>>> -			  DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>>> +	if (flags & COMPRESSION) {
>>> +		bo = xe_bo_create_caching(fd, vm, bo_size,
>>> +					  flags & SYSTEM ?
>>> +					  system_memory(fd) :
>>> +					  vram_if_possible(fd, eci->gt_id),
>>> +					  DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
>> This limits BO creation for VRAM right. So, the compression case will not
>> work for IGPU?
> 
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM gets squashed in
> ___xe_bo_create if placement is system:
> 
> 382         /*
> 383          * In case vram_if_possible returned system_memory,
> 384          * visible VRAM cannot be requested through flags
> 385          */
> 386         if (!vram_selected(fd, placement))
> 387                 create.flags &= ~DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
> 
> So this test works on dGPU and iGPU. I've verfied this test on BMG /
> PTL.
> 
> Matt
> 
>> -Satya.> +					  DRM_XE_GEM_CPU_CACHING_WC);
>>> +	} else {
>>> +		bo = xe_bo_create(fd, vm, bo_size,
>>> +				  flags & SYSTEM ?
>>> +				  system_memory(fd) :
>>> +				  vram_if_possible(fd, eci->gt_id),
>>> +				  DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>>> +	}
>>>    	data = xe_bo_map(fd, bo, bo_size);
>>>    	for (i = 0; i < n_exec_queues; i++) {
>>> @@ -94,7 +108,14 @@ xe_legacy_test_mode(int fd, struct drm_xe_engine_class_instance *eci,
>>>    	sync[0].handle = syncobj_create(fd, 0);
>>>    	/* Binding mechanism based on use_capture_mode */
>>> -	if (use_capture_mode) {
>>> +	if (flags & COMPRESSION) {
>>> +		int ret;
>>> +
>>> +		ret = __xe_vm_bind(fd, vm, 0, bo, 0, addr, bo_size,
>>> +				   DRM_XE_VM_BIND_OP_MAP, 0, sync, 1, 0,
>>> +				   intel_get_pat_idx_uc_comp(fd), 0);
>>> +		igt_assert(!ret);
>>> +	} else if (use_capture_mode) {
>>>    		__xe_vm_bind_assert(fd, vm, 0, bo, 0, addr, bo_size,
>>>    				    DRM_XE_VM_BIND_OP_MAP, flags, sync, 1, 0, 0);
>>>    	} else {
>>> @@ -141,7 +162,8 @@ xe_legacy_test_mode(int fd, struct drm_xe_engine_class_instance *eci,
>>>    		xe_exec(fd, &exec);
>>> -		if (!i && !(flags & CAT_ERROR) && !use_capture_mode)
>>> +		if (!i && !(flags & CAT_ERROR) && !use_capture_mode &&
>>> +		    !(flags & COMPRESSION))
>>>    			xe_spin_wait_started(&data[i].spin);
>>>    	}
>>> @@ -202,7 +224,7 @@ xe_legacy_test_mode(int fd, struct drm_xe_engine_class_instance *eci,
>>>    	xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
>>>    	igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
>>> -	if (!use_capture_mode && !(flags & (GT_RESET | CANCEL))) {
>>> +	if (!use_capture_mode && !(flags & (GT_RESET | CANCEL | COMPRESSION))) {
>>>    		for (i = flags & LONG_SPIN ? n_exec_queues : 1;
>>>    		     i < n_execs + extra_execs; i++)
>>>    			igt_assert_eq(data[i].data, 0xc0ffee);
>>> diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c
>>> index 113ceb2178..f5db1ff8ba 100644
>>> --- a/tests/intel/xe_exec_reset.c
>>> +++ b/tests/intel/xe_exec_reset.c
>>> @@ -123,6 +123,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci,
>>>    #define GT1				(0x1 << 10)
>>>    #define LONG_SPIN_REUSE_QUEUE		(0x1 << 11)
>>>    #define SYSTEM				(0x1 << 12)
>>> +#define COMPRESSION			(0x1 << 13)
>>>    /**
>>>     * SUBTEST: %s-cat-error
>>> @@ -702,6 +703,9 @@ static void *thread(void *data)
>>>     * SUBTEST: long-spin-sys-reuse-many-preempt-threads
>>>     * Description: Test long spinners with many preemptable jobs on each engine instance with a thread, use queues again spinners complete, both GTs, use system memory
>>>     *
>>> + * SUBTEST: long-spin-comp-reuse-many-preempt-threads
>>> + * Description: Test long spinners with many preemptable jobs on each engine instance with a thread, use queues again spinners complete, both GTs, use compressed memory
>>> + *
>>>     * SUBTEST: long-spin-reuse-many-preempt-gt0-threads
>>>     * Description: Test long spinners with many preemptable jobs on each engine instance with a thread, use queues again spinners complete, primary GT
>>>     *
>>> @@ -878,6 +882,10 @@ igt_main
>>>    		threads(fd, 2, 16, SYSTEM | LONG_SPIN | PREEMPT |
>>>    			LONG_SPIN_REUSE_QUEUE);
>>> +	igt_subtest("long-spin-comp-reuse-many-preempt-threads")
>>> +		threads(fd, 2, 16, COMPRESSION | LONG_SPIN | PREEMPT |
>>> +			LONG_SPIN_REUSE_QUEUE);
>>> +
>>>    	igt_subtest("long-spin-reuse-many-preempt-gt0-threads")
>>>    		threads(fd, 2, 16, LONG_SPIN | PREEMPT | GT0 |
>>>    			LONG_SPIN_REUSE_QUEUE);
>>
LGTM.
Reviewed-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>