From: "Bernatowicz, Marcin" <marcin.bernatowicz@linux.intel.com>
To: Matthew Brost <matthew.brost@intel.com>, igt-dev@lists.freedesktop.org
Subject: Re: [PATCH v3 2/5] tests/intel/xe_exec_reset: Add timeslice preempt test
Date: Tue, 30 Sep 2025 15:10:11 +0200 [thread overview]
Message-ID: <c1dd9b99-c071-408c-8248-c112e28b49b3@linux.intel.com> (raw)
In-Reply-To: <20250923211333.766147-3-matthew.brost@intel.com>
On 9/23/2025 11:13 PM, Matthew Brost wrote:
> Add tests in which submit multiple preemptable spinners to same hardware
> engine ensuring a cumulative longer timeout and validating the restart
> paths in the DRM scheduler TDR (Timeout Detection and Recovery).
>
> v3:
> - Spell out TDR (Kamal)
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
> lib/xe/xe_legacy.c | 5 +++--
> tests/intel/xe_exec_reset.c | 25 +++++++++++++++++++++++--
> 2 files changed, 26 insertions(+), 4 deletions(-)
>
> diff --git a/lib/xe/xe_legacy.c b/lib/xe/xe_legacy.c
> index 669ecff7aa..9d2da7f413 100644
> --- a/lib/xe/xe_legacy.c
> +++ b/lib/xe/xe_legacy.c
> @@ -12,6 +12,7 @@
>
> /* Batch buffer element count, in number of dwords(u32) */
> #define BATCH_DW_COUNT 16
> +#define CANCEL (0x1 << 7)
> #define PREEMPT (0x1 << 6)
> #define CAT_ERROR (0x1 << 5)
> #define CLOSE_EXEC_QUEUES (0x1 << 2)
> @@ -100,7 +101,7 @@ xe_legacy_test_mode(int fd, struct drm_xe_engine_class_instance *eci,
> u64 exec_addr;
> int e = i % n_exec_queues;
>
> - if (!i) {
> + if (!i || flags & CANCEL) {
> spin_opts.addr = base_addr + spin_offset;
> xe_spin_init(&data[i].spin, &spin_opts);
> exec_addr = spin_opts.addr;
> @@ -155,7 +156,7 @@ xe_legacy_test_mode(int fd, struct drm_xe_engine_class_instance *eci,
> xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
> igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
>
> - if (!use_capture_mode && !(flags & GT_RESET)) {
> + if (!use_capture_mode && !(flags & (GT_RESET | CANCEL))) {
> for (i = 1; i < n_execs; i++)
> igt_assert_eq(data[i].data, 0xc0ffee);
> }
> diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c
> index 72b85d3e7b..88e9df6fbb 100644
> --- a/tests/intel/xe_exec_reset.c
> +++ b/tests/intel/xe_exec_reset.c
> @@ -117,6 +117,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci,
> #define PARALLEL (0x1 << 4)
> #define CAT_ERROR (0x1 << 5)
> #define PREEMPT (0x1 << 6)
> +#define CANCEL (0x1 << 7)
>
> /**
> * SUBTEST: %s-cat-error
> @@ -302,6 +303,12 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs,
> * SUBTEST: cancel-preempt
> * Description: Test job cancel with a preemptable job
> *
> + * SUBTEST: cancel-timeslice-preempt
> + * Description: Test job cancel with 2 preemptable jobs
> + *
> + * SUBTEST: cancel-timeslice-many-preempt
> + * Description: Test job cancel with many preemptable jobs
> + *
> * SUBTEST: gt-reset
> * Description: Test GT reset
> *
> @@ -396,7 +403,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci,
> uint64_t exec_addr;
> int e = i % n_exec_queues;
>
> - if (!i) {
> + if (!i || flags & CANCEL) {
> spin_opts.addr = base_addr + spin_offset;
> xe_spin_init(&data[i].spin, &spin_opts);
> exec_addr = spin_opts.addr;
> @@ -451,7 +458,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci,
> xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
> xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, 3 * NSEC_PER_SEC);
>
> - if (!(flags & GT_RESET)) {
> + if (!(flags & (GT_RESET | CANCEL))) {
> for (i = 1; i < n_execs; i++)
> igt_assert_eq(data[i].data, 0xc0ffee);
> }
> @@ -680,6 +687,20 @@ igt_main
> break;
> }
>
> + igt_subtest("cancel-timeslice-preempt")
> + xe_for_each_engine(fd, hwe) {
> + xe_legacy_test_mode(fd, hwe, 2, 2, CANCEL | PREEMPT,
> + LEGACY_MODE_ADDR, false);
> + break;
> + }
> +
> + igt_subtest("cancel-timeslice-many-preempt")
> + xe_for_each_engine(fd, hwe) {
> + xe_legacy_test_mode(fd, hwe, 4, 4, CANCEL | PREEMPT,
> + LEGACY_MODE_ADDR, false);
> + break;
> + }
> +
LGTM,
Reviewed-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
> igt_subtest("gt-reset")
> xe_for_each_engine(fd, hwe)
> xe_legacy_test_mode(fd, hwe, 2, 2, GT_RESET,
next prev parent reply other threads:[~2025-09-30 13:10 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-23 21:13 [PATCH v3 0/5] Add tests to help verify VF migration Matthew Brost
2025-09-23 21:13 ` [PATCH v3 1/5] tests/intel/xe_exec_reset: Add job cancel tests Matthew Brost
2025-09-30 11:21 ` Bernatowicz, Marcin
2025-09-23 21:13 ` [PATCH v3 2/5] tests/intel/xe_exec_reset: Add timeslice preempt test Matthew Brost
2025-09-30 13:10 ` Bernatowicz, Marcin [this message]
2025-09-23 21:13 ` [PATCH v3 3/5] tests/intel/xe_exec_reset: Long spin tests Matthew Brost
2025-09-30 13:12 ` Bernatowicz, Marcin
2025-09-23 21:13 ` [PATCH v3 4/5] tests/intel/xe_exec_reset: Add long-spin-sys-reuse-many-preempt-threads Matthew Brost
2025-09-30 13:13 ` Bernatowicz, Marcin
2025-09-23 21:13 ` [PATCH v3 5/5] tests/intel/xe_exec_reset: Add long-spin-comp-reuse-many-preempt-threads Matthew Brost
2025-09-30 14:29 ` Bernatowicz, Marcin
2025-10-01 2:24 ` Matthew Brost
2025-10-01 17:41 ` Bernatowicz, Marcin
2025-09-30 17:35 ` Kamil Konieczny
2025-10-01 2:18 ` Matthew Brost
2025-10-01 11:55 ` Kamil Konieczny
2025-10-01 11:46 ` K V P, Satyanarayana
2025-10-06 9:17 ` Matthew Brost
2025-10-06 11:37 ` K V P, Satyanarayana
2025-09-24 1:48 ` ✓ Xe.CI.BAT: success for Add tests to help verify VF migration (rev3) Patchwork
2025-09-24 2:05 ` ✓ i915.CI.BAT: " Patchwork
2025-09-24 6:26 ` ✗ Xe.CI.Full: failure " Patchwork
2025-09-24 16:44 ` ✗ i915.CI.Full: " Patchwork
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