[PATCH v6 00/16] CMTG enablement

[PATCH v6 00/16] CMTG enablement

[Animesh Manna]

Common mode timing generator (CMTG) support is added NVL onwards.
Enable CMTG which will be needed by other fearure like dynamic dc
state enablement later.

Testing ongoing, currently counters are incrementing as expected.

Animesh Manna (13):
  drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG
  drm/i915/cmtg: Set CMTG clock select
  drm/i915/cmtg: Add cmtg transcoder offset in struct _device_info
  drm/i915/cmtg: Set timings for CMTG
  drm/i915/cmtg: Program VRR registers of CMTG
  drm/i915/cmtg: Set transcoder mn for CMTG
  drm/i915/cmtg: Add hook to enable CMTG with sync to port
  drm/i915/cmtg: Add a hook to make eDP transcoder secondary
  drm/i915/cmtg: Split CMTG support check from intel_cmtg_is_allowed()
  drm/i915/cmtg: Add CMTG interrupt handling
  drm/i915/cmtg: Add trigger to enable/disable cmtg
  drm/i915/cmtg: Restore CMTG after DC6 entry
  [NOT FOR REVIEW] debug patch

Dibin Moolakadan Subrahmanian (3):
  drm/i915/cmtg: Modify existing hook to disable CMTG
  drm/i915/cmtg: Add CMTG HWGB programming
  drm/i915/cmtg: Add CMTG scan line programming

 drivers/gpu/drm/i915/display/intel_cmtg.c     | 328 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  15 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  24 +-
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |   5 +
 drivers/gpu/drm/i915/display/intel_display.c  |  35 ++
 .../drm/i915/display/intel_display_device.c   |  14 +
 .../drm/i915/display/intel_display_device.h   |   2 +-
 .../gpu/drm/i915/display/intel_display_irq.c  |  12 +
 .../drm/i915/display/intel_display_limits.h   |   2 +
 .../drm/i915/display/intel_display_power.c    |  25 ++
 .../drm/i915/display/intel_display_power.h    |   3 +
 .../gpu/drm/i915/display/intel_display_regs.h |   6 +
 .../drm/i915/display/intel_display_types.h    |   4 +
 drivers/gpu/drm/i915/display/intel_vrr.c      |   5 +
 14 files changed, 469 insertions(+), 11 deletions(-)

-- 
2.29.0

[PATCH v6 01/16] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG

[Animesh Manna]

CMTG will be enabled only with DC3co, so add a separate function
intel_cmtg_is_allowed() to check the prerequisites for enabling CMTG.
DC3co will be enabled in a separate patch.

v2:
- Remove separate flag for DC3co from crtc_state. [Uma, Dibin]

v3:
- Do not access power domain members directly. [Jani]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c | 15 ++++++++++++++-
 drivers/gpu/drm/i915/display/intel_cmtg.h |  4 ++++
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index e1fdc6fe9762..dc039bea452c 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -4,7 +4,6 @@
  */
 
 #include <linux/string_choices.h>
-#include <linux/types.h>
 
 #include <drm/drm_device.h>
 #include <drm/drm_print.h>
@@ -16,6 +15,7 @@
 #include "intel_display_device.h"
 #include "intel_display_power.h"
 #include "intel_display_regs.h"
+#include "intel_display_types.h"
 
 /**
  * DOC: Common Primary Timing Generator (CMTG)
@@ -185,3 +185,16 @@ void intel_cmtg_sanitize(struct intel_display *display)
 
 	intel_cmtg_disable(display, &cmtg_config);
 }
+
+bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B) &&
+	    DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
+	    intel_display_power_get_current_dc_state(display) == DC_STATE_EN_DC3CO)
+		return true;
+
+	return false;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index ba62199adaa2..ed540581738f 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -6,8 +6,12 @@
 #ifndef __INTEL_CMTG_H__
 #define __INTEL_CMTG_H__
 
+#include <linux/types.h>
+
 struct intel_display;
+struct intel_crtc_state;
 
 void intel_cmtg_sanitize(struct intel_display *display);
+bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_CMTG_H__ */
-- 
2.29.0

Re: [PATCH v6 01/16] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG

[Dibin Moolakadan Subrahmanian]

On 13-05-2026 22:08, Animesh Manna wrote:
> CMTG will be enabled only with DC3co, so add a separate function
> intel_cmtg_is_allowed() to check the prerequisites for enabling CMTG.
> DC3co will be enabled in a separate patch.
>
> v2:
> - Remove separate flag for DC3co from crtc_state. [Uma, Dibin]
>
> v3:
> - Do not access power domain members directly. [Jani]
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_cmtg.c | 15 ++++++++++++++-
>   drivers/gpu/drm/i915/display/intel_cmtg.h |  4 ++++
>   2 files changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index e1fdc6fe9762..dc039bea452c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -4,7 +4,6 @@
>    */
>   
>   #include <linux/string_choices.h>
> -#include <linux/types.h>
>   
>   #include <drm/drm_device.h>
>   #include <drm/drm_print.h>
> @@ -16,6 +15,7 @@
>   #include "intel_display_device.h"
>   #include "intel_display_power.h"
>   #include "intel_display_regs.h"
> +#include "intel_display_types.h"
>   
>   /**
>    * DOC: Common Primary Timing Generator (CMTG)
> @@ -185,3 +185,16 @@ void intel_cmtg_sanitize(struct intel_display *display)
>   
>   	intel_cmtg_disable(display, &cmtg_config);
>   }
> +
> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B) &&
> +	    DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
> +	    intel_display_power_get_current_dc_state(display) == DC_STATE_EN_DC3CO)

I would enable CMTG before setting the DC3CO state, since CMTG running is a must condition for DC3CO.
Doing it the current way creates a cyclic dependency.

> +		return true;
> +
> +	return false;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index ba62199adaa2..ed540581738f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -6,8 +6,12 @@
>   #ifndef __INTEL_CMTG_H__
>   #define __INTEL_CMTG_H__
>   
> +#include <linux/types.h>
> +
>   struct intel_display;
> +struct intel_crtc_state;
>   
>   void intel_cmtg_sanitize(struct intel_display *display);
> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
>   
>   #endif /* __INTEL_CMTG_H__ */

RE: [PATCH v6 01/16] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG

[Manna, Animesh]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Thursday, May 21, 2026 1:49 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>
> Subject: Re: [PATCH v6 01/16] drm/i915/cmtg: Add intel_cmtg_is_allowed()
> for CMTG
> 
> 
> On 13-05-2026 22:08, Animesh Manna wrote:
> > CMTG will be enabled only with DC3co, so add a separate function
> > intel_cmtg_is_allowed() to check the prerequisites for enabling CMTG.
> > DC3co will be enabled in a separate patch.
> >
> > v2:
> > - Remove separate flag for DC3co from crtc_state. [Uma, Dibin]
> >
> > v3:
> > - Do not access power domain members directly. [Jani]
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_cmtg.c | 15 ++++++++++++++-
> >   drivers/gpu/drm/i915/display/intel_cmtg.h |  4 ++++
> >   2 files changed, 18 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > index e1fdc6fe9762..dc039bea452c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > @@ -4,7 +4,6 @@
> >    */
> >
> >   #include <linux/string_choices.h>
> > -#include <linux/types.h>
> >
> >   #include <drm/drm_device.h>
> >   #include <drm/drm_print.h>
> > @@ -16,6 +15,7 @@
> >   #include "intel_display_device.h"
> >   #include "intel_display_power.h"
> >   #include "intel_display_regs.h"
> > +#include "intel_display_types.h"
> >
> >   /**
> >    * DOC: Common Primary Timing Generator (CMTG) @@ -185,3 +185,16
> @@
> > void intel_cmtg_sanitize(struct intel_display *display)
> >
> >   	intel_cmtg_disable(display, &cmtg_config);
> >   }
> > +
> > +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
> > +{
> > +	struct intel_display *display = to_intel_display(crtc_state);
> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +
> > +	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder ==
> TRANSCODER_B) &&
> > +	    DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_EDP) &&
> > +	    intel_display_power_get_current_dc_state(display) ==
> > +DC_STATE_EN_DC3CO)
> 
> I would enable CMTG before setting the DC3CO state, since CMTG running is
> a must condition for DC3CO.
> Doing it the current way creates a cyclic dependency.

Copy -pasting from bspec:
CMTG must be enabled with dynamic DC states.​​​

Dynamic DC state refers to Dc3co/Dc6v.
So added a check for dc-state which will be used inside cmtg functions. Do not want to allow touching CMTG register if target_dc_state is not DC3co.

Again copy-pasting from bspec:
CMTG state needs to be saved and restored during power state transitions.

Which means CMTG will lose its value with DC5/DC6. So want to be little cautious while handling CMTG.

We should finalize what will be the target_dc_state based use case like PSR2/LOBF/PR-ALPM and single EDP configuration.
This is the only flag and based on that CMTG and DC3co will be enabled. So, no cyclic dependency. Good to know if I am missing anything.

Regards,
Animesh

> 
> > +		return true;
> > +
> > +	return false;
> > +}
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > index ba62199adaa2..ed540581738f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > @@ -6,8 +6,12 @@
> >   #ifndef __INTEL_CMTG_H__
> >   #define __INTEL_CMTG_H__
> >
> > +#include <linux/types.h>
> > +
> >   struct intel_display;
> > +struct intel_crtc_state;
> >
> >   void intel_cmtg_sanitize(struct intel_display *display);
> > +bool intel_cmtg_is_allowed(const struct intel_crtc_state
> > +*crtc_state);
> >
> >   #endif /* __INTEL_CMTG_H__ */

Re: [PATCH v6 01/16] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG

[Dibin Moolakadan Subrahmanian]

On 21-05-2026 14:31, Manna, Animesh wrote:
>
>> -----Original Message-----
>> From: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> Sent: Thursday, May 21, 2026 1:49 PM
>> To: Manna, Animesh <animesh.manna@intel.com>; intel-
>> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
>> Cc: Shankar, Uma <uma.shankar@intel.com>; ville.syrjala@linux.intel.com;
>> Nikula, Jani <jani.nikula@intel.com>
>> Subject: Re: [PATCH v6 01/16] drm/i915/cmtg: Add intel_cmtg_is_allowed()
>> for CMTG
>>
>>
>> On 13-05-2026 22:08, Animesh Manna wrote:
>>> CMTG will be enabled only with DC3co, so add a separate function
>>> intel_cmtg_is_allowed() to check the prerequisites for enabling CMTG.
>>> DC3co will be enabled in a separate patch.
>>>
>>> v2:
>>> - Remove separate flag for DC3co from crtc_state. [Uma, Dibin]
>>>
>>> v3:
>>> - Do not access power domain members directly. [Jani]
>>>
>>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/display/intel_cmtg.c | 15 ++++++++++++++-
>>>    drivers/gpu/drm/i915/display/intel_cmtg.h |  4 ++++
>>>    2 files changed, 18 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
>>> b/drivers/gpu/drm/i915/display/intel_cmtg.c
>>> index e1fdc6fe9762..dc039bea452c 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
>>> @@ -4,7 +4,6 @@
>>>     */
>>>
>>>    #include <linux/string_choices.h>
>>> -#include <linux/types.h>
>>>
>>>    #include <drm/drm_device.h>
>>>    #include <drm/drm_print.h>
>>> @@ -16,6 +15,7 @@
>>>    #include "intel_display_device.h"
>>>    #include "intel_display_power.h"
>>>    #include "intel_display_regs.h"
>>> +#include "intel_display_types.h"
>>>
>>>    /**
>>>     * DOC: Common Primary Timing Generator (CMTG) @@ -185,3 +185,16
>> @@
>>> void intel_cmtg_sanitize(struct intel_display *display)
>>>
>>>    	intel_cmtg_disable(display, &cmtg_config);
>>>    }
>>> +
>>> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
>>> +{
>>> +	struct intel_display *display = to_intel_display(crtc_state);
>>> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>>> +
>>> +	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder ==
>> TRANSCODER_B) &&
>>> +	    DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state,
>> INTEL_OUTPUT_EDP) &&
>>> +	    intel_display_power_get_current_dc_state(display) ==
>>> +DC_STATE_EN_DC3CO)
>> I would enable CMTG before setting the DC3CO state, since CMTG running is
>> a must condition for DC3CO.
>> Doing it the current way creates a cyclic dependency.
> Copy -pasting from bspec:
> CMTG must be enabled with dynamic DC states.​​​
>
> Dynamic DC state refers to Dc3co/Dc6v.
> So added a check for dc-state which will be used inside cmtg functions. Do not want to allow touching CMTG register if target_dc_state is not DC3co.
>
> Again copy-pasting from bspec:
> CMTG state needs to be saved and restored during power state transitions.
>
> Which means CMTG will lose its value with DC5/DC6. So want to be little cautious while handling CMTG.

I can see DC6 restore is already handled in patch 15.

target_dc_state is a software state doesn't guarantee any actual DC state register write.

I think its better to leave the target dc state decision to DC3CO implementation
rather than using  it as flag variable for CMTG enable check.

>
> We should finalize what will be the target_dc_state based use case like PSR2/LOBF/PR-ALPM and single EDP configuration.
> This is the only flag and based on that CMTG and DC3co will be enabled. So, no cyclic dependency. Good to know if I am missing anything.
>
> Regards,
> Animesh
>
>>> +		return true;
>>> +
>>> +	return false;
>>> +}
>>> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
>>> b/drivers/gpu/drm/i915/display/intel_cmtg.h
>>> index ba62199adaa2..ed540581738f 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
>>> @@ -6,8 +6,12 @@
>>>    #ifndef __INTEL_CMTG_H__
>>>    #define __INTEL_CMTG_H__
>>>
>>> +#include <linux/types.h>
>>> +
>>>    struct intel_display;
>>> +struct intel_crtc_state;
>>>
>>>    void intel_cmtg_sanitize(struct intel_display *display);
>>> +bool intel_cmtg_is_allowed(const struct intel_crtc_state
>>> +*crtc_state);
>>>
>>>    #endif /* __INTEL_CMTG_H__ */

RE: [PATCH v6 01/16] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG

[Manna, Animesh]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Thursday, May 21, 2026 6:06 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>
> Subject: Re: [PATCH v6 01/16] drm/i915/cmtg: Add intel_cmtg_is_allowed()
> for CMTG
> 
> 
> On 21-05-2026 14:31, Manna, Animesh wrote:
> >
> >> -----Original Message-----
> >> From: Dibin Moolakadan Subrahmanian
> >> <dibin.moolakadan.subrahmanian@intel.com>
> >> Sent: Thursday, May 21, 2026 1:49 PM
> >> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> >> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> >> Cc: Shankar, Uma <uma.shankar@intel.com>;
> >> ville.syrjala@linux.intel.com; Nikula, Jani <jani.nikula@intel.com>
> >> Subject: Re: [PATCH v6 01/16] drm/i915/cmtg: Add
> >> intel_cmtg_is_allowed() for CMTG
> >>
> >>
> >> On 13-05-2026 22:08, Animesh Manna wrote:
> >>> CMTG will be enabled only with DC3co, so add a separate function
> >>> intel_cmtg_is_allowed() to check the prerequisites for enabling CMTG.
> >>> DC3co will be enabled in a separate patch.
> >>>
> >>> v2:
> >>> - Remove separate flag for DC3co from crtc_state. [Uma, Dibin]
> >>>
> >>> v3:
> >>> - Do not access power domain members directly. [Jani]
> >>>
> >>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> >>> ---
> >>>    drivers/gpu/drm/i915/display/intel_cmtg.c | 15 ++++++++++++++-
> >>>    drivers/gpu/drm/i915/display/intel_cmtg.h |  4 ++++
> >>>    2 files changed, 18 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> >>> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> >>> index e1fdc6fe9762..dc039bea452c 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> >>> @@ -4,7 +4,6 @@
> >>>     */
> >>>
> >>>    #include <linux/string_choices.h> -#include <linux/types.h>
> >>>
> >>>    #include <drm/drm_device.h>
> >>>    #include <drm/drm_print.h>
> >>> @@ -16,6 +15,7 @@
> >>>    #include "intel_display_device.h"
> >>>    #include "intel_display_power.h"
> >>>    #include "intel_display_regs.h"
> >>> +#include "intel_display_types.h"
> >>>
> >>>    /**
> >>>     * DOC: Common Primary Timing Generator (CMTG) @@ -185,3
> +185,16
> >> @@
> >>> void intel_cmtg_sanitize(struct intel_display *display)
> >>>
> >>>    	intel_cmtg_disable(display, &cmtg_config);
> >>>    }
> >>> +
> >>> +bool intel_cmtg_is_allowed(const struct intel_crtc_state
> >>> +*crtc_state) {
> >>> +	struct intel_display *display = to_intel_display(crtc_state);
> >>> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >>> +
> >>> +	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder ==
> >> TRANSCODER_B) &&
> >>> +	    DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state,
> >> INTEL_OUTPUT_EDP) &&
> >>> +	    intel_display_power_get_current_dc_state(display) ==
> >>> +DC_STATE_EN_DC3CO)
> >> I would enable CMTG before setting the DC3CO state, since CMTG
> >> running is a must condition for DC3CO.
> >> Doing it the current way creates a cyclic dependency.
> > Copy -pasting from bspec:
> > CMTG must be enabled with dynamic DC states.​​​
> >
> > Dynamic DC state refers to Dc3co/Dc6v.
> > So added a check for dc-state which will be used inside cmtg functions. Do
> not want to allow touching CMTG register if target_dc_state is not DC3co.
> >
> > Again copy-pasting from bspec:
> > CMTG state needs to be saved and restored during power state transitions.
> >
> > Which means CMTG will lose its value with DC5/DC6. So want to be little
> cautious while handling CMTG.
> 
> I can see DC6 restore is already handled in patch 15.
> 
> target_dc_state is a software state doesn't guarantee any actual DC state
> register write.
> 
> I think its better to leave the target dc state decision to DC3CO
> implementation rather than using  it as flag variable for CMTG enable check.

This is just a protective measure, in my opinion not harmful.

Regards,
Animesh

> 
> >
> > We should finalize what will be the target_dc_state based use case like
> PSR2/LOBF/PR-ALPM and single EDP configuration.
> > This is the only flag and based on that CMTG and DC3co will be enabled. So,
> no cyclic dependency. Good to know if I am missing anything.
> >
> > Regards,
> > Animesh
> >
> >>> +		return true;
> >>> +
> >>> +	return false;
> >>> +}
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> >>> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> >>> index ba62199adaa2..ed540581738f 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> >>> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> >>> @@ -6,8 +6,12 @@
> >>>    #ifndef __INTEL_CMTG_H__
> >>>    #define __INTEL_CMTG_H__
> >>>
> >>> +#include <linux/types.h>
> >>> +
> >>>    struct intel_display;
> >>> +struct intel_crtc_state;
> >>>
> >>>    void intel_cmtg_sanitize(struct intel_display *display);
> >>> +bool intel_cmtg_is_allowed(const struct intel_crtc_state
> >>> +*crtc_state);
> >>>
> >>>    #endif /* __INTEL_CMTG_H__ */

RE: [PATCH v6 01/16] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG

[Shankar, Uma]

> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Friday, May 22, 2026 10:31 AM
> To: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>
> Subject: RE: [PATCH v6 01/16] drm/i915/cmtg: Add intel_cmtg_is_allowed() for
> CMTG
> 
> 
> 
> > -----Original Message-----
> > From: Dibin Moolakadan Subrahmanian
> > <dibin.moolakadan.subrahmanian@intel.com>
> > Sent: Thursday, May 21, 2026 6:06 PM
> > To: Manna, Animesh <animesh.manna@intel.com>; intel-
> > gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > Cc: Shankar, Uma <uma.shankar@intel.com>;
> > ville.syrjala@linux.intel.com; Nikula, Jani <jani.nikula@intel.com>
> > Subject: Re: [PATCH v6 01/16] drm/i915/cmtg: Add
> > intel_cmtg_is_allowed() for CMTG
> >
> >
> > On 21-05-2026 14:31, Manna, Animesh wrote:
> > >
> > >> -----Original Message-----
> > >> From: Dibin Moolakadan Subrahmanian
> > >> <dibin.moolakadan.subrahmanian@intel.com>
> > >> Sent: Thursday, May 21, 2026 1:49 PM
> > >> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> > >> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > >> Cc: Shankar, Uma <uma.shankar@intel.com>;
> > >> ville.syrjala@linux.intel.com; Nikula, Jani <jani.nikula@intel.com>
> > >> Subject: Re: [PATCH v6 01/16] drm/i915/cmtg: Add
> > >> intel_cmtg_is_allowed() for CMTG
> > >>
> > >>
> > >> On 13-05-2026 22:08, Animesh Manna wrote:
> > >>> CMTG will be enabled only with DC3co, so add a separate function
> > >>> intel_cmtg_is_allowed() to check the prerequisites for enabling CMTG.
> > >>> DC3co will be enabled in a separate patch.
> > >>>
> > >>> v2:
> > >>> - Remove separate flag for DC3co from crtc_state. [Uma, Dibin]
> > >>>
> > >>> v3:
> > >>> - Do not access power domain members directly. [Jani]
> > >>>
> > >>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > >>> ---
> > >>>    drivers/gpu/drm/i915/display/intel_cmtg.c | 15 ++++++++++++++-
> > >>>    drivers/gpu/drm/i915/display/intel_cmtg.h |  4 ++++
> > >>>    2 files changed, 18 insertions(+), 1 deletion(-)
> > >>>
> > >>> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > >>> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > >>> index e1fdc6fe9762..dc039bea452c 100644
> > >>> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > >>> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > >>> @@ -4,7 +4,6 @@
> > >>>     */
> > >>>
> > >>>    #include <linux/string_choices.h> -#include <linux/types.h>
> > >>>
> > >>>    #include <drm/drm_device.h>
> > >>>    #include <drm/drm_print.h>
> > >>> @@ -16,6 +15,7 @@
> > >>>    #include "intel_display_device.h"
> > >>>    #include "intel_display_power.h"
> > >>>    #include "intel_display_regs.h"
> > >>> +#include "intel_display_types.h"
> > >>>
> > >>>    /**
> > >>>     * DOC: Common Primary Timing Generator (CMTG) @@ -185,3
> > +185,16
> > >> @@
> > >>> void intel_cmtg_sanitize(struct intel_display *display)
> > >>>
> > >>>    	intel_cmtg_disable(display, &cmtg_config);
> > >>>    }
> > >>> +
> > >>> +bool intel_cmtg_is_allowed(const struct intel_crtc_state
> > >>> +*crtc_state) {
> > >>> +	struct intel_display *display = to_intel_display(crtc_state);
> > >>> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > >>> +
> > >>> +	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder ==
> > >> TRANSCODER_B) &&
> > >>> +	    DISPLAY_VER(display) == 35 &&
> > >>> +intel_crtc_has_type(crtc_state,
> > >> INTEL_OUTPUT_EDP) &&
> > >>> +	    intel_display_power_get_current_dc_state(display) ==
> > >>> +DC_STATE_EN_DC3CO)
> > >> I would enable CMTG before setting the DC3CO state, since CMTG
> > >> running is a must condition for DC3CO.
> > >> Doing it the current way creates a cyclic dependency.
> > > Copy -pasting from bspec:
> > > CMTG must be enabled with dynamic DC states.​​​
> > >
> > > Dynamic DC state refers to Dc3co/Dc6v.
> > > So added a check for dc-state which will be used inside cmtg
> > > functions. Do
> > not want to allow touching CMTG register if target_dc_state is not DC3co.
> > >
> > > Again copy-pasting from bspec:
> > > CMTG state needs to be saved and restored during power state transitions.
> > >
> > > Which means CMTG will lose its value with DC5/DC6. So want to be
> > > little
> > cautious while handling CMTG.
> >
> > I can see DC6 restore is already handled in patch 15.
> >
> > target_dc_state is a software state doesn't guarantee any actual DC
> > state register write.
> >
> > I think its better to leave the target dc state decision to DC3CO
> > implementation rather than using  it as flag variable for CMTG enable check.
> 
> This is just a protective measure, in my opinion not harmful.

I think we can leave CMTG enabling to the caller. Caller should check if CMTG
is needed and call the enable helper. No need for CMTG to check for target DC state.

Also during restore from DC6, before enabling DC3CO CMTG timing registers which lose
value should be restored. This will simplify the checks.

Regards,
Uma Shankar

> Regards,
> Animesh
> 
> >
> > >
> > > We should finalize what will be the target_dc_state based use case
> > > like
> > PSR2/LOBF/PR-ALPM and single EDP configuration.
> > > This is the only flag and based on that CMTG and DC3co will be
> > > enabled. So,
> > no cyclic dependency. Good to know if I am missing anything.
> > >
> > > Regards,
> > > Animesh
> > >
> > >>> +		return true;
> > >>> +
> > >>> +	return false;
> > >>> +}
> > >>> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > >>> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > >>> index ba62199adaa2..ed540581738f 100644
> > >>> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > >>> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > >>> @@ -6,8 +6,12 @@
> > >>>    #ifndef __INTEL_CMTG_H__
> > >>>    #define __INTEL_CMTG_H__
> > >>>
> > >>> +#include <linux/types.h>
> > >>> +
> > >>>    struct intel_display;
> > >>> +struct intel_crtc_state;
> > >>>
> > >>>    void intel_cmtg_sanitize(struct intel_display *display);
> > >>> +bool intel_cmtg_is_allowed(const struct intel_crtc_state
> > >>> +*crtc_state);
> > >>>
> > >>>    #endif /* __INTEL_CMTG_H__ */

[PATCH v6 02/16] drm/i915/cmtg: Set CMTG clock select

[Animesh Manna]

Program the CMTG Clock Select register based on the transcoder used.

v2:
- Correct mask for PHY B. [Jani]
- Use REG_FIELD_PREP() for enable value. [Dibin]
- Extend cmtg clock select for xe3plpd. [Dibin]

v3:
- CMTG support removed for old platform.

v4:
- Optimize further with else-if. [Uma]
- Correct CMTG_CLK_SEL_B_MASK. [Uma]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 22 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  2 ++
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  5 +++++
 4 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index dc039bea452c..cfe59c604506 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -198,3 +198,25 @@ bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
 
 	return false;
 }
+
+void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 clk_sel_clr = 0;
+	u32 clk_sel_set = 0;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	if (cpu_transcoder == TRANSCODER_A) {
+		clk_sel_clr = CMTG_CLK_SEL_A_MASK;
+		clk_sel_set = CMTG_CLK_SELECT_PHYA_ENABLE;
+	} else if (cpu_transcoder == TRANSCODER_B) {
+		clk_sel_clr = CMTG_CLK_SEL_B_MASK;
+		clk_sel_set = CMTG_CLK_SELECT_PHYB_ENABLE;
+	}
+
+	if (clk_sel_set)
+		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index ed540581738f..87092ce6d67b 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 945a35578284..4a80b88d88fd 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -10,8 +10,10 @@
 
 #define CMTG_CLK_SEL			_MMIO(0x46160)
 #define CMTG_CLK_SEL_A_MASK		REG_GENMASK(31, 29)
+#define CMTG_CLK_SELECT_PHYA_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x4)
 #define CMTG_CLK_SEL_A_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0)
 #define CMTG_CLK_SEL_B_MASK		REG_GENMASK(15, 13)
+#define CMTG_CLK_SELECT_PHYB_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0x6)
 #define CMTG_CLK_SEL_B_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
 
 #define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index d832e44ef62a..6a7481578e61 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -9,6 +9,7 @@
 #include <drm/drm_print.h>
 
 #include "intel_alpm.h"
+#include "intel_cmtg.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_display_regs.h"
@@ -3418,10 +3419,14 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder,
 void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
 				const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
 		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
+
+	if (HAS_LT_PHY(display))
+		intel_cmtg_set_clk_select(crtc_state);
 }
 
 /*
-- 
2.29.0

Re: [PATCH v6 02/16] drm/i915/cmtg: Set CMTG clock select

[Dibin Moolakadan Subrahmanian]

On 13-05-2026 22:08, Animesh Manna wrote:
> Program the CMTG Clock Select register based on the transcoder used.
>
> v2:
> - Correct mask for PHY B. [Jani]
> - Use REG_FIELD_PREP() for enable value. [Dibin]
> - Extend cmtg clock select for xe3plpd. [Dibin]
>
> v3:
> - CMTG support removed for old platform.
>
> v4:
> - Optimize further with else-if. [Uma]
> - Correct CMTG_CLK_SEL_B_MASK. [Uma]
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_cmtg.c     | 22 +++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
>   .../gpu/drm/i915/display/intel_cmtg_regs.h    |  2 ++
>   drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  5 +++++
>   4 files changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index dc039bea452c..cfe59c604506 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -198,3 +198,25 @@ bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
>   
>   	return false;
>   }
> +
> +void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 clk_sel_clr = 0;
> +	u32 clk_sel_set = 0;
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	if (cpu_transcoder == TRANSCODER_A) {
> +		clk_sel_clr = CMTG_CLK_SEL_A_MASK;
> +		clk_sel_set = CMTG_CLK_SELECT_PHYA_ENABLE;
> +	} else if (cpu_transcoder == TRANSCODER_B) {
> +		clk_sel_clr = CMTG_CLK_SEL_B_MASK;
> +		clk_sel_set = CMTG_CLK_SELECT_PHYB_ENABLE;
> +	}
> +
> +	if (clk_sel_set)
> +		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
> +}

This comment applies to the entire CMTG programming series, but adding it here since this is the first
TRANSCODER/PHY programming step.

There are IGT cases where TRANSCODER_B is not mapped to PORT_B, so the current|else if|
flow can fail because PHY B may not be enabled.

Please check whether the programming sequence here is correct and
what TRANSCODER/PORT/PHY combinations are supported for CMTG.

> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index ed540581738f..87092ce6d67b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -11,6 +11,7 @@
>   struct intel_display;
>   struct intel_crtc_state;
>   
> +void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
>   void intel_cmtg_sanitize(struct intel_display *display);
>   bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
>   
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 945a35578284..4a80b88d88fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -10,8 +10,10 @@
>   
>   #define CMTG_CLK_SEL			_MMIO(0x46160)
>   #define CMTG_CLK_SEL_A_MASK		REG_GENMASK(31, 29)
> +#define CMTG_CLK_SELECT_PHYA_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x4)
>   #define CMTG_CLK_SEL_A_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0)
>   #define CMTG_CLK_SEL_B_MASK		REG_GENMASK(15, 13)
> +#define CMTG_CLK_SELECT_PHYB_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0x6)
>   #define CMTG_CLK_SEL_B_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
>   
>   #define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index d832e44ef62a..6a7481578e61 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -9,6 +9,7 @@
>   #include <drm/drm_print.h>
>   
>   #include "intel_alpm.h"
> +#include "intel_cmtg.h"
>   #include "intel_cx0_phy.h"
>   #include "intel_cx0_phy_regs.h"
>   #include "intel_display_regs.h"
> @@ -3418,10 +3419,14 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder,
>   void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
>   				const struct intel_crtc_state *crtc_state)
>   {
> +	struct intel_display *display = to_intel_display(encoder);
>   	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>   
>   	if (intel_tc_port_in_tbt_alt_mode(dig_port))
>   		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
> +
> +	if (HAS_LT_PHY(display))
> +		intel_cmtg_set_clk_select(crtc_state);
>   }
>   
>   /*

RE: [PATCH v6 02/16] drm/i915/cmtg: Set CMTG clock select

[Manna, Animesh]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Thursday, May 21, 2026 2:01 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>
> Subject: Re: [PATCH v6 02/16] drm/i915/cmtg: Set CMTG clock select
> 
> 
> On 13-05-2026 22:08, Animesh Manna wrote:
> > Program the CMTG Clock Select register based on the transcoder used.
> >
> > v2:
> > - Correct mask for PHY B. [Jani]
> > - Use REG_FIELD_PREP() for enable value. [Dibin]
> > - Extend cmtg clock select for xe3plpd. [Dibin]
> >
> > v3:
> > - CMTG support removed for old platform.
> >
> > v4:
> > - Optimize further with else-if. [Uma]
> > - Correct CMTG_CLK_SEL_B_MASK. [Uma]
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > Signed-off-by: Dibin Moolakadan Subrahmanian
> > <dibin.moolakadan.subrahmanian@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_cmtg.c     | 22 +++++++++++++++++++
> >   drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
> >   .../gpu/drm/i915/display/intel_cmtg_regs.h    |  2 ++
> >   drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  5 +++++
> >   4 files changed, 30 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > index dc039bea452c..cfe59c604506 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > @@ -198,3 +198,25 @@ bool intel_cmtg_is_allowed(const struct
> > intel_crtc_state *crtc_state)
> >
> >   	return false;
> >   }
> > +
> > +void intel_cmtg_set_clk_select(const struct intel_crtc_state
> > +*crtc_state) {
> > +	struct intel_display *display = to_intel_display(crtc_state);
> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +	u32 clk_sel_clr = 0;
> > +	u32 clk_sel_set = 0;
> > +
> > +	if (!intel_cmtg_is_allowed(crtc_state))
> > +		return;
> > +
> > +	if (cpu_transcoder == TRANSCODER_A) {
> > +		clk_sel_clr = CMTG_CLK_SEL_A_MASK;
> > +		clk_sel_set = CMTG_CLK_SELECT_PHYA_ENABLE;
> > +	} else if (cpu_transcoder == TRANSCODER_B) {
> > +		clk_sel_clr = CMTG_CLK_SEL_B_MASK;
> > +		clk_sel_set = CMTG_CLK_SELECT_PHYB_ENABLE;
> > +	}
> > +
> > +	if (clk_sel_set)
> > +		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> clk_sel_set); }
> 
> This comment applies to the entire CMTG programming series, but adding it
> here since this is the first TRANSCODER/PHY programming step.
> 
> There are IGT cases where TRANSCODER_B is not mapped to PORT_B, so the
> current|else if| flow can fail because PHY B may not be enabled.
> 
> Please check whether the programming sequence here is correct and what
> TRANSCODER/PORT/PHY combinations are supported for CMTG.

We should restrict CMTG usage if port and transcoder is not matching. This is limitation from hardware.
The Dc3co should not be allowed if transcoder and port is not matching.
CMTG will rely on target_dc_state which will be set if dc3co is allowed.

Regards,
Animesh
 
> 
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > index ed540581738f..87092ce6d67b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > @@ -11,6 +11,7 @@
> >   struct intel_display;
> >   struct intel_crtc_state;
> >
> > +void intel_cmtg_set_clk_select(const struct intel_crtc_state
> > +*crtc_state);
> >   void intel_cmtg_sanitize(struct intel_display *display);
> >   bool intel_cmtg_is_allowed(const struct intel_crtc_state
> > *crtc_state);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > index 945a35578284..4a80b88d88fd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > @@ -10,8 +10,10 @@
> >
> >   #define CMTG_CLK_SEL			_MMIO(0x46160)
> >   #define CMTG_CLK_SEL_A_MASK		REG_GENMASK(31, 29)
> > +#define CMTG_CLK_SELECT_PHYA_ENABLE
> 	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x4)
> >   #define CMTG_CLK_SEL_A_DISABLED
> 	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0)
> >   #define CMTG_CLK_SEL_B_MASK		REG_GENMASK(15, 13)
> > +#define CMTG_CLK_SELECT_PHYB_ENABLE
> 	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0x6)
> >   #define CMTG_CLK_SEL_B_DISABLED
> 	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
> >
> >   #define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index d832e44ef62a..6a7481578e61 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -9,6 +9,7 @@
> >   #include <drm/drm_print.h>
> >
> >   #include "intel_alpm.h"
> > +#include "intel_cmtg.h"
> >   #include "intel_cx0_phy.h"
> >   #include "intel_cx0_phy_regs.h"
> >   #include "intel_display_regs.h"
> > @@ -3418,10 +3419,14 @@ void intel_mtl_pll_enable(struct intel_encoder
> *encoder,
> >   void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
> >   				const struct intel_crtc_state *crtc_state)
> >   {
> > +	struct intel_display *display = to_intel_display(encoder);
> >   	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> >
> >   	if (intel_tc_port_in_tbt_alt_mode(dig_port))
> >   		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state-
> >port_clock);
> > +
> > +	if (HAS_LT_PHY(display))
> > +		intel_cmtg_set_clk_select(crtc_state);
> >   }
> >
> >   /*

Re: [PATCH v6 02/16] drm/i915/cmtg: Set CMTG clock select

[Dibin Moolakadan Subrahmanian]

On 21-05-2026 17:41, Manna, Animesh wrote:
>
>> -----Original Message-----
>> From: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> Sent: Thursday, May 21, 2026 2:01 PM
>> To: Manna, Animesh <animesh.manna@intel.com>; intel-
>> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
>> Cc: Shankar, Uma <uma.shankar@intel.com>; ville.syrjala@linux.intel.com;
>> Nikula, Jani <jani.nikula@intel.com>
>> Subject: Re: [PATCH v6 02/16] drm/i915/cmtg: Set CMTG clock select
>>
>>
>> On 13-05-2026 22:08, Animesh Manna wrote:
>>> Program the CMTG Clock Select register based on the transcoder used.
>>>
>>> v2:
>>> - Correct mask for PHY B. [Jani]
>>> - Use REG_FIELD_PREP() for enable value. [Dibin]
>>> - Extend cmtg clock select for xe3plpd. [Dibin]
>>>
>>> v3:
>>> - CMTG support removed for old platform.
>>>
>>> v4:
>>> - Optimize further with else-if. [Uma]
>>> - Correct CMTG_CLK_SEL_B_MASK. [Uma]
>>>
>>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>>> Signed-off-by: Dibin Moolakadan Subrahmanian
>>> <dibin.moolakadan.subrahmanian@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/display/intel_cmtg.c     | 22 +++++++++++++++++++
>>>    drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
>>>    .../gpu/drm/i915/display/intel_cmtg_regs.h    |  2 ++
>>>    drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  5 +++++
>>>    4 files changed, 30 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
>>> b/drivers/gpu/drm/i915/display/intel_cmtg.c
>>> index dc039bea452c..cfe59c604506 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
>>> @@ -198,3 +198,25 @@ bool intel_cmtg_is_allowed(const struct
>>> intel_crtc_state *crtc_state)
>>>
>>>    	return false;
>>>    }
>>> +
>>> +void intel_cmtg_set_clk_select(const struct intel_crtc_state
>>> +*crtc_state) {
>>> +	struct intel_display *display = to_intel_display(crtc_state);
>>> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>>> +	u32 clk_sel_clr = 0;
>>> +	u32 clk_sel_set = 0;
>>> +
>>> +	if (!intel_cmtg_is_allowed(crtc_state))
>>> +		return;
>>> +
>>> +	if (cpu_transcoder == TRANSCODER_A) {
>>> +		clk_sel_clr = CMTG_CLK_SEL_A_MASK;
>>> +		clk_sel_set = CMTG_CLK_SELECT_PHYA_ENABLE;
>>> +	} else if (cpu_transcoder == TRANSCODER_B) {
>>> +		clk_sel_clr = CMTG_CLK_SEL_B_MASK;
>>> +		clk_sel_set = CMTG_CLK_SELECT_PHYB_ENABLE;
>>> +	}
>>> +
>>> +	if (clk_sel_set)
>>> +		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
>> clk_sel_set); }
>>
>> This comment applies to the entire CMTG programming series, but adding it
>> here since this is the first TRANSCODER/PHY programming step.
>>
>> There are IGT cases where TRANSCODER_B is not mapped to PORT_B, so the
>> current|else if| flow can fail because PHY B may not be enabled.
>>
>> Please check whether the programming sequence here is correct and what
>> TRANSCODER/PORT/PHY combinations are supported for CMTG.
> We should restrict CMTG usage if port and transcoder is not matching. This is limitation from hardware.
> The Dc3co should not be allowed if transcoder and port is not matching.
> CMTG will rely on target_dc_state which will be set if dc3co is allowed.

TRANSCODER_A,PORT_B configuration is valid for DC3CO.

as per Bspec DC3CO is supported in below combinations.
Transcoder A to port A or B
Transcoder B to port A or B

>
> Regards,
> Animesh
>   
>>> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
>>> b/drivers/gpu/drm/i915/display/intel_cmtg.h
>>> index ed540581738f..87092ce6d67b 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
>>> @@ -11,6 +11,7 @@
>>>    struct intel_display;
>>>    struct intel_crtc_state;
>>>
>>> +void intel_cmtg_set_clk_select(const struct intel_crtc_state
>>> +*crtc_state);
>>>    void intel_cmtg_sanitize(struct intel_display *display);
>>>    bool intel_cmtg_is_allowed(const struct intel_crtc_state
>>> *crtc_state);
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
>>> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
>>> index 945a35578284..4a80b88d88fd 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
>>> @@ -10,8 +10,10 @@
>>>
>>>    #define CMTG_CLK_SEL			_MMIO(0x46160)
>>>    #define CMTG_CLK_SEL_A_MASK		REG_GENMASK(31, 29)
>>> +#define CMTG_CLK_SELECT_PHYA_ENABLE
>> 	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x4)
>>>    #define CMTG_CLK_SEL_A_DISABLED
>> 	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0)
>>>    #define CMTG_CLK_SEL_B_MASK		REG_GENMASK(15, 13)
>>> +#define CMTG_CLK_SELECT_PHYB_ENABLE
>> 	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0x6)
>>>    #define CMTG_CLK_SEL_B_DISABLED
>> 	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
>>>    #define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
>>> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>> index d832e44ef62a..6a7481578e61 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>> @@ -9,6 +9,7 @@
>>>    #include <drm/drm_print.h>
>>>
>>>    #include "intel_alpm.h"
>>> +#include "intel_cmtg.h"
>>>    #include "intel_cx0_phy.h"
>>>    #include "intel_cx0_phy_regs.h"
>>>    #include "intel_display_regs.h"
>>> @@ -3418,10 +3419,14 @@ void intel_mtl_pll_enable(struct intel_encoder
>> *encoder,
>>>    void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
>>>    				const struct intel_crtc_state *crtc_state)
>>>    {
>>> +	struct intel_display *display = to_intel_display(encoder);
>>>    	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>>>
>>>    	if (intel_tc_port_in_tbt_alt_mode(dig_port))
>>>    		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state-
>>> port_clock);
>>> +
>>> +	if (HAS_LT_PHY(display))
>>> +		intel_cmtg_set_clk_select(crtc_state);
>>>    }
>>>
>>>    /*

RE: [PATCH v6 02/16] drm/i915/cmtg: Set CMTG clock select

[Manna, Animesh]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Thursday, May 21, 2026 6:11 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>
> Subject: Re: [PATCH v6 02/16] drm/i915/cmtg: Set CMTG clock select
> 
> 
> On 21-05-2026 17:41, Manna, Animesh wrote:
> >
> >> -----Original Message-----
> >> From: Dibin Moolakadan Subrahmanian
> >> <dibin.moolakadan.subrahmanian@intel.com>
> >> Sent: Thursday, May 21, 2026 2:01 PM
> >> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> >> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> >> Cc: Shankar, Uma <uma.shankar@intel.com>;
> >> ville.syrjala@linux.intel.com; Nikula, Jani <jani.nikula@intel.com>
> >> Subject: Re: [PATCH v6 02/16] drm/i915/cmtg: Set CMTG clock select
> >>
> >>
> >> On 13-05-2026 22:08, Animesh Manna wrote:
> >>> Program the CMTG Clock Select register based on the transcoder used.
> >>>
> >>> v2:
> >>> - Correct mask for PHY B. [Jani]
> >>> - Use REG_FIELD_PREP() for enable value. [Dibin]
> >>> - Extend cmtg clock select for xe3plpd. [Dibin]
> >>>
> >>> v3:
> >>> - CMTG support removed for old platform.
> >>>
> >>> v4:
> >>> - Optimize further with else-if. [Uma]
> >>> - Correct CMTG_CLK_SEL_B_MASK. [Uma]
> >>>
> >>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> >>> Signed-off-by: Dibin Moolakadan Subrahmanian
> >>> <dibin.moolakadan.subrahmanian@intel.com>
> >>> ---
> >>>    drivers/gpu/drm/i915/display/intel_cmtg.c     | 22
> +++++++++++++++++++
> >>>    drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
> >>>    .../gpu/drm/i915/display/intel_cmtg_regs.h    |  2 ++
> >>>    drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  5 +++++
> >>>    4 files changed, 30 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> >>> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> >>> index dc039bea452c..cfe59c604506 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> >>> @@ -198,3 +198,25 @@ bool intel_cmtg_is_allowed(const struct
> >>> intel_crtc_state *crtc_state)
> >>>
> >>>    	return false;
> >>>    }
> >>> +
> >>> +void intel_cmtg_set_clk_select(const struct intel_crtc_state
> >>> +*crtc_state) {
> >>> +	struct intel_display *display = to_intel_display(crtc_state);
> >>> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >>> +	u32 clk_sel_clr = 0;
> >>> +	u32 clk_sel_set = 0;
> >>> +
> >>> +	if (!intel_cmtg_is_allowed(crtc_state))
> >>> +		return;
> >>> +
> >>> +	if (cpu_transcoder == TRANSCODER_A) {
> >>> +		clk_sel_clr = CMTG_CLK_SEL_A_MASK;
> >>> +		clk_sel_set = CMTG_CLK_SELECT_PHYA_ENABLE;
> >>> +	} else if (cpu_transcoder == TRANSCODER_B) {
> >>> +		clk_sel_clr = CMTG_CLK_SEL_B_MASK;
> >>> +		clk_sel_set = CMTG_CLK_SELECT_PHYB_ENABLE;
> >>> +	}
> >>> +
> >>> +	if (clk_sel_set)
> >>> +		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> >> clk_sel_set); }
> >>
> >> This comment applies to the entire CMTG programming series, but
> >> adding it here since this is the first TRANSCODER/PHY programming step.
> >>
> >> There are IGT cases where TRANSCODER_B is not mapped to PORT_B, so
> >> the
> >> current|else if| flow can fail because PHY B may not be enabled.
> >>
> >> Please check whether the programming sequence here is correct and
> >> what TRANSCODER/PORT/PHY combinations are supported for CMTG.
> > We should restrict CMTG usage if port and transcoder is not matching. This
> is limitation from hardware.
> > The Dc3co should not be allowed if transcoder and port is not matching.
> > CMTG will rely on target_dc_state which will be set if dc3co is allowed.
> 
> TRANSCODER_A,PORT_B configuration is valid for DC3CO.
> 
> as per Bspec DC3CO is supported in below combinations.
> Transcoder A to port A or B
> Transcoder B to port A or B

Dc3co is "Only supported with CMTG." So, if CMTG cannot be enabled, dc3co also will follow the same.

Regards,
Animesh
> 
> >
> > Regards,
> > Animesh
> >
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> >>> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> >>> index ed540581738f..87092ce6d67b 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> >>> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> >>> @@ -11,6 +11,7 @@
> >>>    struct intel_display;
> >>>    struct intel_crtc_state;
> >>>
> >>> +void intel_cmtg_set_clk_select(const struct intel_crtc_state
> >>> +*crtc_state);
> >>>    void intel_cmtg_sanitize(struct intel_display *display);
> >>>    bool intel_cmtg_is_allowed(const struct intel_crtc_state
> >>> *crtc_state);
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> >>> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> >>> index 945a35578284..4a80b88d88fd 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> >>> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> >>> @@ -10,8 +10,10 @@
> >>>
> >>>    #define CMTG_CLK_SEL			_MMIO(0x46160)
> >>>    #define CMTG_CLK_SEL_A_MASK		REG_GENMASK(31, 29)
> >>> +#define CMTG_CLK_SELECT_PHYA_ENABLE
> >> 	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x4)
> >>>    #define CMTG_CLK_SEL_A_DISABLED
> >> 	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0)
> >>>    #define CMTG_CLK_SEL_B_MASK		REG_GENMASK(15, 13)
> >>> +#define CMTG_CLK_SELECT_PHYB_ENABLE
> >> 	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0x6)
> >>>    #define CMTG_CLK_SEL_B_DISABLED
> >> 	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
> >>>    #define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >>> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >>> index d832e44ef62a..6a7481578e61 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >>> @@ -9,6 +9,7 @@
> >>>    #include <drm/drm_print.h>
> >>>
> >>>    #include "intel_alpm.h"
> >>> +#include "intel_cmtg.h"
> >>>    #include "intel_cx0_phy.h"
> >>>    #include "intel_cx0_phy_regs.h"
> >>>    #include "intel_display_regs.h"
> >>> @@ -3418,10 +3419,14 @@ void intel_mtl_pll_enable(struct
> >>> intel_encoder
> >> *encoder,
> >>>    void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
> >>>    				const struct intel_crtc_state *crtc_state)
> >>>    {
> >>> +	struct intel_display *display = to_intel_display(encoder);
> >>>    	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> >>>
> >>>    	if (intel_tc_port_in_tbt_alt_mode(dig_port))
> >>>    		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state-
> >>> port_clock);
> >>> +
> >>> +	if (HAS_LT_PHY(display))
> >>> +		intel_cmtg_set_clk_select(crtc_state);
> >>>    }
> >>>
> >>>    /*

[PATCH v6 03/16] drm/i915/cmtg: Add cmtg transcoder offset in struct _device_info

[Animesh Manna]

As all cmtg registers offset from base cmtg register is similar to
normal transcoder register, so follow existing way of defining
transcoder register for cmtg as well. Add base CMTG offset in
struct _display_device_info which will be used to derive the actual
register address for platform supporting CMTG.

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 .../gpu/drm/i915/display/intel_display_device.c    | 14 ++++++++++++++
 .../gpu/drm/i915/display/intel_display_device.h    |  2 +-
 .../gpu/drm/i915/display/intel_display_limits.h    |  2 ++
 3 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 7260990038dd..b46db2e255b0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -101,6 +101,8 @@ static const struct intel_display_device_info no_display = {};
 #define TRANSCODER_EDP_OFFSET 0x6f000
 #define TRANSCODER_DSI0_OFFSET	0x6b000
 #define TRANSCODER_DSI1_OFFSET	0x6b800
+#define TRANSCODER_CMTG0_OFFSET 0x6F000
+#define TRANSCODER_CMTG1_OFFSET 0x6F100
 
 #define CURSOR_A_OFFSET 0x70080
 #define CURSOR_B_OFFSET 0x700c0
@@ -1352,6 +1354,18 @@ static const struct intel_display_device_info xe2_lpd_display = {
 		BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) |
 		BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
 	.__runtime_defaults.has_dbuf_overlap_detection = true,
+	.trans_offsets = {
+		[TRANSCODER_A] = TRANSCODER_A_OFFSET,
+		[TRANSCODER_B] = TRANSCODER_B_OFFSET,
+		[TRANSCODER_C] = TRANSCODER_C_OFFSET,
+		[TRANSCODER_D] = TRANSCODER_D_OFFSET,
+		[TRANSCODER_CMTG0] = TRANSCODER_CMTG0_OFFSET,
+		[TRANSCODER_CMTG1] = TRANSCODER_CMTG1_OFFSET,
+	},
+	.__runtime_defaults.cpu_transcoder_mask =
+		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
+		BIT(TRANSCODER_CMTG0) | BIT(TRANSCODER_CMTG1),
 };
 
 static const struct intel_display_device_info wcl_display = {
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 074e3ba8fb77..ceafda7479d8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -293,7 +293,7 @@ struct intel_display_runtime_info {
 	u32 rawclk_freq;
 
 	u8 pipe_mask;
-	u8 cpu_transcoder_mask;
+	u16 cpu_transcoder_mask;
 	u16 port_mask;
 
 	u8 num_sprites[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h b/drivers/gpu/drm/i915/display/intel_display_limits.h
index 453f7b720815..ea89473c177f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_limits.h
+++ b/drivers/gpu/drm/i915/display/intel_display_limits.h
@@ -45,6 +45,8 @@ enum transcoder {
 	TRANSCODER_DSI_1,
 	TRANSCODER_DSI_A = TRANSCODER_DSI_0,	/* legacy DSI */
 	TRANSCODER_DSI_C = TRANSCODER_DSI_1,	/* legacy DSI */
+	TRANSCODER_CMTG0,
+	TRANSCODER_CMTG1,
 
 	I915_MAX_TRANSCODERS
 };
-- 
2.29.0

[PATCH v6 04/16] drm/i915/cmtg: Set timings for CMTG

[Animesh Manna]

Timing registers are separate for CMTG, read transcoder register
and program cmtg transcoder with those values.

v2:
- Use sw state instead of reading directly from hardware. [Jani]
- Move set_timing later after encoder enable. [Dibin]

v3:
- Replace id with trans. [Jani]
- Program cmtg set_timing() along with primary transcoder timing.

v4:
- Use _MMIO_TRANS() for cmtg registers instead of direct
multiplication. [Jani]

v5:
- Modify register definition approach and match existing
transcoder definition. [Ville]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c    | 72 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h    |  1 +
 drivers/gpu/drm/i915/display/intel_display.c |  4 ++
 3 files changed, 77 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index cfe59c604506..a314e73e9fcb 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -220,3 +220,75 @@ void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
 	if (clk_sel_set)
 		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
 }
+
+static inline enum transcoder to_cmtg_transcoder(enum transcoder cpu_transcoder)
+{
+	switch (cpu_transcoder) {
+	case TRANSCODER_A:
+		return TRANSCODER_CMTG0;
+	case TRANSCODER_B:
+		return TRANSCODER_CMTG1;
+	default:
+		return INVALID_TRANSCODER;
+	}
+}
+
+void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
+	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
+
+	/*
+	 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
+	 * bits are not required. Since the support for these bits is going to
+	 * be deprecated in upcoming platforms, avoid writing these bits for the
+	 * platforms that do not use legacy Timing Generator.
+	 */
+	crtc_vtotal = 1;
+
+	/*
+	 * VBLANK_START not used by hw, just clear it
+	 * to make it stand out in register dumps.
+	 */
+	crtc_vblank_start = 1;
+
+	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
+
+	if (lrr) {
+		intel_de_write(display, TRANS_VTOTAL(display, cmtg_transcoder),
+			       VACTIVE(crtc_vdisplay - 1) |
+			       VTOTAL(crtc_vtotal - 1));
+		intel_de_write(display, TRANS_VBLANK(display, cmtg_transcoder),
+			       VBLANK_START(crtc_vblank_start - 1) |
+			       VBLANK_END(crtc_vblank_end - 1));
+		return;
+	}
+
+	intel_de_write(display, TRANS_HTOTAL(display, cmtg_transcoder),
+		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
+		       HTOTAL(adjusted_mode->crtc_htotal - 1));
+	intel_de_write(display, TRANS_HBLANK(display, cmtg_transcoder),
+		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
+		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
+	intel_de_write(display, TRANS_HSYNC(display, cmtg_transcoder),
+		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
+		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
+	intel_de_write(display, TRANS_VTOTAL(display, cmtg_transcoder),
+		       VACTIVE(crtc_vdisplay - 1) |
+		       VTOTAL(crtc_vtotal - 1));
+	intel_de_write(display, TRANS_VBLANK(display, cmtg_transcoder),
+		       VBLANK_START(crtc_vblank_start - 1) |
+		       VBLANK_END(crtc_vblank_end - 1));
+	intel_de_write(display, TRANS_VSYNC(display, cmtg_transcoder),
+		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
+		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
+	intel_de_write(display, TRANS_SET_CONTEXT_LATENCY(display, cmtg_transcoder),
+		       crtc_state->set_context_latency);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 87092ce6d67b..53a44f505dd2 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
 void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d5cf1476c7b9..701cb4f9d70d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -60,6 +60,7 @@
 #include "intel_bw.h"
 #include "intel_cdclk.h"
 #include "intel_clock_gating.h"
+#include "intel_cmtg.h"
 #include "intel_color.h"
 #include "intel_crt.h"
 #include "intel_crtc.h"
@@ -2753,6 +2754,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 		intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
 			       crtc_state->min_hblank);
 	}
+
+	intel_cmtg_set_timings(crtc_state, false);
 }
 
 static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
@@ -2814,6 +2817,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
 		       VACTIVE(crtc_vdisplay - 1) |
 		       VTOTAL(crtc_vtotal - 1));
 
+	intel_cmtg_set_timings(crtc_state, true);
 	intel_vrr_set_fixed_rr_timings(crtc_state);
 	intel_vrr_transcoder_enable(crtc_state);
 }
-- 
2.29.0

[PATCH v6 05/16] drm/i915/cmtg: Program VRR registers of CMTG

[Animesh Manna]

Program the VRR registers of CMTG, as the VRR timing generator
will always be enabled for NVL.

v2: Use sw state instead of reading from hardware. [Jani]
v3: Program cmtg vrr control and timing registers along with
vrr transcoder registers.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c | 34 +++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h |  2 ++
 drivers/gpu/drm/i915/display/intel_vrr.c  |  5 ++++
 3 files changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index a314e73e9fcb..0a2d838319f9 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -16,6 +16,7 @@
 #include "intel_display_power.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
+#include "intel_vrr_regs.h"
 
 /**
  * DOC: Common Primary Timing Generator (CMTG)
@@ -292,3 +293,36 @@ void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
 	intel_de_write(display, TRANS_SET_CONTEXT_LATENCY(display, cmtg_transcoder),
 		       crtc_state->set_context_latency);
 }
+
+void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	intel_de_write(display, TRANS_VRR_VMIN(display, cmtg_transcoder), crtc_state->vrr.vmin - 1);
+	intel_de_write(display, TRANS_VRR_VMAX(display, cmtg_transcoder), crtc_state->vrr.vmax - 1);
+	intel_de_write(display, TRANS_VRR_FLIPLINE(display, cmtg_transcoder),
+		       crtc_state->vrr.flipline - 1);
+}
+
+void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
+	u32 vrr_ctl;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	vrr_ctl = VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN |
+		  XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
+
+	/* TODO: The code below may need to be revisited once CMRR is enabled */
+	if (crtc_state->cmrr.enable)
+		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
+
+	intel_de_write(display, TRANS_VRR_CTL(display, cmtg_transcoder), vrr_ctl);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 53a44f505dd2..c92e3a62ff0d 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,8 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
 void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 1b09992ce9fd..1260ceb7958e 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -7,6 +7,7 @@
 #include <drm/drm_print.h>
 
 #include "intel_alpm.h"
+#include "intel_cmtg.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
@@ -334,6 +335,8 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
 		       intel_vrr_fixed_rr_hw_vmax(crtc_state) - 1);
 	intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
 		       intel_vrr_fixed_rr_hw_flipline(crtc_state) - 1);
+
+	intel_cmtg_set_vrr_timings(crtc_state);
 }
 
 static
@@ -932,6 +935,8 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
 		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
 
 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
+
+	intel_cmtg_set_vrr_ctl(crtc_state);
 }
 
 static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
-- 
2.29.0

[PATCH v6 06/16] drm/i915/cmtg: Set transcoder mn for CMTG

[Animesh Manna]

Program CMTG link M/N.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c    | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h    |  1 +
 drivers/gpu/drm/i915/display/intel_display.c |  1 +
 3 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 0a2d838319f9..d490c57ba8b7 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -326,3 +326,16 @@ void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
 
 	intel_de_write(display, TRANS_VRR_CTL(display, cmtg_transcoder), vrr_ctl);
 }
+
+void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
+	const struct intel_link_m_n *m_n = &crtc_state->dp_m_n;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	intel_de_write(display, PIPE_DATA_M1(display, cmtg_transcoder), m_n->link_m);
+	intel_de_write(display, PIPE_DATA_N1(display, cmtg_transcoder), m_n->link_n);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index c92e3a62ff0d..6796eb727eef 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 701cb4f9d70d..dd53049898ea 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1615,6 +1615,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
 					       &crtc_state->dp_m2_n2);
 	}
 
+	intel_cmtg_set_m_n(crtc_state);
 	intel_set_transcoder_timings(crtc_state);
 
 	if (cpu_transcoder != TRANSCODER_EDP)
-- 
2.29.0

[PATCH v6 07/16] drm/i915/cmtg: Add hook to enable CMTG with sync to port

[Animesh Manna]

Add a hook to enable CMTG by programming CMTG CTL with Sync to Port.
When CMTG starts running, the Sync to Port bit will be cleared. Add
a wait to check its running status and trigger WARN_ON() on timeout.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 27 ++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  7 +++--
 3 files changed, 29 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index d490c57ba8b7..000b4957e546 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -104,11 +104,11 @@ static void intel_cmtg_get_config(struct intel_display *display,
 {
 	u32 val;
 
-	val = intel_de_read(display, TRANS_CMTG_CTL_A);
+	val = intel_de_read(display, TRANS_CMTG_CTL(TRANSCODER_A));
 	cmtg_config->cmtg_a_enable = val & CMTG_ENABLE;
 
 	if (intel_cmtg_has_cmtg_b(display)) {
-		val = intel_de_read(display, TRANS_CMTG_CTL_B);
+		val = intel_de_read(display, TRANS_CMTG_CTL(TRANSCODER_B));
 		cmtg_config->cmtg_b_enable = val & CMTG_ENABLE;
 	}
 
@@ -141,14 +141,14 @@ static void intel_cmtg_disable(struct intel_display *display,
 
 	if (cmtg_config->cmtg_a_enable) {
 		drm_dbg_kms(display->drm, "Disabling CMTG A\n");
-		intel_de_rmw(display, TRANS_CMTG_CTL_A, CMTG_ENABLE, 0);
+		intel_de_rmw(display, TRANS_CMTG_CTL(TRANSCODER_A), CMTG_ENABLE, 0);
 		clk_sel_clr |= CMTG_CLK_SEL_A_MASK;
 		clk_sel_set |= CMTG_CLK_SEL_A_DISABLED;
 	}
 
 	if (cmtg_config->cmtg_b_enable) {
 		drm_dbg_kms(display->drm, "Disabling CMTG B\n");
-		intel_de_rmw(display, TRANS_CMTG_CTL_B, CMTG_ENABLE, 0);
+		intel_de_rmw(display, TRANS_CMTG_CTL(TRANSCODER_B), CMTG_ENABLE, 0);
 		clk_sel_clr |= CMTG_CLK_SEL_B_MASK;
 		clk_sel_set |= CMTG_CLK_SEL_B_DISABLED;
 	}
@@ -339,3 +339,22 @@ void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state)
 	intel_de_write(display, PIPE_DATA_M1(display, cmtg_transcoder), m_n->link_m);
 	intel_de_write(display, PIPE_DATA_N1(display, cmtg_transcoder), m_n->link_n);
 }
+
+void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 cmtg_ctl;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	cmtg_ctl = CMTG_SYNC_TO_PORT | CMTG_ENABLE;
+
+	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), 0, cmtg_ctl);
+	if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder),
+				       CMTG_SYNC_TO_PORT, 50)) {
+		drm_WARN(display->drm, 1, "CMTG: %s enable timeout\n",
+			 transcoder_name(cpu_transcoder));
+	}
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 6796eb727eef..64ff6a19948a 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 4a80b88d88fd..a93236bf7b75 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -16,8 +16,11 @@
 #define CMTG_CLK_SELECT_PHYB_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0x6)
 #define CMTG_CLK_SEL_B_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
 
-#define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
-#define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
+#define _TRANS_CMTG_CTL_A		0x6fa88
+#define _TRANS_CMTG_CTL_B		0x6fb88
+#define TRANS_CMTG_CTL(trans)		_MMIO_TRANS((trans), \
+						    _TRANS_CMTG_CTL_A, _TRANS_CMTG_CTL_B)
 #define  CMTG_ENABLE			REG_BIT(31)
+#define  CMTG_SYNC_TO_PORT		REG_BIT(29)
 
 #endif /* __INTEL_CMTG_REGS_H__ */
-- 
2.29.0

[PATCH v6 08/16] drm/i915/cmtg: Add a hook to make eDP transcoder secondary

[Animesh Manna]

Program DDI_FUNC_CTL2 to configure the eDP transcoder as secondary
to the CMTG transcoder.

v2:
- Update commit header to be more clear. [Uma]

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h |  1 +
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 000b4957e546..a53049f6cbbd 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -358,3 +358,16 @@ void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
 			 transcoder_name(cpu_transcoder));
 	}
 }
+
+void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);
+
+	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 64ff6a19948a..12abbafa7d08 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
-- 
2.29.0

[PATCH v6 09/16] drm/i915/cmtg: Split CMTG support check from intel_cmtg_is_allowed()

[Animesh Manna]

Introduce a dedicated hook to check whether CMTG is supported. This
helper is used in both the enable and disable sequences, while
intel_cmtg_is_allowed() is now used only in enable path.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index a53049f6cbbd..99dce9506d5b 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -82,6 +82,18 @@ static void intel_cmtg_dump_config(struct intel_display *display,
 		    str_yes_no(cmtg_config->trans_b_secondary));
 }
 
+static bool intel_cmtg_is_supported(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B) &&
+	    DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+		return true;
+
+	return false;
+}
+
 static bool intel_cmtg_transcoder_is_secondary(struct intel_display *display,
 					       enum transcoder trans)
 {
@@ -190,10 +202,8 @@ void intel_cmtg_sanitize(struct intel_display *display)
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
-	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B) &&
-	    DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
+	if (intel_cmtg_is_supported(crtc_state) &&
 	    intel_display_power_get_current_dc_state(display) == DC_STATE_EN_DC3CO)
 		return true;
 
-- 
2.29.0

[PATCH v6 10/16] drm/i915/cmtg: Modify existing hook to disable CMTG

[Animesh Manna]

From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>

Earlier cmtg_disable() used to disable all instances of CMTG
which cannot handle individual request for specific CMTG instance.
Introduce cmtg_disable_all() which will disable all cmtg instances
and cmtg_disable() only disable specific instance.

v2:
- Use intel_de_rmw to simplify. [Uma]

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 55 ++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  1 +
 3 files changed, 42 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 99dce9506d5b..79238a99ca46 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -94,6 +94,18 @@ static bool intel_cmtg_is_supported(const struct intel_crtc_state *crtc_state)
 	return false;
 }
 
+static inline enum transcoder to_cmtg_transcoder(enum transcoder cpu_transcoder)
+{
+	switch (cpu_transcoder) {
+	case TRANSCODER_A:
+		return TRANSCODER_CMTG0;
+	case TRANSCODER_B:
+		return TRANSCODER_CMTG1;
+	default:
+		return INVALID_TRANSCODER;
+	}
+}
+
 static bool intel_cmtg_transcoder_is_secondary(struct intel_display *display,
 					       enum transcoder trans)
 {
@@ -137,8 +149,8 @@ static bool intel_cmtg_disable_requires_modeset(struct intel_display *display,
 	return cmtg_config->trans_a_secondary || cmtg_config->trans_b_secondary;
 }
 
-static void intel_cmtg_disable(struct intel_display *display,
-			       struct intel_cmtg_config *cmtg_config)
+static void intel_cmtg_disable_all(struct intel_display *display,
+				   struct intel_cmtg_config *cmtg_config)
 {
 	u32 clk_sel_clr = 0;
 	u32 clk_sel_set = 0;
@@ -169,6 +181,31 @@ static void intel_cmtg_disable(struct intel_display *display,
 		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
 }
 
+void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
+
+	if (!intel_cmtg_is_supported(crtc_state))
+		return;
+
+	intel_de_rmw(display, TRANS_VRR_CTL(display, cmtg_transcoder),
+		     VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN, 0);
+
+	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
+		     PORT_SYNC_MODE_ENABLE, 0);
+
+	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_ENABLE, 0);
+
+	if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_STATE, 50)) {
+		drm_WARN(display->drm, 1, "CMTG: %s disable timeout\n",
+			 transcoder_name(cpu_transcoder));
+		return;
+	}
+
+	drm_dbg_kms(display->drm, "CMTG: %s disabled\n", transcoder_name(cpu_transcoder));
+}
 /*
  * Read out CMTG configuration and, on platforms that allow disabling it without
  * a modeset, do it.
@@ -196,7 +233,7 @@ void intel_cmtg_sanitize(struct intel_display *display)
 	if (intel_cmtg_disable_requires_modeset(display, &cmtg_config))
 		return;
 
-	intel_cmtg_disable(display, &cmtg_config);
+	intel_cmtg_disable_all(display, &cmtg_config);
 }
 
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
@@ -232,18 +269,6 @@ void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
 		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
 }
 
-static inline enum transcoder to_cmtg_transcoder(enum transcoder cpu_transcoder)
-{
-	switch (cpu_transcoder) {
-	case TRANSCODER_A:
-		return TRANSCODER_CMTG0;
-	case TRANSCODER_B:
-		return TRANSCODER_CMTG1;
-	default:
-		return INVALID_TRANSCODER;
-	}
-}
-
 void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 12abbafa7d08..79785afccc51 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_disable(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index a93236bf7b75..240a02cd4a3a 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -22,5 +22,6 @@
 						    _TRANS_CMTG_CTL_A, _TRANS_CMTG_CTL_B)
 #define  CMTG_ENABLE			REG_BIT(31)
 #define  CMTG_SYNC_TO_PORT		REG_BIT(29)
+#define  CMTG_STATE			REG_BIT(23)
 
 #endif /* __INTEL_CMTG_REGS_H__ */
-- 
2.29.0

[PATCH v6 11/16] drm/i915/cmtg: Add CMTG interrupt handling

[Animesh Manna]

Add support fot vsync, vblank, and delayed vlank interrupts of
CMTG which are part of DE port interrupt.

v2:
- Use consistent DC3co check as used in earlier patches. [Uma]
- Use else-if instead of separate if block. [Uma]
- Merge mask and unmask function as it is similar. [Uma]
- Modify DISPLAY_VER() check. [Uma]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 42 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  2 +
 .../gpu/drm/i915/display/intel_display_irq.c  | 12 ++++++
 .../gpu/drm/i915/display/intel_display_regs.h |  6 +++
 4 files changed, 62 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 79238a99ca46..f069b8b46b9f 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -13,6 +13,7 @@
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_device.h"
+#include "intel_display_irq.h"
 #include "intel_display_power.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
@@ -406,3 +407,44 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
 
 	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
 }
+
+static void intel_cmtg_mask_interrupt(const struct intel_crtc_state *crtc_state, bool mask)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 interrupt_mask = 0;
+
+	if (!intel_cmtg_is_supported(crtc_state))
+		return;
+
+	if (cpu_transcoder == TRANSCODER_A)
+		interrupt_mask = CMTG_VBLANK_A | CMTG_DELAYED_VBLANK_A | CMTG_VSYNC_A;
+	else if (cpu_transcoder == TRANSCODER_B)
+		interrupt_mask = CMTG_VBLANK_B | CMTG_DELAYED_VBLANK_B | CMTG_VSYNC_B;
+
+	if (mask)
+		bdw_update_port_irq(display, interrupt_mask, 0);
+	else
+		bdw_update_port_irq(display, interrupt_mask, interrupt_mask);
+}
+
+void intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	spin_lock_irq(&display->irq.lock);
+	intel_cmtg_mask_interrupt(crtc_state, false);
+	spin_unlock_irq(&display->irq.lock);
+}
+
+void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	spin_lock_irq(&display->irq.lock);
+	intel_cmtg_mask_interrupt(crtc_state, true);
+	spin_unlock_irq(&display->irq.lock);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 79785afccc51..8fcb44d6398f 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -21,5 +21,7 @@ void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
 void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_CMTG_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index b5bfdebc66ca..cf5881d96587 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1467,6 +1467,18 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
 				found = true;
 			}
 
+			if (DISPLAY_VER(display) == 35) {
+				if (iir & (CMTG_VBLANK_A | CMTG_VSYNC_A | CMTG_DELAYED_VBLANK_A)) {
+					intel_handle_vblank(display, PIPE_A);
+					found = true;
+				}
+
+				if (iir & (CMTG_VBLANK_B | CMTG_VSYNC_B | CMTG_DELAYED_VBLANK_B)) {
+					intel_handle_vblank(display, PIPE_B);
+					found = true;
+				}
+			}
+
 			if (DISPLAY_VER(display) >= 11) {
 				u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index bc508995ad8b..a5ffe5420b0b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1458,6 +1458,12 @@
 #define  GEN9_AUX_CHANNEL_B		(1 << 25)
 #define  DSI1_TE			(1 << 24)
 #define  DSI0_TE			(1 << 23)
+#define  CMTG_VSYNC_B			(1 << 19)
+#define  CMTG_DELAYED_VBLANK_B		(1 << 18)
+#define  CMTG_VBLANK_B			(1 << 17)
+#define  CMTG_VSYNC_A			(1 << 16)
+#define  CMTG_DELAYED_VBLANK_A		(1 << 15)
+#define  CMTG_VBLANK_A			(1 << 14)
 #define  GEN8_DE_PORT_HOTPLUG(hpd_pin)	REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
 #define  BXT_DE_PORT_HOTPLUG_MASK	(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
 					 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
-- 
2.29.0

[PATCH v6 12/16] drm/i915/cmtg: Add CMTG HWGB programming

[Animesh Manna]

From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>

Program CMTG guardband to generate the Lower/Upper and early entry
guardband indicators to the DMC for DC3co control.

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 25 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  8 ++++++
 3 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index f069b8b46b9f..cd3b2d093017 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -448,3 +448,28 @@ void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state)
 	intel_cmtg_mask_interrupt(crtc_state, true);
 	spin_unlock_irq(&display->irq.lock);
 }
+
+void intel_cmtg_set_hwgb(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 breakeven_gb;
+	u32 dc5_exit_latency;
+	u32 line_time_us = 75;
+	u32 val;
+
+	if (crtc_state->linetime)
+		line_time_us = DIV_ROUND_UP(crtc_state->linetime, 8);
+
+	/* Break Even Guardband - DC3co Entry Latency / linetime )*/
+	breakeven_gb = DIV_ROUND_UP(55, line_time_us);
+
+	/* DC5 Exit Latency - DC3co Exit Latency / linetime ) */
+	dc5_exit_latency = DIV_ROUND_UP(40, line_time_us);
+
+	val = REG_FIELD_PREP(CMTG_HW_GB_BREAKEVEN_MASK, breakeven_gb) |
+	REG_FIELD_PREP(CMTG_HW_GB_DC5_EXIT_LATENCY_MASK, dc5_exit_latency) |
+	REG_FIELD_PREP(CMTG_HW_GB_UP_LW_BG_DIFF_MASK, 1);
+
+	intel_de_write(display, CMTG_HW_GB(cpu_transcoder), val);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 8fcb44d6398f..2c801a74acf9 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -23,5 +23,6 @@ void intel_cmtg_sanitize(struct intel_display *display);
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_set_hwgb(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_CMTG_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 240a02cd4a3a..6404f763bd52 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -24,4 +24,12 @@
 #define  CMTG_SYNC_TO_PORT		REG_BIT(29)
 #define  CMTG_STATE			REG_BIT(23)
 
+#define _CMTG_HW_GB_A				0x6FA8C
+#define _CMTG_HW_GB_B				0x6FB8C
+#define CMTG_HW_GB(trans)			_MMIO_TRANS((trans), \
+							    _CMTG_HW_GB_A, _CMTG_HW_GB_B)
+#define CMTG_HW_GB_BREAKEVEN_MASK		REG_GENMASK(11, 0)
+#define CMTG_HW_GB_DC5_EXIT_LATENCY_MASK	REG_GENMASK(27, 16)
+#define CMTG_HW_GB_UP_LW_BG_DIFF_MASK		REG_GENMASK(31, 28)
+
 #endif /* __INTEL_CMTG_REGS_H__ */
-- 
2.29.0

[PATCH v6 13/16] drm/i915/cmtg: Add CMTG scan line programming

[Animesh Manna]

From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>

Enable the hardware based guardband calculations which allows
DC3co to remain enabled when timings are changing from one fixed
refresh rate to another fixed refresh rate.

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c      | 1 +
 drivers/gpu/drm/i915/display/intel_cmtg_regs.h | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index cd3b2d093017..e30819eb6ea7 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -404,6 +404,7 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
 		return;
 
 	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);
+	intel_de_rmw(display, CMTG_SCANLINE_GB1(cpu_transcoder), 0, CMTG_HW_GB_ENABLE);
 
 	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
 }
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 6404f763bd52..275f57e5ee0b 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -32,4 +32,10 @@
 #define CMTG_HW_GB_DC5_EXIT_LATENCY_MASK	REG_GENMASK(27, 16)
 #define CMTG_HW_GB_UP_LW_BG_DIFF_MASK		REG_GENMASK(31, 28)
 
+#define _CMTG_SCANLINE_GB1_A		0x456A0
+#define _CMTG_SCANLINE_GB1_B		0x456C0
+#define CMTG_SCANLINE_GB1(trans)	_MMIO_TRANS((trans), \
+						    _CMTG_SCANLINE_GB1_A, _CMTG_SCANLINE_GB1_B)
+#define  CMTG_HW_GB_ENABLE		REG_BIT(31)
+
 #endif /* __INTEL_CMTG_REGS_H__ */
-- 
2.29.0

[PATCH v6 14/16] drm/i915/cmtg: Add trigger to enable/disable cmtg

[Animesh Manna]

Enable CMTG with fixed refresh rate mode and with dynamic
dc state enabled.

Disable CMTG with transcoder disable or if there is a transition
to vrr mode from fixed refresh rate mode.

v2:
- Move the enabled flag update to avoid issue in the disable timeout
path. [Uma]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     |  5 +++++
 drivers/gpu/drm/i915/display/intel_display.c  | 20 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  4 ++++
 3 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index e30819eb6ea7..f3ec4d9402a0 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -185,12 +185,15 @@ static void intel_cmtg_disable_all(struct intel_display *display,
 void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder);
 
 	if (!intel_cmtg_is_supported(crtc_state))
 		return;
 
+	crtc->cmtg.enabled = false;
+
 	intel_de_rmw(display, TRANS_VRR_CTL(display, cmtg_transcoder),
 		     VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN, 0);
 
@@ -398,6 +401,7 @@ void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
 void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 	if (!intel_cmtg_is_allowed(crtc_state))
@@ -406,6 +410,7 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
 	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);
 	intel_de_rmw(display, CMTG_SCANLINE_GB1(cpu_transcoder), 0, CMTG_HW_GB_ENABLE);
 
+	crtc->cmtg.enabled = true;
 	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index dd53049898ea..6dc561713c35 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1771,6 +1771,8 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
 	struct intel_crtc *pipe_crtc;
 	int i;
 
+	if (crtc->cmtg.enabled)
+		intel_cmtg_disable(old_crtc_state);
 	/*
 	 * FIXME collapse everything to one hook.
 	 * Need care with mst->ddi interactions.
@@ -6857,6 +6859,12 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 	if (intel_crtc_needs_fastset(new_crtc_state) &&
 	    old_crtc_state->inherited)
 		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
+
+	if (crtc->cmtg.enabled && (intel_crtc_vrr_enabling(state, crtc) ||
+				   !intel_cmtg_is_allowed(new_crtc_state))) {
+		intel_cmtg_disable(new_crtc_state);
+		intel_cmtg_disable_interrupt(new_crtc_state);
+	}
 }
 
 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
@@ -7534,6 +7542,18 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	/* FIXME probably need to sequence this properly */
 	intel_program_dpkgc_latency(state);
 
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		bool modeset = intel_crtc_needs_modeset(new_crtc_state);
+
+		/* CMTG needs to be restored on DC6 exit and on modset*/
+		if (modeset && new_crtc_state->hw.active && !crtc->cmtg.enabled) {
+			intel_cmtg_enable_sync(new_crtc_state);
+			intel_cmtg_set_hwgb(new_crtc_state);
+			intel_cmtg_enable_ddi(new_crtc_state);
+			intel_cmtg_enable_interrupt(new_crtc_state);
+		}
+	}
+
 	intel_wait_for_vblank_workers(state);
 
 	/* FIXME: We should call drm_atomic_helper_commit_hw_done() here
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 26e59110e743..0e627c7bf2b9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1571,6 +1571,10 @@ struct intel_crtc {
 #endif
 
 	bool vblank_psr_notify;
+
+	struct {
+		bool enabled;
+	} cmtg;
 };
 
 struct intel_plane_error {
-- 
2.29.0

[PATCH v6 15/16] drm/i915/cmtg: Restore CMTG after DC6 entry

[Animesh Manna]

Restore CMTG registers after DC6 exit, as they lose their values
in the low-power state.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 12 ++++++++-
 .../drm/i915/display/intel_display_power.c    | 25 +++++++++++++++++++
 .../drm/i915/display/intel_display_power.h    |  3 +++
 3 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6dc561713c35..324a2c722422 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7544,9 +7544,19 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
 		bool modeset = intel_crtc_needs_modeset(new_crtc_state);
+		bool dc3co_to_dc6 = intel_display_power_get_dc3co_to_dc6(display);
 
 		/* CMTG needs to be restored on DC6 exit and on modset*/
-		if (modeset && new_crtc_state->hw.active && !crtc->cmtg.enabled) {
+		if ((modeset || dc3co_to_dc6) && new_crtc_state->hw.active && !crtc->cmtg.enabled) {
+			if (dc3co_to_dc6) {
+				intel_cmtg_set_clk_select(new_crtc_state);
+				intel_cmtg_set_timings(new_crtc_state, false);
+				intel_cmtg_set_vrr_timings(new_crtc_state);
+				intel_cmtg_set_vrr_ctl(new_crtc_state);
+				intel_cmtg_set_m_n(new_crtc_state);
+				intel_display_power_reset_dc3co_to_dc6(display);
+			}
+
 			intel_cmtg_enable_sync(new_crtc_state);
 			intel_cmtg_set_hwgb(new_crtc_state);
 			intel_cmtg_enable_ddi(new_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 80ecf373fb19..a0ea46895e2e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -285,6 +285,27 @@ sanitize_target_dc_state(struct intel_display *display,
 	return target_dc_state;
 }
 
+bool intel_display_power_get_dc3co_to_dc6(struct intel_display *display)
+{
+	struct i915_power_domains *power_domains = &display->power.domains;
+	bool ret;
+
+	mutex_lock(&power_domains->lock);
+	ret = power_domains->dc3co_to_dc6;
+	mutex_unlock(&power_domains->lock);
+
+	return ret;
+}
+
+void intel_display_power_reset_dc3co_to_dc6(struct intel_display *display)
+{
+	struct i915_power_domains *power_domains = &display->power.domains;
+
+	mutex_lock(&power_domains->lock);
+	power_domains->dc3co_to_dc6 = false;
+	mutex_unlock(&power_domains->lock);
+}
+
 /**
  * intel_display_power_set_target_dc_state - Set target dc state.
  * @display: display device
@@ -320,6 +341,10 @@ void intel_display_power_set_target_dc_state(struct intel_display *display,
 	if (!dc_off_enabled)
 		intel_power_well_enable(display, power_well);
 
+	if (power_domains->target_dc_state == DC_STATE_EN_DC3CO &&
+	    state == DC_STATE_EN_UPTO_DC6)
+		power_domains->dc3co_to_dc6 = true;
+
 	power_domains->target_dc_state = state;
 
 	if (!dc_off_enabled)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index d616d5d09cbe..ce1225bbc789 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -138,6 +138,7 @@ struct i915_power_domains {
 	 */
 	bool initializing;
 	bool display_core_suspended;
+	bool dc3co_to_dc6;
 	int power_well_count;
 
 	u32 dc_state;
@@ -183,6 +184,8 @@ void intel_display_power_suspend_late(struct intel_display *display, bool s2idle
 void intel_display_power_resume_early(struct intel_display *display);
 void intel_display_power_suspend(struct intel_display *display);
 void intel_display_power_resume(struct intel_display *display);
+bool intel_display_power_get_dc3co_to_dc6(struct intel_display *display);
+void intel_display_power_reset_dc3co_to_dc6(struct intel_display *display);
 void intel_display_power_set_target_dc_state(struct intel_display *display,
 					     u32 state);
 u32 intel_display_power_get_current_dc_state(struct intel_display *display);
-- 
2.29.0

Re: [PATCH v6 15/16] drm/i915/cmtg: Restore CMTG after DC6 entry

[Dibin Moolakadan Subrahmanian]

On 13-05-2026 22:08, Animesh Manna wrote:
> Restore CMTG registers after DC6 exit, as they lose their values
> in the low-power state.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_display.c  | 12 ++++++++-
>   .../drm/i915/display/intel_display_power.c    | 25 +++++++++++++++++++
>   .../drm/i915/display/intel_display_power.h    |  3 +++
>   3 files changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6dc561713c35..324a2c722422 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7544,9 +7544,19 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>   
>   	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>   		bool modeset = intel_crtc_needs_modeset(new_crtc_state);
> +		bool dc3co_to_dc6 = intel_display_power_get_dc3co_to_dc6(display);
>   
>   		/* CMTG needs to be restored on DC6 exit and on modset*/
> -		if (modeset && new_crtc_state->hw.active && !crtc->cmtg.enabled) {
> +		if ((modeset || dc3co_to_dc6) && new_crtc_state->hw.active && !crtc->cmtg.enabled) {
> +			if (dc3co_to_dc6) {
> +				intel_cmtg_set_clk_select(new_crtc_state);
> +				intel_cmtg_set_timings(new_crtc_state, false);

In the restore path, will the `lrr` argument always be false?
In patch 4, the same function is called with `lrr = true`.

> +				intel_cmtg_set_vrr_timings(new_crtc_state);
> +				intel_cmtg_set_vrr_ctl(new_crtc_state);
> +				intel_cmtg_set_m_n(new_crtc_state);
> +				intel_display_power_reset_dc3co_to_dc6(display);
> +			}
> +
>   			intel_cmtg_enable_sync(new_crtc_state);

As this path also executes after DC6 exit, please also follow the BSpec
CMTG enable sequence for the PSR2 deep sleep case.

CMTG will not start running until PSR2 deep sleep exit completes, so this
sequence can fail here for the non-modeset case.

>   			intel_cmtg_set_hwgb(new_crtc_state);
>   			intel_cmtg_enable_ddi(new_crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 80ecf373fb19..a0ea46895e2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -285,6 +285,27 @@ sanitize_target_dc_state(struct intel_display *display,
>   	return target_dc_state;
>   }
>   
> +bool intel_display_power_get_dc3co_to_dc6(struct intel_display *display)
> +{
> +	struct i915_power_domains *power_domains = &display->power.domains;
> +	bool ret;
> +
> +	mutex_lock(&power_domains->lock);
> +	ret = power_domains->dc3co_to_dc6;
> +	mutex_unlock(&power_domains->lock);
> +
> +	return ret;
> +}
> +
> +void intel_display_power_reset_dc3co_to_dc6(struct intel_display *display)
> +{
> +	struct i915_power_domains *power_domains = &display->power.domains;
> +
> +	mutex_lock(&power_domains->lock);
> +	power_domains->dc3co_to_dc6 = false;
> +	mutex_unlock(&power_domains->lock);
> +}
> +
>   /**
>    * intel_display_power_set_target_dc_state - Set target dc state.
>    * @display: display device
> @@ -320,6 +341,10 @@ void intel_display_power_set_target_dc_state(struct intel_display *display,
>   	if (!dc_off_enabled)
>   		intel_power_well_enable(display, power_well);
>   
> +	if (power_domains->target_dc_state == DC_STATE_EN_DC3CO &&
> +	    state == DC_STATE_EN_UPTO_DC6)
> +		power_domains->dc3co_to_dc6 = true;
> +

This only updates the software target DC state and does not guarantee an
actual DC6 entry or exit.
If the intent is to detect a real DC6 exit transition, then
gen9_disable_dc_states() looks like the more appropriate place for this.
I can also see existing PHY restore related comments there.

>   	power_domains->target_dc_state = state;
>   
>   	if (!dc_off_enabled)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index d616d5d09cbe..ce1225bbc789 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -138,6 +138,7 @@ struct i915_power_domains {
>   	 */
>   	bool initializing;
>   	bool display_core_suspended;
> +	bool dc3co_to_dc6;
>   	int power_well_count;
>   
>   	u32 dc_state;
> @@ -183,6 +184,8 @@ void intel_display_power_suspend_late(struct intel_display *display, bool s2idle
>   void intel_display_power_resume_early(struct intel_display *display);
>   void intel_display_power_suspend(struct intel_display *display);
>   void intel_display_power_resume(struct intel_display *display);
> +bool intel_display_power_get_dc3co_to_dc6(struct intel_display *display);
> +void intel_display_power_reset_dc3co_to_dc6(struct intel_display *display);
>   void intel_display_power_set_target_dc_state(struct intel_display *display,
>   					     u32 state);
>   u32 intel_display_power_get_current_dc_state(struct intel_display *display);

RE: [PATCH v6 15/16] drm/i915/cmtg: Restore CMTG after DC6 entry

[Manna, Animesh]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Thursday, May 21, 2026 5:17 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; ville.syrjala@linux.intel.com;
> Nikula, Jani <jani.nikula@intel.com>
> Subject: Re: [PATCH v6 15/16] drm/i915/cmtg: Restore CMTG after DC6 entry
> 
> 
> On 13-05-2026 22:08, Animesh Manna wrote:
> > Restore CMTG registers after DC6 exit, as they lose their values in
> > the low-power state.
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_display.c  | 12 ++++++++-
> >   .../drm/i915/display/intel_display_power.c    | 25 +++++++++++++++++++
> >   .../drm/i915/display/intel_display_power.h    |  3 +++
> >   3 files changed, 39 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 6dc561713c35..324a2c722422 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -7544,9 +7544,19 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> >
> >   	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> >   		bool modeset = intel_crtc_needs_modeset(new_crtc_state);
> > +		bool dc3co_to_dc6 =
> intel_display_power_get_dc3co_to_dc6(display);
> >
> >   		/* CMTG needs to be restored on DC6 exit and on modset*/
> > -		if (modeset && new_crtc_state->hw.active && !crtc-
> >cmtg.enabled) {
> > +		if ((modeset || dc3co_to_dc6) && new_crtc_state->hw.active
> && !crtc->cmtg.enabled) {
> > +			if (dc3co_to_dc6) {
> > +				intel_cmtg_set_clk_select(new_crtc_state);
> > +				intel_cmtg_set_timings(new_crtc_state,
> false);
> 
> In the restore path, will the `lrr` argument always be false?
> In patch 4, the same function is called with `lrr = true`.

During lrr mode it will be true, otherwise always false.

> 
> > +				intel_cmtg_set_vrr_timings(new_crtc_state);
> > +				intel_cmtg_set_vrr_ctl(new_crtc_state);
> > +				intel_cmtg_set_m_n(new_crtc_state);
> > +
> 	intel_display_power_reset_dc3co_to_dc6(display);
> > +			}
> > +
> >   			intel_cmtg_enable_sync(new_crtc_state);
> 
> As this path also executes after DC6 exit, please also follow the BSpec CMTG
> enable sequence for the PSR2 deep sleep case.

In PSR2 deep sleep case target_dc_state will be set to DC6 which should restrict CMTG access.

> 
> CMTG will not start running until PSR2 deep sleep exit completes, so this
> sequence can fail here for the non-modeset case.

Once PSR2 deep exit is completed then only we should set target_dc_state to Dc3co.

> 
> >   			intel_cmtg_set_hwgb(new_crtc_state);
> >   			intel_cmtg_enable_ddi(new_crtc_state);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 80ecf373fb19..a0ea46895e2e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -285,6 +285,27 @@ sanitize_target_dc_state(struct intel_display
> *display,
> >   	return target_dc_state;
> >   }
> >
> > +bool intel_display_power_get_dc3co_to_dc6(struct intel_display
> > +*display) {
> > +	struct i915_power_domains *power_domains = &display-
> >power.domains;
> > +	bool ret;
> > +
> > +	mutex_lock(&power_domains->lock);
> > +	ret = power_domains->dc3co_to_dc6;
> > +	mutex_unlock(&power_domains->lock);
> > +
> > +	return ret;
> > +}
> > +
> > +void intel_display_power_reset_dc3co_to_dc6(struct intel_display
> > +*display) {
> > +	struct i915_power_domains *power_domains = &display-
> >power.domains;
> > +
> > +	mutex_lock(&power_domains->lock);
> > +	power_domains->dc3co_to_dc6 = false;
> > +	mutex_unlock(&power_domains->lock);
> > +}
> > +
> >   /**
> >    * intel_display_power_set_target_dc_state - Set target dc state.
> >    * @display: display device
> > @@ -320,6 +341,10 @@ void
> intel_display_power_set_target_dc_state(struct intel_display *display,
> >   	if (!dc_off_enabled)
> >   		intel_power_well_enable(display, power_well);
> >
> > +	if (power_domains->target_dc_state == DC_STATE_EN_DC3CO &&
> > +	    state == DC_STATE_EN_UPTO_DC6)
> > +		power_domains->dc3co_to_dc6 = true;
> > +
> 
> This only updates the software target DC state and does not guarantee an
> actual DC6 entry or exit.
> If the intent is to detect a real DC6 exit transition, then
> gen9_disable_dc_states() looks like the more appropriate place for this.
> I can also see existing PHY restore related comments there.

From driver we are just allowing Dc-state, actual entry/exit is controlled by DMC.
I need both current requested state and previous dc-state so added here.

Regards,
Animesh

> 
> >   	power_domains->target_dc_state = state;
> >
> >   	if (!dc_off_enabled)
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> > b/drivers/gpu/drm/i915/display/intel_display_power.h
> > index d616d5d09cbe..ce1225bbc789 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> > @@ -138,6 +138,7 @@ struct i915_power_domains {
> >   	 */
> >   	bool initializing;
> >   	bool display_core_suspended;
> > +	bool dc3co_to_dc6;
> >   	int power_well_count;
> >
> >   	u32 dc_state;
> > @@ -183,6 +184,8 @@ void intel_display_power_suspend_late(struct
> intel_display *display, bool s2idle
> >   void intel_display_power_resume_early(struct intel_display *display);
> >   void intel_display_power_suspend(struct intel_display *display);
> >   void intel_display_power_resume(struct intel_display *display);
> > +bool intel_display_power_get_dc3co_to_dc6(struct intel_display
> > +*display); void intel_display_power_reset_dc3co_to_dc6(struct
> > +intel_display *display);
> >   void intel_display_power_set_target_dc_state(struct intel_display
> *display,
> >   					     u32 state);
> >   u32 intel_display_power_get_current_dc_state(struct intel_display
> > *display);

[PATCH v6 16/16] [NOT FOR REVIEW] debug patch

[Animesh Manna]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c | 24 ++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index f3ec4d9402a0..dd85a7ec7ecf 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -242,10 +242,11 @@ void intel_cmtg_sanitize(struct intel_display *display)
 
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
+	//struct intel_display *display = to_intel_display(crtc_state);
 
-	if (intel_cmtg_is_supported(crtc_state) &&
-	    intel_display_power_get_current_dc_state(display) == DC_STATE_EN_DC3CO)
+	//if (intel_cmtg_is_supported(crtc_state) &&
+	//    intel_display_power_get_current_dc_state(display) == DC_STATE_EN_DC3CO)
+	if (intel_cmtg_is_supported(crtc_state))
 		return true;
 
 	return false;
@@ -331,6 +332,14 @@ void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
 		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
 	intel_de_write(display, TRANS_SET_CONTEXT_LATENCY(display, cmtg_transcoder),
 		       crtc_state->set_context_latency);
+
+	drm_dbg_kms(display->drm, "0x%x\n", INTEL_DISPLAY_DEVICE_TRANS_OFFSET(display, cmtg_transcoder));
+	drm_dbg_kms(display->drm, "0x%x\n", TRANS_HTOTAL(display, cmtg_transcoder).reg);
+	drm_dbg_kms(display->drm, "0x%x\n", TRANS_HBLANK(display, cmtg_transcoder).reg);
+	drm_dbg_kms(display->drm, "0x%x\n", TRANS_HSYNC(display, cmtg_transcoder).reg);
+	drm_dbg_kms(display->drm, "0x%x\n", TRANS_VTOTAL(display, cmtg_transcoder).reg);
+	drm_dbg_kms(display->drm, "0x%x\n", TRANS_VBLANK(display, cmtg_transcoder).reg);
+	drm_dbg_kms(display->drm, "0x%x\n", TRANS_VSYNC(display, cmtg_transcoder).reg);
 }
 
 void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state)
@@ -345,6 +354,10 @@ void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state)
 	intel_de_write(display, TRANS_VRR_VMAX(display, cmtg_transcoder), crtc_state->vrr.vmax - 1);
 	intel_de_write(display, TRANS_VRR_FLIPLINE(display, cmtg_transcoder),
 		       crtc_state->vrr.flipline - 1);
+
+	drm_dbg_kms(display->drm, "0x%x, 0x%x\n", TRANS_VRR_VMIN(display, cmtg_transcoder).reg, crtc_state->vrr.vmin - 1);
+	drm_dbg_kms(display->drm, "0x%x, 0x%x\n", TRANS_VRR_VMAX(display, cmtg_transcoder).reg, crtc_state->vrr.vmax - 1);
+	drm_dbg_kms(display->drm, "0x%x, 0x%x\n", TRANS_VRR_FLIPLINE(display, cmtg_transcoder).reg, crtc_state->vrr.flipline - 1);
 }
 
 void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
@@ -364,6 +377,7 @@ void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
 		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
 
 	intel_de_write(display, TRANS_VRR_CTL(display, cmtg_transcoder), vrr_ctl);
+	drm_dbg_kms(display->drm, "0x%x, 0x%x\n", TRANS_VRR_CTL(display, cmtg_transcoder).reg, vrr_ctl);
 }
 
 void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state)
@@ -377,6 +391,8 @@ void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state)
 
 	intel_de_write(display, PIPE_DATA_M1(display, cmtg_transcoder), m_n->link_m);
 	intel_de_write(display, PIPE_DATA_N1(display, cmtg_transcoder), m_n->link_n);
+	drm_dbg_kms(display->drm, "0x%x, 0x%x\n", PIPE_DATA_M1(display, cmtg_transcoder).reg, m_n->link_m);
+	drm_dbg_kms(display->drm, "0x%x, 0x%x\n", PIPE_DATA_N1(display, cmtg_transcoder).reg, m_n->link_n);
 }
 
 void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
@@ -391,6 +407,7 @@ void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
 	cmtg_ctl = CMTG_SYNC_TO_PORT | CMTG_ENABLE;
 
 	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), 0, cmtg_ctl);
+	drm_dbg_kms(display->drm, "0x%x, 0x%x\n", TRANS_CMTG_CTL(cpu_transcoder).reg, cmtg_ctl);
 	if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder),
 				       CMTG_SYNC_TO_PORT, 50)) {
 		drm_WARN(display->drm, 1, "CMTG: %s enable timeout\n",
@@ -478,4 +495,5 @@ void intel_cmtg_set_hwgb(const struct intel_crtc_state *crtc_state)
 	REG_FIELD_PREP(CMTG_HW_GB_UP_LW_BG_DIFF_MASK, 1);
 
 	intel_de_write(display, CMTG_HW_GB(cpu_transcoder), val);
+	drm_dbg_kms(display->drm, "0x%x, 0x%x\n", CMTG_HW_GB(cpu_transcoder).reg, val);
 }
-- 
2.29.0

✗ CI.checkpatch: warning for CMTG enablement (rev7)

[Patchwork]

== Series Details ==

Series: CMTG enablement (rev7)
URL   : https://patchwork.freedesktop.org/series/157663/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
061140b9bc586ae7f40abc1249c97e1cc72d1b9d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 9ae8b54527ff539ef61366cc6efb3b1e119281ef
Author: Animesh Manna <animesh.manna@intel.com>
Date:   Wed May 13 22:08:57 2026 +0530

    debug patch
    
    Signed-off-by: Animesh Manna <animesh.manna@intel.com>
+ /mt/dim checkpatch 848634197d2738329d56c588df7cd8f21c0f7568 drm-intel
e2cc46ce878e drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG
bab6f74badf6 drm/i915/cmtg: Set CMTG clock select
423f7e25fc75 drm/i915/cmtg: Add cmtg transcoder offset in struct _device_info
b0bdad27f800 drm/i915/cmtg: Set timings for CMTG
6f10adbe80e7 drm/i915/cmtg: Program VRR registers of CMTG
08662491fe34 drm/i915/cmtg: Set transcoder mn for CMTG
647f628e5d27 drm/i915/cmtg: Add hook to enable CMTG with sync to port
60bd17c13d2c drm/i915/cmtg: Add a hook to make eDP transcoder secondary
6e6e1e0d9ea8 drm/i915/cmtg: Split CMTG support check from intel_cmtg_is_allowed()
3e62465a6b20 drm/i915/cmtg: Modify existing hook to disable CMTG
52dae93bc3f8 drm/i915/cmtg: Add CMTG interrupt handling
93c53fabbefd drm/i915/cmtg: Add CMTG HWGB programming
cbe71baeadcc drm/i915/cmtg: Add CMTG scan line programming
6735a09bcae7 drm/i915/cmtg: Add trigger to enable/disable cmtg
94cb3d92cb5d drm/i915/cmtg: Restore CMTG after DC6 entry
9ae8b54527ff debug patch
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:32: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#32: FILE: drivers/gpu/drm/i915/display/intel_cmtg.c:336:
+	drm_dbg_kms(display->drm, "0x%x\n", INTEL_DISPLAY_DEVICE_TRANS_OFFSET(display, cmtg_transcoder));

-:47: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#47: FILE: drivers/gpu/drm/i915/display/intel_cmtg.c:358:
+	drm_dbg_kms(display->drm, "0x%x, 0x%x\n", TRANS_VRR_VMIN(display, cmtg_transcoder).reg, crtc_state->vrr.vmin - 1);

-:48: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#48: FILE: drivers/gpu/drm/i915/display/intel_cmtg.c:359:
+	drm_dbg_kms(display->drm, "0x%x, 0x%x\n", TRANS_VRR_VMAX(display, cmtg_transcoder).reg, crtc_state->vrr.vmax - 1);

-:49: WARNING:LONG_LINE: line length of 130 exceeds 100 columns
#49: FILE: drivers/gpu/drm/i915/display/intel_cmtg.c:360:
+	drm_dbg_kms(display->drm, "0x%x, 0x%x\n", TRANS_VRR_FLIPLINE(display, cmtg_transcoder).reg, crtc_state->vrr.flipline - 1);

-:57: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#57: FILE: drivers/gpu/drm/i915/display/intel_cmtg.c:380:
+	drm_dbg_kms(display->drm, "0x%x, 0x%x\n", TRANS_VRR_CTL(display, cmtg_transcoder).reg, vrr_ctl);

-:65: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#65: FILE: drivers/gpu/drm/i915/display/intel_cmtg.c:394:
+	drm_dbg_kms(display->drm, "0x%x, 0x%x\n", PIPE_DATA_M1(display, cmtg_transcoder).reg, m_n->link_m);

-:66: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#66: FILE: drivers/gpu/drm/i915/display/intel_cmtg.c:395:
+	drm_dbg_kms(display->drm, "0x%x, 0x%x\n", PIPE_DATA_N1(display, cmtg_transcoder).reg, m_n->link_n);

total: 0 errors, 8 warnings, 0 checks, 65 lines checked

✓ CI.KUnit: success for CMTG enablement (rev7)

[Patchwork]

== Series Details ==

Series: CMTG enablement (rev7)
URL   : https://patchwork.freedesktop.org/series/157663/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[17:58:50] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:58:55] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:59:26] Starting KUnit Kernel (1/1)...
[17:59:26] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:59:26] ================== guc_buf (11 subtests) ===================
[17:59:26] [PASSED] test_smallest
[17:59:26] [PASSED] test_largest
[17:59:26] [PASSED] test_granular
[17:59:26] [PASSED] test_unique
[17:59:26] [PASSED] test_overlap
[17:59:26] [PASSED] test_reusable
[17:59:26] [PASSED] test_too_big
[17:59:26] [PASSED] test_flush
[17:59:26] [PASSED] test_lookup
[17:59:26] [PASSED] test_data
[17:59:26] [PASSED] test_class
[17:59:26] ===================== [PASSED] guc_buf =====================
[17:59:26] =================== guc_dbm (7 subtests) ===================
[17:59:26] [PASSED] test_empty
[17:59:26] [PASSED] test_default
[17:59:26] ======================== test_size  ========================
[17:59:26] [PASSED] 4
[17:59:26] [PASSED] 8
[17:59:26] [PASSED] 32
[17:59:26] [PASSED] 256
[17:59:26] ==================== [PASSED] test_size ====================
[17:59:26] ======================= test_reuse  ========================
[17:59:26] [PASSED] 4
[17:59:26] [PASSED] 8
[17:59:26] [PASSED] 32
[17:59:26] [PASSED] 256
[17:59:26] =================== [PASSED] test_reuse ====================
[17:59:26] =================== test_range_overlap  ====================
[17:59:26] [PASSED] 4
[17:59:26] [PASSED] 8
[17:59:26] [PASSED] 32
[17:59:26] [PASSED] 256
[17:59:26] =============== [PASSED] test_range_overlap ================
[17:59:26] =================== test_range_compact  ====================
[17:59:26] [PASSED] 4
[17:59:26] [PASSED] 8
[17:59:26] [PASSED] 32
[17:59:26] [PASSED] 256
[17:59:26] =============== [PASSED] test_range_compact ================
[17:59:26] ==================== test_range_spare  =====================
[17:59:26] [PASSED] 4
[17:59:26] [PASSED] 8
[17:59:26] [PASSED] 32
[17:59:26] [PASSED] 256
[17:59:26] ================ [PASSED] test_range_spare =================
[17:59:26] ===================== [PASSED] guc_dbm =====================
[17:59:26] =================== guc_idm (6 subtests) ===================
[17:59:26] [PASSED] bad_init
[17:59:26] [PASSED] no_init
[17:59:26] [PASSED] init_fini
[17:59:26] [PASSED] check_used
[17:59:26] [PASSED] check_quota
[17:59:26] [PASSED] check_all
[17:59:26] ===================== [PASSED] guc_idm =====================
[17:59:26] ================== no_relay (3 subtests) ===================
[17:59:26] [PASSED] xe_drops_guc2pf_if_not_ready
[17:59:26] [PASSED] xe_drops_guc2vf_if_not_ready
[17:59:26] [PASSED] xe_rejects_send_if_not_ready
[17:59:26] ==================== [PASSED] no_relay =====================
[17:59:26] ================== pf_relay (14 subtests) ==================
[17:59:26] [PASSED] pf_rejects_guc2pf_too_short
[17:59:26] [PASSED] pf_rejects_guc2pf_too_long
[17:59:26] [PASSED] pf_rejects_guc2pf_no_payload
[17:59:26] [PASSED] pf_fails_no_payload
[17:59:26] [PASSED] pf_fails_bad_origin
[17:59:26] [PASSED] pf_fails_bad_type
[17:59:26] [PASSED] pf_txn_reports_error
[17:59:26] [PASSED] pf_txn_sends_pf2guc
[17:59:26] [PASSED] pf_sends_pf2guc
[17:59:26] [SKIPPED] pf_loopback_nop
[17:59:26] [SKIPPED] pf_loopback_echo
[17:59:26] [SKIPPED] pf_loopback_fail
[17:59:26] [SKIPPED] pf_loopback_busy
[17:59:26] [SKIPPED] pf_loopback_retry
[17:59:26] ==================== [PASSED] pf_relay =====================
[17:59:26] ================== vf_relay (3 subtests) ===================
[17:59:26] [PASSED] vf_rejects_guc2vf_too_short
[17:59:26] [PASSED] vf_rejects_guc2vf_too_long
[17:59:26] [PASSED] vf_rejects_guc2vf_no_payload
[17:59:26] ==================== [PASSED] vf_relay =====================
[17:59:26] ================ pf_gt_config (9 subtests) =================
[17:59:26] [PASSED] fair_contexts_1vf
[17:59:26] [PASSED] fair_doorbells_1vf
[17:59:26] [PASSED] fair_ggtt_1vf
[17:59:26] ====================== fair_vram_1vf  ======================
[17:59:26] [PASSED] 3.50 GiB
[17:59:26] [PASSED] 11.5 GiB
[17:59:26] [PASSED] 15.5 GiB
[17:59:26] [PASSED] 31.5 GiB
[17:59:26] [PASSED] 63.5 GiB
[17:59:26] [PASSED] 1.91 GiB
[17:59:26] ================== [PASSED] fair_vram_1vf ==================
[17:59:26] ================ fair_vram_1vf_admin_only  =================
[17:59:26] [PASSED] 3.50 GiB
[17:59:26] [PASSED] 11.5 GiB
[17:59:26] [PASSED] 15.5 GiB
[17:59:26] [PASSED] 31.5 GiB
[17:59:26] [PASSED] 63.5 GiB
[17:59:26] [PASSED] 1.91 GiB
[17:59:26] ============ [PASSED] fair_vram_1vf_admin_only =============
[17:59:26] ====================== fair_contexts  ======================
[17:59:26] [PASSED] 1 VF
[17:59:26] [PASSED] 2 VFs
[17:59:26] [PASSED] 3 VFs
[17:59:26] [PASSED] 4 VFs
[17:59:26] [PASSED] 5 VFs
[17:59:26] [PASSED] 6 VFs
[17:59:26] [PASSED] 7 VFs
[17:59:26] [PASSED] 8 VFs
[17:59:26] [PASSED] 9 VFs
[17:59:26] [PASSED] 10 VFs
[17:59:26] [PASSED] 11 VFs
[17:59:26] [PASSED] 12 VFs
[17:59:26] [PASSED] 13 VFs
[17:59:26] [PASSED] 14 VFs
[17:59:26] [PASSED] 15 VFs
[17:59:26] [PASSED] 16 VFs
[17:59:26] [PASSED] 17 VFs
[17:59:26] [PASSED] 18 VFs
[17:59:26] [PASSED] 19 VFs
[17:59:26] [PASSED] 20 VFs
[17:59:26] [PASSED] 21 VFs
[17:59:26] [PASSED] 22 VFs
[17:59:26] [PASSED] 23 VFs
[17:59:26] [PASSED] 24 VFs
[17:59:26] [PASSED] 25 VFs
[17:59:26] [PASSED] 26 VFs
[17:59:26] [PASSED] 27 VFs
[17:59:26] [PASSED] 28 VFs
[17:59:26] [PASSED] 29 VFs
[17:59:26] [PASSED] 30 VFs
[17:59:26] [PASSED] 31 VFs
[17:59:26] [PASSED] 32 VFs
[17:59:26] [PASSED] 33 VFs
[17:59:26] [PASSED] 34 VFs
[17:59:26] [PASSED] 35 VFs
[17:59:26] [PASSED] 36 VFs
[17:59:26] [PASSED] 37 VFs
[17:59:26] [PASSED] 38 VFs
[17:59:26] [PASSED] 39 VFs
[17:59:26] [PASSED] 40 VFs
[17:59:26] [PASSED] 41 VFs
[17:59:26] [PASSED] 42 VFs
[17:59:26] [PASSED] 43 VFs
[17:59:26] [PASSED] 44 VFs
[17:59:26] [PASSED] 45 VFs
[17:59:26] [PASSED] 46 VFs
[17:59:26] [PASSED] 47 VFs
[17:59:26] [PASSED] 48 VFs
[17:59:26] [PASSED] 49 VFs
[17:59:26] [PASSED] 50 VFs
[17:59:26] [PASSED] 51 VFs
[17:59:26] [PASSED] 52 VFs
[17:59:26] [PASSED] 53 VFs
[17:59:26] [PASSED] 54 VFs
[17:59:26] [PASSED] 55 VFs
[17:59:26] [PASSED] 56 VFs
[17:59:26] [PASSED] 57 VFs
[17:59:26] [PASSED] 58 VFs
[17:59:26] [PASSED] 59 VFs
[17:59:26] [PASSED] 60 VFs
[17:59:26] [PASSED] 61 VFs
[17:59:26] [PASSED] 62 VFs
[17:59:26] [PASSED] 63 VFs
[17:59:26] ================== [PASSED] fair_contexts ==================
[17:59:26] ===================== fair_doorbells  ======================
[17:59:26] [PASSED] 1 VF
[17:59:26] [PASSED] 2 VFs
[17:59:26] [PASSED] 3 VFs
[17:59:26] [PASSED] 4 VFs
[17:59:26] [PASSED] 5 VFs
[17:59:26] [PASSED] 6 VFs
[17:59:26] [PASSED] 7 VFs
[17:59:26] [PASSED] 8 VFs
[17:59:26] [PASSED] 9 VFs
[17:59:26] [PASSED] 10 VFs
[17:59:26] [PASSED] 11 VFs
[17:59:26] [PASSED] 12 VFs
[17:59:26] [PASSED] 13 VFs
[17:59:26] [PASSED] 14 VFs
[17:59:26] [PASSED] 15 VFs
[17:59:26] [PASSED] 16 VFs
[17:59:26] [PASSED] 17 VFs
[17:59:26] [PASSED] 18 VFs
[17:59:26] [PASSED] 19 VFs
[17:59:26] [PASSED] 20 VFs
[17:59:26] [PASSED] 21 VFs
[17:59:26] [PASSED] 22 VFs
[17:59:26] [PASSED] 23 VFs
[17:59:26] [PASSED] 24 VFs
[17:59:26] [PASSED] 25 VFs
[17:59:26] [PASSED] 26 VFs
[17:59:26] [PASSED] 27 VFs
[17:59:26] [PASSED] 28 VFs
[17:59:26] [PASSED] 29 VFs
[17:59:26] [PASSED] 30 VFs
[17:59:26] [PASSED] 31 VFs
[17:59:26] [PASSED] 32 VFs
[17:59:26] [PASSED] 33 VFs
[17:59:26] [PASSED] 34 VFs
[17:59:26] [PASSED] 35 VFs
[17:59:26] [PASSED] 36 VFs
[17:59:26] [PASSED] 37 VFs
[17:59:26] [PASSED] 38 VFs
[17:59:26] [PASSED] 39 VFs
[17:59:26] [PASSED] 40 VFs
[17:59:26] [PASSED] 41 VFs
[17:59:26] [PASSED] 42 VFs
[17:59:26] [PASSED] 43 VFs
[17:59:26] [PASSED] 44 VFs
[17:59:26] [PASSED] 45 VFs
[17:59:26] [PASSED] 46 VFs
[17:59:26] [PASSED] 47 VFs
[17:59:26] [PASSED] 48 VFs
[17:59:26] [PASSED] 49 VFs
[17:59:26] [PASSED] 50 VFs
[17:59:26] [PASSED] 51 VFs
[17:59:26] [PASSED] 52 VFs
[17:59:26] [PASSED] 53 VFs
[17:59:26] [PASSED] 54 VFs
[17:59:26] [PASSED] 55 VFs
[17:59:26] [PASSED] 56 VFs
[17:59:26] [PASSED] 57 VFs
[17:59:26] [PASSED] 58 VFs
[17:59:26] [PASSED] 59 VFs
[17:59:26] [PASSED] 60 VFs
[17:59:26] [PASSED] 61 VFs
[17:59:26] [PASSED] 62 VFs
[17:59:26] [PASSED] 63 VFs
[17:59:26] ================= [PASSED] fair_doorbells ==================
[17:59:26] ======================== fair_ggtt  ========================
[17:59:26] [PASSED] 1 VF
[17:59:26] [PASSED] 2 VFs
[17:59:26] [PASSED] 3 VFs
[17:59:26] [PASSED] 4 VFs
[17:59:26] [PASSED] 5 VFs
[17:59:26] [PASSED] 6 VFs
[17:59:26] [PASSED] 7 VFs
[17:59:26] [PASSED] 8 VFs
[17:59:26] [PASSED] 9 VFs
[17:59:26] [PASSED] 10 VFs
[17:59:26] [PASSED] 11 VFs
[17:59:26] [PASSED] 12 VFs
[17:59:26] [PASSED] 13 VFs
[17:59:26] [PASSED] 14 VFs
[17:59:26] [PASSED] 15 VFs
[17:59:26] [PASSED] 16 VFs
[17:59:26] [PASSED] 17 VFs
[17:59:26] [PASSED] 18 VFs
[17:59:26] [PASSED] 19 VFs
[17:59:26] [PASSED] 20 VFs
[17:59:26] [PASSED] 21 VFs
[17:59:26] [PASSED] 22 VFs
[17:59:26] [PASSED] 23 VFs
[17:59:26] [PASSED] 24 VFs
[17:59:26] [PASSED] 25 VFs
[17:59:26] [PASSED] 26 VFs
[17:59:26] [PASSED] 27 VFs
[17:59:26] [PASSED] 28 VFs
[17:59:26] [PASSED] 29 VFs
[17:59:26] [PASSED] 30 VFs
[17:59:26] [PASSED] 31 VFs
[17:59:26] [PASSED] 32 VFs
[17:59:26] [PASSED] 33 VFs
[17:59:26] [PASSED] 34 VFs
[17:59:26] [PASSED] 35 VFs
[17:59:26] [PASSED] 36 VFs
[17:59:26] [PASSED] 37 VFs
[17:59:26] [PASSED] 38 VFs
[17:59:26] [PASSED] 39 VFs
[17:59:26] [PASSED] 40 VFs
[17:59:26] [PASSED] 41 VFs
[17:59:26] [PASSED] 42 VFs
[17:59:26] [PASSED] 43 VFs
[17:59:26] [PASSED] 44 VFs
[17:59:26] [PASSED] 45 VFs
[17:59:26] [PASSED] 46 VFs
[17:59:26] [PASSED] 47 VFs
[17:59:26] [PASSED] 48 VFs
[17:59:26] [PASSED] 49 VFs
[17:59:26] [PASSED] 50 VFs
[17:59:26] [PASSED] 51 VFs
[17:59:26] [PASSED] 52 VFs
[17:59:26] [PASSED] 53 VFs
[17:59:26] [PASSED] 54 VFs
[17:59:26] [PASSED] 55 VFs
[17:59:26] [PASSED] 56 VFs
[17:59:26] [PASSED] 57 VFs
[17:59:26] [PASSED] 58 VFs
[17:59:26] [PASSED] 59 VFs
[17:59:26] [PASSED] 60 VFs
[17:59:26] [PASSED] 61 VFs
[17:59:26] [PASSED] 62 VFs
[17:59:26] [PASSED] 63 VFs
[17:59:26] ==================== [PASSED] fair_ggtt ====================
[17:59:26] ======================== fair_vram  ========================
[17:59:26] [PASSED] 1 VF
[17:59:26] [PASSED] 2 VFs
[17:59:26] [PASSED] 3 VFs
[17:59:26] [PASSED] 4 VFs
[17:59:26] [PASSED] 5 VFs
[17:59:26] [PASSED] 6 VFs
[17:59:26] [PASSED] 7 VFs
[17:59:26] [PASSED] 8 VFs
[17:59:26] [PASSED] 9 VFs
[17:59:26] [PASSED] 10 VFs
[17:59:26] [PASSED] 11 VFs
[17:59:26] [PASSED] 12 VFs
[17:59:26] [PASSED] 13 VFs
[17:59:26] [PASSED] 14 VFs
[17:59:26] [PASSED] 15 VFs
[17:59:26] [PASSED] 16 VFs
[17:59:26] [PASSED] 17 VFs
[17:59:26] [PASSED] 18 VFs
[17:59:26] [PASSED] 19 VFs
[17:59:26] [PASSED] 20 VFs
[17:59:26] [PASSED] 21 VFs
[17:59:26] [PASSED] 22 VFs
[17:59:26] [PASSED] 23 VFs
[17:59:26] [PASSED] 24 VFs
[17:59:26] [PASSED] 25 VFs
[17:59:26] [PASSED] 26 VFs
[17:59:26] [PASSED] 27 VFs
[17:59:26] [PASSED] 28 VFs
[17:59:26] [PASSED] 29 VFs
[17:59:26] [PASSED] 30 VFs
[17:59:26] [PASSED] 31 VFs
[17:59:26] [PASSED] 32 VFs
[17:59:26] [PASSED] 33 VFs
[17:59:26] [PASSED] 34 VFs
[17:59:26] [PASSED] 35 VFs
[17:59:26] [PASSED] 36 VFs
[17:59:26] [PASSED] 37 VFs
[17:59:26] [PASSED] 38 VFs
[17:59:26] [PASSED] 39 VFs
[17:59:26] [PASSED] 40 VFs
[17:59:26] [PASSED] 41 VFs
[17:59:26] [PASSED] 42 VFs
[17:59:26] [PASSED] 43 VFs
[17:59:26] [PASSED] 44 VFs
[17:59:26] [PASSED] 45 VFs
[17:59:26] [PASSED] 46 VFs
[17:59:26] [PASSED] 47 VFs
[17:59:26] [PASSED] 48 VFs
[17:59:26] [PASSED] 49 VFs
[17:59:26] [PASSED] 50 VFs
[17:59:26] [PASSED] 51 VFs
[17:59:26] [PASSED] 52 VFs
[17:59:26] [PASSED] 53 VFs
[17:59:26] [PASSED] 54 VFs
[17:59:26] [PASSED] 55 VFs
[17:59:26] [PASSED] 56 VFs
[17:59:26] [PASSED] 57 VFs
[17:59:26] [PASSED] 58 VFs
[17:59:26] [PASSED] 59 VFs
[17:59:26] [PASSED] 60 VFs
[17:59:26] [PASSED] 61 VFs
[17:59:26] [PASSED] 62 VFs
[17:59:26] [PASSED] 63 VFs
[17:59:26] ==================== [PASSED] fair_vram ====================
[17:59:26] ================== [PASSED] pf_gt_config ===================
[17:59:26] ===================== lmtt (1 subtest) =====================
[17:59:26] ======================== test_ops  =========================
[17:59:26] [PASSED] 2-level
[17:59:26] [PASSED] multi-level
[17:59:26] ==================== [PASSED] test_ops =====================
[17:59:26] ====================== [PASSED] lmtt =======================
[17:59:26] ================= pf_service (11 subtests) =================
[17:59:26] [PASSED] pf_negotiate_any
[17:59:26] [PASSED] pf_negotiate_base_match
[17:59:26] [PASSED] pf_negotiate_base_newer
[17:59:26] [PASSED] pf_negotiate_base_next
[17:59:26] [SKIPPED] pf_negotiate_base_older
[17:59:26] [PASSED] pf_negotiate_base_prev
[17:59:26] [PASSED] pf_negotiate_latest_match
[17:59:26] [PASSED] pf_negotiate_latest_newer
[17:59:26] [PASSED] pf_negotiate_latest_next
[17:59:26] [SKIPPED] pf_negotiate_latest_older
[17:59:26] [SKIPPED] pf_negotiate_latest_prev
[17:59:26] =================== [PASSED] pf_service ====================
[17:59:26] ================= xe_guc_g2g (2 subtests) ==================
[17:59:26] ============== xe_live_guc_g2g_kunit_default  ==============
[17:59:26] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[17:59:26] ============== xe_live_guc_g2g_kunit_allmem  ===============
[17:59:26] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[17:59:26] =================== [SKIPPED] xe_guc_g2g ===================
[17:59:26] =================== xe_mocs (2 subtests) ===================
[17:59:26] ================ xe_live_mocs_kernel_kunit  ================
[17:59:26] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[17:59:26] ================ xe_live_mocs_reset_kunit  =================
[17:59:26] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[17:59:26] ==================== [SKIPPED] xe_mocs =====================
[17:59:26] ================= xe_migrate (2 subtests) ==================
[17:59:26] ================= xe_migrate_sanity_kunit  =================
[17:59:26] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[17:59:26] ================== xe_validate_ccs_kunit  ==================
[17:59:26] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[17:59:26] =================== [SKIPPED] xe_migrate ===================
[17:59:26] ================== xe_dma_buf (1 subtest) ==================
[17:59:26] ==================== xe_dma_buf_kunit  =====================
[17:59:26] ================ [SKIPPED] xe_dma_buf_kunit ================
[17:59:26] =================== [SKIPPED] xe_dma_buf ===================
[17:59:26] ================= xe_bo_shrink (1 subtest) =================
[17:59:26] =================== xe_bo_shrink_kunit  ====================
[17:59:26] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[17:59:26] ================== [SKIPPED] xe_bo_shrink ==================
[17:59:26] ==================== xe_bo (2 subtests) ====================
[17:59:26] ================== xe_ccs_migrate_kunit  ===================
[17:59:26] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[17:59:26] ==================== xe_bo_evict_kunit  ====================
[17:59:26] =============== [SKIPPED] xe_bo_evict_kunit ================
[17:59:26] ===================== [SKIPPED] xe_bo ======================
[17:59:26] ==================== args (13 subtests) ====================
[17:59:26] [PASSED] count_args_test
[17:59:26] [PASSED] call_args_example
[17:59:26] [PASSED] call_args_test
[17:59:26] [PASSED] drop_first_arg_example
[17:59:26] [PASSED] drop_first_arg_test
[17:59:26] [PASSED] first_arg_example
[17:59:26] [PASSED] first_arg_test
[17:59:26] [PASSED] last_arg_example
[17:59:26] [PASSED] last_arg_test
[17:59:26] [PASSED] pick_arg_example
[17:59:26] [PASSED] if_args_example
[17:59:26] [PASSED] if_args_test
[17:59:26] [PASSED] sep_comma_example
[17:59:26] ====================== [PASSED] args =======================
[17:59:26] =================== xe_pci (3 subtests) ====================
[17:59:26] ==================== check_graphics_ip  ====================
[17:59:26] [PASSED] 12.00 Xe_LP
[17:59:26] [PASSED] 12.10 Xe_LP+
[17:59:26] [PASSED] 12.55 Xe_HPG
[17:59:26] [PASSED] 12.60 Xe_HPC
[17:59:26] [PASSED] 12.70 Xe_LPG
[17:59:26] [PASSED] 12.71 Xe_LPG
[17:59:26] [PASSED] 12.74 Xe_LPG+
[17:59:26] [PASSED] 20.01 Xe2_HPG
[17:59:26] [PASSED] 20.02 Xe2_HPG
[17:59:26] [PASSED] 20.04 Xe2_LPG
[17:59:26] [PASSED] 30.00 Xe3_LPG
[17:59:26] [PASSED] 30.01 Xe3_LPG
[17:59:26] [PASSED] 30.03 Xe3_LPG
[17:59:26] [PASSED] 30.04 Xe3_LPG
[17:59:26] [PASSED] 30.05 Xe3_LPG
[17:59:26] [PASSED] 35.10 Xe3p_LPG
[17:59:26] [PASSED] 35.11 Xe3p_XPC
[17:59:26] ================ [PASSED] check_graphics_ip ================
[17:59:26] ===================== check_media_ip  ======================
[17:59:26] [PASSED] 12.00 Xe_M
[17:59:26] [PASSED] 12.55 Xe_HPM
[17:59:26] [PASSED] 13.00 Xe_LPM+
[17:59:26] [PASSED] 13.01 Xe2_HPM
[17:59:26] [PASSED] 20.00 Xe2_LPM
[17:59:26] [PASSED] 30.00 Xe3_LPM
[17:59:26] [PASSED] 30.02 Xe3_LPM
[17:59:26] [PASSED] 35.00 Xe3p_LPM
[17:59:26] [PASSED] 35.03 Xe3p_HPM
[17:59:26] ================= [PASSED] check_media_ip ==================
[17:59:26] =================== check_platform_desc  ===================
[17:59:26] [PASSED] 0x9A60 (TIGERLAKE)
[17:59:26] [PASSED] 0x9A68 (TIGERLAKE)
[17:59:26] [PASSED] 0x9A70 (TIGERLAKE)
[17:59:26] [PASSED] 0x9A40 (TIGERLAKE)
[17:59:26] [PASSED] 0x9A49 (TIGERLAKE)
[17:59:26] [PASSED] 0x9A59 (TIGERLAKE)
[17:59:26] [PASSED] 0x9A78 (TIGERLAKE)
[17:59:26] [PASSED] 0x9AC0 (TIGERLAKE)
[17:59:26] [PASSED] 0x9AC9 (TIGERLAKE)
[17:59:26] [PASSED] 0x9AD9 (TIGERLAKE)
[17:59:26] [PASSED] 0x9AF8 (TIGERLAKE)
[17:59:26] [PASSED] 0x4C80 (ROCKETLAKE)
[17:59:26] [PASSED] 0x4C8A (ROCKETLAKE)
[17:59:26] [PASSED] 0x4C8B (ROCKETLAKE)
[17:59:26] [PASSED] 0x4C8C (ROCKETLAKE)
[17:59:26] [PASSED] 0x4C90 (ROCKETLAKE)
[17:59:26] [PASSED] 0x4C9A (ROCKETLAKE)
[17:59:26] [PASSED] 0x4680 (ALDERLAKE_S)
[17:59:26] [PASSED] 0x4682 (ALDERLAKE_S)
[17:59:26] [PASSED] 0x4688 (ALDERLAKE_S)
[17:59:26] [PASSED] 0x468A (ALDERLAKE_S)
[17:59:26] [PASSED] 0x468B (ALDERLAKE_S)
[17:59:26] [PASSED] 0x4690 (ALDERLAKE_S)
[17:59:26] [PASSED] 0x4692 (ALDERLAKE_S)
[17:59:26] [PASSED] 0x4693 (ALDERLAKE_S)
[17:59:26] [PASSED] 0x46A0 (ALDERLAKE_P)
[17:59:26] [PASSED] 0x46A1 (ALDERLAKE_P)
[17:59:26] [PASSED] 0x46A2 (ALDERLAKE_P)
[17:59:26] [PASSED] 0x46A3 (ALDERLAKE_P)
[17:59:26] [PASSED] 0x46A6 (ALDERLAKE_P)
[17:59:26] [PASSED] 0x46A8 (ALDERLAKE_P)
[17:59:26] [PASSED] 0x46AA (ALDERLAKE_P)
[17:59:26] [PASSED] 0x462A (ALDERLAKE_P)
[17:59:26] [PASSED] 0x4626 (ALDERLAKE_P)
[17:59:26] [PASSED] 0x4628 (ALDERLAKE_P)
[17:59:26] [PASSED] 0x46B0 (ALDERLAKE_P)
[17:59:26] [PASSED] 0x46B1 (ALDERLAKE_P)
[17:59:26] [PASSED] 0x46B2 (ALDERLAKE_P)
[17:59:26] [PASSED] 0x46B3 (ALDERLAKE_P)
[17:59:26] [PASSED] 0x46C0 (ALDERLAKE_P)
[17:59:26] [PASSED] 0x46C1 (ALDERLAKE_P)
[17:59:26] [PASSED] 0x46C2 (ALDERLAKE_P)
[17:59:26] [PASSED] 0x46C3 (ALDERLAKE_P)
[17:59:26] [PASSED] 0x46D0 (ALDERLAKE_N)
[17:59:26] [PASSED] 0x46D1 (ALDERLAKE_N)
[17:59:26] [PASSED] 0x46D2 (ALDERLAKE_N)
[17:59:26] [PASSED] 0x46D3 (ALDERLAKE_N)
[17:59:26] [PASSED] 0x46D4 (ALDERLAKE_N)
[17:59:26] [PASSED] 0xA721 (ALDERLAKE_P)
[17:59:26] [PASSED] 0xA7A1 (ALDERLAKE_P)
[17:59:26] [PASSED] 0xA7A9 (ALDERLAKE_P)
[17:59:26] [PASSED] 0xA7AC (ALDERLAKE_P)
[17:59:26] [PASSED] 0xA7AD (ALDERLAKE_P)
[17:59:26] [PASSED] 0xA720 (ALDERLAKE_P)
[17:59:26] [PASSED] 0xA7A0 (ALDERLAKE_P)
[17:59:26] [PASSED] 0xA7A8 (ALDERLAKE_P)
[17:59:26] [PASSED] 0xA7AA (ALDERLAKE_P)
[17:59:26] [PASSED] 0xA7AB (ALDERLAKE_P)
[17:59:26] [PASSED] 0xA780 (ALDERLAKE_S)
[17:59:26] [PASSED] 0xA781 (ALDERLAKE_S)
[17:59:26] [PASSED] 0xA782 (ALDERLAKE_S)
[17:59:26] [PASSED] 0xA783 (ALDERLAKE_S)
[17:59:26] [PASSED] 0xA788 (ALDERLAKE_S)
[17:59:26] [PASSED] 0xA789 (ALDERLAKE_S)
[17:59:26] [PASSED] 0xA78A (ALDERLAKE_S)
[17:59:26] [PASSED] 0xA78B (ALDERLAKE_S)
[17:59:26] [PASSED] 0x4905 (DG1)
[17:59:26] [PASSED] 0x4906 (DG1)
[17:59:26] [PASSED] 0x4907 (DG1)
[17:59:26] [PASSED] 0x4908 (DG1)
[17:59:26] [PASSED] 0x4909 (DG1)
[17:59:26] [PASSED] 0x56C0 (DG2)
[17:59:26] [PASSED] 0x56C2 (DG2)
[17:59:26] [PASSED] 0x56C1 (DG2)
[17:59:26] [PASSED] 0x7D51 (METEORLAKE)
[17:59:26] [PASSED] 0x7DD1 (METEORLAKE)
[17:59:26] [PASSED] 0x7D41 (METEORLAKE)
[17:59:26] [PASSED] 0x7D67 (METEORLAKE)
[17:59:26] [PASSED] 0xB640 (METEORLAKE)
[17:59:26] [PASSED] 0x56A0 (DG2)
[17:59:26] [PASSED] 0x56A1 (DG2)
[17:59:26] [PASSED] 0x56A2 (DG2)
[17:59:26] [PASSED] 0x56BE (DG2)
[17:59:26] [PASSED] 0x56BF (DG2)
[17:59:26] [PASSED] 0x5690 (DG2)
[17:59:26] [PASSED] 0x5691 (DG2)
[17:59:26] [PASSED] 0x5692 (DG2)
[17:59:26] [PASSED] 0x56A5 (DG2)
[17:59:26] [PASSED] 0x56A6 (DG2)
[17:59:26] [PASSED] 0x56B0 (DG2)
[17:59:26] [PASSED] 0x56B1 (DG2)
[17:59:26] [PASSED] 0x56BA (DG2)
[17:59:26] [PASSED] 0x56BB (DG2)
[17:59:26] [PASSED] 0x56BC (DG2)
[17:59:26] [PASSED] 0x56BD (DG2)
[17:59:26] [PASSED] 0x5693 (DG2)
[17:59:26] [PASSED] 0x5694 (DG2)
[17:59:26] [PASSED] 0x5695 (DG2)
[17:59:26] [PASSED] 0x56A3 (DG2)
[17:59:26] [PASSED] 0x56A4 (DG2)
[17:59:26] [PASSED] 0x56B2 (DG2)
[17:59:26] [PASSED] 0x56B3 (DG2)
[17:59:26] [PASSED] 0x5696 (DG2)
[17:59:26] [PASSED] 0x5697 (DG2)
[17:59:26] [PASSED] 0xB69 (PVC)
[17:59:26] [PASSED] 0xB6E (PVC)
[17:59:26] [PASSED] 0xBD4 (PVC)
[17:59:26] [PASSED] 0xBD5 (PVC)
[17:59:26] [PASSED] 0xBD6 (PVC)
[17:59:26] [PASSED] 0xBD7 (PVC)
[17:59:26] [PASSED] 0xBD8 (PVC)
[17:59:26] [PASSED] 0xBD9 (PVC)
[17:59:26] [PASSED] 0xBDA (PVC)
[17:59:26] [PASSED] 0xBDB (PVC)
[17:59:26] [PASSED] 0xBE0 (PVC)
[17:59:26] [PASSED] 0xBE1 (PVC)
[17:59:26] [PASSED] 0xBE5 (PVC)
[17:59:26] [PASSED] 0x7D40 (METEORLAKE)
[17:59:26] [PASSED] 0x7D45 (METEORLAKE)
[17:59:26] [PASSED] 0x7D55 (METEORLAKE)
[17:59:26] [PASSED] 0x7D60 (METEORLAKE)
[17:59:26] [PASSED] 0x7DD5 (METEORLAKE)
[17:59:26] [PASSED] 0x6420 (LUNARLAKE)
[17:59:26] [PASSED] 0x64A0 (LUNARLAKE)
[17:59:26] [PASSED] 0x64B0 (LUNARLAKE)
[17:59:26] [PASSED] 0xE202 (BATTLEMAGE)
[17:59:26] [PASSED] 0xE209 (BATTLEMAGE)
[17:59:26] [PASSED] 0xE20B (BATTLEMAGE)
[17:59:26] [PASSED] 0xE20C (BATTLEMAGE)
[17:59:26] [PASSED] 0xE20D (BATTLEMAGE)
[17:59:26] [PASSED] 0xE210 (BATTLEMAGE)
[17:59:26] [PASSED] 0xE211 (BATTLEMAGE)
[17:59:26] [PASSED] 0xE212 (BATTLEMAGE)
[17:59:26] [PASSED] 0xE216 (BATTLEMAGE)
[17:59:26] [PASSED] 0xE220 (BATTLEMAGE)
[17:59:26] [PASSED] 0xE221 (BATTLEMAGE)
[17:59:26] [PASSED] 0xE222 (BATTLEMAGE)
[17:59:26] [PASSED] 0xE223 (BATTLEMAGE)
[17:59:26] [PASSED] 0xB080 (PANTHERLAKE)
[17:59:26] [PASSED] 0xB081 (PANTHERLAKE)
[17:59:26] [PASSED] 0xB082 (PANTHERLAKE)
[17:59:26] [PASSED] 0xB083 (PANTHERLAKE)
[17:59:26] [PASSED] 0xB084 (PANTHERLAKE)
[17:59:26] [PASSED] 0xB085 (PANTHERLAKE)
[17:59:26] [PASSED] 0xB086 (PANTHERLAKE)
[17:59:26] [PASSED] 0xB087 (PANTHERLAKE)
[17:59:26] [PASSED] 0xB08F (PANTHERLAKE)
[17:59:26] [PASSED] 0xB090 (PANTHERLAKE)
[17:59:26] [PASSED] 0xB0A0 (PANTHERLAKE)
[17:59:26] [PASSED] 0xB0B0 (PANTHERLAKE)
[17:59:26] [PASSED] 0xFD80 (PANTHERLAKE)
[17:59:26] [PASSED] 0xFD81 (PANTHERLAKE)
[17:59:26] [PASSED] 0xD740 (NOVALAKE_S)
[17:59:26] [PASSED] 0xD741 (NOVALAKE_S)
[17:59:26] [PASSED] 0xD742 (NOVALAKE_S)
[17:59:26] [PASSED] 0xD743 (NOVALAKE_S)
[17:59:26] [PASSED] 0xD744 (NOVALAKE_S)
[17:59:26] [PASSED] 0xD745 (NOVALAKE_S)
[17:59:26] [PASSED] 0x674C (CRESCENTISLAND)
[17:59:26] [PASSED] 0x674D (CRESCENTISLAND)
[17:59:26] [PASSED] 0x674E (CRESCENTISLAND)
[17:59:26] [PASSED] 0x674F (CRESCENTISLAND)
[17:59:26] [PASSED] 0x6750 (CRESCENTISLAND)
[17:59:26] [PASSED] 0xD750 (NOVALAKE_P)
[17:59:26] [PASSED] 0xD751 (NOVALAKE_P)
[17:59:26] [PASSED] 0xD752 (NOVALAKE_P)
[17:59:26] [PASSED] 0xD753 (NOVALAKE_P)
[17:59:26] [PASSED] 0xD754 (NOVALAKE_P)
[17:59:26] [PASSED] 0xD755 (NOVALAKE_P)
[17:59:26] [PASSED] 0xD756 (NOVALAKE_P)
[17:59:26] [PASSED] 0xD757 (NOVALAKE_P)
[17:59:26] [PASSED] 0xD75F (NOVALAKE_P)
[17:59:26] =============== [PASSED] check_platform_desc ===============
[17:59:26] ===================== [PASSED] xe_pci ======================
[17:59:26] =================== xe_rtp (2 subtests) ====================
[17:59:26] =============== xe_rtp_process_to_sr_tests  ================
[17:59:26] [PASSED] coalesce-same-reg
[17:59:26] [PASSED] no-match-no-add
[17:59:26] [PASSED] match-or
[17:59:26] [PASSED] match-or-xfail
[17:59:26] [PASSED] no-match-no-add-multiple-rules
[17:59:26] [PASSED] two-regs-two-entries
[17:59:26] [PASSED] clr-one-set-other
[17:59:26] [PASSED] set-field
[17:59:26] [PASSED] conflict-duplicate
[17:59:26] [PASSED] conflict-not-disjoint
[17:59:26] [PASSED] conflict-reg-type
[17:59:26] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[17:59:26] ================== xe_rtp_process_tests  ===================
[17:59:26] [PASSED] active1
[17:59:26] [PASSED] active2
[17:59:26] [PASSED] active-inactive
[17:59:26] [PASSED] inactive-active
[17:59:26] [PASSED] inactive-1st_or_active-inactive
[17:59:26] [PASSED] inactive-2nd_or_active-inactive
[17:59:26] [PASSED] inactive-last_or_active-inactive
[17:59:26] [PASSED] inactive-no_or_active-inactive
[17:59:26] ============== [PASSED] xe_rtp_process_tests ===============
[17:59:26] ===================== [PASSED] xe_rtp ======================
[17:59:26] ==================== xe_wa (1 subtest) =====================
[17:59:26] ======================== xe_wa_gt  =========================
[17:59:26] [PASSED] TIGERLAKE B0
[17:59:26] [PASSED] DG1 A0
[17:59:26] [PASSED] DG1 B0
[17:59:26] [PASSED] ALDERLAKE_S A0
[17:59:26] [PASSED] ALDERLAKE_S B0
[17:59:26] [PASSED] ALDERLAKE_S C0
[17:59:26] [PASSED] ALDERLAKE_S D0
[17:59:26] [PASSED] ALDERLAKE_P A0
[17:59:26] [PASSED] ALDERLAKE_P B0
[17:59:26] [PASSED] ALDERLAKE_P C0
[17:59:26] [PASSED] ALDERLAKE_S RPLS D0
[17:59:26] [PASSED] ALDERLAKE_P RPLU E0
[17:59:26] [PASSED] DG2 G10 C0
[17:59:26] [PASSED] DG2 G11 B1
[17:59:26] [PASSED] DG2 G12 A1
[17:59:26] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:59:26] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:59:26] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[17:59:26] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[17:59:26] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[17:59:26] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[17:59:26] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[17:59:26] ==================== [PASSED] xe_wa_gt =====================
[17:59:26] ====================== [PASSED] xe_wa ======================
[17:59:26] ============================================================
[17:59:26] Testing complete. Ran 601 tests: passed: 583, skipped: 18
[17:59:26] Elapsed time: 36.053s total, 4.279s configuring, 31.158s building, 0.600s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[17:59:26] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:59:28] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:59:52] Starting KUnit Kernel (1/1)...
[17:59:52] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:59:53] ============ drm_test_pick_cmdline (2 subtests) ============
[17:59:53] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[17:59:53] =============== drm_test_pick_cmdline_named  ===============
[17:59:53] [PASSED] NTSC
[17:59:53] [PASSED] NTSC-J
[17:59:53] [PASSED] PAL
[17:59:53] [PASSED] PAL-M
[17:59:53] =========== [PASSED] drm_test_pick_cmdline_named ===========
[17:59:53] ============== [PASSED] drm_test_pick_cmdline ==============
[17:59:53] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[17:59:53] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[17:59:53] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[17:59:53] =========== drm_validate_clone_mode (2 subtests) ===========
[17:59:53] ============== drm_test_check_in_clone_mode  ===============
[17:59:53] [PASSED] in_clone_mode
[17:59:53] [PASSED] not_in_clone_mode
[17:59:53] ========== [PASSED] drm_test_check_in_clone_mode ===========
[17:59:53] =============== drm_test_check_valid_clones  ===============
[17:59:53] [PASSED] not_in_clone_mode
[17:59:53] [PASSED] valid_clone
[17:59:53] [PASSED] invalid_clone
[17:59:53] =========== [PASSED] drm_test_check_valid_clones ===========
[17:59:53] ============= [PASSED] drm_validate_clone_mode =============
[17:59:53] ============= drm_validate_modeset (1 subtest) =============
[17:59:53] [PASSED] drm_test_check_connector_changed_modeset
[17:59:53] ============== [PASSED] drm_validate_modeset ===============
[17:59:53] ====== drm_test_bridge_get_current_state (2 subtests) ======
[17:59:53] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[17:59:53] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[17:59:53] ======== [PASSED] drm_test_bridge_get_current_state ========
[17:59:53] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[17:59:53] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[17:59:53] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[17:59:53] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[17:59:53] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[17:59:53] ============== drm_bridge_alloc (2 subtests) ===============
[17:59:53] [PASSED] drm_test_drm_bridge_alloc_basic
[17:59:53] [PASSED] drm_test_drm_bridge_alloc_get_put
[17:59:53] ================ [PASSED] drm_bridge_alloc =================
[17:59:53] ============= drm_cmdline_parser (40 subtests) =============
[17:59:53] [PASSED] drm_test_cmdline_force_d_only
[17:59:53] [PASSED] drm_test_cmdline_force_D_only_dvi
[17:59:53] [PASSED] drm_test_cmdline_force_D_only_hdmi
[17:59:53] [PASSED] drm_test_cmdline_force_D_only_not_digital
[17:59:53] [PASSED] drm_test_cmdline_force_e_only
[17:59:53] [PASSED] drm_test_cmdline_res
[17:59:53] [PASSED] drm_test_cmdline_res_vesa
[17:59:53] [PASSED] drm_test_cmdline_res_vesa_rblank
[17:59:53] [PASSED] drm_test_cmdline_res_rblank
[17:59:53] [PASSED] drm_test_cmdline_res_bpp
[17:59:53] [PASSED] drm_test_cmdline_res_refresh
[17:59:53] [PASSED] drm_test_cmdline_res_bpp_refresh
[17:59:53] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[17:59:53] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[17:59:53] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[17:59:53] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[17:59:53] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[17:59:53] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[17:59:53] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[17:59:53] [PASSED] drm_test_cmdline_res_margins_force_on
[17:59:53] [PASSED] drm_test_cmdline_res_vesa_margins
[17:59:53] [PASSED] drm_test_cmdline_name
[17:59:53] [PASSED] drm_test_cmdline_name_bpp
[17:59:53] [PASSED] drm_test_cmdline_name_option
[17:59:53] [PASSED] drm_test_cmdline_name_bpp_option
[17:59:53] [PASSED] drm_test_cmdline_rotate_0
[17:59:53] [PASSED] drm_test_cmdline_rotate_90
[17:59:53] [PASSED] drm_test_cmdline_rotate_180
[17:59:53] [PASSED] drm_test_cmdline_rotate_270
[17:59:53] [PASSED] drm_test_cmdline_hmirror
[17:59:53] [PASSED] drm_test_cmdline_vmirror
[17:59:53] [PASSED] drm_test_cmdline_margin_options
[17:59:53] [PASSED] drm_test_cmdline_multiple_options
[17:59:53] [PASSED] drm_test_cmdline_bpp_extra_and_option
[17:59:53] [PASSED] drm_test_cmdline_extra_and_option
[17:59:53] [PASSED] drm_test_cmdline_freestanding_options
[17:59:53] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[17:59:53] [PASSED] drm_test_cmdline_panel_orientation
[17:59:53] ================ drm_test_cmdline_invalid  =================
[17:59:53] [PASSED] margin_only
[17:59:53] [PASSED] interlace_only
[17:59:53] [PASSED] res_missing_x
[17:59:53] [PASSED] res_missing_y
[17:59:53] [PASSED] res_bad_y
[17:59:53] [PASSED] res_missing_y_bpp
[17:59:53] [PASSED] res_bad_bpp
[17:59:53] [PASSED] res_bad_refresh
[17:59:53] [PASSED] res_bpp_refresh_force_on_off
[17:59:53] [PASSED] res_invalid_mode
[17:59:53] [PASSED] res_bpp_wrong_place_mode
[17:59:53] [PASSED] name_bpp_refresh
[17:59:53] [PASSED] name_refresh
[17:59:53] [PASSED] name_refresh_wrong_mode
[17:59:53] [PASSED] name_refresh_invalid_mode
[17:59:53] [PASSED] rotate_multiple
[17:59:53] [PASSED] rotate_invalid_val
[17:59:53] [PASSED] rotate_truncated
[17:59:53] [PASSED] invalid_option
[17:59:53] [PASSED] invalid_tv_option
[17:59:53] [PASSED] truncated_tv_option
[17:59:53] ============ [PASSED] drm_test_cmdline_invalid =============
[17:59:53] =============== drm_test_cmdline_tv_options  ===============
[17:59:53] [PASSED] NTSC
[17:59:53] [PASSED] NTSC_443
[17:59:53] [PASSED] NTSC_J
[17:59:53] [PASSED] PAL
[17:59:53] [PASSED] PAL_M
[17:59:53] [PASSED] PAL_N
[17:59:53] [PASSED] SECAM
[17:59:53] [PASSED] MONO_525
[17:59:53] [PASSED] MONO_625
[17:59:53] =========== [PASSED] drm_test_cmdline_tv_options ===========
[17:59:53] =============== [PASSED] drm_cmdline_parser ================
[17:59:53] ========== drmm_connector_hdmi_init (20 subtests) ==========
[17:59:53] [PASSED] drm_test_connector_hdmi_init_valid
[17:59:53] [PASSED] drm_test_connector_hdmi_init_bpc_8
[17:59:53] [PASSED] drm_test_connector_hdmi_init_bpc_10
[17:59:53] [PASSED] drm_test_connector_hdmi_init_bpc_12
[17:59:53] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[17:59:53] [PASSED] drm_test_connector_hdmi_init_bpc_null
[17:59:53] [PASSED] drm_test_connector_hdmi_init_formats_empty
[17:59:53] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[17:59:53] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[17:59:53] [PASSED] supported_formats=0x9 yuv420_allowed=1
[17:59:53] [PASSED] supported_formats=0x9 yuv420_allowed=0
[17:59:53] [PASSED] supported_formats=0x5 yuv420_allowed=1
[17:59:53] [PASSED] supported_formats=0x5 yuv420_allowed=0
[17:59:53] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[17:59:53] [PASSED] drm_test_connector_hdmi_init_null_ddc
[17:59:53] [PASSED] drm_test_connector_hdmi_init_null_product
[17:59:53] [PASSED] drm_test_connector_hdmi_init_null_vendor
[17:59:53] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[17:59:53] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[17:59:53] [PASSED] drm_test_connector_hdmi_init_product_valid
[17:59:53] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[17:59:53] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[17:59:53] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[17:59:53] ========= drm_test_connector_hdmi_init_type_valid  =========
[17:59:53] [PASSED] HDMI-A
[17:59:53] [PASSED] HDMI-B
[17:59:53] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[17:59:53] ======== drm_test_connector_hdmi_init_type_invalid  ========
[17:59:53] [PASSED] Unknown
[17:59:53] [PASSED] VGA
[17:59:53] [PASSED] DVI-I
[17:59:53] [PASSED] DVI-D
[17:59:53] [PASSED] DVI-A
[17:59:53] [PASSED] Composite
[17:59:53] [PASSED] SVIDEO
[17:59:53] [PASSED] LVDS
[17:59:53] [PASSED] Component
[17:59:53] [PASSED] DIN
[17:59:53] [PASSED] DP
[17:59:53] [PASSED] TV
[17:59:53] [PASSED] eDP
[17:59:53] [PASSED] Virtual
[17:59:53] [PASSED] DSI
[17:59:53] [PASSED] DPI
[17:59:53] [PASSED] Writeback
[17:59:53] [PASSED] SPI
[17:59:53] [PASSED] USB
[17:59:53] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[17:59:53] ============ [PASSED] drmm_connector_hdmi_init =============
[17:59:53] ============= drmm_connector_init (3 subtests) =============
[17:59:53] [PASSED] drm_test_drmm_connector_init
[17:59:53] [PASSED] drm_test_drmm_connector_init_null_ddc
[17:59:53] ========= drm_test_drmm_connector_init_type_valid  =========
[17:59:53] [PASSED] Unknown
[17:59:53] [PASSED] VGA
[17:59:53] [PASSED] DVI-I
[17:59:53] [PASSED] DVI-D
[17:59:53] [PASSED] DVI-A
[17:59:53] [PASSED] Composite
[17:59:53] [PASSED] SVIDEO
[17:59:53] [PASSED] LVDS
[17:59:53] [PASSED] Component
[17:59:53] [PASSED] DIN
[17:59:53] [PASSED] DP
[17:59:53] [PASSED] HDMI-A
[17:59:53] [PASSED] HDMI-B
[17:59:53] [PASSED] TV
[17:59:53] [PASSED] eDP
[17:59:53] [PASSED] Virtual
[17:59:53] [PASSED] DSI
[17:59:53] [PASSED] DPI
[17:59:53] [PASSED] Writeback
[17:59:53] [PASSED] SPI
[17:59:53] [PASSED] USB
[17:59:53] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[17:59:53] =============== [PASSED] drmm_connector_init ===============
[17:59:53] ========= drm_connector_dynamic_init (6 subtests) ==========
[17:59:53] [PASSED] drm_test_drm_connector_dynamic_init
[17:59:53] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[17:59:53] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[17:59:53] [PASSED] drm_test_drm_connector_dynamic_init_properties
[17:59:53] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[17:59:53] [PASSED] Unknown
[17:59:53] [PASSED] VGA
[17:59:53] [PASSED] DVI-I
[17:59:53] [PASSED] DVI-D
[17:59:53] [PASSED] DVI-A
[17:59:53] [PASSED] Composite
[17:59:53] [PASSED] SVIDEO
[17:59:53] [PASSED] LVDS
[17:59:53] [PASSED] Component
[17:59:53] [PASSED] DIN
[17:59:53] [PASSED] DP
[17:59:53] [PASSED] HDMI-A
[17:59:53] [PASSED] HDMI-B
[17:59:53] [PASSED] TV
[17:59:53] [PASSED] eDP
[17:59:53] [PASSED] Virtual
[17:59:53] [PASSED] DSI
[17:59:53] [PASSED] DPI
[17:59:53] [PASSED] Writeback
[17:59:53] [PASSED] SPI
[17:59:53] [PASSED] USB
[17:59:53] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[17:59:53] ======== drm_test_drm_connector_dynamic_init_name  =========
[17:59:53] [PASSED] Unknown
[17:59:53] [PASSED] VGA
[17:59:53] [PASSED] DVI-I
[17:59:53] [PASSED] DVI-D
[17:59:53] [PASSED] DVI-A
[17:59:53] [PASSED] Composite
[17:59:53] [PASSED] SVIDEO
[17:59:53] [PASSED] LVDS
[17:59:53] [PASSED] Component
[17:59:53] [PASSED] DIN
[17:59:53] [PASSED] DP
[17:59:53] [PASSED] HDMI-A
[17:59:53] [PASSED] HDMI-B
[17:59:53] [PASSED] TV
[17:59:53] [PASSED] eDP
[17:59:53] [PASSED] Virtual
[17:59:53] [PASSED] DSI
[17:59:53] [PASSED] DPI
[17:59:53] [PASSED] Writeback
[17:59:53] [PASSED] SPI
[17:59:53] [PASSED] USB
[17:59:53] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[17:59:53] =========== [PASSED] drm_connector_dynamic_init ============
[17:59:53] ==== drm_connector_dynamic_register_early (4 subtests) =====
[17:59:53] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[17:59:53] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[17:59:53] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[17:59:53] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[17:59:53] ====== [PASSED] drm_connector_dynamic_register_early =======
[17:59:53] ======= drm_connector_dynamic_register (7 subtests) ========
[17:59:53] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[17:59:53] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[17:59:53] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[17:59:53] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[17:59:53] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[17:59:53] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[17:59:53] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[17:59:53] ========= [PASSED] drm_connector_dynamic_register ==========
[17:59:53] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[17:59:53] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[17:59:53] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[17:59:53] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[17:59:53] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[17:59:53] ========== drm_test_get_tv_mode_from_name_valid  ===========
[17:59:53] [PASSED] NTSC
[17:59:53] [PASSED] NTSC-443
[17:59:53] [PASSED] NTSC-J
[17:59:53] [PASSED] PAL
[17:59:53] [PASSED] PAL-M
[17:59:53] [PASSED] PAL-N
[17:59:53] [PASSED] SECAM
[17:59:53] [PASSED] Mono
[17:59:53] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[17:59:53] [PASSED] drm_test_get_tv_mode_from_name_truncated
[17:59:53] ============ [PASSED] drm_get_tv_mode_from_name ============
[17:59:53] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[17:59:53] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[17:59:53] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[17:59:53] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[17:59:53] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[17:59:53] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[17:59:53] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[17:59:53] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[17:59:53] [PASSED] VIC 96
[17:59:53] [PASSED] VIC 97
[17:59:53] [PASSED] VIC 101
[17:59:53] [PASSED] VIC 102
[17:59:53] [PASSED] VIC 106
[17:59:53] [PASSED] VIC 107
[17:59:53] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[17:59:53] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[17:59:53] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[17:59:53] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[17:59:53] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[17:59:53] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[17:59:53] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[17:59:53] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[17:59:53] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[17:59:53] [PASSED] Automatic
[17:59:53] [PASSED] Full
[17:59:53] [PASSED] Limited 16:235
[17:59:53] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[17:59:53] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[17:59:53] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[17:59:53] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[17:59:53] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[17:59:53] [PASSED] RGB
[17:59:53] [PASSED] YUV 4:2:0
[17:59:53] [PASSED] YUV 4:2:2
[17:59:53] [PASSED] YUV 4:4:4
[17:59:53] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[17:59:53] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[17:59:53] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[17:59:53] ============= drm_damage_helper (21 subtests) ==============
[17:59:53] [PASSED] drm_test_damage_iter_no_damage
[17:59:53] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[17:59:53] [PASSED] drm_test_damage_iter_no_damage_src_moved
[17:59:53] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[17:59:53] [PASSED] drm_test_damage_iter_no_damage_not_visible
[17:59:53] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[17:59:53] [PASSED] drm_test_damage_iter_no_damage_no_fb
[17:59:53] [PASSED] drm_test_damage_iter_simple_damage
[17:59:53] [PASSED] drm_test_damage_iter_single_damage
[17:59:53] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[17:59:53] [PASSED] drm_test_damage_iter_single_damage_outside_src
[17:59:53] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[17:59:53] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[17:59:53] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[17:59:53] [PASSED] drm_test_damage_iter_single_damage_src_moved
[17:59:53] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[17:59:53] [PASSED] drm_test_damage_iter_damage
[17:59:53] [PASSED] drm_test_damage_iter_damage_one_intersect
[17:59:53] [PASSED] drm_test_damage_iter_damage_one_outside
[17:59:53] [PASSED] drm_test_damage_iter_damage_src_moved
[17:59:53] [PASSED] drm_test_damage_iter_damage_not_visible
[17:59:53] ================ [PASSED] drm_damage_helper ================
[17:59:53] ============== drm_dp_mst_helper (3 subtests) ==============
[17:59:53] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[17:59:53] [PASSED] Clock 154000 BPP 30 DSC disabled
[17:59:53] [PASSED] Clock 234000 BPP 30 DSC disabled
[17:59:53] [PASSED] Clock 297000 BPP 24 DSC disabled
[17:59:53] [PASSED] Clock 332880 BPP 24 DSC enabled
[17:59:53] [PASSED] Clock 324540 BPP 24 DSC enabled
[17:59:53] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[17:59:53] ============== drm_test_dp_mst_calc_pbn_div  ===============
[17:59:53] [PASSED] Link rate 2000000 lane count 4
[17:59:53] [PASSED] Link rate 2000000 lane count 2
[17:59:53] [PASSED] Link rate 2000000 lane count 1
[17:59:53] [PASSED] Link rate 1350000 lane count 4
[17:59:53] [PASSED] Link rate 1350000 lane count 2
[17:59:53] [PASSED] Link rate 1350000 lane count 1
[17:59:53] [PASSED] Link rate 1000000 lane count 4
[17:59:53] [PASSED] Link rate 1000000 lane count 2
[17:59:53] [PASSED] Link rate 1000000 lane count 1
[17:59:53] [PASSED] Link rate 810000 lane count 4
[17:59:53] [PASSED] Link rate 810000 lane count 2
[17:59:53] [PASSED] Link rate 810000 lane count 1
[17:59:53] [PASSED] Link rate 540000 lane count 4
[17:59:53] [PASSED] Link rate 540000 lane count 2
[17:59:53] [PASSED] Link rate 540000 lane count 1
[17:59:53] [PASSED] Link rate 270000 lane count 4
[17:59:53] [PASSED] Link rate 270000 lane count 2
[17:59:53] [PASSED] Link rate 270000 lane count 1
[17:59:53] [PASSED] Link rate 162000 lane count 4
[17:59:53] [PASSED] Link rate 162000 lane count 2
[17:59:53] [PASSED] Link rate 162000 lane count 1
[17:59:53] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[17:59:53] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[17:59:53] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[17:59:53] [PASSED] DP_POWER_UP_PHY with port number
[17:59:53] [PASSED] DP_POWER_DOWN_PHY with port number
[17:59:53] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[17:59:53] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[17:59:53] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[17:59:53] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[17:59:53] [PASSED] DP_QUERY_PAYLOAD with port number
[17:59:53] [PASSED] DP_QUERY_PAYLOAD with VCPI
[17:59:53] [PASSED] DP_REMOTE_DPCD_READ with port number
[17:59:53] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[17:59:53] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[17:59:53] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[17:59:53] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[17:59:53] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[17:59:53] [PASSED] DP_REMOTE_I2C_READ with port number
[17:59:53] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[17:59:53] [PASSED] DP_REMOTE_I2C_READ with transactions array
[17:59:53] [PASSED] DP_REMOTE_I2C_WRITE with port number
[17:59:53] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[17:59:53] [PASSED] DP_REMOTE_I2C_WRITE with data array
[17:59:53] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[17:59:53] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[17:59:53] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[17:59:53] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[17:59:53] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[17:59:53] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[17:59:53] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[17:59:53] ================ [PASSED] drm_dp_mst_helper ================
[17:59:53] ================== drm_exec (7 subtests) ===================
[17:59:53] [PASSED] sanitycheck
[17:59:53] [PASSED] test_lock
[17:59:53] [PASSED] test_lock_unlock
[17:59:53] [PASSED] test_duplicates
[17:59:53] [PASSED] test_prepare
[17:59:53] [PASSED] test_prepare_array
[17:59:53] [PASSED] test_multiple_loops
[17:59:53] ==================== [PASSED] drm_exec =====================
[17:59:53] =========== drm_format_helper_test (17 subtests) ===========
[17:59:53] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[17:59:53] [PASSED] single_pixel_source_buffer
[17:59:53] [PASSED] single_pixel_clip_rectangle
[17:59:53] [PASSED] well_known_colors
[17:59:53] [PASSED] destination_pitch
[17:59:53] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[17:59:53] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[17:59:53] [PASSED] single_pixel_source_buffer
[17:59:53] [PASSED] single_pixel_clip_rectangle
[17:59:53] [PASSED] well_known_colors
[17:59:53] [PASSED] destination_pitch
[17:59:53] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[17:59:53] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[17:59:53] [PASSED] single_pixel_source_buffer
[17:59:53] [PASSED] single_pixel_clip_rectangle
[17:59:53] [PASSED] well_known_colors
[17:59:53] [PASSED] destination_pitch
[17:59:53] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[17:59:53] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[17:59:53] [PASSED] single_pixel_source_buffer
[17:59:53] [PASSED] single_pixel_clip_rectangle
[17:59:53] [PASSED] well_known_colors
[17:59:53] [PASSED] destination_pitch
[17:59:53] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[17:59:53] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[17:59:53] [PASSED] single_pixel_source_buffer
[17:59:53] [PASSED] single_pixel_clip_rectangle
[17:59:53] [PASSED] well_known_colors
[17:59:53] [PASSED] destination_pitch
[17:59:53] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[17:59:53] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[17:59:53] [PASSED] single_pixel_source_buffer
[17:59:53] [PASSED] single_pixel_clip_rectangle
[17:59:53] [PASSED] well_known_colors
[17:59:53] [PASSED] destination_pitch
[17:59:53] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[17:59:53] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[17:59:53] [PASSED] single_pixel_source_buffer
[17:59:53] [PASSED] single_pixel_clip_rectangle
[17:59:53] [PASSED] well_known_colors
[17:59:53] [PASSED] destination_pitch
[17:59:53] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[17:59:53] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[17:59:53] [PASSED] single_pixel_source_buffer
[17:59:53] [PASSED] single_pixel_clip_rectangle
[17:59:53] [PASSED] well_known_colors
[17:59:53] [PASSED] destination_pitch
[17:59:53] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[17:59:53] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[17:59:53] [PASSED] single_pixel_source_buffer
[17:59:53] [PASSED] single_pixel_clip_rectangle
[17:59:53] [PASSED] well_known_colors
[17:59:53] [PASSED] destination_pitch
[17:59:53] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[17:59:53] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[17:59:53] [PASSED] single_pixel_source_buffer
[17:59:53] [PASSED] single_pixel_clip_rectangle
[17:59:53] [PASSED] well_known_colors
[17:59:53] [PASSED] destination_pitch
[17:59:53] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[17:59:53] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[17:59:53] [PASSED] single_pixel_source_buffer
[17:59:53] [PASSED] single_pixel_clip_rectangle
[17:59:53] [PASSED] well_known_colors
[17:59:53] [PASSED] destination_pitch
[17:59:53] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[17:59:53] ============== drm_test_fb_xrgb8888_to_mono  ===============
[17:59:53] [PASSED] single_pixel_source_buffer
[17:59:53] [PASSED] single_pixel_clip_rectangle
[17:59:53] [PASSED] well_known_colors
[17:59:53] [PASSED] destination_pitch
[17:59:53] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[17:59:53] ==================== drm_test_fb_swab  =====================
[17:59:53] [PASSED] single_pixel_source_buffer
[17:59:53] [PASSED] single_pixel_clip_rectangle
[17:59:53] [PASSED] well_known_colors
[17:59:53] [PASSED] destination_pitch
[17:59:53] ================ [PASSED] drm_test_fb_swab =================
[17:59:53] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[17:59:53] [PASSED] single_pixel_source_buffer
[17:59:53] [PASSED] single_pixel_clip_rectangle
[17:59:53] [PASSED] well_known_colors
[17:59:53] [PASSED] destination_pitch
[17:59:53] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[17:59:53] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[17:59:53] [PASSED] single_pixel_source_buffer
[17:59:53] [PASSED] single_pixel_clip_rectangle
[17:59:53] [PASSED] well_known_colors
[17:59:53] [PASSED] destination_pitch
[17:59:53] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[17:59:53] ================= drm_test_fb_clip_offset  =================
[17:59:53] [PASSED] pass through
[17:59:53] [PASSED] horizontal offset
[17:59:53] [PASSED] vertical offset
[17:59:53] [PASSED] horizontal and vertical offset
[17:59:53] [PASSED] horizontal offset (custom pitch)
[17:59:53] [PASSED] vertical offset (custom pitch)
[17:59:53] [PASSED] horizontal and vertical offset (custom pitch)
[17:59:53] ============= [PASSED] drm_test_fb_clip_offset =============
[17:59:53] =================== drm_test_fb_memcpy  ====================
[17:59:53] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[17:59:53] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[17:59:53] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[17:59:53] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[17:59:53] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[17:59:53] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[17:59:53] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[17:59:53] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[17:59:53] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[17:59:53] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[17:59:53] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[17:59:53] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[17:59:53] =============== [PASSED] drm_test_fb_memcpy ================
[17:59:53] ============= [PASSED] drm_format_helper_test ==============
[17:59:53] ================= drm_format (18 subtests) =================
[17:59:53] [PASSED] drm_test_format_block_width_invalid
[17:59:53] [PASSED] drm_test_format_block_width_one_plane
[17:59:53] [PASSED] drm_test_format_block_width_two_plane
[17:59:53] [PASSED] drm_test_format_block_width_three_plane
[17:59:53] [PASSED] drm_test_format_block_width_tiled
[17:59:53] [PASSED] drm_test_format_block_height_invalid
[17:59:53] [PASSED] drm_test_format_block_height_one_plane
[17:59:53] [PASSED] drm_test_format_block_height_two_plane
[17:59:53] [PASSED] drm_test_format_block_height_three_plane
[17:59:53] [PASSED] drm_test_format_block_height_tiled
[17:59:53] [PASSED] drm_test_format_min_pitch_invalid
[17:59:53] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[17:59:53] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[17:59:53] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[17:59:53] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[17:59:53] [PASSED] drm_test_format_min_pitch_two_plane
[17:59:53] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[17:59:53] [PASSED] drm_test_format_min_pitch_tiled
[17:59:53] =================== [PASSED] drm_format ====================
[17:59:53] ============== drm_framebuffer (10 subtests) ===============
[17:59:53] ========== drm_test_framebuffer_check_src_coords  ==========
[17:59:53] [PASSED] Success: source fits into fb
[17:59:53] [PASSED] Fail: overflowing fb with x-axis coordinate
[17:59:53] [PASSED] Fail: overflowing fb with y-axis coordinate
[17:59:53] [PASSED] Fail: overflowing fb with source width
[17:59:53] [PASSED] Fail: overflowing fb with source height
[17:59:53] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[17:59:53] [PASSED] drm_test_framebuffer_cleanup
[17:59:53] =============== drm_test_framebuffer_create  ===============
[17:59:53] [PASSED] ABGR8888 normal sizes
[17:59:53] [PASSED] ABGR8888 max sizes
[17:59:53] [PASSED] ABGR8888 pitch greater than min required
[17:59:53] [PASSED] ABGR8888 pitch less than min required
[17:59:53] [PASSED] ABGR8888 Invalid width
[17:59:53] [PASSED] ABGR8888 Invalid buffer handle
[17:59:53] [PASSED] No pixel format
[17:59:53] [PASSED] ABGR8888 Width 0
[17:59:53] [PASSED] ABGR8888 Height 0
[17:59:53] [PASSED] ABGR8888 Out of bound height * pitch combination
[17:59:53] [PASSED] ABGR8888 Large buffer offset
[17:59:53] [PASSED] ABGR8888 Buffer offset for inexistent plane
[17:59:53] [PASSED] ABGR8888 Invalid flag
[17:59:53] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[17:59:53] [PASSED] ABGR8888 Valid buffer modifier
[17:59:53] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[17:59:53] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[17:59:53] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[17:59:53] [PASSED] NV12 Normal sizes
[17:59:53] [PASSED] NV12 Max sizes
[17:59:53] [PASSED] NV12 Invalid pitch
[17:59:53] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[17:59:53] [PASSED] NV12 different  modifier per-plane
[17:59:53] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[17:59:53] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[17:59:53] [PASSED] NV12 Modifier for inexistent plane
[17:59:53] [PASSED] NV12 Handle for inexistent plane
[17:59:53] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[17:59:53] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[17:59:53] [PASSED] YVU420 Normal sizes
[17:59:53] [PASSED] YVU420 Max sizes
[17:59:53] [PASSED] YVU420 Invalid pitch
[17:59:53] [PASSED] YVU420 Different pitches
[17:59:53] [PASSED] YVU420 Different buffer offsets/pitches
[17:59:53] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[17:59:53] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[17:59:53] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[17:59:53] [PASSED] YVU420 Valid modifier
[17:59:53] [PASSED] YVU420 Different modifiers per plane
[17:59:53] [PASSED] YVU420 Modifier for inexistent plane
[17:59:53] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[17:59:53] [PASSED] X0L2 Normal sizes
[17:59:53] [PASSED] X0L2 Max sizes
[17:59:53] [PASSED] X0L2 Invalid pitch
[17:59:53] [PASSED] X0L2 Pitch greater than minimum required
[17:59:53] [PASSED] X0L2 Handle for inexistent plane
[17:59:53] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[17:59:53] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[17:59:53] [PASSED] X0L2 Valid modifier
[17:59:53] [PASSED] X0L2 Modifier for inexistent plane
[17:59:53] =========== [PASSED] drm_test_framebuffer_create ===========
[17:59:53] [PASSED] drm_test_framebuffer_free
[17:59:53] [PASSED] drm_test_framebuffer_init
[17:59:53] [PASSED] drm_test_framebuffer_init_bad_format
[17:59:53] [PASSED] drm_test_framebuffer_init_dev_mismatch
[17:59:53] [PASSED] drm_test_framebuffer_lookup
[17:59:53] [PASSED] drm_test_framebuffer_lookup_inexistent
[17:59:53] [PASSED] drm_test_framebuffer_modifiers_not_supported
[17:59:53] ================= [PASSED] drm_framebuffer =================
[17:59:53] ================ drm_gem_shmem (8 subtests) ================
[17:59:53] [PASSED] drm_gem_shmem_test_obj_create
[17:59:53] [PASSED] drm_gem_shmem_test_obj_create_private
[17:59:53] [PASSED] drm_gem_shmem_test_pin_pages
[17:59:53] [PASSED] drm_gem_shmem_test_vmap
[17:59:53] [PASSED] drm_gem_shmem_test_get_sg_table
[17:59:53] [PASSED] drm_gem_shmem_test_get_pages_sgt
[17:59:53] [PASSED] drm_gem_shmem_test_madvise
[17:59:53] [PASSED] drm_gem_shmem_test_purge
[17:59:53] ================== [PASSED] drm_gem_shmem ==================
[17:59:53] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[17:59:53] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[17:59:53] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[17:59:53] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[17:59:53] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[17:59:53] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[17:59:53] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[17:59:53] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[17:59:53] [PASSED] Automatic
[17:59:53] [PASSED] Full
[17:59:53] [PASSED] Limited 16:235
[17:59:53] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[17:59:53] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[17:59:53] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[17:59:53] [PASSED] drm_test_check_disable_connector
[17:59:53] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[17:59:53] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[17:59:53] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[17:59:53] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[17:59:53] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[17:59:53] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[17:59:53] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[17:59:53] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[17:59:53] [PASSED] drm_test_check_output_bpc_dvi
[17:59:53] [PASSED] drm_test_check_output_bpc_format_vic_1
[17:59:53] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[17:59:53] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[17:59:53] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[17:59:53] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[17:59:53] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[17:59:53] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[17:59:53] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[17:59:53] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[17:59:53] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[17:59:53] [PASSED] drm_test_check_broadcast_rgb_value
[17:59:53] [PASSED] drm_test_check_bpc_8_value
[17:59:53] [PASSED] drm_test_check_bpc_10_value
[17:59:53] [PASSED] drm_test_check_bpc_12_value
[17:59:53] [PASSED] drm_test_check_format_value
[17:59:53] [PASSED] drm_test_check_tmds_char_value
[17:59:53] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[17:59:53] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[17:59:53] [PASSED] drm_test_check_mode_valid
[17:59:53] [PASSED] drm_test_check_mode_valid_reject
[17:59:53] [PASSED] drm_test_check_mode_valid_reject_rate
[17:59:53] [PASSED] drm_test_check_mode_valid_reject_max_clock
[17:59:53] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[17:59:53] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[17:59:53] [PASSED] drm_test_check_infoframes
[17:59:53] [PASSED] drm_test_check_reject_avi_infoframe
[17:59:53] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[17:59:53] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[17:59:53] [PASSED] drm_test_check_reject_audio_infoframe
[17:59:53] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[17:59:53] ================= drm_managed (2 subtests) =================
[17:59:53] [PASSED] drm_test_managed_release_action
[17:59:53] [PASSED] drm_test_managed_run_action
[17:59:53] =================== [PASSED] drm_managed ===================
[17:59:53] =================== drm_mm (6 subtests) ====================
[17:59:53] [PASSED] drm_test_mm_init
[17:59:53] [PASSED] drm_test_mm_debug
[17:59:53] [PASSED] drm_test_mm_align32
[17:59:53] [PASSED] drm_test_mm_align64
[17:59:53] [PASSED] drm_test_mm_lowest
[17:59:53] [PASSED] drm_test_mm_highest
[17:59:53] ===================== [PASSED] drm_mm ======================
[17:59:53] ============= drm_modes_analog_tv (5 subtests) =============
[17:59:53] [PASSED] drm_test_modes_analog_tv_mono_576i
[17:59:53] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[17:59:53] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[17:59:53] [PASSED] drm_test_modes_analog_tv_pal_576i
[17:59:53] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[17:59:53] =============== [PASSED] drm_modes_analog_tv ===============
[17:59:53] ============== drm_plane_helper (2 subtests) ===============
[17:59:53] =============== drm_test_check_plane_state  ================
[17:59:53] [PASSED] clipping_simple
[17:59:53] [PASSED] clipping_rotate_reflect
[17:59:53] [PASSED] positioning_simple
[17:59:53] [PASSED] upscaling
[17:59:53] [PASSED] downscaling
[17:59:53] [PASSED] rounding1
[17:59:53] [PASSED] rounding2
[17:59:53] [PASSED] rounding3
[17:59:53] [PASSED] rounding4
[17:59:53] =========== [PASSED] drm_test_check_plane_state ============
[17:59:53] =========== drm_test_check_invalid_plane_state  ============
[17:59:53] [PASSED] positioning_invalid
[17:59:53] [PASSED] upscaling_invalid
[17:59:53] [PASSED] downscaling_invalid
[17:59:53] ======= [PASSED] drm_test_check_invalid_plane_state ========
[17:59:53] ================ [PASSED] drm_plane_helper =================
[17:59:53] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[17:59:53] ====== drm_test_connector_helper_tv_get_modes_check  =======
[17:59:53] [PASSED] None
[17:59:53] [PASSED] PAL
[17:59:53] [PASSED] NTSC
[17:59:53] [PASSED] Both, NTSC Default
[17:59:53] [PASSED] Both, PAL Default
[17:59:53] [PASSED] Both, NTSC Default, with PAL on command-line
[17:59:53] [PASSED] Both, PAL Default, with NTSC on command-line
[17:59:53] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[17:59:53] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[17:59:53] ================== drm_rect (9 subtests) ===================
[17:59:53] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[17:59:53] [PASSED] drm_test_rect_clip_scaled_not_clipped
[17:59:53] [PASSED] drm_test_rect_clip_scaled_clipped
[17:59:53] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[17:59:53] ================= drm_test_rect_intersect  =================
[17:59:53] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[17:59:53] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[17:59:53] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[17:59:53] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[17:59:53] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[17:59:53] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[17:59:53] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[17:59:53] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[17:59:53] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[17:59:53] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[17:59:53] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[17:59:53] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[17:59:53] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[17:59:53] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[17:59:53] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[17:59:53] ============= [PASSED] drm_test_rect_intersect =============
[17:59:53] ================ drm_test_rect_calc_hscale  ================
[17:59:53] [PASSED] normal use
[17:59:53] [PASSED] out of max range
[17:59:53] [PASSED] out of min range
[17:59:53] [PASSED] zero dst
[17:59:53] [PASSED] negative src
[17:59:53] [PASSED] negative dst
[17:59:53] ============ [PASSED] drm_test_rect_calc_hscale ============
[17:59:53] ================ drm_test_rect_calc_vscale  ================
[17:59:53] [PASSED] normal use
[17:59:53] [PASSED] out of max range
[17:59:53] [PASSED] out of min range
[17:59:53] [PASSED] zero dst
[17:59:53] [PASSED] negative src
[17:59:53] [PASSED] negative dst
[17:59:53] ============ [PASSED] drm_test_rect_calc_vscale ============
[17:59:53] ================== drm_test_rect_rotate  ===================
[17:59:53] [PASSED] reflect-x
[17:59:53] [PASSED] reflect-y
[17:59:53] [PASSED] rotate-0
[17:59:53] [PASSED] rotate-90
[17:59:53] [PASSED] rotate-180
[17:59:53] [PASSED] rotate-270
[17:59:53] ============== [PASSED] drm_test_rect_rotate ===============
[17:59:53] ================ drm_test_rect_rotate_inv  =================
[17:59:53] [PASSED] reflect-x
[17:59:53] [PASSED] reflect-y
[17:59:53] [PASSED] rotate-0
[17:59:53] [PASSED] rotate-90
[17:59:53] [PASSED] rotate-180
[17:59:53] [PASSED] rotate-270
[17:59:53] ============ [PASSED] drm_test_rect_rotate_inv =============
[17:59:53] ==================== [PASSED] drm_rect =====================
[17:59:53] ============ drm_sysfb_modeset_test (1 subtest) ============
[17:59:53] ============ drm_test_sysfb_build_fourcc_list  =============
[17:59:53] [PASSED] no native formats
[17:59:53] [PASSED] XRGB8888 as native format
[17:59:53] [PASSED] remove duplicates
[17:59:53] [PASSED] convert alpha formats
[17:59:53] [PASSED] random formats
[17:59:53] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[17:59:53] ============= [PASSED] drm_sysfb_modeset_test ==============
[17:59:53] ================== drm_fixp (2 subtests) ===================
[17:59:53] [PASSED] drm_test_int2fixp
[17:59:53] [PASSED] drm_test_sm2fixp
[17:59:53] ==================== [PASSED] drm_fixp =====================
[17:59:53] ============================================================
[17:59:53] Testing complete. Ran 621 tests: passed: 621
[17:59:53] Elapsed time: 26.136s total, 1.615s configuring, 24.355s building, 0.120s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[17:59:53] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:59:54] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[18:00:04] Starting KUnit Kernel (1/1)...
[18:00:04] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[18:00:04] ================= ttm_device (5 subtests) ==================
[18:00:04] [PASSED] ttm_device_init_basic
[18:00:04] [PASSED] ttm_device_init_multiple
[18:00:04] [PASSED] ttm_device_fini_basic
[18:00:04] [PASSED] ttm_device_init_no_vma_man
[18:00:04] ================== ttm_device_init_pools  ==================
[18:00:04] [PASSED] No DMA allocations, no DMA32 required
[18:00:04] [PASSED] DMA allocations, DMA32 required
[18:00:04] [PASSED] No DMA allocations, DMA32 required
[18:00:04] [PASSED] DMA allocations, no DMA32 required
[18:00:04] ============== [PASSED] ttm_device_init_pools ==============
[18:00:04] =================== [PASSED] ttm_device ====================
[18:00:04] ================== ttm_pool (8 subtests) ===================
[18:00:04] ================== ttm_pool_alloc_basic  ===================
[18:00:04] [PASSED] One page
[18:00:04] [PASSED] More than one page
[18:00:04] [PASSED] Above the allocation limit
[18:00:04] [PASSED] One page, with coherent DMA mappings enabled
[18:00:04] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[18:00:04] ============== [PASSED] ttm_pool_alloc_basic ===============
[18:00:04] ============== ttm_pool_alloc_basic_dma_addr  ==============
[18:00:04] [PASSED] One page
[18:00:04] [PASSED] More than one page
[18:00:04] [PASSED] Above the allocation limit
[18:00:04] [PASSED] One page, with coherent DMA mappings enabled
[18:00:04] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[18:00:04] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[18:00:04] [PASSED] ttm_pool_alloc_order_caching_match
[18:00:04] [PASSED] ttm_pool_alloc_caching_mismatch
[18:00:04] [PASSED] ttm_pool_alloc_order_mismatch
[18:00:04] [PASSED] ttm_pool_free_dma_alloc
[18:00:04] [PASSED] ttm_pool_free_no_dma_alloc
[18:00:04] [PASSED] ttm_pool_fini_basic
[18:00:04] ==================== [PASSED] ttm_pool =====================
[18:00:04] ================ ttm_resource (8 subtests) =================
[18:00:04] ================= ttm_resource_init_basic  =================
[18:00:04] [PASSED] Init resource in TTM_PL_SYSTEM
[18:00:04] [PASSED] Init resource in TTM_PL_VRAM
[18:00:04] [PASSED] Init resource in a private placement
[18:00:04] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[18:00:04] ============= [PASSED] ttm_resource_init_basic =============
[18:00:04] [PASSED] ttm_resource_init_pinned
[18:00:04] [PASSED] ttm_resource_fini_basic
[18:00:04] [PASSED] ttm_resource_manager_init_basic
[18:00:04] [PASSED] ttm_resource_manager_usage_basic
[18:00:04] [PASSED] ttm_resource_manager_set_used_basic
[18:00:04] [PASSED] ttm_sys_man_alloc_basic
[18:00:04] [PASSED] ttm_sys_man_free_basic
[18:00:04] ================== [PASSED] ttm_resource ===================
[18:00:04] =================== ttm_tt (15 subtests) ===================
[18:00:04] ==================== ttm_tt_init_basic  ====================
[18:00:04] [PASSED] Page-aligned size
[18:00:04] [PASSED] Extra pages requested
[18:00:04] ================ [PASSED] ttm_tt_init_basic ================
[18:00:04] [PASSED] ttm_tt_init_misaligned
[18:00:04] [PASSED] ttm_tt_fini_basic
[18:00:04] [PASSED] ttm_tt_fini_sg
[18:00:04] [PASSED] ttm_tt_fini_shmem
[18:00:04] [PASSED] ttm_tt_create_basic
[18:00:04] [PASSED] ttm_tt_create_invalid_bo_type
[18:00:04] [PASSED] ttm_tt_create_ttm_exists
[18:00:04] [PASSED] ttm_tt_create_failed
[18:00:04] [PASSED] ttm_tt_destroy_basic
[18:00:04] [PASSED] ttm_tt_populate_null_ttm
[18:00:04] [PASSED] ttm_tt_populate_populated_ttm
[18:00:04] [PASSED] ttm_tt_unpopulate_basic
[18:00:04] [PASSED] ttm_tt_unpopulate_empty_ttm
[18:00:04] [PASSED] ttm_tt_swapin_basic
[18:00:04] ===================== [PASSED] ttm_tt ======================
[18:00:04] =================== ttm_bo (14 subtests) ===================
[18:00:04] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[18:00:04] [PASSED] Cannot be interrupted and sleeps
[18:00:04] [PASSED] Cannot be interrupted, locks straight away
[18:00:04] [PASSED] Can be interrupted, sleeps
[18:00:04] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[18:00:04] [PASSED] ttm_bo_reserve_locked_no_sleep
[18:00:04] [PASSED] ttm_bo_reserve_no_wait_ticket
[18:00:04] [PASSED] ttm_bo_reserve_double_resv
[18:00:04] [PASSED] ttm_bo_reserve_interrupted
[18:00:04] [PASSED] ttm_bo_reserve_deadlock
[18:00:04] [PASSED] ttm_bo_unreserve_basic
[18:00:04] [PASSED] ttm_bo_unreserve_pinned
[18:00:04] [PASSED] ttm_bo_unreserve_bulk
[18:00:04] [PASSED] ttm_bo_fini_basic
[18:00:04] [PASSED] ttm_bo_fini_shared_resv
[18:00:04] [PASSED] ttm_bo_pin_basic
[18:00:04] [PASSED] ttm_bo_pin_unpin_resource
[18:00:04] [PASSED] ttm_bo_multiple_pin_one_unpin
[18:00:04] ===================== [PASSED] ttm_bo ======================
[18:00:04] ============== ttm_bo_validate (22 subtests) ===============
[18:00:04] ============== ttm_bo_init_reserved_sys_man  ===============
[18:00:04] [PASSED] Buffer object for userspace
[18:00:04] [PASSED] Kernel buffer object
[18:00:04] [PASSED] Shared buffer object
[18:00:04] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[18:00:04] ============== ttm_bo_init_reserved_mock_man  ==============
[18:00:04] [PASSED] Buffer object for userspace
[18:00:04] [PASSED] Kernel buffer object
[18:00:04] [PASSED] Shared buffer object
[18:00:04] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[18:00:04] [PASSED] ttm_bo_init_reserved_resv
[18:00:04] ================== ttm_bo_validate_basic  ==================
[18:00:04] [PASSED] Buffer object for userspace
[18:00:04] [PASSED] Kernel buffer object
[18:00:04] [PASSED] Shared buffer object
[18:00:04] ============== [PASSED] ttm_bo_validate_basic ==============
[18:00:04] [PASSED] ttm_bo_validate_invalid_placement
[18:00:04] ============= ttm_bo_validate_same_placement  ==============
[18:00:04] [PASSED] System manager
[18:00:04] [PASSED] VRAM manager
[18:00:04] ========= [PASSED] ttm_bo_validate_same_placement ==========
[18:00:04] [PASSED] ttm_bo_validate_failed_alloc
[18:00:04] [PASSED] ttm_bo_validate_pinned
[18:00:04] [PASSED] ttm_bo_validate_busy_placement
[18:00:04] ================ ttm_bo_validate_multihop  =================
[18:00:04] [PASSED] Buffer object for userspace
[18:00:04] [PASSED] Kernel buffer object
[18:00:04] [PASSED] Shared buffer object
[18:00:04] ============ [PASSED] ttm_bo_validate_multihop =============
[18:00:04] ========== ttm_bo_validate_no_placement_signaled  ==========
[18:00:04] [PASSED] Buffer object in system domain, no page vector
[18:00:04] [PASSED] Buffer object in system domain with an existing page vector
[18:00:04] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[18:00:04] ======== ttm_bo_validate_no_placement_not_signaled  ========
[18:00:04] [PASSED] Buffer object for userspace
[18:00:04] [PASSED] Kernel buffer object
[18:00:04] [PASSED] Shared buffer object
[18:00:04] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[18:00:04] [PASSED] ttm_bo_validate_move_fence_signaled
[18:00:04] ========= ttm_bo_validate_move_fence_not_signaled  =========
[18:00:04] [PASSED] Waits for GPU
[18:00:04] [PASSED] Tries to lock straight away
[18:00:04] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[18:00:04] [PASSED] ttm_bo_validate_swapout
[18:00:04] [PASSED] ttm_bo_validate_happy_evict
[18:00:04] [PASSED] ttm_bo_validate_all_pinned_evict
[18:00:04] [PASSED] ttm_bo_validate_allowed_only_evict
[18:00:04] [PASSED] ttm_bo_validate_deleted_evict
[18:00:04] [PASSED] ttm_bo_validate_busy_domain_evict
[18:00:04] [PASSED] ttm_bo_validate_evict_gutting
[18:00:04] [PASSED] ttm_bo_validate_recrusive_evict
[18:00:04] ================= [PASSED] ttm_bo_validate =================
[18:00:04] ============================================================
[18:00:04] Testing complete. Ran 102 tests: passed: 102
[18:00:04] Elapsed time: 11.521s total, 1.716s configuring, 9.591s building, 0.177s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for CMTG enablement (rev7)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 936 bytes --]

== Series Details ==

Series: CMTG enablement (rev7)
URL   : https://patchwork.freedesktop.org/series/157663/
State : success

== Summary ==

CI Bug Log - changes from xe-5058-21b42374be17d486baf9392b56377afde67a778d_BAT -> xe-pw-157663v7_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5058-21b42374be17d486baf9392b56377afde67a778d -> xe-pw-157663v7

  IGT_8909: e68d82b442e3909dd053c97542aeb029707124cf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5058-21b42374be17d486baf9392b56377afde67a778d: 21b42374be17d486baf9392b56377afde67a778d
  xe-pw-157663v7: 157663v7

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/index.html

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✗ i915.CI.BAT: failure for CMTG enablement (rev6)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 10811 bytes --]

== Series Details ==

Series: CMTG enablement (rev6)
URL   : https://patchwork.freedesktop.org/series/157664/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_18486 -> Patchwork_157664v6
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_157664v6 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_157664v6, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/index.html

Participating hosts (42 -> 40)
------------------------------

  Missing    (2): bat-dg2-13 fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_157664v6:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@load:
    - bat-adlp-6:         [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/bat-adlp-6/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/bat-adlp-6/igt@i915_module_load@load.html
    - bat-arlh-3:         [PASS][3] -> [ABORT][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/bat-arlh-3/igt@i915_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/bat-arlh-3/igt@i915_module_load@load.html
    - bat-dg1-7:          [PASS][5] -> [ABORT][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/bat-dg1-7/igt@i915_module_load@load.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/bat-dg1-7/igt@i915_module_load@load.html
    - fi-glk-j4005:       [PASS][7] -> [ABORT][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/fi-glk-j4005/igt@i915_module_load@load.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/fi-glk-j4005/igt@i915_module_load@load.html
    - bat-adlp-9:         [PASS][9] -> [ABORT][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/bat-adlp-9/igt@i915_module_load@load.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/bat-adlp-9/igt@i915_module_load@load.html
    - bat-twl-2:          [PASS][11] -> [ABORT][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/bat-twl-2/igt@i915_module_load@load.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/bat-twl-2/igt@i915_module_load@load.html
    - bat-rpls-4:         [PASS][13] -> [ABORT][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/bat-rpls-4/igt@i915_module_load@load.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/bat-rpls-4/igt@i915_module_load@load.html
    - fi-cfl-8700k:       [PASS][15] -> [ABORT][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/fi-cfl-8700k/igt@i915_module_load@load.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/fi-cfl-8700k/igt@i915_module_load@load.html
    - bat-twl-1:          [PASS][17] -> [ABORT][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/bat-twl-1/igt@i915_module_load@load.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/bat-twl-1/igt@i915_module_load@load.html
    - bat-jsl-5:          [PASS][19] -> [ABORT][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/bat-jsl-5/igt@i915_module_load@load.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/bat-jsl-5/igt@i915_module_load@load.html
    - bat-apl-1:          [PASS][21] -> [ABORT][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/bat-apl-1/igt@i915_module_load@load.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/bat-apl-1/igt@i915_module_load@load.html
    - bat-dg2-14:         [PASS][23] -> [ABORT][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/bat-dg2-14/igt@i915_module_load@load.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/bat-dg2-14/igt@i915_module_load@load.html
    - bat-arls-5:         [PASS][25] -> [ABORT][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/bat-arls-5/igt@i915_module_load@load.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/bat-arls-5/igt@i915_module_load@load.html
    - fi-tgl-1115g4:      [PASS][27] -> [ABORT][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/fi-tgl-1115g4/igt@i915_module_load@load.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/fi-tgl-1115g4/igt@i915_module_load@load.html
    - fi-cfl-guc:         [PASS][29] -> [ABORT][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/fi-cfl-guc/igt@i915_module_load@load.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/fi-cfl-guc/igt@i915_module_load@load.html
    - bat-mtlp-9:         [PASS][31] -> [ABORT][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/bat-mtlp-9/igt@i915_module_load@load.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/bat-mtlp-9/igt@i915_module_load@load.html
    - bat-arls-6:         [PASS][33] -> [ABORT][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/bat-arls-6/igt@i915_module_load@load.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/bat-arls-6/igt@i915_module_load@load.html
    - bat-dg2-9:          [PASS][35] -> [ABORT][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/bat-dg2-9/igt@i915_module_load@load.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/bat-dg2-9/igt@i915_module_load@load.html
    - fi-hsw-4770:        [PASS][37] -> [ABORT][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/fi-hsw-4770/igt@i915_module_load@load.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/fi-hsw-4770/igt@i915_module_load@load.html
    - fi-cfl-8109u:       [PASS][39] -> [ABORT][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/fi-cfl-8109u/igt@i915_module_load@load.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/fi-cfl-8109u/igt@i915_module_load@load.html
    - bat-mtlp-8:         [PASS][41] -> [ABORT][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/bat-mtlp-8/igt@i915_module_load@load.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/bat-mtlp-8/igt@i915_module_load@load.html
    - bat-dg2-8:          [PASS][43] -> [ABORT][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/bat-dg2-8/igt@i915_module_load@load.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/bat-dg2-8/igt@i915_module_load@load.html
    - bat-adls-6:         [PASS][45] -> [ABORT][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/bat-adls-6/igt@i915_module_load@load.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/bat-adls-6/igt@i915_module_load@load.html

  * igt@kms_busy@basic:
    - fi-skl-6600u:       [PASS][47] -> [ABORT][48] +1 other test abort
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/fi-skl-6600u/igt@kms_busy@basic.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/fi-skl-6600u/igt@kms_busy@basic.html

  * igt@kms_busy@basic@modeset:
    - bat-rplp-1:         [PASS][49] -> [ABORT][50] +1 other test abort
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/bat-rplp-1/igt@kms_busy@basic@modeset.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/bat-rplp-1/igt@kms_busy@basic@modeset.html

  * igt@kms_force_connector_basic@force-connector-state:
    - fi-rkl-11600:       [PASS][51] -> [ABORT][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/fi-rkl-11600/igt@kms_force_connector_basic@force-connector-state.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/fi-rkl-11600/igt@kms_force_connector_basic@force-connector-state.html
    - fi-kbl-x1275:       [PASS][53] -> [ABORT][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/fi-kbl-x1275/igt@kms_force_connector_basic@force-connector-state.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/fi-kbl-x1275/igt@kms_force_connector_basic@force-connector-state.html
    - fi-kbl-8809g:       [PASS][55] -> [ABORT][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/fi-kbl-8809g/igt@kms_force_connector_basic@force-connector-state.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/fi-kbl-8809g/igt@kms_force_connector_basic@force-connector-state.html
    - bat-dg1-6:          [PASS][57] -> [ABORT][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/bat-dg1-6/igt@kms_force_connector_basic@force-connector-state.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/bat-dg1-6/igt@kms_force_connector_basic@force-connector-state.html

  * igt@kms_force_connector_basic@force-edid:
    - bat-kbl-2:          [PASS][59] -> [ABORT][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/bat-kbl-2/igt@kms_force_connector_basic@force-edid.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/bat-kbl-2/igt@kms_force_connector_basic@force-edid.html

  
Known issues
------------

  Here are the changes found in Patchwork_157664v6 that come from known issues:

### IGT changes ###

#### Warnings ####

  * igt@i915_module_load@load:
    - fi-kbl-7567u:       [DMESG-WARN][61] ([i915#13735] / [i915#15673] / [i915#180]) -> [ABORT][62] ([i915#180])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18486/fi-kbl-7567u/igt@i915_module_load@load.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/fi-kbl-7567u/igt@i915_module_load@load.html

  
  [i915#13735]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13735
  [i915#15673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15673
  [i915#180]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/180


Build changes
-------------

  * Linux: CI_DRM_18486 -> Patchwork_157664v6

  CI-20190529: 20190529
  CI_DRM_18486: e54a14bbf920aa5eefc70aba9927482ebe630f8b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8909: e68d82b442e3909dd053c97542aeb029707124cf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_157664v6: e54a14bbf920aa5eefc70aba9927482ebe630f8b @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157664v6/index.html

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✗ Xe.CI.FULL: failure for CMTG enablement (rev7)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 22136 bytes --]

== Series Details ==

Series: CMTG enablement (rev7)
URL   : https://patchwork.freedesktop.org/series/157663/
State : failure

== Summary ==

CI Bug Log - changes from xe-5058-21b42374be17d486baf9392b56377afde67a778d_FULL -> xe-pw-157663v7_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-157663v7_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-157663v7_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-157663v7_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-race-prefetch:
    - shard-bmg:          [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5058-21b42374be17d486baf9392b56377afde67a778d/shard-bmg-8/igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-race-prefetch.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-2/igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-race-prefetch.html

  
Known issues
------------

  Here are the changes found in xe-pw-157663v7_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#2370])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#2327]) +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#1124]) +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html

  * igt@kms_bw@linear-tiling-2-displays-target-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#367])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_bw@linear-tiling-2-displays-target-2560x1440p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2887]) +4 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs.html

  * igt@kms_chamelium_hpd@dp-hpd-storm-disable:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2252]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html

  * igt@kms_content_protection@mei-interface:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#7642])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-5/igt@kms_content_protection@mei-interface.html

  * igt@kms_cursor_crc@cursor-offscreen-128x42:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2320]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_cursor_crc@cursor-offscreen-128x42.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#4354] / [Intel XE#5882])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#2244])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-lnl-3/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2244])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#6126] / [Intel XE#776])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [PASS][15] -> [FAIL][16] ([Intel XE#301]) +1 other test fail
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5058-21b42374be17d486baf9392b56377afde67a778d/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [PASS][17] -> [FAIL][18] ([Intel XE#301] / [Intel XE#3149])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5058-21b42374be17d486baf9392b56377afde67a778d/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@wf_vblank-ts-check-interruptible:
    - shard-lnl:          [PASS][19] -> [FAIL][20] ([Intel XE#5408] / [Intel XE#6266]) +1 other test fail
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5058-21b42374be17d486baf9392b56377afde67a778d/shard-lnl-8/igt@kms_flip@wf_vblank-ts-check-interruptible.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-lnl-2/igt@kms_flip@wf_vblank-ts-check-interruptible.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#7178] / [Intel XE#7351])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#4141]) +3 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2311]) +12 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#656] / [Intel XE#7905]) +3 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-modesetfrombusy:
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#7865]) +3 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcpsrhdr-modesetfrombusy.html

  * igt@kms_frontbuffer_tracking@hdr-abgr161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#7061])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_frontbuffer_tracking@hdr-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2313]) +16 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#7905]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-lnl-3/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#6901])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#7283])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier-source-clamping:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#7283])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-lnl-3/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier-source-clamping.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#1489]) +1 other test skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr@psr2-no-drrs:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_psr@psr2-no-drrs.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#2330] / [Intel XE#5813])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#2509] / [Intel XE#7437])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#1499])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@xe_eudebug_online@single-step:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#7636]) +1 other test skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@xe_eudebug_online@single-step.html

  * igt@xe_evict@evict-beng-small-cm:
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#6540] / [Intel XE#688])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-lnl-3/igt@xe_evict@evict-beng-small-cm.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#2322] / [Intel XE#7372])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind.html

  * igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-race-imm:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#7136])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-race-imm.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-dyn-priority-smem:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#6874]) +6 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@xe_exec_multi_queue@few-execs-preempt-mode-dyn-priority-smem.html

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-basic-smem:
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#6874]) +2 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-lnl-3/igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-basic-smem.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-basic:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#7138])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@xe_exec_threads@threads-multi-queue-mixed-basic.html

  * igt@xe_page_reclaim@binds-1g-partial:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#7793])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@xe_page_reclaim@binds-1g-partial.html

  * igt@xe_pm@d3cold-basic-exec:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#2284] / [Intel XE#7370])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@xe_pm@d3cold-basic-exec.html

  * igt@xe_pmu@engine-activity-accuracy-90:
    - shard-lnl:          [PASS][47] -> [FAIL][48] ([Intel XE#7072]) +3 other tests fail
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5058-21b42374be17d486baf9392b56377afde67a778d/shard-lnl-2/igt@xe_pmu@engine-activity-accuracy-90.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-lnl-2/igt@xe_pmu@engine-activity-accuracy-90.html

  * igt@xe_query@multigpu-query-hwconfig:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#944])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@xe_query@multigpu-query-hwconfig.html

  * igt@xe_vm@overcommit-nonfault-vram-lr-external-nodefer:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#7892])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-lnl-3/igt@xe_vm@overcommit-nonfault-vram-lr-external-nodefer.html

  
#### Possible fixes ####

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [INCOMPLETE][51] ([Intel XE#7084]) -> [PASS][52] +1 other test pass
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5058-21b42374be17d486baf9392b56377afde67a778d/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-lnl:          [FAIL][53] ([Intel XE#301]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5058-21b42374be17d486baf9392b56377afde67a778d/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][55] ([Intel XE#1503]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5058-21b42374be17d486baf9392b56377afde67a778d/shard-bmg-10/igt@kms_hdr@invalid-hdr.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-3/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb16161616f:
    - shard-bmg:          [SKIP][57] ([Intel XE#7922]) -> [PASS][58] +1 other test pass
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5058-21b42374be17d486baf9392b56377afde67a778d/shard-bmg-10/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb16161616f.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-3/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb16161616f.html

  * igt@kms_hdr@static-swap:
    - shard-bmg:          [INCOMPLETE][59] -> [PASS][60] +1 other test pass
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5058-21b42374be17d486baf9392b56377afde67a778d/shard-bmg-3/igt@kms_hdr@static-swap.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_hdr@static-swap.html

  * igt@kms_hdr@static-toggle-dpms@pipe-a-hdmi-a-3-xrgb2101010:
    - shard-bmg:          [SKIP][61] ([Intel XE#7915]) -> [PASS][62] +5 other tests pass
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5058-21b42374be17d486baf9392b56377afde67a778d/shard-bmg-7/igt@kms_hdr@static-toggle-dpms@pipe-a-hdmi-a-3-xrgb2101010.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-10/igt@kms_hdr@static-toggle-dpms@pipe-a-hdmi-a-3-xrgb2101010.html

  * igt@xe_exec_reset@long-spin-sys-reuse-many-preempt-threads:
    - shard-bmg:          [FAIL][63] ([Intel XE#7850]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5058-21b42374be17d486baf9392b56377afde67a778d/shard-bmg-2/igt@xe_exec_reset@long-spin-sys-reuse-many-preempt-threads.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-bmg-1/igt@xe_exec_reset@long-spin-sys-reuse-many-preempt-threads.html

  
#### Warnings ####

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-lnl:          [FAIL][65] ([Intel XE#301]) -> [FAIL][66] ([Intel XE#301] / [Intel XE#3149])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5058-21b42374be17d486baf9392b56377afde67a778d/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2370
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#5408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5408
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#5882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5882
  [Intel XE#6126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6126
  [Intel XE#6266]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6266
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7072]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7072
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7850
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7892]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7892
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#7915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7915
  [Intel XE#7922]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7922
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5058-21b42374be17d486baf9392b56377afde67a778d -> xe-pw-157663v7

  IGT_8909: e68d82b442e3909dd053c97542aeb029707124cf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5058-21b42374be17d486baf9392b56377afde67a778d: 21b42374be17d486baf9392b56377afde67a778d
  xe-pw-157663v7: 157663v7

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v7/index.html

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