* [PATCH 1/9] ppc/ppc405: Remove tests
2025-01-10 14:17 [PATCH 0/9] ppc: Remove 405 CPU family Cédric Le Goater
@ 2025-01-10 14:17 ` Cédric Le Goater
2025-01-10 16:04 ` Philippe Mathieu-Daudé
2025-01-10 14:17 ` [PATCH 2/9] ppc/ppc405: Remove boards Cédric Le Goater
` (7 subsequent siblings)
8 siblings, 1 reply; 29+ messages in thread
From: Cédric Le Goater @ 2025-01-10 14:17 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, Nicholas Piggin, Daniel Henrique Barboza,
Cédric Le Goater
Since we are about to remove all support for PPC 405, start by
removing the tests referring to the ref405ep machine.
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
tests/qtest/m48t59-test.c | 5 -----
tests/functional/meson.build | 1 -
tests/functional/test_ppc_405.py | 37 --------------------------------
tests/qtest/meson.build | 1 -
4 files changed, 44 deletions(-)
delete mode 100755 tests/functional/test_ppc_405.py
diff --git a/tests/qtest/m48t59-test.c b/tests/qtest/m48t59-test.c
index 605797ab785d..1e39a0e8f07a 100644
--- a/tests/qtest/m48t59-test.c
+++ b/tests/qtest/m48t59-test.c
@@ -247,11 +247,6 @@ static void base_setup(void)
base_year = 1968;
base_machine = "SS-5";
use_mmio = true;
- } else if (g_str_equal(arch, "ppc") || g_str_equal(arch, "ppc64")) {
- base = 0xF0000000;
- base_year = 1968;
- base_machine = "ref405ep";
- use_mmio = true;
} else {
g_assert_not_reached();
}
diff --git a/tests/functional/meson.build b/tests/functional/meson.build
index a5087fcb34fc..9dd26d0ee8c4 100644
--- a/tests/functional/meson.build
+++ b/tests/functional/meson.build
@@ -156,7 +156,6 @@ tests_ppc_system_quick = [
]
tests_ppc_system_thorough = [
- 'ppc_405',
'ppc_40p',
'ppc_amiga',
'ppc_bamboo',
diff --git a/tests/functional/test_ppc_405.py b/tests/functional/test_ppc_405.py
deleted file mode 100755
index 9851c03ee998..000000000000
--- a/tests/functional/test_ppc_405.py
+++ /dev/null
@@ -1,37 +0,0 @@
-#!/usr/bin/env python3
-#
-# Test that the U-Boot firmware boots on ppc 405 machines and check the console
-#
-# Copyright (c) 2021 Red Hat, Inc.
-#
-# This work is licensed under the terms of the GNU GPL, version 2 or
-# later. See the COPYING file in the top-level directory.
-
-from qemu_test import QemuSystemTest, Asset
-from qemu_test import wait_for_console_pattern
-from qemu_test import exec_command_and_wait_for_pattern
-
-class Ppc405Machine(QemuSystemTest):
-
- timeout = 90
-
- ASSET_UBOOT = Asset(
- ('https://gitlab.com/huth/u-boot/-/raw/taihu-2021-10-09/'
- 'u-boot-taihu.bin'),
- 'a076bb6cdeaafa406330e51e074b66d8878d9036d67d4caa0137be03ee4c112c')
-
- def do_test_ppc405(self):
- file_path = self.ASSET_UBOOT.fetch()
- self.vm.set_console(console_index=1)
- self.vm.add_args('-bios', file_path)
- self.vm.launch()
- wait_for_console_pattern(self, 'AMCC PPC405EP Evaluation Board')
- exec_command_and_wait_for_pattern(self, 'reset', 'AMCC PowerPC 405EP')
-
- def test_ppc_ref405ep(self):
- self.require_accelerator("tcg")
- self.set_machine('ref405ep')
- self.do_test_ppc405()
-
-if __name__ == '__main__':
- QemuSystemTest.main()
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index c5a70021c50c..48885917d279 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -168,7 +168,6 @@ qtests_mips64el = qtests_mips
qtests_ppc = \
qtests_filter + \
(config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] : []) + \
- (config_all_devices.has_key('CONFIG_M48T59') ? ['m48t59-test'] : []) + \
(config_all_accel.has_key('CONFIG_TCG') ? ['prom-env-test'] : []) + \
(config_all_accel.has_key('CONFIG_TCG') ? ['boot-serial-test'] : []) + \
['boot-order-test']
--
2.47.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 1/9] ppc/ppc405: Remove tests
2025-01-10 14:17 ` [PATCH 1/9] ppc/ppc405: Remove tests Cédric Le Goater
@ 2025-01-10 16:04 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-10 16:04 UTC (permalink / raw)
To: Cédric Le Goater, qemu-devel
Cc: qemu-ppc, Nicholas Piggin, Daniel Henrique Barboza
On 10/1/25 15:17, Cédric Le Goater wrote:
> Since we are about to remove all support for PPC 405, start by
> removing the tests referring to the ref405ep machine.
>
> Signed-off-by: Cédric Le Goater <clg@redhat.com>
> ---
> tests/qtest/m48t59-test.c | 5 -----
> tests/functional/meson.build | 1 -
> tests/functional/test_ppc_405.py | 37 --------------------------------
> tests/qtest/meson.build | 1 -
> 4 files changed, 44 deletions(-)
> delete mode 100755 tests/functional/test_ppc_405.py
Missing removal of MAINTAINERS' entry for the test.
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 2/9] ppc/ppc405: Remove boards
2025-01-10 14:17 [PATCH 0/9] ppc: Remove 405 CPU family Cédric Le Goater
2025-01-10 14:17 ` [PATCH 1/9] ppc/ppc405: Remove tests Cédric Le Goater
@ 2025-01-10 14:17 ` Cédric Le Goater
2025-01-10 16:05 ` Philippe Mathieu-Daudé
2025-01-10 14:17 ` [PATCH 3/9] ppc/ppc405: Remove CPU Cédric Le Goater
` (6 subsequent siblings)
8 siblings, 1 reply; 29+ messages in thread
From: Cédric Le Goater @ 2025-01-10 14:17 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, Nicholas Piggin, Daniel Henrique Barboza,
Cédric Le Goater
The ref405ep machine is the only PPC 405 machine. Drop all support by
removing the SoC and associated devices as-well as the machine.
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
MAINTAINERS | 6 -
docs/about/deprecated.rst | 8 -
docs/about/removed-features.rst | 7 +
docs/system/ppc/embedded.rst | 1 -
hw/ppc/ppc405.h | 186 -----
hw/ppc/ppc405_boards.c | 520 -------------
hw/ppc/ppc405_uc.c | 1216 -------------------------------
hw/ppc/Kconfig | 9 -
hw/ppc/meson.build | 3 -
9 files changed, 7 insertions(+), 1949 deletions(-)
delete mode 100644 hw/ppc/ppc405.h
delete mode 100644 hw/ppc/ppc405_boards.c
delete mode 100644 hw/ppc/ppc405_uc.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 2101b5121756..dc48ec4ac081 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1387,12 +1387,6 @@ F: hw/openrisc/openrisc_sim.c
PowerPC Machines
----------------
-405 (ref405ep)
-L: qemu-ppc@nongnu.org
-S: Orphan
-F: hw/ppc/ppc405*
-F: tests/functional/test_ppc_405.py
-
Bamboo
L: qemu-ppc@nongnu.org
S: Orphan
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 4a3c302962a0..db9edfc24a0c 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -243,14 +243,6 @@ These old machine types are quite neglected nowadays and thus might have
various pitfalls with regards to live migration. Use a newer machine type
instead.
-PPC 405 ``ref405ep`` machine (since 9.1)
-''''''''''''''''''''''''''''''''''''''''
-
-The ``ref405ep`` machine and PPC 405 CPU have no known users, firmware
-images are not available, OpenWRT dropped support in 2019, U-Boot in
-2017, Linux also is dropping support in 2024. It is time to let go of
-this ancient hardware and focus on newer CPUs and platforms.
-
Big-Endian variants of MicroBlaze ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` machines (since 9.2)
''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst
index c6616ce05e59..1a0dae7cf259 100644
--- a/docs/about/removed-features.rst
+++ b/docs/about/removed-features.rst
@@ -1065,6 +1065,13 @@ for all machine types using the PXA2xx and OMAP2 SoCs. We are also
dropping the ``cheetah`` OMAP1 board, because we don't have any
test images for it and don't know of anybody who does.
+ppc ``ref405ep`` machine (removed in 10.0)
+''''''''''''''''''''''''''''''''''''''''''
+
+This machine was removed because PPC 405 CPU have no known users,
+firmware images are not available, OpenWRT dropped support in 2019,
+U-Boot in 2017, and Linux in 2024.
+
linux-user mode CPUs
--------------------
diff --git a/docs/system/ppc/embedded.rst b/docs/system/ppc/embedded.rst
index af3b3d9fa460..5cb7d98b450d 100644
--- a/docs/system/ppc/embedded.rst
+++ b/docs/system/ppc/embedded.rst
@@ -4,6 +4,5 @@ Embedded family boards
- ``bamboo`` bamboo
- ``mpc8544ds`` mpc8544ds
- ``ppce500`` generic paravirt e500 platform
-- ``ref405ep`` ref405ep
- ``sam460ex`` aCube Sam460ex
- ``virtex-ml507`` Xilinx Virtex ML507 reference design
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
deleted file mode 100644
index 9a4312691e15..000000000000
--- a/hw/ppc/ppc405.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * QEMU PowerPC 405 shared definitions
- *
- * Copyright (c) 2007 Jocelyn Mayer
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef PPC405_H
-#define PPC405_H
-
-#include "qom/object.h"
-#include "hw/ppc/ppc4xx.h"
-#include "hw/intc/ppc-uic.h"
-#include "hw/i2c/ppc4xx_i2c.h"
-
-/* PLB to OPB bridge */
-#define TYPE_PPC405_POB "ppc405-pob"
-OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
-struct Ppc405PobState {
- Ppc4xxDcrDeviceState parent_obj;
-
- uint32_t bear;
- uint32_t besr0;
- uint32_t besr1;
-};
-
-/* OPB arbitrer */
-#define TYPE_PPC405_OPBA "ppc405-opba"
-OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
-struct Ppc405OpbaState {
- SysBusDevice parent_obj;
-
- MemoryRegion io;
- uint8_t cr;
- uint8_t pr;
-};
-
-/* DMA controller */
-#define TYPE_PPC405_DMA "ppc405-dma"
-OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA);
-struct Ppc405DmaState {
- Ppc4xxDcrDeviceState parent_obj;
-
- qemu_irq irqs[4];
- uint32_t cr[4];
- uint32_t ct[4];
- uint32_t da[4];
- uint32_t sa[4];
- uint32_t sg[4];
- uint32_t sr;
- uint32_t sgc;
- uint32_t slp;
- uint32_t pol;
-};
-
-/* GPIO */
-#define TYPE_PPC405_GPIO "ppc405-gpio"
-OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO);
-struct Ppc405GpioState {
- SysBusDevice parent_obj;
-
- MemoryRegion io;
- uint32_t or;
- uint32_t tcr;
- uint32_t osrh;
- uint32_t osrl;
- uint32_t tsrh;
- uint32_t tsrl;
- uint32_t odr;
- uint32_t ir;
- uint32_t rr1;
- uint32_t isr1h;
- uint32_t isr1l;
-};
-
-/* On Chip Memory */
-#define TYPE_PPC405_OCM "ppc405-ocm"
-OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM);
-struct Ppc405OcmState {
- Ppc4xxDcrDeviceState parent_obj;
-
- MemoryRegion ram;
- MemoryRegion isarc_ram;
- MemoryRegion dsarc_ram;
- uint32_t isarc;
- uint32_t isacntl;
- uint32_t dsarc;
- uint32_t dsacntl;
-};
-
-/* General purpose timers */
-#define TYPE_PPC405_GPT "ppc405-gpt"
-OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT);
-struct Ppc405GptState {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
-
- int64_t tb_offset;
- uint32_t tb_freq;
- QEMUTimer *timer;
- qemu_irq irqs[5];
- uint32_t oe;
- uint32_t ol;
- uint32_t im;
- uint32_t is;
- uint32_t ie;
- uint32_t comp[5];
- uint32_t mask[5];
-};
-
-#define TYPE_PPC405_CPC "ppc405-cpc"
-OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC);
-
-enum {
- PPC405EP_CPU_CLK = 0,
- PPC405EP_PLB_CLK = 1,
- PPC405EP_OPB_CLK = 2,
- PPC405EP_EBC_CLK = 3,
- PPC405EP_MAL_CLK = 4,
- PPC405EP_PCI_CLK = 5,
- PPC405EP_UART0_CLK = 6,
- PPC405EP_UART1_CLK = 7,
- PPC405EP_CLK_NB = 8,
-};
-
-struct Ppc405CpcState {
- Ppc4xxDcrDeviceState parent_obj;
-
- uint32_t sysclk;
- clk_setup_t clk_setup[PPC405EP_CLK_NB];
- uint32_t boot;
- uint32_t epctl;
- uint32_t pllmr[2];
- uint32_t ucr;
- uint32_t srr;
- uint32_t jtagid;
- uint32_t pci;
- /* Clock and power management */
- uint32_t er;
- uint32_t fr;
- uint32_t sr;
-};
-
-#define TYPE_PPC405_SOC "ppc405-soc"
-OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
-
-struct Ppc405SoCState {
- /* Private */
- DeviceState parent_obj;
-
- /* Public */
- PowerPCCPU cpu;
- PPCUIC uic;
- Ppc405CpcState cpc;
- Ppc405GptState gpt;
- Ppc405OcmState ocm;
- Ppc405GpioState gpio;
- Ppc405DmaState dma;
- PPC4xxI2CState i2c;
- Ppc4xxEbcState ebc;
- Ppc405OpbaState opba;
- Ppc405PobState pob;
- Ppc4xxPlbState plb;
- Ppc4xxMalState mal;
- Ppc4xxSdramDdrState sdram;
-};
-
-#endif /* PPC405_H */
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
deleted file mode 100644
index e9f65fab70d4..000000000000
--- a/hw/ppc/ppc405_boards.c
+++ /dev/null
@@ -1,520 +0,0 @@
-/*
- * QEMU PowerPC 405 evaluation boards emulation
- *
- * Copyright (c) 2007 Jocelyn Mayer
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "qemu/osdep.h"
-#include "qemu/units.h"
-#include "qapi/error.h"
-#include "qemu/datadir.h"
-#include "cpu.h"
-#include "hw/ppc/ppc.h"
-#include "hw/qdev-properties.h"
-#include "hw/sysbus.h"
-#include "ppc405.h"
-#include "hw/rtc/m48t59.h"
-#include "hw/block/flash.h"
-#include "system/qtest.h"
-#include "system/reset.h"
-#include "system/block-backend.h"
-#include "hw/boards.h"
-#include "qemu/error-report.h"
-#include "hw/loader.h"
-#include "qemu/cutils.h"
-#include "elf.h"
-
-#define BIOS_FILENAME "ppc405_rom.bin"
-#define BIOS_SIZE (2 * MiB)
-
-#define KERNEL_LOAD_ADDR 0x01000000
-#define INITRD_LOAD_ADDR 0x01800000
-
-#define PPC405EP_SDRAM_BASE 0x00000000
-#define PPC405EP_SRAM_BASE 0xFFF00000
-#define PPC405EP_SRAM_SIZE (512 * KiB)
-
-#define USE_FLASH_BIOS
-
-#define TYPE_PPC405_MACHINE MACHINE_TYPE_NAME("ppc405")
-OBJECT_DECLARE_SIMPLE_TYPE(Ppc405MachineState, PPC405_MACHINE);
-
-struct Ppc405MachineState {
- /* Private */
- MachineState parent_obj;
- /* Public */
-
- Ppc405SoCState soc;
-};
-
-/* CPU reset handler when booting directly from a loaded kernel */
-static struct boot_info {
- uint32_t entry;
- uint32_t bdloc;
- uint32_t initrd_base;
- uint32_t initrd_size;
- uint32_t cmdline_base;
- uint32_t cmdline_size;
-} boot_info;
-
-static void main_cpu_reset(void *opaque)
-{
- PowerPCCPU *cpu = opaque;
- CPUPPCState *env = &cpu->env;
- struct boot_info *bi = env->load_info;
-
- cpu_reset(CPU(cpu));
-
- /* stack: top of sram */
- env->gpr[1] = PPC405EP_SRAM_BASE + PPC405EP_SRAM_SIZE - 8;
-
- /* Tune our boot state */
- env->gpr[3] = bi->bdloc;
- env->gpr[4] = bi->initrd_base;
- env->gpr[5] = bi->initrd_base + bi->initrd_size;
- env->gpr[6] = bi->cmdline_base;
- env->gpr[7] = bi->cmdline_size;
-
- env->nip = bi->entry;
-}
-
-/* Bootinfo as set-up by u-boot */
-typedef struct {
- uint32_t bi_memstart;
- uint32_t bi_memsize;
- uint32_t bi_flashstart;
- uint32_t bi_flashsize;
- uint32_t bi_flashoffset; /* 0x10 */
- uint32_t bi_sramstart;
- uint32_t bi_sramsize;
- uint32_t bi_bootflags;
- uint32_t bi_ipaddr; /* 0x20 */
- uint8_t bi_enetaddr[6];
- uint16_t bi_ethspeed;
- uint32_t bi_intfreq;
- uint32_t bi_busfreq; /* 0x30 */
- uint32_t bi_baudrate;
- uint8_t bi_s_version[4];
- uint8_t bi_r_version[32];
- uint32_t bi_procfreq;
- uint32_t bi_plb_busfreq;
- uint32_t bi_pci_busfreq;
- uint8_t bi_pci_enetaddr[6];
- uint8_t bi_pci_enetaddr2[6]; /* PPC405EP specific */
- uint32_t bi_opbfreq;
- uint32_t bi_iic_fast[2];
-} ppc4xx_bd_info_t;
-
-static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd,
- ram_addr_t ram_size)
-{
- memset(bd, 0, sizeof(*bd));
-
- bd->bi_memstart = PPC405EP_SDRAM_BASE;
- bd->bi_memsize = ram_size;
- bd->bi_sramstart = PPC405EP_SRAM_BASE;
- bd->bi_sramsize = PPC405EP_SRAM_SIZE;
- bd->bi_bootflags = 0;
- bd->bi_intfreq = 133333333;
- bd->bi_busfreq = 33333333;
- bd->bi_baudrate = 115200;
- bd->bi_s_version[0] = 'Q';
- bd->bi_s_version[1] = 'M';
- bd->bi_s_version[2] = 'U';
- bd->bi_s_version[3] = '\0';
- bd->bi_r_version[0] = 'Q';
- bd->bi_r_version[1] = 'E';
- bd->bi_r_version[2] = 'M';
- bd->bi_r_version[3] = 'U';
- bd->bi_r_version[4] = '\0';
- bd->bi_procfreq = 133333333;
- bd->bi_plb_busfreq = 33333333;
- bd->bi_pci_busfreq = 33333333;
- bd->bi_opbfreq = 33333333;
-}
-
-static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd)
-{
- CPUState *cs = env_cpu(env);
- ram_addr_t bdloc;
- int i, n;
-
- /* We put the bd structure at the top of memory */
- if (bd->bi_memsize >= 0x01000000UL) {
- bdloc = 0x01000000UL - sizeof(ppc4xx_bd_info_t);
- } else {
- bdloc = bd->bi_memsize - sizeof(ppc4xx_bd_info_t);
- }
- stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart);
- stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize);
- stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart);
- stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize);
- stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset);
- stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart);
- stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize);
- stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
- stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
- for (i = 0; i < 6; i++) {
- stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
- }
- stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
- stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
- stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
- stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
- for (i = 0; i < 4; i++) {
- stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
- }
- for (i = 0; i < 32; i++) {
- stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
- }
- stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq);
- stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq);
- stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq);
- for (i = 0; i < 6; i++) {
- stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]);
- }
- n = 0x70; /* includes 2 bytes hole */
- for (i = 0; i < 6; i++) {
- stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
- }
- stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
- n += 4;
- for (i = 0; i < 2; i++) {
- stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]);
- n += 4;
- }
-
- return bdloc;
-}
-
-static ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size)
-{
- ppc4xx_bd_info_t bd;
-
- memset(&bd, 0, sizeof(bd));
-
- ppc405_set_default_bootinfo(&bd, ram_size);
-
- return __ppc405_set_bootinfo(env, &bd);
-}
-
-static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
-{
- CPUPPCState *env = &cpu->env;
- hwaddr boot_entry;
- hwaddr kernel_base;
- int kernel_size;
- hwaddr initrd_base;
- int initrd_size;
- ram_addr_t bdloc;
- int len;
-
- bdloc = ppc405_set_bootinfo(env, machine->ram_size);
- boot_info.bdloc = bdloc;
-
- kernel_size = load_elf(machine->kernel_filename, NULL, NULL, NULL,
- &boot_entry, &kernel_base, NULL, NULL,
- 1, PPC_ELF_MACHINE, 0, 0);
- if (kernel_size < 0) {
- error_report("Could not load kernel '%s' : %s",
- machine->kernel_filename, load_elf_strerror(kernel_size));
- exit(1);
- }
- boot_info.entry = boot_entry;
-
- /* load initrd */
- if (machine->initrd_filename) {
- initrd_base = INITRD_LOAD_ADDR;
- initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
- machine->ram_size - initrd_base);
- if (initrd_size < 0) {
- error_report("could not load initial ram disk '%s'",
- machine->initrd_filename);
- exit(1);
- }
-
- boot_info.initrd_base = initrd_base;
- boot_info.initrd_size = initrd_size;
- }
-
- if (machine->kernel_cmdline) {
- len = strlen(machine->kernel_cmdline);
- bdloc -= ((len + 255) & ~255);
- cpu_physical_memory_write(bdloc, machine->kernel_cmdline, len + 1);
- boot_info.cmdline_base = bdloc;
- boot_info.cmdline_size = bdloc + len;
- }
-
- /* Install our custom reset handler to start from Linux */
- qemu_register_reset(main_cpu_reset, cpu);
- env->load_info = &boot_info;
-}
-
-static void ppc405_init(MachineState *machine)
-{
- Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
- const char *kernel_filename = machine->kernel_filename;
- MemoryRegion *sysmem = get_system_memory();
-
- object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
- TYPE_PPC405_SOC);
- object_property_set_link(OBJECT(&ppc405->soc), "dram",
- OBJECT(machine->ram), &error_abort);
- object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
- &error_abort);
- qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
-
- /* allocate and load BIOS */
- if (machine->firmware) {
- MemoryRegion *bios = g_new(MemoryRegion, 1);
- g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
- machine->firmware);
- long bios_size;
-
- memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
- &error_fatal);
-
- if (!filename) {
- error_report("Could not find firmware '%s'", machine->firmware);
- exit(1);
- }
-
- bios_size = load_image_size(filename,
- memory_region_get_ram_ptr(bios),
- BIOS_SIZE);
- if (bios_size < 0) {
- error_report("Could not load PowerPC BIOS '%s'", machine->firmware);
- exit(1);
- }
-
- bios_size = (bios_size + 0xfff) & ~0xfff;
- memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
- }
-
- /* Load kernel and initrd using U-Boot images */
- if (kernel_filename && machine->firmware) {
- target_ulong kernel_base, initrd_base;
- long kernel_size, initrd_size;
-
- kernel_base = KERNEL_LOAD_ADDR;
- kernel_size = load_image_targphys(kernel_filename, kernel_base,
- machine->ram_size - kernel_base);
- if (kernel_size < 0) {
- error_report("could not load kernel '%s'", kernel_filename);
- exit(1);
- }
-
- /* load initrd */
- if (machine->initrd_filename) {
- initrd_base = INITRD_LOAD_ADDR;
- initrd_size = load_image_targphys(machine->initrd_filename,
- initrd_base,
- machine->ram_size - initrd_base);
- if (initrd_size < 0) {
- error_report("could not load initial ram disk '%s'",
- machine->initrd_filename);
- exit(1);
- }
- }
-
- /* Load ELF kernel and rootfs.cpio */
- } else if (kernel_filename && !machine->firmware) {
- ppc4xx_sdram_ddr_enable(&ppc405->soc.sdram);
- boot_from_kernel(machine, &ppc405->soc.cpu);
- }
-}
-
-static void ppc405_machine_class_init(ObjectClass *oc, void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
-
- mc->desc = "PPC405 generic machine";
- mc->init = ppc405_init;
- mc->default_ram_size = 128 * MiB;
- mc->default_ram_id = "ppc405.ram";
- mc->deprecation_reason = "machine is old and unmaintained";
-}
-
-static const TypeInfo ppc405_machine_type = {
- .name = TYPE_PPC405_MACHINE,
- .parent = TYPE_MACHINE,
- .instance_size = sizeof(Ppc405MachineState),
- .class_init = ppc405_machine_class_init,
- .abstract = true,
-};
-
-/*****************************************************************************/
-/* PPC405EP reference board (IBM) */
-/*
- * Standalone board with:
- * - PowerPC 405EP CPU
- * - SDRAM (0x00000000)
- * - Flash (0xFFF80000)
- * - SRAM (0xFFF00000)
- * - NVRAM (0xF0000000)
- * - FPGA (0xF0300000)
- */
-
-#define PPC405EP_NVRAM_BASE 0xF0000000
-#define PPC405EP_FPGA_BASE 0xF0300000
-#define PPC405EP_FLASH_BASE 0xFFF80000
-
-#define TYPE_REF405EP_FPGA "ref405ep-fpga"
-OBJECT_DECLARE_SIMPLE_TYPE(Ref405epFpgaState, REF405EP_FPGA);
-struct Ref405epFpgaState {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
-
- uint8_t reg0;
- uint8_t reg1;
-};
-
-static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
-{
- Ref405epFpgaState *fpga = opaque;
- uint32_t ret;
-
- switch (addr) {
- case 0x0:
- ret = fpga->reg0;
- break;
- case 0x1:
- ret = fpga->reg1;
- break;
- default:
- ret = 0;
- break;
- }
-
- return ret;
-}
-
-static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
- unsigned size)
-{
- Ref405epFpgaState *fpga = opaque;
-
- switch (addr) {
- case 0x0:
- /* Read only */
- break;
- case 0x1:
- fpga->reg1 = value;
- break;
- default:
- break;
- }
-}
-
-static const MemoryRegionOps ref405ep_fpga_ops = {
- .read = ref405ep_fpga_readb,
- .write = ref405ep_fpga_writeb,
- .impl.min_access_size = 1,
- .impl.max_access_size = 1,
- .valid.min_access_size = 1,
- .valid.max_access_size = 4,
- .endianness = DEVICE_BIG_ENDIAN,
-};
-
-static void ref405ep_fpga_reset(DeviceState *dev)
-{
- Ref405epFpgaState *fpga = REF405EP_FPGA(dev);
-
- fpga->reg0 = 0x00;
- fpga->reg1 = 0x0F;
-}
-
-static void ref405ep_fpga_realize(DeviceState *dev, Error **errp)
-{
- Ref405epFpgaState *s = REF405EP_FPGA(dev);
-
- memory_region_init_io(&s->iomem, OBJECT(s), &ref405ep_fpga_ops, s,
- "fpga", 0x00000100);
- sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
-}
-
-static void ref405ep_fpga_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- dc->realize = ref405ep_fpga_realize;
- device_class_set_legacy_reset(dc, ref405ep_fpga_reset);
- /* Reason: only works as part of a ppc405 board */
- dc->user_creatable = false;
-}
-
-static const TypeInfo ref405ep_fpga_type = {
- .name = TYPE_REF405EP_FPGA,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(Ref405epFpgaState),
- .class_init = ref405ep_fpga_class_init,
-};
-
-static void ref405ep_init(MachineState *machine)
-{
- DeviceState *dev;
- SysBusDevice *s;
- MemoryRegion *sram = g_new(MemoryRegion, 1);
-
- ppc405_init(machine);
-
- /* allocate SRAM */
- memory_region_init_ram(sram, NULL, "ref405ep.sram", PPC405EP_SRAM_SIZE,
- &error_fatal);
- memory_region_add_subregion(get_system_memory(), PPC405EP_SRAM_BASE, sram);
-
- /* Register FPGA */
- dev = qdev_new(TYPE_REF405EP_FPGA);
- object_property_add_child(OBJECT(machine), "fpga", OBJECT(dev));
- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, PPC405EP_FPGA_BASE);
-
- /* Register NVRAM */
- dev = qdev_new("sysbus-m48t08");
- qdev_prop_set_int32(dev, "base-year", 1968);
- s = SYS_BUS_DEVICE(dev);
- sysbus_realize_and_unref(s, &error_fatal);
- sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
-}
-
-static void ref405ep_class_init(ObjectClass *oc, void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
-
- mc->desc = "ref405ep";
- mc->init = ref405ep_init;
-}
-
-static const TypeInfo ref405ep_type = {
- .name = MACHINE_TYPE_NAME("ref405ep"),
- .parent = TYPE_PPC405_MACHINE,
- .class_init = ref405ep_class_init,
-};
-
-static void ppc405_machine_init(void)
-{
- type_register_static(&ppc405_machine_type);
- type_register_static(&ref405ep_type);
- type_register_static(&ref405ep_fpga_type);
-}
-
-type_init(ppc405_machine_init)
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
deleted file mode 100644
index 8250824a1a24..000000000000
--- a/hw/ppc/ppc405_uc.c
+++ /dev/null
@@ -1,1216 +0,0 @@
-/*
- * QEMU PowerPC 405 embedded processors emulation
- *
- * Copyright (c) 2007 Jocelyn Mayer
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "qemu/osdep.h"
-#include "qemu/units.h"
-#include "qapi/error.h"
-#include "qemu/log.h"
-#include "cpu.h"
-#include "hw/ppc/ppc.h"
-#include "hw/i2c/ppc4xx_i2c.h"
-#include "hw/irq.h"
-#include "hw/qdev-properties.h"
-#include "ppc405.h"
-#include "hw/char/serial-mm.h"
-#include "qemu/timer.h"
-#include "system/reset.h"
-#include "system/system.h"
-#include "exec/address-spaces.h"
-#include "hw/intc/ppc-uic.h"
-#include "trace.h"
-
-/*****************************************************************************/
-/* Shared peripherals */
-
-/*****************************************************************************/
-/* PLB to OPB bridge */
-enum {
- POB0_BESR0 = 0x0A0,
- POB0_BESR1 = 0x0A2,
- POB0_BEAR = 0x0A4,
-};
-
-static uint32_t dcr_read_pob(void *opaque, int dcrn)
-{
- Ppc405PobState *pob = opaque;
- uint32_t ret;
-
- switch (dcrn) {
- case POB0_BEAR:
- ret = pob->bear;
- break;
- case POB0_BESR0:
- ret = pob->besr0;
- break;
- case POB0_BESR1:
- ret = pob->besr1;
- break;
- default:
- /* Avoid gcc warning */
- ret = 0;
- break;
- }
-
- return ret;
-}
-
-static void dcr_write_pob(void *opaque, int dcrn, uint32_t val)
-{
- Ppc405PobState *pob = opaque;
-
- switch (dcrn) {
- case POB0_BEAR:
- /* Read only */
- break;
- case POB0_BESR0:
- /* Write-clear */
- pob->besr0 &= ~val;
- break;
- case POB0_BESR1:
- /* Write-clear */
- pob->besr1 &= ~val;
- break;
- }
-}
-
-static void ppc405_pob_reset(DeviceState *dev)
-{
- Ppc405PobState *pob = PPC405_POB(dev);
-
- /* No error */
- pob->bear = 0x00000000;
- pob->besr0 = 0x0000000;
- pob->besr1 = 0x0000000;
-}
-
-static void ppc405_pob_realize(DeviceState *dev, Error **errp)
-{
- Ppc405PobState *pob = PPC405_POB(dev);
- Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
-
- ppc4xx_dcr_register(dcr, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
- ppc4xx_dcr_register(dcr, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
- ppc4xx_dcr_register(dcr, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
-}
-
-static void ppc405_pob_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- dc->realize = ppc405_pob_realize;
- device_class_set_legacy_reset(dc, ppc405_pob_reset);
- /* Reason: only works as function of a ppc4xx SoC */
- dc->user_creatable = false;
-}
-
-/*****************************************************************************/
-/* OPB arbitrer */
-static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
-{
- Ppc405OpbaState *opba = opaque;
- uint32_t ret;
-
- switch (addr) {
- case 0x00:
- ret = opba->cr;
- break;
- case 0x01:
- ret = opba->pr;
- break;
- default:
- ret = 0x00;
- break;
- }
-
- trace_opba_readb(addr, ret);
- return ret;
-}
-
-static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,
- unsigned size)
-{
- Ppc405OpbaState *opba = opaque;
-
- trace_opba_writeb(addr, value);
-
- switch (addr) {
- case 0x00:
- opba->cr = value & 0xF8;
- break;
- case 0x01:
- opba->pr = value & 0xFF;
- break;
- default:
- break;
- }
-}
-static const MemoryRegionOps opba_ops = {
- .read = opba_readb,
- .write = opba_writeb,
- .impl.min_access_size = 1,
- .impl.max_access_size = 1,
- .valid.min_access_size = 1,
- .valid.max_access_size = 4,
- .endianness = DEVICE_BIG_ENDIAN,
-};
-
-static void ppc405_opba_reset(DeviceState *dev)
-{
- Ppc405OpbaState *opba = PPC405_OPBA(dev);
-
- opba->cr = 0x00; /* No dynamic priorities - park disabled */
- opba->pr = 0x11;
-}
-
-static void ppc405_opba_realize(DeviceState *dev, Error **errp)
-{
- Ppc405OpbaState *s = PPC405_OPBA(dev);
-
- memory_region_init_io(&s->io, OBJECT(s), &opba_ops, s, "opba", 2);
- sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io);
-}
-
-static void ppc405_opba_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- dc->realize = ppc405_opba_realize;
- device_class_set_legacy_reset(dc, ppc405_opba_reset);
- /* Reason: only works as function of a ppc4xx SoC */
- dc->user_creatable = false;
-}
-
-/*****************************************************************************/
-/* Code decompression controller */
-/* XXX: TODO */
-
-/*****************************************************************************/
-/* DMA controller */
-enum {
- DMA0_CR0 = 0x100,
- DMA0_CT0 = 0x101,
- DMA0_DA0 = 0x102,
- DMA0_SA0 = 0x103,
- DMA0_SG0 = 0x104,
- DMA0_CR1 = 0x108,
- DMA0_CT1 = 0x109,
- DMA0_DA1 = 0x10A,
- DMA0_SA1 = 0x10B,
- DMA0_SG1 = 0x10C,
- DMA0_CR2 = 0x110,
- DMA0_CT2 = 0x111,
- DMA0_DA2 = 0x112,
- DMA0_SA2 = 0x113,
- DMA0_SG2 = 0x114,
- DMA0_CR3 = 0x118,
- DMA0_CT3 = 0x119,
- DMA0_DA3 = 0x11A,
- DMA0_SA3 = 0x11B,
- DMA0_SG3 = 0x11C,
- DMA0_SR = 0x120,
- DMA0_SGC = 0x123,
- DMA0_SLP = 0x125,
- DMA0_POL = 0x126,
-};
-
-static uint32_t dcr_read_dma(void *opaque, int dcrn)
-{
- return 0;
-}
-
-static void dcr_write_dma(void *opaque, int dcrn, uint32_t val)
-{
-}
-
-static void ppc405_dma_reset(DeviceState *dev)
-{
- Ppc405DmaState *dma = PPC405_DMA(dev);
- int i;
-
- for (i = 0; i < 4; i++) {
- dma->cr[i] = 0x00000000;
- dma->ct[i] = 0x00000000;
- dma->da[i] = 0x00000000;
- dma->sa[i] = 0x00000000;
- dma->sg[i] = 0x00000000;
- }
- dma->sr = 0x00000000;
- dma->sgc = 0x00000000;
- dma->slp = 0x7C000000;
- dma->pol = 0x00000000;
-}
-
-static void ppc405_dma_realize(DeviceState *dev, Error **errp)
-{
- Ppc405DmaState *dma = PPC405_DMA(dev);
- Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
- int i;
-
- for (i = 0; i < ARRAY_SIZE(dma->irqs); i++) {
- sysbus_init_irq(SYS_BUS_DEVICE(dma), &dma->irqs[i]);
- }
-
- ppc4xx_dcr_register(dcr, DMA0_CR0, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_CT0, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_DA0, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_SA0, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_SG0, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_CR1, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_CT1, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_DA1, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_SA1, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_SG1, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_CR2, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_CT2, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_DA2, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_SA2, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_SG2, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_CR3, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_CT3, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_DA3, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_SA3, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_SG3, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_SR, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_SGC, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_SLP, dma, &dcr_read_dma, &dcr_write_dma);
- ppc4xx_dcr_register(dcr, DMA0_POL, dma, &dcr_read_dma, &dcr_write_dma);
-}
-
-static void ppc405_dma_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- dc->realize = ppc405_dma_realize;
- device_class_set_legacy_reset(dc, ppc405_dma_reset);
- /* Reason: only works as function of a ppc4xx SoC */
- dc->user_creatable = false;
-}
-
-/*****************************************************************************/
-/* GPIO */
-static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size)
-{
- trace_ppc405_gpio_read(addr, size);
- return 0;
-}
-
-static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value,
- unsigned size)
-{
- trace_ppc405_gpio_write(addr, size, value);
-}
-
-static const MemoryRegionOps ppc405_gpio_ops = {
- .read = ppc405_gpio_read,
- .write = ppc405_gpio_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
-};
-
-static void ppc405_gpio_realize(DeviceState *dev, Error **errp)
-{
- Ppc405GpioState *s = PPC405_GPIO(dev);
-
- memory_region_init_io(&s->io, OBJECT(s), &ppc405_gpio_ops, s, "gpio",
- 0x38);
- sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io);
-}
-
-static void ppc405_gpio_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- dc->realize = ppc405_gpio_realize;
- /* Reason: only works as function of a ppc4xx SoC */
- dc->user_creatable = false;
-}
-
-/*****************************************************************************/
-/* On Chip Memory */
-enum {
- OCM0_ISARC = 0x018,
- OCM0_ISACNTL = 0x019,
- OCM0_DSARC = 0x01A,
- OCM0_DSACNTL = 0x01B,
-};
-
-static void ocm_update_mappings(Ppc405OcmState *ocm,
- uint32_t isarc, uint32_t isacntl,
- uint32_t dsarc, uint32_t dsacntl)
-{
- trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc,
- ocm->isacntl, ocm->dsarc, ocm->dsacntl);
-
- if (ocm->isarc != isarc ||
- (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
- if (ocm->isacntl & 0x80000000) {
- /* Unmap previously assigned memory region */
- trace_ocm_unmap("ISA", ocm->isarc);
- memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
- }
- if (isacntl & 0x80000000) {
- /* Map new instruction memory region */
- trace_ocm_map("ISA", isarc);
- memory_region_add_subregion(get_system_memory(), isarc,
- &ocm->isarc_ram);
- }
- }
- if (ocm->dsarc != dsarc ||
- (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
- if (ocm->dsacntl & 0x80000000) {
- /* Beware not to unmap the region we just mapped */
- if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
- /* Unmap previously assigned memory region */
- trace_ocm_unmap("DSA", ocm->dsarc);
- memory_region_del_subregion(get_system_memory(),
- &ocm->dsarc_ram);
- }
- }
- if (dsacntl & 0x80000000) {
- /* Beware not to remap the region we just mapped */
- if (!(isacntl & 0x80000000) || dsarc != isarc) {
- /* Map new data memory region */
- trace_ocm_map("DSA", dsarc);
- memory_region_add_subregion(get_system_memory(), dsarc,
- &ocm->dsarc_ram);
- }
- }
- }
-}
-
-static uint32_t dcr_read_ocm(void *opaque, int dcrn)
-{
- Ppc405OcmState *ocm = opaque;
- uint32_t ret;
-
- switch (dcrn) {
- case OCM0_ISARC:
- ret = ocm->isarc;
- break;
- case OCM0_ISACNTL:
- ret = ocm->isacntl;
- break;
- case OCM0_DSARC:
- ret = ocm->dsarc;
- break;
- case OCM0_DSACNTL:
- ret = ocm->dsacntl;
- break;
- default:
- ret = 0;
- break;
- }
-
- return ret;
-}
-
-static void dcr_write_ocm(void *opaque, int dcrn, uint32_t val)
-{
- Ppc405OcmState *ocm = opaque;
- uint32_t isarc, dsarc, isacntl, dsacntl;
-
- isarc = ocm->isarc;
- dsarc = ocm->dsarc;
- isacntl = ocm->isacntl;
- dsacntl = ocm->dsacntl;
- switch (dcrn) {
- case OCM0_ISARC:
- isarc = val & 0xFC000000;
- break;
- case OCM0_ISACNTL:
- isacntl = val & 0xC0000000;
- break;
- case OCM0_DSARC:
- isarc = val & 0xFC000000;
- break;
- case OCM0_DSACNTL:
- isacntl = val & 0xC0000000;
- break;
- }
- ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
- ocm->isarc = isarc;
- ocm->dsarc = dsarc;
- ocm->isacntl = isacntl;
- ocm->dsacntl = dsacntl;
-}
-
-static void ppc405_ocm_reset(DeviceState *dev)
-{
- Ppc405OcmState *ocm = PPC405_OCM(dev);
- uint32_t isarc, dsarc, isacntl, dsacntl;
-
- isarc = 0x00000000;
- isacntl = 0x00000000;
- dsarc = 0x00000000;
- dsacntl = 0x00000000;
- ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
- ocm->isarc = isarc;
- ocm->dsarc = dsarc;
- ocm->isacntl = isacntl;
- ocm->dsacntl = dsacntl;
-}
-
-static void ppc405_ocm_realize(DeviceState *dev, Error **errp)
-{
- Ppc405OcmState *ocm = PPC405_OCM(dev);
- Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
-
- /* XXX: Size is 4096 or 0x04000000 */
- memory_region_init_ram(&ocm->isarc_ram, OBJECT(ocm), "ppc405.ocm", 4 * KiB,
- &error_fatal);
- memory_region_init_alias(&ocm->dsarc_ram, OBJECT(ocm), "ppc405.dsarc",
- &ocm->isarc_ram, 0, 4 * KiB);
-
- ppc4xx_dcr_register(dcr, OCM0_ISARC, ocm, &dcr_read_ocm, &dcr_write_ocm);
- ppc4xx_dcr_register(dcr, OCM0_ISACNTL, ocm, &dcr_read_ocm, &dcr_write_ocm);
- ppc4xx_dcr_register(dcr, OCM0_DSARC, ocm, &dcr_read_ocm, &dcr_write_ocm);
- ppc4xx_dcr_register(dcr, OCM0_DSACNTL, ocm, &dcr_read_ocm, &dcr_write_ocm);
-}
-
-static void ppc405_ocm_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- dc->realize = ppc405_ocm_realize;
- device_class_set_legacy_reset(dc, ppc405_ocm_reset);
- /* Reason: only works as function of a ppc4xx SoC */
- dc->user_creatable = false;
-}
-
-/*****************************************************************************/
-/* General purpose timers */
-static int ppc4xx_gpt_compare(Ppc405GptState *gpt, int n)
-{
- /* XXX: TODO */
- return 0;
-}
-
-static void ppc4xx_gpt_set_output(Ppc405GptState *gpt, int n, int level)
-{
- /* XXX: TODO */
-}
-
-static void ppc4xx_gpt_set_outputs(Ppc405GptState *gpt)
-{
- uint32_t mask;
- int i;
-
- mask = 0x80000000;
- for (i = 0; i < 5; i++) {
- if (gpt->oe & mask) {
- /* Output is enabled */
- if (ppc4xx_gpt_compare(gpt, i)) {
- /* Comparison is OK */
- ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
- } else {
- /* Comparison is KO */
- ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
- }
- }
- mask = mask >> 1;
- }
-}
-
-static void ppc4xx_gpt_set_irqs(Ppc405GptState *gpt)
-{
- uint32_t mask;
- int i;
-
- mask = 0x00008000;
- for (i = 0; i < 5; i++) {
- if (gpt->is & gpt->im & mask) {
- qemu_irq_raise(gpt->irqs[i]);
- } else {
- qemu_irq_lower(gpt->irqs[i]);
- }
- mask = mask >> 1;
- }
-}
-
-static void ppc4xx_gpt_compute_timer(Ppc405GptState *gpt)
-{
- /* XXX: TODO */
-}
-
-static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
-{
- Ppc405GptState *gpt = opaque;
- uint32_t ret;
- int idx;
-
- trace_ppc4xx_gpt_read(addr, size);
-
- switch (addr) {
- case 0x00:
- /* Time base counter */
- ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset,
- gpt->tb_freq, NANOSECONDS_PER_SECOND);
- break;
- case 0x10:
- /* Output enable */
- ret = gpt->oe;
- break;
- case 0x14:
- /* Output level */
- ret = gpt->ol;
- break;
- case 0x18:
- /* Interrupt mask */
- ret = gpt->im;
- break;
- case 0x1C:
- case 0x20:
- /* Interrupt status */
- ret = gpt->is;
- break;
- case 0x24:
- /* Interrupt enable */
- ret = gpt->ie;
- break;
- case 0x80 ... 0x90:
- /* Compare timer */
- idx = (addr - 0x80) >> 2;
- ret = gpt->comp[idx];
- break;
- case 0xC0 ... 0xD0:
- /* Compare mask */
- idx = (addr - 0xC0) >> 2;
- ret = gpt->mask[idx];
- break;
- default:
- ret = -1;
- break;
- }
-
- return ret;
-}
-
-static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value,
- unsigned size)
-{
- Ppc405GptState *gpt = opaque;
- int idx;
-
- trace_ppc4xx_gpt_write(addr, size, value);
-
- switch (addr) {
- case 0x00:
- /* Time base counter */
- gpt->tb_offset = muldiv64(value, NANOSECONDS_PER_SECOND, gpt->tb_freq)
- - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
- ppc4xx_gpt_compute_timer(gpt);
- break;
- case 0x10:
- /* Output enable */
- gpt->oe = value & 0xF8000000;
- ppc4xx_gpt_set_outputs(gpt);
- break;
- case 0x14:
- /* Output level */
- gpt->ol = value & 0xF8000000;
- ppc4xx_gpt_set_outputs(gpt);
- break;
- case 0x18:
- /* Interrupt mask */
- gpt->im = value & 0x0000F800;
- break;
- case 0x1C:
- /* Interrupt status set */
- gpt->is |= value & 0x0000F800;
- ppc4xx_gpt_set_irqs(gpt);
- break;
- case 0x20:
- /* Interrupt status clear */
- gpt->is &= ~(value & 0x0000F800);
- ppc4xx_gpt_set_irqs(gpt);
- break;
- case 0x24:
- /* Interrupt enable */
- gpt->ie = value & 0x0000F800;
- ppc4xx_gpt_set_irqs(gpt);
- break;
- case 0x80 ... 0x90:
- /* Compare timer */
- idx = (addr - 0x80) >> 2;
- gpt->comp[idx] = value & 0xF8000000;
- ppc4xx_gpt_compute_timer(gpt);
- break;
- case 0xC0 ... 0xD0:
- /* Compare mask */
- idx = (addr - 0xC0) >> 2;
- gpt->mask[idx] = value & 0xF8000000;
- ppc4xx_gpt_compute_timer(gpt);
- break;
- }
-}
-
-static const MemoryRegionOps gpt_ops = {
- .read = ppc4xx_gpt_read,
- .write = ppc4xx_gpt_write,
- .valid.min_access_size = 4,
- .valid.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
-};
-
-static void ppc4xx_gpt_cb(void *opaque)
-{
- Ppc405GptState *gpt = opaque;
-
- ppc4xx_gpt_set_irqs(gpt);
- ppc4xx_gpt_set_outputs(gpt);
- ppc4xx_gpt_compute_timer(gpt);
-}
-
-static void ppc405_gpt_reset(DeviceState *dev)
-{
- Ppc405GptState *gpt = PPC405_GPT(dev);
- int i;
-
- timer_del(gpt->timer);
- gpt->oe = 0x00000000;
- gpt->ol = 0x00000000;
- gpt->im = 0x00000000;
- gpt->is = 0x00000000;
- gpt->ie = 0x00000000;
- for (i = 0; i < 5; i++) {
- gpt->comp[i] = 0x00000000;
- gpt->mask[i] = 0x00000000;
- }
-}
-
-static void ppc405_gpt_realize(DeviceState *dev, Error **errp)
-{
- Ppc405GptState *s = PPC405_GPT(dev);
- SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
- int i;
-
- s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, s);
- memory_region_init_io(&s->iomem, OBJECT(s), &gpt_ops, s, "gpt", 0xd4);
- sysbus_init_mmio(sbd, &s->iomem);
-
- for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
- sysbus_init_irq(sbd, &s->irqs[i]);
- }
-}
-
-static void ppc405_gpt_finalize(Object *obj)
-{
- /* timer will be NULL if the GPT wasn't realized */
- if (PPC405_GPT(obj)->timer) {
- timer_del(PPC405_GPT(obj)->timer);
- }
-}
-
-static void ppc405_gpt_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- dc->realize = ppc405_gpt_realize;
- device_class_set_legacy_reset(dc, ppc405_gpt_reset);
- /* Reason: only works as function of a ppc4xx SoC */
- dc->user_creatable = false;
-}
-
-/*****************************************************************************/
-/* PowerPC 405EP */
-/* CPU control */
-enum {
- PPC405EP_CPC0_PLLMR0 = 0x0F0,
- PPC405EP_CPC0_BOOT = 0x0F1,
- PPC405EP_CPC0_EPCTL = 0x0F3,
- PPC405EP_CPC0_PLLMR1 = 0x0F4,
- PPC405EP_CPC0_UCR = 0x0F5,
- PPC405EP_CPC0_SRR = 0x0F6,
- PPC405EP_CPC0_JTAGID = 0x0F7,
- PPC405EP_CPC0_PCI = 0x0F9,
-#if 0
- PPC405EP_CPC0_ER = xxx,
- PPC405EP_CPC0_FR = xxx,
- PPC405EP_CPC0_SR = xxx,
-#endif
-};
-
-static void ppc405ep_compute_clocks(Ppc405CpcState *cpc)
-{
- uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
- uint32_t UART0_clk, UART1_clk;
- uint64_t VCO_out, PLL_out;
- int M, D;
-
- VCO_out = 0;
- if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
- M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
- trace_ppc405ep_clocks_compute("FBMUL", (cpc->pllmr[1] >> 20) & 0xF, M);
- D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
- trace_ppc405ep_clocks_compute("FWDA", (cpc->pllmr[1] >> 16) & 0x7, D);
- VCO_out = (uint64_t)cpc->sysclk * M * D;
- if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
- /* Error - unlock the PLL */
- qemu_log_mask(LOG_GUEST_ERROR, "VCO out of range %" PRIu64 "\n",
- VCO_out);
-#if 0
- cpc->pllmr[1] &= ~0x80000000;
- goto pll_bypass;
-#endif
- }
- PLL_out = VCO_out / D;
- /* Pretend the PLL is locked */
- cpc->boot |= 0x00000001;
- } else {
-#if 0
- pll_bypass:
-#endif
- PLL_out = cpc->sysclk;
- if (cpc->pllmr[1] & 0x40000000) {
- /* Pretend the PLL is not locked */
- cpc->boot &= ~0x00000001;
- }
- }
- /* Now, compute all other clocks */
- D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
- trace_ppc405ep_clocks_compute("CCDV", (cpc->pllmr[0] >> 20) & 0x3, D);
- CPU_clk = PLL_out / D;
- D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
- trace_ppc405ep_clocks_compute("CBDV", (cpc->pllmr[0] >> 16) & 0x3, D);
- PLB_clk = CPU_clk / D;
- D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
- trace_ppc405ep_clocks_compute("OPDV", (cpc->pllmr[0] >> 12) & 0x3, D);
- OPB_clk = PLB_clk / D;
- D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
- trace_ppc405ep_clocks_compute("EPDV", (cpc->pllmr[0] >> 8) & 0x3, D);
- EBC_clk = PLB_clk / D;
- D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
- trace_ppc405ep_clocks_compute("MPDV", (cpc->pllmr[0] >> 4) & 0x3, D);
- MAL_clk = PLB_clk / D;
- D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
- trace_ppc405ep_clocks_compute("PPDV", cpc->pllmr[0] & 0x3, D);
- PCI_clk = PLB_clk / D;
- D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
- trace_ppc405ep_clocks_compute("U0DIV", cpc->ucr & 0x7F, D);
- UART0_clk = PLL_out / D;
- D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
- trace_ppc405ep_clocks_compute("U1DIV", (cpc->ucr >> 8) & 0x7F, D);
- UART1_clk = PLL_out / D;
-
- if (trace_event_get_state_backends(TRACE_PPC405EP_CLOCKS_SETUP)) {
- g_autofree char *trace = g_strdup_printf(
- "Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
- " PLL out %" PRIu64 " Hz\n"
- "CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
- " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
- " UART1 %" PRIu32 "\n",
- cpc->sysclk, VCO_out, PLL_out,
- CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
- UART0_clk, UART1_clk);
- trace_ppc405ep_clocks_setup(trace);
- }
-
- /* Setup CPU clocks */
- clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
- /* Setup PLB clock */
- clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
- /* Setup OPB clock */
- clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
- /* Setup external clock */
- clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
- /* Setup MAL clock */
- clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
- /* Setup PCI clock */
- clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
- /* Setup UART0 clock */
- clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
- /* Setup UART1 clock */
- clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
-}
-
-static uint32_t dcr_read_epcpc(void *opaque, int dcrn)
-{
- Ppc405CpcState *cpc = opaque;
- uint32_t ret;
-
- switch (dcrn) {
- case PPC405EP_CPC0_BOOT:
- ret = cpc->boot;
- break;
- case PPC405EP_CPC0_EPCTL:
- ret = cpc->epctl;
- break;
- case PPC405EP_CPC0_PLLMR0:
- ret = cpc->pllmr[0];
- break;
- case PPC405EP_CPC0_PLLMR1:
- ret = cpc->pllmr[1];
- break;
- case PPC405EP_CPC0_UCR:
- ret = cpc->ucr;
- break;
- case PPC405EP_CPC0_SRR:
- ret = cpc->srr;
- break;
- case PPC405EP_CPC0_JTAGID:
- ret = cpc->jtagid;
- break;
- case PPC405EP_CPC0_PCI:
- ret = cpc->pci;
- break;
- default:
- /* Avoid gcc warning */
- ret = 0;
- break;
- }
-
- return ret;
-}
-
-static void dcr_write_epcpc(void *opaque, int dcrn, uint32_t val)
-{
- Ppc405CpcState *cpc = opaque;
-
- switch (dcrn) {
- case PPC405EP_CPC0_BOOT:
- /* Read-only register */
- break;
- case PPC405EP_CPC0_EPCTL:
- /* Don't care for now */
- cpc->epctl = val & 0xC00000F3;
- break;
- case PPC405EP_CPC0_PLLMR0:
- cpc->pllmr[0] = val & 0x00633333;
- ppc405ep_compute_clocks(cpc);
- break;
- case PPC405EP_CPC0_PLLMR1:
- cpc->pllmr[1] = val & 0xC0F73FFF;
- ppc405ep_compute_clocks(cpc);
- break;
- case PPC405EP_CPC0_UCR:
- /* UART control - don't care for now */
- cpc->ucr = val & 0x003F7F7F;
- break;
- case PPC405EP_CPC0_SRR:
- cpc->srr = val;
- break;
- case PPC405EP_CPC0_JTAGID:
- /* Read-only */
- break;
- case PPC405EP_CPC0_PCI:
- cpc->pci = val;
- break;
- }
-}
-
-static void ppc405_cpc_reset(DeviceState *dev)
-{
- Ppc405CpcState *cpc = PPC405_CPC(dev);
-
- cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
- cpc->epctl = 0x00000000;
- cpc->pllmr[0] = 0x00021002;
- cpc->pllmr[1] = 0x80a552be;
- cpc->ucr = 0x00004646;
- cpc->srr = 0x00040000;
- cpc->pci = 0x00000000;
- cpc->er = 0x00000000;
- cpc->fr = 0x00000000;
- cpc->sr = 0x00000000;
- cpc->jtagid = 0x20267049;
- ppc405ep_compute_clocks(cpc);
-}
-
-/* XXX: sysclk should be between 25 and 100 MHz */
-static void ppc405_cpc_realize(DeviceState *dev, Error **errp)
-{
- Ppc405CpcState *cpc = PPC405_CPC(dev);
- Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
-
- assert(dcr->cpu);
- cpc->clk_setup[PPC405EP_CPU_CLK].cb =
- ppc_40x_timers_init(&dcr->cpu->env, cpc->sysclk, PPC_INTERRUPT_PIT);
- cpc->clk_setup[PPC405EP_CPU_CLK].opaque = &dcr->cpu->env;
-
- ppc4xx_dcr_register(dcr, PPC405EP_CPC0_BOOT, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc4xx_dcr_register(dcr, PPC405EP_CPC0_EPCTL, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PLLMR0, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PLLMR1, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc4xx_dcr_register(dcr, PPC405EP_CPC0_UCR, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc4xx_dcr_register(dcr, PPC405EP_CPC0_SRR, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc4xx_dcr_register(dcr, PPC405EP_CPC0_JTAGID, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PCI, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
-}
-
-static const Property ppc405_cpc_properties[] = {
- DEFINE_PROP_UINT32("sys-clk", Ppc405CpcState, sysclk, 0),
-};
-
-static void ppc405_cpc_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- dc->realize = ppc405_cpc_realize;
- device_class_set_legacy_reset(dc, ppc405_cpc_reset);
- /* Reason: only works as function of a ppc4xx SoC */
- dc->user_creatable = false;
- device_class_set_props(dc, ppc405_cpc_properties);
-}
-
-/* PPC405_SOC */
-
-static void ppc405_soc_instance_init(Object *obj)
-{
- Ppc405SoCState *s = PPC405_SOC(obj);
-
- object_initialize_child(obj, "cpu", &s->cpu,
- POWERPC_CPU_TYPE_NAME("405ep"));
-
- object_initialize_child(obj, "uic", &s->uic, TYPE_PPC_UIC);
-
- object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC);
- object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
-
- object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT);
-
- object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM);
-
- object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO);
-
- object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
-
- object_initialize_child(obj, "i2c", &s->i2c, TYPE_PPC4xx_I2C);
-
- object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC4xx_EBC);
-
- object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
-
- object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
-
- object_initialize_child(obj, "plb", &s->plb, TYPE_PPC4xx_PLB);
-
- object_initialize_child(obj, "mal", &s->mal, TYPE_PPC4xx_MAL);
-
- object_initialize_child(obj, "sdram", &s->sdram, TYPE_PPC4xx_SDRAM_DDR);
- object_property_add_alias(obj, "dram", OBJECT(&s->sdram), "dram");
-}
-
-static void ppc405_reset(void *opaque)
-{
- cpu_reset(CPU(opaque));
-}
-
-static void ppc405_soc_realize(DeviceState *dev, Error **errp)
-{
- Ppc405SoCState *s = PPC405_SOC(dev);
- CPUPPCState *env;
- SysBusDevice *sbd;
- int i;
-
- /* init CPUs */
- if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
- return;
- }
- qemu_register_reset(ppc405_reset, &s->cpu);
-
- env = &s->cpu.env;
-
- ppc_dcr_init(env, NULL, NULL);
-
- /* CPU control */
- if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->cpc), &s->cpu, errp)) {
- return;
- }
-
- /* PLB arbitrer */
- if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->plb), &s->cpu, errp)) {
- return;
- }
-
- /* PLB to OPB bridge */
- if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->pob), &s->cpu, errp)) {
- return;
- }
-
- /* OBP arbitrer */
- sbd = SYS_BUS_DEVICE(&s->opba);
- if (!sysbus_realize(sbd, errp)) {
- return;
- }
- sysbus_mmio_map(sbd, 0, 0xef600600);
-
- /* Universal interrupt controller */
- if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->uic), &s->cpu, errp)) {
- return;
- }
- sbd = SYS_BUS_DEVICE(&s->uic);
- sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT,
- qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT));
- sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT,
- qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
-
- /* SDRAM controller */
- /*
- * We use the 440 DDR SDRAM controller which has more regs and features
- * but it's compatible enough for now
- */
- object_property_set_int(OBJECT(&s->sdram), "nbanks", 2, &error_abort);
- if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->sdram), &s->cpu, errp)) {
- return;
- }
- /* XXX 405EP has no ECC interrupt */
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdram), 0,
- qdev_get_gpio_in(DEVICE(&s->uic), 17));
-
- /* External bus controller */
- if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
- return;
- }
-
- /* DMA controller */
- if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->dma), &s->cpu, errp)) {
- return;
- }
- sbd = SYS_BUS_DEVICE(&s->dma);
- for (i = 0; i < ARRAY_SIZE(s->dma.irqs); i++) {
- sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(&s->uic), 5 + i));
- }
-
- /* I2C controller */
- sbd = SYS_BUS_DEVICE(&s->i2c);
- if (!sysbus_realize(sbd, errp)) {
- return;
- }
- sysbus_mmio_map(sbd, 0, 0xef600500);
- sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(DEVICE(&s->uic), 2));
-
- /* GPIO */
- sbd = SYS_BUS_DEVICE(&s->gpio);
- if (!sysbus_realize(sbd, errp)) {
- return;
- }
- sysbus_mmio_map(sbd, 0, 0xef600700);
-
- /* Serial ports */
- if (serial_hd(0) != NULL) {
- serial_mm_init(get_system_memory(), 0xef600300, 0,
- qdev_get_gpio_in(DEVICE(&s->uic), 0),
- PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
- DEVICE_BIG_ENDIAN);
- }
- if (serial_hd(1) != NULL) {
- serial_mm_init(get_system_memory(), 0xef600400, 0,
- qdev_get_gpio_in(DEVICE(&s->uic), 1),
- PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
- DEVICE_BIG_ENDIAN);
- }
-
- /* OCM */
- if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ocm), &s->cpu, errp)) {
- return;
- }
-
- /* GPT */
- sbd = SYS_BUS_DEVICE(&s->gpt);
- if (!sysbus_realize(sbd, errp)) {
- return;
- }
- sysbus_mmio_map(sbd, 0, 0xef600000);
- for (i = 0; i < ARRAY_SIZE(s->gpt.irqs); i++) {
- sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(&s->uic), 19 + i));
- }
-
- /* MAL */
- object_property_set_int(OBJECT(&s->mal), "txc-num", 4, &error_abort);
- object_property_set_int(OBJECT(&s->mal), "rxc-num", 2, &error_abort);
- if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->mal), &s->cpu, errp)) {
- return;
- }
- sbd = SYS_BUS_DEVICE(&s->mal);
- for (i = 0; i < ARRAY_SIZE(s->mal.irqs); i++) {
- sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(&s->uic), 11 + i));
- }
-
- /* Ethernet */
- /* Uses UIC IRQs 9, 15, 17 */
-}
-
-static void ppc405_soc_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- dc->realize = ppc405_soc_realize;
- /* Reason: only works as part of a ppc405 board/machine */
- dc->user_creatable = false;
-}
-
-static const TypeInfo ppc405_types[] = {
- {
- .name = TYPE_PPC405_POB,
- .parent = TYPE_PPC4xx_DCR_DEVICE,
- .instance_size = sizeof(Ppc405PobState),
- .class_init = ppc405_pob_class_init,
- }, {
- .name = TYPE_PPC405_OPBA,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(Ppc405OpbaState),
- .class_init = ppc405_opba_class_init,
- }, {
- .name = TYPE_PPC405_DMA,
- .parent = TYPE_PPC4xx_DCR_DEVICE,
- .instance_size = sizeof(Ppc405DmaState),
- .class_init = ppc405_dma_class_init,
- }, {
- .name = TYPE_PPC405_GPIO,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(Ppc405GpioState),
- .class_init = ppc405_gpio_class_init,
- }, {
- .name = TYPE_PPC405_OCM,
- .parent = TYPE_PPC4xx_DCR_DEVICE,
- .instance_size = sizeof(Ppc405OcmState),
- .class_init = ppc405_ocm_class_init,
- }, {
- .name = TYPE_PPC405_GPT,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(Ppc405GptState),
- .instance_finalize = ppc405_gpt_finalize,
- .class_init = ppc405_gpt_class_init,
- }, {
- .name = TYPE_PPC405_CPC,
- .parent = TYPE_PPC4xx_DCR_DEVICE,
- .instance_size = sizeof(Ppc405CpcState),
- .class_init = ppc405_cpc_class_init,
- }, {
- .name = TYPE_PPC405_SOC,
- .parent = TYPE_DEVICE,
- .instance_size = sizeof(Ppc405SoCState),
- .instance_init = ppc405_soc_instance_init,
- .class_init = ppc405_soc_class_init,
- }
-};
-
-DEFINE_TYPES(ppc405_types)
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index b44d91bebb2a..ced6bbc7404e 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -44,15 +44,6 @@ config POWERNV
select SSI_M25P80
select PNV_SPI
-config PPC405
- bool
- default y
- depends on PPC
- select M48T59
- select PFLASH_CFI02
- select PPC4XX
- select SERIAL_MM
-
config PPC440
bool
default y
diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
index 7cd91898699e..9893f8adebb0 100644
--- a/hw/ppc/meson.build
+++ b/hw/ppc/meson.build
@@ -57,9 +57,6 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(
'pnv_n1_chiplet.c',
))
# PowerPC 4xx boards
-ppc_ss.add(when: 'CONFIG_PPC405', if_true: files(
- 'ppc405_boards.c',
- 'ppc405_uc.c'))
ppc_ss.add(when: 'CONFIG_PPC440', if_true: files(
'ppc440_bamboo.c',
'ppc440_uc.c'))
--
2.47.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 2/9] ppc/ppc405: Remove boards
2025-01-10 14:17 ` [PATCH 2/9] ppc/ppc405: Remove boards Cédric Le Goater
@ 2025-01-10 16:05 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-10 16:05 UTC (permalink / raw)
To: Cédric Le Goater, qemu-devel
Cc: qemu-ppc, Nicholas Piggin, Daniel Henrique Barboza
On 10/1/25 15:17, Cédric Le Goater wrote:
> The ref405ep machine is the only PPC 405 machine. Drop all support by
> removing the SoC and associated devices as-well as the machine.
>
> Signed-off-by: Cédric Le Goater <clg@redhat.com>
> ---
> MAINTAINERS | 6 -
> docs/about/deprecated.rst | 8 -
> docs/about/removed-features.rst | 7 +
> docs/system/ppc/embedded.rst | 1 -
> hw/ppc/ppc405.h | 186 -----
> hw/ppc/ppc405_boards.c | 520 -------------
> hw/ppc/ppc405_uc.c | 1216 -------------------------------
> hw/ppc/Kconfig | 9 -
> hw/ppc/meson.build | 3 -
> 9 files changed, 7 insertions(+), 1949 deletions(-)
> delete mode 100644 hw/ppc/ppc405.h
> delete mode 100644 hw/ppc/ppc405_boards.c
> delete mode 100644 hw/ppc/ppc405_uc.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 2101b5121756..dc48ec4ac081 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1387,12 +1387,6 @@ F: hw/openrisc/openrisc_sim.c
>
> PowerPC Machines
> ----------------
> -405 (ref405ep)
> -L: qemu-ppc@nongnu.org
> -S: Orphan
> -F: hw/ppc/ppc405*
> -F: tests/functional/test_ppc_405.py
Ah here we go :) This line belong to the previous patch (nitpicking...)
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 3/9] ppc/ppc405: Remove CPU
2025-01-10 14:17 [PATCH 0/9] ppc: Remove 405 CPU family Cédric Le Goater
2025-01-10 14:17 ` [PATCH 1/9] ppc/ppc405: Remove tests Cédric Le Goater
2025-01-10 14:17 ` [PATCH 2/9] ppc/ppc405: Remove boards Cédric Le Goater
@ 2025-01-10 14:17 ` Cédric Le Goater
2025-01-10 16:15 ` Philippe Mathieu-Daudé
2025-01-10 14:17 ` [PATCH 4/9] ppc/ppc405: Remove storage control (SLER) SPR Cédric Le Goater
` (5 subsequent siblings)
8 siblings, 1 reply; 29+ messages in thread
From: Cédric Le Goater @ 2025-01-10 14:17 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, Nicholas Piggin, Daniel Henrique Barboza,
Cédric Le Goater
Remove the 405 CPU family and all SPR definitions that don't have
specific read/write handlers.
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
target/ppc/cpu-models.h | 30 -----
target/ppc/cpu.h | 9 --
target/ppc/cpu-models.c | 57 ----------
target/ppc/cpu_init.c | 246 ----------------------------------------
4 files changed, 342 deletions(-)
diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
index 72ad31ba50d7..f23cb383d683 100644
--- a/target/ppc/cpu-models.h
+++ b/target/ppc/cpu-models.h
@@ -39,36 +39,6 @@ extern PowerPCCPUAlias ppc_cpu_aliases[];
/* PVR definitions for most known PowerPC */
enum {
/* IBM Processor for Network Resources */
- CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
- /* PowerPC 405 family */
- /* PowerPC 405 cores */
- CPU_POWERPC_405D2 = 0x20010000,
- CPU_POWERPC_405D4 = 0x41810000,
- /* PowerPC 405 microcontrollers */
- /* XXX: missing 0x200108a0 */
- CPU_POWERPC_405CRa = 0x40110041,
- CPU_POWERPC_405CRb = 0x401100C5,
- CPU_POWERPC_405CRc = 0x40110145,
- CPU_POWERPC_405EP = 0x51210950,
- CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
- CPU_POWERPC_405GPa = 0x40110000,
- CPU_POWERPC_405GPb = 0x40110040,
- CPU_POWERPC_405GPc = 0x40110082,
- CPU_POWERPC_405GPd = 0x401100C4,
- CPU_POWERPC_405GPR = 0x50910951,
- CPU_POWERPC_405LP = 0x41F10000,
- /* IBM network processors */
- CPU_POWERPC_NPE405H = 0x414100C0,
- CPU_POWERPC_NPE405H2 = 0x41410140,
- CPU_POWERPC_NPE405L = 0x416100C0,
- CPU_POWERPC_NPE4GS3 = 0x40B10000,
- /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
- CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
- CPU_POWERPC_STB04 = 0x41810000,
- CPU_POWERPC_STB25 = 0x51510950,
- /* Xilinx cores */
- CPU_POWERPC_X2VP4 = 0x20010820,
- CPU_POWERPC_X2VP20 = 0x20010860,
/* PowerPC 440 family */
/* Generic PowerPC 440 */
#define CPU_POWERPC_440 CPU_POWERPC_440GXf
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 0b8b4c051724..0fe44cedb1b3 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -270,8 +270,6 @@ typedef enum powerpc_input_t {
PPC_FLAGS_INPUT_6xx,
/* BookE bus */
PPC_FLAGS_INPUT_BookE,
- /* PowerPC 405 bus */
- PPC_FLAGS_INPUT_405,
/* PowerPC 970 bus */
PPC_FLAGS_INPUT_970,
/* PowerPC POWER7 bus */
@@ -2172,9 +2170,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_BAMR (0x3B7)
#define SPR_7XX_MMCR0 (0x3B8)
#define SPR_7XX_PMC1 (0x3B9)
-#define SPR_40x_SGR (0x3B9)
#define SPR_7XX_PMC2 (0x3BA)
-#define SPR_40x_DCWR (0x3BA)
#define SPR_7XX_SIAR (0x3BB)
#define SPR_405_SLER (0x3BB)
#define SPR_7XX_MMCR1 (0x3BC)
@@ -2223,7 +2219,6 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_40x_DBSR (0x3F0)
#define SPR_HID1 (0x3F1)
#define SPR_IABR (0x3F2)
-#define SPR_40x_DBCR0 (0x3F2)
#define SPR_Exxx_L1CSR0 (0x3F2)
#define SPR_ICTRL (0x3F3)
#define SPR_HID2 (0x3F3)
@@ -2232,20 +2227,16 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_440_DBDR (0x3F3)
#define SPR_LDSTDB (0x3F4)
#define SPR_750_TDCL (0x3F4)
-#define SPR_40x_IAC1 (0x3F4)
#define SPR_MMUCSR0 (0x3F4)
#define SPR_970_HID4 (0x3F4)
#define SPR_DABR (0x3F5)
#define DABR_MASK (~(target_ulong)0x7)
#define SPR_Exxx_BUCSR (0x3F5)
-#define SPR_40x_IAC2 (0x3F5)
-#define SPR_40x_DAC1 (0x3F6)
#define SPR_MSSCR0 (0x3F6)
#define SPR_970_HID5 (0x3F6)
#define SPR_MSSSR0 (0x3F7)
#define SPR_MSSCR1 (0x3F7)
#define SPR_DABRX (0x3F7)
-#define SPR_40x_DAC2 (0x3F7)
#define SPR_MMUCFG (0x3F7)
#define SPR_LDSTCR (0x3F8)
#define SPR_L2PMCR (0x3F8)
diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
index ece348178188..9d8f479fae70 100644
--- a/target/ppc/cpu-models.c
+++ b/target/ppc/cpu-models.c
@@ -67,56 +67,6 @@
POWERPC_DEF_SVR(_name, _desc, _pvr, POWERPC_SVR_NONE, _type)
/* Embedded PowerPC */
- /* PowerPC 405 family */
- /* PowerPC 405 cores */
- POWERPC_DEF("405d2", CPU_POWERPC_405D2, 405,
- "PowerPC 405 D2")
- POWERPC_DEF("405d4", CPU_POWERPC_405D4, 405,
- "PowerPC 405 D4")
- /* PowerPC 405 microcontrollers */
- POWERPC_DEF("405cra", CPU_POWERPC_405CRa, 405,
- "PowerPC 405 CRa")
- POWERPC_DEF("405crb", CPU_POWERPC_405CRb, 405,
- "PowerPC 405 CRb")
- POWERPC_DEF("405crc", CPU_POWERPC_405CRc, 405,
- "PowerPC 405 CRc")
- POWERPC_DEF("405ep", CPU_POWERPC_405EP, 405,
- "PowerPC 405 EP")
- POWERPC_DEF("405ez", CPU_POWERPC_405EZ, 405,
- "PowerPC 405 EZ")
- POWERPC_DEF("405gpa", CPU_POWERPC_405GPa, 405,
- "PowerPC 405 GPa")
- POWERPC_DEF("405gpb", CPU_POWERPC_405GPb, 405,
- "PowerPC 405 GPb")
- POWERPC_DEF("405gpc", CPU_POWERPC_405GPc, 405,
- "PowerPC 405 GPc")
- POWERPC_DEF("405gpd", CPU_POWERPC_405GPd, 405,
- "PowerPC 405 GPd")
- POWERPC_DEF("405gpr", CPU_POWERPC_405GPR, 405,
- "PowerPC 405 GPR")
- POWERPC_DEF("405lp", CPU_POWERPC_405LP, 405,
- "PowerPC 405 LP")
- POWERPC_DEF("npe405h", CPU_POWERPC_NPE405H, 405,
- "Npe405 H")
- POWERPC_DEF("npe405h2", CPU_POWERPC_NPE405H2, 405,
- "Npe405 H2")
- POWERPC_DEF("npe405l", CPU_POWERPC_NPE405L, 405,
- "Npe405 L")
- POWERPC_DEF("npe4gs3", CPU_POWERPC_NPE4GS3, 405,
- "Npe4GS3")
- /* PowerPC 401/403/405 based set-top-box microcontrollers */
- POWERPC_DEF("stb03", CPU_POWERPC_STB03, 405,
- "STB03xx")
- POWERPC_DEF("stb04", CPU_POWERPC_STB04, 405,
- "STB04xx")
- POWERPC_DEF("stb25", CPU_POWERPC_STB25, 405,
- "STB25xx")
- /* Xilinx PowerPC 405 cores */
- POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405,
- NULL)
- POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405,
- NULL)
- /* PowerPC 440 family */
#if defined(TODO_USER_ONLY)
POWERPC_DEF("440", CPU_POWERPC_440, 440GP,
"Generic PowerPC 440")
@@ -742,13 +692,6 @@
/* PowerPC CPU aliases */
PowerPCCPUAlias ppc_cpu_aliases[] = {
- { "405", "405d4" },
- { "405cr", "405crc" },
- { "405gp", "405gpd" },
- { "405gpe", "405crc" },
- { "x2vp7", "x2vp4" },
- { "x2vp50", "x2vp20" },
-
{ "440ep", "440epb" },
{ "460ex", "460exb" },
#if defined(TODO_USER_ONLY)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index c05c2dc42dca..da92dce54624 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -1087,177 +1087,6 @@ static void register_440_sprs(CPUPPCState *env)
0x00000000);
}
-/* SPR shared between PowerPC 40x implementations */
-static void register_40x_sprs(CPUPPCState *env)
-{
- /* Cache */
- /* not emulated, as QEMU do not emulate caches */
- spr_register(env, SPR_40x_DCCR, "DCCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* not emulated, as QEMU do not emulate caches */
- spr_register(env, SPR_40x_ICCR, "ICCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* not emulated, as QEMU do not emulate caches */
- spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- /* Exception */
- spr_register(env, SPR_40x_DEAR, "DEAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_40x_ESR, "ESR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_40x_EVPR, "EVPR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_prefix,
- 0x00000000);
- spr_register(env, SPR_40x_SRR2, "SRR2",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_40x_SRR3, "SRR3",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Timers */
- spr_register(env, SPR_40x_PIT, "PIT",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_40x_pit, &spr_write_40x_pit,
- 0x00000000);
- spr_register(env, SPR_40x_TCR, "TCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_40x_tcr,
- 0x00000000);
- spr_register(env, SPR_40x_TSR, "TSR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_40x_tsr,
- 0x00000000);
-}
-
-/* SPR specific to PowerPC 405 implementation */
-static void register_405_sprs(CPUPPCState *env)
-{
- /* MMU */
- spr_register(env, SPR_40x_PID, "PID",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_40x_pid,
- 0x00000000);
- spr_register(env, SPR_4xx_CCR0, "CCR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00700000);
- /* Debug interface */
- spr_register(env, SPR_40x_DBCR0, "DBCR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_40x_dbcr0,
- 0x00000000);
-
- spr_register(env, SPR_405_DBCR1, "DBCR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_40x_DBSR, "DBSR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_clear,
- /* Last reset was system reset */
- 0x00000300);
-
- spr_register(env, SPR_40x_DAC1, "DAC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_40x_DAC2, "DAC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_405_DVC1, "DVC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_405_DVC2, "DVC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_40x_IAC1, "IAC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_40x_IAC2, "IAC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_405_IAC3, "IAC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_405_IAC4, "IAC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Storage control */
- spr_register(env, SPR_405_SLER, "SLER",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_40x_sler,
- 0x00000000);
- spr_register(env, SPR_40x_ZPR, "ZPR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_405_SU0R, "SU0R",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* SPRG */
- spr_register(env, SPR_USPRG0, "USPRG0",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_SPRG4, "SPRG4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG5, "SPRG5",
- SPR_NOACCESS, SPR_NOACCESS,
- spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG6, "SPRG6",
- SPR_NOACCESS, SPR_NOACCESS,
- spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG7, "SPRG7",
- SPR_NOACCESS, SPR_NOACCESS,
- spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- /* Bus access control */
- /* not emulated, as QEMU never does speculative access */
- spr_register(env, SPR_40x_SGR, "SGR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0xFFFFFFFF);
- /* not emulated, as QEMU do not emulate caches */
- spr_register(env, SPR_40x_DCWR, "DCWR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-
static void register_5xx_8xx_sprs(CPUPPCState *env)
{
/* Exception processing */
@@ -1644,30 +1473,6 @@ static void register_8xx_sprs(CPUPPCState *env)
/*****************************************************************************/
/* Exception vectors models */
-static void init_excp_4xx(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
- env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
- env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
- env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
- env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
- env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
- env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
- env->ivor_mask = 0x0000FFF0UL;
- env->ivpr_mask = 0xFFFF0000UL;
- /* Hardware reset vector */
- env->hreset_vector = 0xFFFFFFFCUL;
-#endif
-}
-
static void init_excp_MPC5xx(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
@@ -2138,57 +1943,6 @@ static void init_tlbs_emb(CPUPPCState *env)
#endif
}
-static void init_proc_405(CPUPPCState *env)
-{
- register_40x_sprs(env);
- register_405_sprs(env);
- register_usprgh_sprs(env);
-
- init_tlbs_emb(env);
- init_excp_4xx(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc40x_irq_init(env_archcpu(env));
-
- SET_FIT_PERIOD(8, 12, 16, 20);
- SET_WDT_PERIOD(16, 20, 24, 28);
-}
-
-POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 405";
- pcc->init_proc = init_proc_405;
- pcc->check_pow = check_pow_nocheck;
- pcc->check_attn = check_attn_none;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_DCR | PPC_WRTEE |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
- PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
- pcc->msr_mask = (1ull << MSR_WE) |
- (1ull << MSR_CE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_DWE) |
- (1ull << MSR_DE) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR);
- pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
- pcc->excp_model = POWERPC_EXCP_40x;
- pcc->bus_model = PPC_FLAGS_INPUT_405;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
- POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
-}
-
static void init_proc_440EP(CPUPPCState *env)
{
register_BookE_sprs(env, 0x000000000000FFFFULL);
--
2.47.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 3/9] ppc/ppc405: Remove CPU
2025-01-10 14:17 ` [PATCH 3/9] ppc/ppc405: Remove CPU Cédric Le Goater
@ 2025-01-10 16:15 ` Philippe Mathieu-Daudé
2025-01-10 16:25 ` Richard Henderson
0 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-10 16:15 UTC (permalink / raw)
To: Cédric Le Goater, qemu-devel
Cc: qemu-ppc, Nicholas Piggin, Daniel Henrique Barboza,
Laurent Vivier, Richard Henderson
Hi Cédric,
Cc'ing Laurent & Richard for user emulation.
On 10/1/25 15:17, Cédric Le Goater wrote:
> Remove the 405 CPU family and all SPR definitions that don't have
> specific read/write handlers.
>
> Signed-off-by: Cédric Le Goater <clg@redhat.com>
> ---
> target/ppc/cpu-models.h | 30 -----
> target/ppc/cpu.h | 9 --
> target/ppc/cpu-models.c | 57 ----------
> target/ppc/cpu_init.c | 246 ----------------------------------------
> 4 files changed, 342 deletions(-)
>
> diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
> index 72ad31ba50d7..f23cb383d683 100644
> --- a/target/ppc/cpu-models.h
> +++ b/target/ppc/cpu-models.h
> @@ -39,36 +39,6 @@ extern PowerPCCPUAlias ppc_cpu_aliases[];
> /* PVR definitions for most known PowerPC */
> enum {
> /* IBM Processor for Network Resources */
> - CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
> - /* PowerPC 405 family */
> - /* PowerPC 405 cores */
> - CPU_POWERPC_405D2 = 0x20010000,
> - CPU_POWERPC_405D4 = 0x41810000,
> - /* PowerPC 405 microcontrollers */
> - /* XXX: missing 0x200108a0 */
> - CPU_POWERPC_405CRa = 0x40110041,
> - CPU_POWERPC_405CRb = 0x401100C5,
> - CPU_POWERPC_405CRc = 0x40110145,
> - CPU_POWERPC_405EP = 0x51210950,
> - CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
> - CPU_POWERPC_405GPa = 0x40110000,
> - CPU_POWERPC_405GPb = 0x40110040,
> - CPU_POWERPC_405GPc = 0x40110082,
> - CPU_POWERPC_405GPd = 0x401100C4,
> - CPU_POWERPC_405GPR = 0x50910951,
> - CPU_POWERPC_405LP = 0x41F10000,
> - /* IBM network processors */
> - CPU_POWERPC_NPE405H = 0x414100C0,
> - CPU_POWERPC_NPE405H2 = 0x41410140,
> - CPU_POWERPC_NPE405L = 0x416100C0,
> - CPU_POWERPC_NPE4GS3 = 0x40B10000,
> - /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
> - CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
> - CPU_POWERPC_STB04 = 0x41810000,
> - CPU_POWERPC_STB25 = 0x51510950,
> - /* Xilinx cores */
> - CPU_POWERPC_X2VP4 = 0x20010820,
> - CPU_POWERPC_X2VP20 = 0x20010860,
> /* PowerPC 440 family */
> diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
> index ece348178188..9d8f479fae70 100644
> --- a/target/ppc/cpu-models.c
> +++ b/target/ppc/cpu-models.c
> @@ -67,56 +67,6 @@
> POWERPC_DEF_SVR(_name, _desc, _pvr, POWERPC_SVR_NONE, _type)
>
> /* Embedded PowerPC */
> - /* PowerPC 405 family */
> - /* PowerPC 405 cores */
> - POWERPC_DEF("405d2", CPU_POWERPC_405D2, 405,
> - "PowerPC 405 D2")
> - POWERPC_DEF("405d4", CPU_POWERPC_405D4, 405,
> - "PowerPC 405 D4")
> - /* PowerPC 405 microcontrollers */
> - POWERPC_DEF("405cra", CPU_POWERPC_405CRa, 405,
> - "PowerPC 405 CRa")
> - POWERPC_DEF("405crb", CPU_POWERPC_405CRb, 405,
> - "PowerPC 405 CRb")
> - POWERPC_DEF("405crc", CPU_POWERPC_405CRc, 405,
> - "PowerPC 405 CRc")
> - POWERPC_DEF("405ep", CPU_POWERPC_405EP, 405,
> - "PowerPC 405 EP")
> - POWERPC_DEF("405ez", CPU_POWERPC_405EZ, 405,
> - "PowerPC 405 EZ")
> - POWERPC_DEF("405gpa", CPU_POWERPC_405GPa, 405,
> - "PowerPC 405 GPa")
> - POWERPC_DEF("405gpb", CPU_POWERPC_405GPb, 405,
> - "PowerPC 405 GPb")
> - POWERPC_DEF("405gpc", CPU_POWERPC_405GPc, 405,
> - "PowerPC 405 GPc")
> - POWERPC_DEF("405gpd", CPU_POWERPC_405GPd, 405,
> - "PowerPC 405 GPd")
> - POWERPC_DEF("405gpr", CPU_POWERPC_405GPR, 405,
> - "PowerPC 405 GPR")
> - POWERPC_DEF("405lp", CPU_POWERPC_405LP, 405,
> - "PowerPC 405 LP")
> - POWERPC_DEF("npe405h", CPU_POWERPC_NPE405H, 405,
> - "Npe405 H")
> - POWERPC_DEF("npe405h2", CPU_POWERPC_NPE405H2, 405,
> - "Npe405 H2")
> - POWERPC_DEF("npe405l", CPU_POWERPC_NPE405L, 405,
> - "Npe405 L")
> - POWERPC_DEF("npe4gs3", CPU_POWERPC_NPE4GS3, 405,
> - "Npe4GS3")
> - /* PowerPC 401/403/405 based set-top-box microcontrollers */
> - POWERPC_DEF("stb03", CPU_POWERPC_STB03, 405,
> - "STB03xx")
> - POWERPC_DEF("stb04", CPU_POWERPC_STB04, 405,
> - "STB04xx")
> - POWERPC_DEF("stb25", CPU_POWERPC_STB25, 405,
> - "STB25xx")
> - /* Xilinx PowerPC 405 cores */
> - POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405,
> - NULL)
> - POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405,
> - NULL)
> - /* PowerPC 440 family */
> #if defined(TODO_USER_ONLY)
> POWERPC_DEF("440", CPU_POWERPC_440, 440GP,
> "Generic PowerPC 440")
> @@ -742,13 +692,6 @@
> /* PowerPC CPU aliases */
>
> PowerPCCPUAlias ppc_cpu_aliases[] = {
> - { "405", "405d4" },
> - { "405cr", "405crc" },
> - { "405gp", "405gpd" },
> - { "405gpe", "405crc" },
> - { "x2vp7", "x2vp4" },
> - { "x2vp50", "x2vp20" },
> /*****************************************************************************/
> /* Exception vectors models */
> -static void init_excp_4xx(CPUPPCState *env)
> -{
> -#if !defined(CONFIG_USER_ONLY)
> - env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
> - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
> - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
> - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
> - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
> - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
> - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
> - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
> - env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
> - env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
> - env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
> - env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
> - env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
> - env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
> - env->ivor_mask = 0x0000FFF0UL;
> - env->ivpr_mask = 0xFFFF0000UL;
> - /* Hardware reset vector */
> - env->hreset_vector = 0xFFFFFFFCUL;
> -#endif
> -}
> -
> static void init_excp_MPC5xx(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> @@ -2138,57 +1943,6 @@ static void init_tlbs_emb(CPUPPCState *env)
> #endif
> }
>
> -static void init_proc_405(CPUPPCState *env)
> -{
> - register_40x_sprs(env);
> - register_405_sprs(env);
> - register_usprgh_sprs(env);
> -
> - init_tlbs_emb(env);
> - init_excp_4xx(env);
> - env->dcache_line_size = 32;
> - env->icache_line_size = 32;
> - /* Allocate hardware IRQ controller */
> - ppc40x_irq_init(env_archcpu(env));
> -
> - SET_FIT_PERIOD(8, 12, 16, 20);
> - SET_WDT_PERIOD(16, 20, 24, 28);
> -}
> -
> -POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
> -{
> - DeviceClass *dc = DEVICE_CLASS(oc);
> - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> -
> - dc->desc = "PowerPC 405";
> - pcc->init_proc = init_proc_405;
> - pcc->check_pow = check_pow_nocheck;
> - pcc->check_attn = check_attn_none;
> - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
> - PPC_DCR | PPC_WRTEE |
> - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
> - PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
> - PPC_MEM_SYNC | PPC_MEM_EIEIO |
> - PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
> - PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
> - pcc->msr_mask = (1ull << MSR_WE) |
> - (1ull << MSR_CE) |
> - (1ull << MSR_EE) |
> - (1ull << MSR_PR) |
> - (1ull << MSR_FP) |
> - (1ull << MSR_ME) |
> - (1ull << MSR_DWE) |
> - (1ull << MSR_DE) |
> - (1ull << MSR_IR) |
> - (1ull << MSR_DR);
> - pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
> - pcc->excp_model = POWERPC_EXCP_40x;
> - pcc->bus_model = PPC_FLAGS_INPUT_405;
> - pcc->bfd_mach = bfd_mach_ppc_403;
> - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
> - POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
> -}
The deprecation message (see previous patch) was about the
"ppc ``ref405ep`` machine". Is that OK we remove these CPUs
for user emulation?
$ qemu-ppc -cpu help|fgrep 405
PowerPC 405d2 PVR 20010000
PowerPC 405gpa PVR 40110000
PowerPC 405gpb PVR 40110040
PowerPC 405cra PVR 40110041
PowerPC 405gpc PVR 40110082
PowerPC 405gpd PVR 401100c4
PowerPC 405gp (alias for 405gpd)
PowerPC 405crb PVR 401100c5
PowerPC 405crc PVR 40110145
PowerPC 405cr (alias for 405crc)
PowerPC 405gpe (alias for 405crc)
PowerPC npe405h PVR 414100c0
PowerPC npe405h2 PVR 41410140
PowerPC 405ez PVR 41511460
PowerPC npe405l PVR 416100c0
PowerPC 405d4 PVR 41810000
PowerPC 405 (alias for 405d4)
PowerPC 405lp PVR 41f10000
PowerPC 405gpr PVR 50910951
PowerPC 405ep PVR 51210950
Regards,
Phil.
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 3/9] ppc/ppc405: Remove CPU
2025-01-10 16:15 ` Philippe Mathieu-Daudé
@ 2025-01-10 16:25 ` Richard Henderson
2025-01-14 7:11 ` Nicholas Piggin
0 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2025-01-10 16:25 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Cédric Le Goater, qemu-devel
Cc: qemu-ppc, Nicholas Piggin, Daniel Henrique Barboza,
Laurent Vivier
On 1/10/25 08:15, Philippe Mathieu-Daudé wrote:
> Hi Cédric,
>
> Cc'ing Laurent & Richard for user emulation.
>
...
> The deprecation message (see previous patch) was about the
> "ppc ``ref405ep`` machine". Is that OK we remove these CPUs
> for user emulation?
>
> $ qemu-ppc -cpu help|fgrep 405
> PowerPC 405d2 PVR 20010000
> PowerPC 405gpa PVR 40110000
> PowerPC 405gpb PVR 40110040
> PowerPC 405cra PVR 40110041
> PowerPC 405gpc PVR 40110082
> PowerPC 405gpd PVR 401100c4
> PowerPC 405gp (alias for 405gpd)
> PowerPC 405crb PVR 401100c5
> PowerPC 405crc PVR 40110145
> PowerPC 405cr (alias for 405crc)
> PowerPC 405gpe (alias for 405crc)
> PowerPC npe405h PVR 414100c0
> PowerPC npe405h2 PVR 41410140
> PowerPC 405ez PVR 41511460
> PowerPC npe405l PVR 416100c0
> PowerPC 405d4 PVR 41810000
> PowerPC 405 (alias for 405d4)
> PowerPC 405lp PVR 41f10000
> PowerPC 405gpr PVR 50910951
> PowerPC 405ep PVR 51210950
Up to the ppc maintainers. I don't know of anything interesting at the user-only level
wrt these cpus.
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/9] ppc/ppc405: Remove CPU
2025-01-10 16:25 ` Richard Henderson
@ 2025-01-14 7:11 ` Nicholas Piggin
2025-01-14 7:47 ` Cédric Le Goater
2025-01-16 10:57 ` Daniel Henrique Barboza
0 siblings, 2 replies; 29+ messages in thread
From: Nicholas Piggin @ 2025-01-14 7:11 UTC (permalink / raw)
To: Richard Henderson, Philippe Mathieu-Daudé,
Cédric Le Goater, qemu-devel
Cc: qemu-ppc, Daniel Henrique Barboza, Laurent Vivier
On Sat Jan 11, 2025 at 2:25 AM AEST, Richard Henderson wrote:
> On 1/10/25 08:15, Philippe Mathieu-Daudé wrote:
> > Hi Cédric,
> >
> > Cc'ing Laurent & Richard for user emulation.
> >
> ...
> > The deprecation message (see previous patch) was about the
> > "ppc ``ref405ep`` machine". Is that OK we remove these CPUs
> > for user emulation?
> >
> > $ qemu-ppc -cpu help|fgrep 405
> > PowerPC 405d2 PVR 20010000
> > PowerPC 405gpa PVR 40110000
> > PowerPC 405gpb PVR 40110040
> > PowerPC 405cra PVR 40110041
> > PowerPC 405gpc PVR 40110082
> > PowerPC 405gpd PVR 401100c4
> > PowerPC 405gp (alias for 405gpd)
> > PowerPC 405crb PVR 401100c5
> > PowerPC 405crc PVR 40110145
> > PowerPC 405cr (alias for 405crc)
> > PowerPC 405gpe (alias for 405crc)
> > PowerPC npe405h PVR 414100c0
> > PowerPC npe405h2 PVR 41410140
> > PowerPC 405ez PVR 41511460
> > PowerPC npe405l PVR 416100c0
> > PowerPC 405d4 PVR 41810000
> > PowerPC 405 (alias for 405d4)
> > PowerPC 405lp PVR 41f10000
> > PowerPC 405gpr PVR 50910951
> > PowerPC 405ep PVR 51210950
>
> Up to the ppc maintainers. I don't know of anything interesting at the user-only level
> wrt these cpus.
Just getting back to things after the break...
We are looking at modeling some microcontrollers on the POWER
chips. There is an OCC power management controller which is a 405
and some other weird cut down 405 derivatives, we're not up to
those yet but we want to model them.
We should be able to remove a bunch of boards and CPUs, I just
haven't started looking, so might be easier to wait for a bit.
If it's not causing others too much problem, could we leave this
in for the time being?
Thanks,
Nick
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/9] ppc/ppc405: Remove CPU
2025-01-14 7:11 ` Nicholas Piggin
@ 2025-01-14 7:47 ` Cédric Le Goater
2026-04-30 5:30 ` Philippe Mathieu-Daudé
2025-01-16 10:57 ` Daniel Henrique Barboza
1 sibling, 1 reply; 29+ messages in thread
From: Cédric Le Goater @ 2025-01-14 7:47 UTC (permalink / raw)
To: Nicholas Piggin, Richard Henderson, Philippe Mathieu-Daudé,
qemu-devel
Cc: qemu-ppc, Daniel Henrique Barboza, Laurent Vivier
On 1/14/25 08:11, Nicholas Piggin wrote:
> On Sat Jan 11, 2025 at 2:25 AM AEST, Richard Henderson wrote:
>> On 1/10/25 08:15, Philippe Mathieu-Daudé wrote:
>>> Hi Cédric,
>>>
>>> Cc'ing Laurent & Richard for user emulation.
>>>
>> ...
>>> The deprecation message (see previous patch) was about the
>>> "ppc ``ref405ep`` machine". Is that OK we remove these CPUs
>>> for user emulation?
>>>
>>> $ qemu-ppc -cpu help|fgrep 405
>>> PowerPC 405d2 PVR 20010000
>>> PowerPC 405gpa PVR 40110000
>>> PowerPC 405gpb PVR 40110040
>>> PowerPC 405cra PVR 40110041
>>> PowerPC 405gpc PVR 40110082
>>> PowerPC 405gpd PVR 401100c4
>>> PowerPC 405gp (alias for 405gpd)
>>> PowerPC 405crb PVR 401100c5
>>> PowerPC 405crc PVR 40110145
>>> PowerPC 405cr (alias for 405crc)
>>> PowerPC 405gpe (alias for 405crc)
>>> PowerPC npe405h PVR 414100c0
>>> PowerPC npe405h2 PVR 41410140
>>> PowerPC 405ez PVR 41511460
>>> PowerPC npe405l PVR 416100c0
>>> PowerPC 405d4 PVR 41810000
>>> PowerPC 405 (alias for 405d4)
>>> PowerPC 405lp PVR 41f10000
>>> PowerPC 405gpr PVR 50910951
>>> PowerPC 405ep PVR 51210950
>>
>> Up to the ppc maintainers. I don't know of anything interesting at the user-only level
>> wrt these cpus.
>
> Just getting back to things after the break...
>
> We are looking at modeling some microcontrollers on the POWER
> chips. There is an OCC power management controller which is a 405
> and some other weird cut down 405 derivatives, we're not up to
> those yet but we want to model them.
>
> We should be able to remove a bunch of boards and CPUs, I just
> haven't started looking, so might be easier to wait for a bit.
> If it's not causing others too much problem, could we leave this
> in for the time being?
Sure. We will need a new SoC for the OCC and a firmware image. I think
these can be built from https://github.com/open-power/occ or, if not,
they should be made available.
Thanks,
C.
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/9] ppc/ppc405: Remove CPU
2025-01-14 7:47 ` Cédric Le Goater
@ 2026-04-30 5:30 ` Philippe Mathieu-Daudé
2026-04-30 6:54 ` Harsh Prateek Bora
0 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-04-30 5:30 UTC (permalink / raw)
To: Cédric Le Goater, Nicholas Piggin, Richard Henderson,
qemu-devel
Cc: qemu-ppc, Daniel Henrique Barboza, Laurent Vivier
On 14/1/25 08:47, Cédric Le Goater wrote:
> On 1/14/25 08:11, Nicholas Piggin wrote:
>> On Sat Jan 11, 2025 at 2:25 AM AEST, Richard Henderson wrote:
>>> On 1/10/25 08:15, Philippe Mathieu-Daudé wrote:
>>>> Hi Cédric,
>>>>
>>>> Cc'ing Laurent & Richard for user emulation.
>>>>
>>> ...
>>>> The deprecation message (see previous patch) was about the
>>>> "ppc ``ref405ep`` machine". Is that OK we remove these CPUs
>>>> for user emulation?
>>>>
>>>> $ qemu-ppc -cpu help|fgrep 405
>>>> PowerPC 405d2 PVR 20010000
>>>> PowerPC 405gpa PVR 40110000
>>>> PowerPC 405gpb PVR 40110040
>>>> PowerPC 405cra PVR 40110041
>>>> PowerPC 405gpc PVR 40110082
>>>> PowerPC 405gpd PVR 401100c4
>>>> PowerPC 405gp (alias for 405gpd)
>>>> PowerPC 405crb PVR 401100c5
>>>> PowerPC 405crc PVR 40110145
>>>> PowerPC 405cr (alias for 405crc)
>>>> PowerPC 405gpe (alias for 405crc)
>>>> PowerPC npe405h PVR 414100c0
>>>> PowerPC npe405h2 PVR 41410140
>>>> PowerPC 405ez PVR 41511460
>>>> PowerPC npe405l PVR 416100c0
>>>> PowerPC 405d4 PVR 41810000
>>>> PowerPC 405 (alias for 405d4)
>>>> PowerPC 405lp PVR 41f10000
>>>> PowerPC 405gpr PVR 50910951
>>>> PowerPC 405ep PVR 51210950
>>>
>>> Up to the ppc maintainers. I don't know of anything interesting at
>>> the user-only level
>>> wrt these cpus.
>>
>> Just getting back to things after the break...
>>
>> We are looking at modeling some microcontrollers on the POWER
>> chips. There is an OCC power management controller which is a 405
>> and some other weird cut down 405 derivatives, we're not up to
>> those yet but we want to model them.
>>
>> We should be able to remove a bunch of boards and CPUs, I just
>> haven't started looking, so might be easier to wait for a bit.
>> If it's not causing others too much problem, could we leave this
>> in for the time being?
>
> Sure. We will need a new SoC for the OCC and a firmware image. I think
> these can be built from https://github.com/open-power/occ or, if not,
> they should be made available.
Should we proceed with this removal now than v11.0.0 is released?
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/9] ppc/ppc405: Remove CPU
2026-04-30 5:30 ` Philippe Mathieu-Daudé
@ 2026-04-30 6:54 ` Harsh Prateek Bora
2026-04-30 15:15 ` Philippe Mathieu-Daudé
2026-04-30 15:35 ` Miles Glenn
0 siblings, 2 replies; 29+ messages in thread
From: Harsh Prateek Bora @ 2026-04-30 6:54 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Cédric Le Goater,
Nicholas Piggin, Richard Henderson, qemu-devel, Glenn Miles
Cc: qemu-ppc, Daniel Henrique Barboza, Laurent Vivier, Chinmay Rath
Adding Glenn (since PPE42 seems to make use of CONFIG_PPC405)
Glenn,
Please take a look and let us know your thoughts.
regards,
Harsh
On 30/04/26 11:00 am, Philippe Mathieu-Daudé wrote:
> On 14/1/25 08:47, Cédric Le Goater wrote:
>> On 1/14/25 08:11, Nicholas Piggin wrote:
>>> On Sat Jan 11, 2025 at 2:25 AM AEST, Richard Henderson wrote:
>>>> On 1/10/25 08:15, Philippe Mathieu-Daudé wrote:
>>>>> Hi Cédric,
>>>>>
>>>>> Cc'ing Laurent & Richard for user emulation.
>>>>>
>>>> ...
>>>>> The deprecation message (see previous patch) was about the
>>>>> "ppc ``ref405ep`` machine". Is that OK we remove these CPUs
>>>>> for user emulation?
>>>>>
>>>>> $ qemu-ppc -cpu help|fgrep 405
>>>>> PowerPC 405d2 PVR 20010000
>>>>> PowerPC 405gpa PVR 40110000
>>>>> PowerPC 405gpb PVR 40110040
>>>>> PowerPC 405cra PVR 40110041
>>>>> PowerPC 405gpc PVR 40110082
>>>>> PowerPC 405gpd PVR 401100c4
>>>>> PowerPC 405gp (alias for 405gpd)
>>>>> PowerPC 405crb PVR 401100c5
>>>>> PowerPC 405crc PVR 40110145
>>>>> PowerPC 405cr (alias for 405crc)
>>>>> PowerPC 405gpe (alias for 405crc)
>>>>> PowerPC npe405h PVR 414100c0
>>>>> PowerPC npe405h2 PVR 41410140
>>>>> PowerPC 405ez PVR 41511460
>>>>> PowerPC npe405l PVR 416100c0
>>>>> PowerPC 405d4 PVR 41810000
>>>>> PowerPC 405 (alias for 405d4)
>>>>> PowerPC 405lp PVR 41f10000
>>>>> PowerPC 405gpr PVR 50910951
>>>>> PowerPC 405ep PVR 51210950
>>>>
>>>> Up to the ppc maintainers. I don't know of anything interesting at
>>>> the user-only level
>>>> wrt these cpus.
>>>
>>> Just getting back to things after the break...
>>>
>>> We are looking at modeling some microcontrollers on the POWER
>>> chips. There is an OCC power management controller which is a 405
>>> and some other weird cut down 405 derivatives, we're not up to
>>> those yet but we want to model them.
>>>
>>> We should be able to remove a bunch of boards and CPUs, I just
>>> haven't started looking, so might be easier to wait for a bit.
>>> If it's not causing others too much problem, could we leave this
>>> in for the time being?
>>
>> Sure. We will need a new SoC for the OCC and a firmware image. I think
>> these can be built from https://github.com/open-power/occ or, if not,
>> they should be made available.
>
> Should we proceed with this removal now than v11.0.0 is released?
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/9] ppc/ppc405: Remove CPU
2026-04-30 6:54 ` Harsh Prateek Bora
@ 2026-04-30 15:15 ` Philippe Mathieu-Daudé
2026-04-30 15:43 ` Miles Glenn
2026-04-30 15:35 ` Miles Glenn
1 sibling, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-04-30 15:15 UTC (permalink / raw)
To: Harsh Prateek Bora, Cédric Le Goater, Nicholas Piggin,
Richard Henderson, qemu-devel, Glenn Miles
Cc: qemu-ppc, Daniel Henrique Barboza, Laurent Vivier, Chinmay Rath
Hi Harsh,
On 30/4/26 08:54, Harsh Prateek Bora wrote:
> Adding Glenn (since PPE42 seems to make use of CONFIG_PPC405)
>
> Glenn,
> Please take a look and let us know your thoughts.
Glenn can have a look, but I think we are good to remove them now,
they have been deprecated for more than 1 year, enough time for
any reaction ;) Otherwise that'd defeat the point of deprecating
and the pain for us to schedule and wait for months.
My 'Should we proceed' was more of a polite ping than a question ;)
> regards,
> Harsh
>
> On 30/04/26 11:00 am, Philippe Mathieu-Daudé wrote:
>> On 14/1/25 08:47, Cédric Le Goater wrote:
>>> On 1/14/25 08:11, Nicholas Piggin wrote:
>>>> On Sat Jan 11, 2025 at 2:25 AM AEST, Richard Henderson wrote:
>>>>> On 1/10/25 08:15, Philippe Mathieu-Daudé wrote:
>>>>>> Hi Cédric,
>>>>>>
>>>>>> Cc'ing Laurent & Richard for user emulation.
>>>>>>
>>>>> ...
>>>>>> The deprecation message (see previous patch) was about the
>>>>>> "ppc ``ref405ep`` machine". Is that OK we remove these CPUs
>>>>>> for user emulation?
>>>>>>
>>>>>> $ qemu-ppc -cpu help|fgrep 405
>>>>>> PowerPC 405d2 PVR 20010000
>>>>>> PowerPC 405gpa PVR 40110000
>>>>>> PowerPC 405gpb PVR 40110040
>>>>>> PowerPC 405cra PVR 40110041
>>>>>> PowerPC 405gpc PVR 40110082
>>>>>> PowerPC 405gpd PVR 401100c4
>>>>>> PowerPC 405gp (alias for 405gpd)
>>>>>> PowerPC 405crb PVR 401100c5
>>>>>> PowerPC 405crc PVR 40110145
>>>>>> PowerPC 405cr (alias for 405crc)
>>>>>> PowerPC 405gpe (alias for 405crc)
>>>>>> PowerPC npe405h PVR 414100c0
>>>>>> PowerPC npe405h2 PVR 41410140
>>>>>> PowerPC 405ez PVR 41511460
>>>>>> PowerPC npe405l PVR 416100c0
>>>>>> PowerPC 405d4 PVR 41810000
>>>>>> PowerPC 405 (alias for 405d4)
>>>>>> PowerPC 405lp PVR 41f10000
>>>>>> PowerPC 405gpr PVR 50910951
>>>>>> PowerPC 405ep PVR 51210950
>>>>>
>>>>> Up to the ppc maintainers. I don't know of anything interesting at
>>>>> the user-only level
>>>>> wrt these cpus.
>>>>
>>>> Just getting back to things after the break...
>>>>
>>>> We are looking at modeling some microcontrollers on the POWER
>>>> chips. There is an OCC power management controller which is a 405
>>>> and some other weird cut down 405 derivatives, we're not up to
>>>> those yet but we want to model them.
>>>>
>>>> We should be able to remove a bunch of boards and CPUs, I just
>>>> haven't started looking, so might be easier to wait for a bit.
>>>> If it's not causing others too much problem, could we leave this
>>>> in for the time being?
>>>
>>> Sure. We will need a new SoC for the OCC and a firmware image. I think
>>> these can be built from https://github.com/open-power/occ or, if not,
>>> they should be made available.
>>
>> Should we proceed with this removal now than v11.0.0 is released?
>>
>
>
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/9] ppc/ppc405: Remove CPU
2026-04-30 15:15 ` Philippe Mathieu-Daudé
@ 2026-04-30 15:43 ` Miles Glenn
2026-05-04 9:48 ` Cédric Le Goater
0 siblings, 1 reply; 29+ messages in thread
From: Miles Glenn @ 2026-04-30 15:43 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Harsh Prateek Bora,
Cédric Le Goater, Nicholas Piggin, Richard Henderson,
qemu-devel
Cc: qemu-ppc, Daniel Henrique Barboza, Laurent Vivier, Chinmay Rath
On Thu, 2026-04-30 at 17:15 +0200, Philippe Mathieu-Daudé wrote:
> Hi Harsh,
>
> On 30/4/26 08:54, Harsh Prateek Bora wrote:
> > Adding Glenn (since PPE42 seems to make use of CONFIG_PPC405)
> >
> > Glenn,
> > Please take a look and let us know your thoughts.
>
> Glenn can have a look, but I think we are good to remove them now,
> they have been deprecated for more than 1 year, enough time for
> any reaction ;) Otherwise that'd defeat the point of deprecating
> and the pain for us to schedule and wait for months.
Philippe,
Sorry, I thought it had been made clear back in August of last year
that we would need the PPC405 CPU to hang around. The topic was
brought up by Cedric when I added support for the PPE42 processor. Is
there some formal process I need to go through to have it removed from
the deprecated list?
Thanks,
Glenn
>
> My 'Should we proceed' was more of a polite ping than a question ;)
>
> > regards,
> > Harsh
> >
> > On 30/04/26 11:00 am, Philippe Mathieu-Daudé wrote:
> > > On 14/1/25 08:47, Cédric Le Goater wrote:
> > > > On 1/14/25 08:11, Nicholas Piggin wrote:
> > > > > On Sat Jan 11, 2025 at 2:25 AM AEST, Richard Henderson wrote:
> > > > > > On 1/10/25 08:15, Philippe Mathieu-Daudé wrote:
> > > > > > > Hi Cédric,
> > > > > > >
> > > > > > > Cc'ing Laurent & Richard for user emulation.
> > > > > > >
> > > > > > ...
> > > > > > > The deprecation message (see previous patch) was about the
> > > > > > > "ppc ``ref405ep`` machine". Is that OK we remove these CPUs
> > > > > > > for user emulation?
> > > > > > >
> > > > > > > $ qemu-ppc -cpu help|fgrep 405
> > > > > > > PowerPC 405d2 PVR 20010000
> > > > > > > PowerPC 405gpa PVR 40110000
> > > > > > > PowerPC 405gpb PVR 40110040
> > > > > > > PowerPC 405cra PVR 40110041
> > > > > > > PowerPC 405gpc PVR 40110082
> > > > > > > PowerPC 405gpd PVR 401100c4
> > > > > > > PowerPC 405gp (alias for 405gpd)
> > > > > > > PowerPC 405crb PVR 401100c5
> > > > > > > PowerPC 405crc PVR 40110145
> > > > > > > PowerPC 405cr (alias for 405crc)
> > > > > > > PowerPC 405gpe (alias for 405crc)
> > > > > > > PowerPC npe405h PVR 414100c0
> > > > > > > PowerPC npe405h2 PVR 41410140
> > > > > > > PowerPC 405ez PVR 41511460
> > > > > > > PowerPC npe405l PVR 416100c0
> > > > > > > PowerPC 405d4 PVR 41810000
> > > > > > > PowerPC 405 (alias for 405d4)
> > > > > > > PowerPC 405lp PVR 41f10000
> > > > > > > PowerPC 405gpr PVR 50910951
> > > > > > > PowerPC 405ep PVR 51210950
> > > > > >
> > > > > > Up to the ppc maintainers. I don't know of anything interesting at
> > > > > > the user-only level
> > > > > > wrt these cpus.
> > > > >
> > > > > Just getting back to things after the break...
> > > > >
> > > > > We are looking at modeling some microcontrollers on the POWER
> > > > > chips. There is an OCC power management controller which is a 405
> > > > > and some other weird cut down 405 derivatives, we're not up to
> > > > > those yet but we want to model them.
> > > > >
> > > > > We should be able to remove a bunch of boards and CPUs, I just
> > > > > haven't started looking, so might be easier to wait for a bit.
> > > > > If it's not causing others too much problem, could we leave this
> > > > > in for the time being?
> > > >
> > > > Sure. We will need a new SoC for the OCC and a firmware image. I think
> > > > these can be built from https://github.com/open-power/occ or, if not,
> > > > they should be made available.
> > >
> > > Should we proceed with this removal now than v11.0.0 is released?
> > >
> >
> >
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/9] ppc/ppc405: Remove CPU
2026-04-30 15:43 ` Miles Glenn
@ 2026-05-04 9:48 ` Cédric Le Goater
2026-05-04 12:32 ` Philippe Mathieu-Daudé
2026-05-05 8:22 ` Daniel P. Berrangé
0 siblings, 2 replies; 29+ messages in thread
From: Cédric Le Goater @ 2026-05-04 9:48 UTC (permalink / raw)
To: milesg, Philippe Mathieu-Daudé, Harsh Prateek Bora,
Nicholas Piggin, Richard Henderson, qemu-devel
Cc: qemu-ppc, Daniel Henrique Barboza, Laurent Vivier, Chinmay Rath
Hello Glenn,
On 4/30/26 17:43, Miles Glenn wrote:
> On Thu, 2026-04-30 at 17:15 +0200, Philippe Mathieu-Daudé wrote:
>> Hi Harsh,
>>
>> On 30/4/26 08:54, Harsh Prateek Bora wrote:
>>> Adding Glenn (since PPE42 seems to make use of CONFIG_PPC405)
>>>
>>> Glenn,
>>> Please take a look and let us know your thoughts.
>>
>> Glenn can have a look, but I think we are good to remove them now,
>> they have been deprecated for more than 1 year, enough time for
>> any reaction ;) Otherwise that'd defeat the point of deprecating
>> and the pain for us to schedule and wait for months.
>
> Philippe,
>
> Sorry, I thought it had been made clear back in August of last year
> that we would need the PPC405 CPU to hang around. The topic was
> brought up by Cedric when I added support for the PPE42 processor. Is
> there some formal process I need to go through to have it removed from
> the deprecated list?
I don't know of any un-deprecation process. I suggest sending a patch
to revert commit 52f0b59ec6b7 ("hw/ppc: Deprecate 405 CPUs"). The commit
log should mention the PPE42 processor which is a stripped down version
of the IBM PowerPC 405 processor.
Thanks,
C.
https://lore.kernel.org/all/20250925201758.652077-1-milesg@linux.ibm.com/
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 3/9] ppc/ppc405: Remove CPU
2026-05-04 9:48 ` Cédric Le Goater
@ 2026-05-04 12:32 ` Philippe Mathieu-Daudé
2026-05-04 14:59 ` Miles Glenn
2026-05-05 8:22 ` Daniel P. Berrangé
1 sibling, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-05-04 12:32 UTC (permalink / raw)
To: Cédric Le Goater, milesg, Harsh Prateek Bora,
Nicholas Piggin, Richard Henderson, qemu-devel,
Daniel P. Berrangé, Thomas Huth
Cc: qemu-ppc, Daniel Henrique Barboza, Laurent Vivier, Chinmay Rath
Cc'ing Daniel and Thomas, our deprecation experts.
On 4/5/26 11:48, Cédric Le Goater wrote:
> Hello Glenn,
>
>
> On 4/30/26 17:43, Miles Glenn wrote:
>> On Thu, 2026-04-30 at 17:15 +0200, Philippe Mathieu-Daudé wrote:
>>> Hi Harsh,
>>>
>>> On 30/4/26 08:54, Harsh Prateek Bora wrote:
>>>> Adding Glenn (since PPE42 seems to make use of CONFIG_PPC405)
>>>>
>>>> Glenn,
>>>> Please take a look and let us know your thoughts.
>>>
>>> Glenn can have a look, but I think we are good to remove them now,
>>> they have been deprecated for more than 1 year, enough time for
>>> any reaction ;) Otherwise that'd defeat the point of deprecating
>>> and the pain for us to schedule and wait for months.
>>
>> Philippe,
>>
>> Sorry, I thought it had been made clear back in August of last year
>> that we would need the PPC405 CPU to hang around. The topic was
>> brought up by Cedric when I added support for the PPE42 processor. Is
>> there some formal process I need to go through to have it removed from
>> the deprecated list?
>
> I don't know of any un-deprecation process. I suggest sending a patch
> to revert commit 52f0b59ec6b7 ("hw/ppc: Deprecate 405 CPUs"). The commit
> log should mention the PPE42 processor which is a stripped down version
> of the IBM PowerPC 405 processor.
That, and updating MAINTAINERS for these CPUs (likely adding a new entry
including at least Glenn).
>
> Thanks,
>
> C.
>
> https://lore.kernel.org/all/20250925201758.652077-1-milesg@linux.ibm.com/
>
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 3/9] ppc/ppc405: Remove CPU
2026-05-04 12:32 ` Philippe Mathieu-Daudé
@ 2026-05-04 14:59 ` Miles Glenn
2026-05-04 17:32 ` Miles Glenn
0 siblings, 1 reply; 29+ messages in thread
From: Miles Glenn @ 2026-05-04 14:59 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Cédric Le Goater,
Harsh Prateek Bora, Nicholas Piggin, Richard Henderson,
qemu-devel, Daniel P. Berrangé, Thomas Huth
Cc: qemu-ppc, Daniel Henrique Barboza, Laurent Vivier, Chinmay Rath
Ok, thanks. I'll go forward with these suggestions.
Glenn
On Mon, 2026-05-04 at 14:32 +0200, Philippe Mathieu-Daudé wrote:
> Cc'ing Daniel and Thomas, our deprecation experts.
>
> On 4/5/26 11:48, Cédric Le Goater wrote:
> > Hello Glenn,
> >
> >
> > On 4/30/26 17:43, Miles Glenn wrote:
> > > On Thu, 2026-04-30 at 17:15 +0200, Philippe Mathieu-Daudé wrote:
> > > > Hi Harsh,
> > > >
> > > > On 30/4/26 08:54, Harsh Prateek Bora wrote:
> > > > > Adding Glenn (since PPE42 seems to make use of CONFIG_PPC405)
> > > > >
> > > > > Glenn,
> > > > > Please take a look and let us know your thoughts.
> > > >
> > > > Glenn can have a look, but I think we are good to remove them now,
> > > > they have been deprecated for more than 1 year, enough time for
> > > > any reaction ;) Otherwise that'd defeat the point of deprecating
> > > > and the pain for us to schedule and wait for months.
> > >
> > > Philippe,
> > >
> > > Sorry, I thought it had been made clear back in August of last year
> > > that we would need the PPC405 CPU to hang around. The topic was
> > > brought up by Cedric when I added support for the PPE42 processor. Is
> > > there some formal process I need to go through to have it removed from
> > > the deprecated list?
> >
> > I don't know of any un-deprecation process. I suggest sending a patch
> > to revert commit 52f0b59ec6b7 ("hw/ppc: Deprecate 405 CPUs"). The commit
> > log should mention the PPE42 processor which is a stripped down version
> > of the IBM PowerPC 405 processor.
>
> That, and updating MAINTAINERS for these CPUs (likely adding a new entry
> including at least Glenn).
>
> > Thanks,
> >
> > C.
> >
> > https://lore.kernel.org/all/20250925201758.652077-1-milesg@linux.ibm.com/
> >
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 3/9] ppc/ppc405: Remove CPU
2026-05-04 14:59 ` Miles Glenn
@ 2026-05-04 17:32 ` Miles Glenn
0 siblings, 0 replies; 29+ messages in thread
From: Miles Glenn @ 2026-05-04 17:32 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Cédric Le Goater,
Harsh Prateek Bora, Nicholas Piggin, Richard Henderson,
qemu-devel, Daniel P. Berrangé, Thomas Huth
Cc: qemu-ppc, Daniel Henrique Barboza, Laurent Vivier, Chinmay Rath
Philippe,
Regarding the MAINTAINERS file, do we really need a new entry in there?
We already have an entry for the PPE42 CPU with myself as maintainer
and I believe the rest is covered by the "PowerPC TCG CPUs" entry.
Were there any files in particular that you had in mind?
Thanks,
Glenn
On Mon, 2026-05-04 at 09:59 -0500, Miles Glenn wrote:
> Ok, thanks. I'll go forward with these suggestions.
>
> Glenn
>
> On Mon, 2026-05-04 at 14:32 +0200, Philippe Mathieu-Daudé wrote:
> > Cc'ing Daniel and Thomas, our deprecation experts.
> >
> > On 4/5/26 11:48, Cédric Le Goater wrote:
> > > Hello Glenn,
> > >
> > >
> > > On 4/30/26 17:43, Miles Glenn wrote:
> > > > On Thu, 2026-04-30 at 17:15 +0200, Philippe Mathieu-Daudé wrote:
> > > > > Hi Harsh,
> > > > >
> > > > > On 30/4/26 08:54, Harsh Prateek Bora wrote:
> > > > > > Adding Glenn (since PPE42 seems to make use of CONFIG_PPC405)
> > > > > >
> > > > > > Glenn,
> > > > > > Please take a look and let us know your thoughts.
> > > > >
> > > > > Glenn can have a look, but I think we are good to remove them now,
> > > > > they have been deprecated for more than 1 year, enough time for
> > > > > any reaction ;) Otherwise that'd defeat the point of deprecating
> > > > > and the pain for us to schedule and wait for months.
> > > >
> > > > Philippe,
> > > >
> > > > Sorry, I thought it had been made clear back in August of last year
> > > > that we would need the PPC405 CPU to hang around. The topic was
> > > > brought up by Cedric when I added support for the PPE42 processor. Is
> > > > there some formal process I need to go through to have it removed from
> > > > the deprecated list?
> > >
> > > I don't know of any un-deprecation process. I suggest sending a patch
> > > to revert commit 52f0b59ec6b7 ("hw/ppc: Deprecate 405 CPUs"). The commit
> > > log should mention the PPE42 processor which is a stripped down version
> > > of the IBM PowerPC 405 processor.
> >
> > That, and updating MAINTAINERS for these CPUs (likely adding a new entry
> > including at least Glenn).
> >
> > > Thanks,
> > >
> > > C.
> > >
> > > https://lore.kernel.org/all/20250925201758.652077-1-milesg@linux.ibm.com/
> > >
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/9] ppc/ppc405: Remove CPU
2026-05-04 9:48 ` Cédric Le Goater
2026-05-04 12:32 ` Philippe Mathieu-Daudé
@ 2026-05-05 8:22 ` Daniel P. Berrangé
1 sibling, 0 replies; 29+ messages in thread
From: Daniel P. Berrangé @ 2026-05-05 8:22 UTC (permalink / raw)
To: Cédric Le Goater
Cc: milesg, Philippe Mathieu-Daudé, Harsh Prateek Bora,
Nicholas Piggin, Richard Henderson, qemu-devel, qemu-ppc,
Daniel Henrique Barboza, Laurent Vivier, Chinmay Rath
On Mon, May 04, 2026 at 11:48:57AM +0200, Cédric Le Goater wrote:
> Hello Glenn,
>
>
> On 4/30/26 17:43, Miles Glenn wrote:
> > On Thu, 2026-04-30 at 17:15 +0200, Philippe Mathieu-Daudé wrote:
> > > Hi Harsh,
> > >
> > > On 30/4/26 08:54, Harsh Prateek Bora wrote:
> > > > Adding Glenn (since PPE42 seems to make use of CONFIG_PPC405)
> > > >
> > > > Glenn,
> > > > Please take a look and let us know your thoughts.
> > >
> > > Glenn can have a look, but I think we are good to remove them now,
> > > they have been deprecated for more than 1 year, enough time for
> > > any reaction ;) Otherwise that'd defeat the point of deprecating
> > > and the pain for us to schedule and wait for months.
> >
> > Philippe,
> >
> > Sorry, I thought it had been made clear back in August of last year
> > that we would need the PPC405 CPU to hang around. The topic was
> > brought up by Cedric when I added support for the PPE42 processor. Is
> > there some formal process I need to go through to have it removed from
> > the deprecated list?
>
> I don't know of any un-deprecation process. I suggest sending a patch
> to revert commit 52f0b59ec6b7 ("hw/ppc: Deprecate 405 CPUs"). The commit
> log should mention the PPE42 processor which is a stripped down version
> of the IBM PowerPC 405 processor.
Yes, that's exactly the process - just remove the text from deprecated.rst
and warning messages printed by the code (if any)
Daniel
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/9] ppc/ppc405: Remove CPU
2026-04-30 6:54 ` Harsh Prateek Bora
2026-04-30 15:15 ` Philippe Mathieu-Daudé
@ 2026-04-30 15:35 ` Miles Glenn
1 sibling, 0 replies; 29+ messages in thread
From: Miles Glenn @ 2026-04-30 15:35 UTC (permalink / raw)
To: Harsh Prateek Bora, Philippe Mathieu-Daudé,
Cédric Le Goater, Nicholas Piggin, Richard Henderson,
qemu-devel
Cc: qemu-ppc, Daniel Henrique Barboza, Laurent Vivier, Chinmay Rath
Please do not remove the PowerPC 405 CPU. We are currently using the
PPE42 CPU which is heavily based on the PowerPC 405 and we will be
using the PowerPC 405 CPU in the near future (probably within a year).
I do not have a problem with the removal of any boards as long as we
keep at least one for regression testing of the PPC405 CPU.
Thank you,
Glenn Miles
On Thu, 2026-04-30 at 12:24 +0530, Harsh Prateek Bora wrote:
> Adding Glenn (since PPE42 seems to make use of CONFIG_PPC405)
>
> Glenn,
> Please take a look and let us know your thoughts.
>
> regards,
> Harsh
>
> On 30/04/26 11:00 am, Philippe Mathieu-Daudé wrote:
> > On 14/1/25 08:47, Cédric Le Goater wrote:
> > > On 1/14/25 08:11, Nicholas Piggin wrote:
> > > > On Sat Jan 11, 2025 at 2:25 AM AEST, Richard Henderson wrote:
> > > > > On 1/10/25 08:15, Philippe Mathieu-Daudé wrote:
> > > > > > Hi Cédric,
> > > > > >
> > > > > > Cc'ing Laurent & Richard for user emulation.
> > > > > >
> > > > > ...
> > > > > > The deprecation message (see previous patch) was about the
> > > > > > "ppc ``ref405ep`` machine". Is that OK we remove these CPUs
> > > > > > for user emulation?
> > > > > >
> > > > > > $ qemu-ppc -cpu help|fgrep 405
> > > > > > PowerPC 405d2 PVR 20010000
> > > > > > PowerPC 405gpa PVR 40110000
> > > > > > PowerPC 405gpb PVR 40110040
> > > > > > PowerPC 405cra PVR 40110041
> > > > > > PowerPC 405gpc PVR 40110082
> > > > > > PowerPC 405gpd PVR 401100c4
> > > > > > PowerPC 405gp (alias for 405gpd)
> > > > > > PowerPC 405crb PVR 401100c5
> > > > > > PowerPC 405crc PVR 40110145
> > > > > > PowerPC 405cr (alias for 405crc)
> > > > > > PowerPC 405gpe (alias for 405crc)
> > > > > > PowerPC npe405h PVR 414100c0
> > > > > > PowerPC npe405h2 PVR 41410140
> > > > > > PowerPC 405ez PVR 41511460
> > > > > > PowerPC npe405l PVR 416100c0
> > > > > > PowerPC 405d4 PVR 41810000
> > > > > > PowerPC 405 (alias for 405d4)
> > > > > > PowerPC 405lp PVR 41f10000
> > > > > > PowerPC 405gpr PVR 50910951
> > > > > > PowerPC 405ep PVR 51210950
> > > > >
> > > > > Up to the ppc maintainers. I don't know of anything interesting at
> > > > > the user-only level
> > > > > wrt these cpus.
> > > >
> > > > Just getting back to things after the break...
> > > >
> > > > We are looking at modeling some microcontrollers on the POWER
> > > > chips. There is an OCC power management controller which is a 405
> > > > and some other weird cut down 405 derivatives, we're not up to
> > > > those yet but we want to model them.
> > > >
> > > > We should be able to remove a bunch of boards and CPUs, I just
> > > > haven't started looking, so might be easier to wait for a bit.
> > > > If it's not causing others too much problem, could we leave this
> > > > in for the time being?
> > >
> > > Sure. We will need a new SoC for the OCC and a firmware image. I think
> > > these can be built from https://github.com/open-power/occ or, if not,
> > > they should be made available.
> >
> > Should we proceed with this removal now than v11.0.0 is released?
> >
>
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/9] ppc/ppc405: Remove CPU
2025-01-14 7:11 ` Nicholas Piggin
2025-01-14 7:47 ` Cédric Le Goater
@ 2025-01-16 10:57 ` Daniel Henrique Barboza
1 sibling, 0 replies; 29+ messages in thread
From: Daniel Henrique Barboza @ 2025-01-16 10:57 UTC (permalink / raw)
To: Nicholas Piggin, Richard Henderson, Philippe Mathieu-Daudé,
Cédric Le Goater, qemu-devel
Cc: qemu-ppc, Laurent Vivier
On 1/14/25 4:11 AM, Nicholas Piggin wrote:
> On Sat Jan 11, 2025 at 2:25 AM AEST, Richard Henderson wrote:
>> On 1/10/25 08:15, Philippe Mathieu-Daudé wrote:
>>> Hi Cédric,
>>>
>>> Cc'ing Laurent & Richard for user emulation.
>>>
>> ...
>>> The deprecation message (see previous patch) was about the
>>> "ppc ``ref405ep`` machine". Is that OK we remove these CPUs
>>> for user emulation?
>>>
>>> $ qemu-ppc -cpu help|fgrep 405
>>> PowerPC 405d2 PVR 20010000
>>> PowerPC 405gpa PVR 40110000
>>> PowerPC 405gpb PVR 40110040
>>> PowerPC 405cra PVR 40110041
>>> PowerPC 405gpc PVR 40110082
>>> PowerPC 405gpd PVR 401100c4
>>> PowerPC 405gp (alias for 405gpd)
>>> PowerPC 405crb PVR 401100c5
>>> PowerPC 405crc PVR 40110145
>>> PowerPC 405cr (alias for 405crc)
>>> PowerPC 405gpe (alias for 405crc)
>>> PowerPC npe405h PVR 414100c0
>>> PowerPC npe405h2 PVR 41410140
>>> PowerPC 405ez PVR 41511460
>>> PowerPC npe405l PVR 416100c0
>>> PowerPC 405d4 PVR 41810000
>>> PowerPC 405 (alias for 405d4)
>>> PowerPC 405lp PVR 41f10000
>>> PowerPC 405gpr PVR 50910951
>>> PowerPC 405ep PVR 51210950
>>
>> Up to the ppc maintainers. I don't know of anything interesting at the user-only level
>> wrt these cpus.
>
> Just getting back to things after the break...
>
> We are looking at modeling some microcontrollers on the POWER
> chips. There is an OCC power management controller which is a 405
> and some other weird cut down 405 derivatives, we're not up to
> those yet but we want to model them.
>
> We should be able to remove a bunch of boards and CPUs, I just
> haven't started looking, so might be easier to wait for a bit.
> If it's not causing others too much problem, could we leave this
> in for the time being?
That's fine, but then we need to at least mark you as a maintainer here:
PowerPC Machines
----------------
405 (ref405ep)
L: qemu-ppc@nongnu.org
S: Orphan <----------------
F: hw/ppc/ppc405*
F: tests/functional/test_ppc_405.py
Either with "S: Odd Fixes" or "S: Maintained" (or S: Supported, if that's really the
case). And perhaps re-visit the deprecation notice too.
I'm being petty here because, right now, all 405 code is marked for deprecation, has no
firmware images and Linux support and etc like Cedric mentioned, and it fits exactly
the criteria everyone else uses for removal. If we want to keep it around we'll need
at least MAINTAINER changes to indicate it.
Thanks,
Daniel
>
> Thanks,
> Nick
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 4/9] ppc/ppc405: Remove storage control (SLER) SPR
2025-01-10 14:17 [PATCH 0/9] ppc: Remove 405 CPU family Cédric Le Goater
` (2 preceding siblings ...)
2025-01-10 14:17 ` [PATCH 3/9] ppc/ppc405: Remove CPU Cédric Le Goater
@ 2025-01-10 14:17 ` Cédric Le Goater
2025-01-10 14:17 ` [PATCH 5/9] ppc/ppc405: Remove 40x exception model Cédric Le Goater
` (4 subsequent siblings)
8 siblings, 0 replies; 29+ messages in thread
From: Cédric Le Goater @ 2025-01-10 14:17 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, Nicholas Piggin, Daniel Henrique Barboza,
Cédric Le Goater
Since the 405 CPU family was phased out, the SLER SPR has no users
anymore.
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
target/ppc/cpu.h | 2 --
target/ppc/helper.h | 1 -
target/ppc/spr_common.h | 1 -
target/ppc/helper_regs.c | 10 ----------
target/ppc/misc_helper.c | 5 -----
target/ppc/translate.c | 6 ------
6 files changed, 25 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 0fe44cedb1b3..2f3741860076 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1620,7 +1620,6 @@ void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
target_ulong load_40x_pit(CPUPPCState *env);
void store_40x_pit(CPUPPCState *env, target_ulong val);
void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
-void store_40x_sler(CPUPPCState *env, uint32_t val);
void store_40x_tcr(CPUPPCState *env, target_ulong val);
void store_40x_tsr(CPUPPCState *env, target_ulong val);
void store_booke_tcr(CPUPPCState *env, target_ulong val);
@@ -2172,7 +2171,6 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_7XX_PMC1 (0x3B9)
#define SPR_7XX_PMC2 (0x3BA)
#define SPR_7XX_SIAR (0x3BB)
-#define SPR_405_SLER (0x3BB)
#define SPR_7XX_MMCR1 (0x3BC)
#define SPR_405_SU0R (0x3BC)
#define SPR_401_SKR (0x3BC)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 5a77e761bd3f..86f3bbc087f6 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -753,7 +753,6 @@ DEF_HELPER_FLAGS_2(store_40x_tcr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_40x_tsr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_2(store_40x_pid, void, env, tl)
DEF_HELPER_2(store_40x_dbcr0, void, env, tl)
-DEF_HELPER_2(store_40x_sler, void, env, tl)
DEF_HELPER_FLAGS_2(store_booke_tcr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_booke_tsr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_3(store_ibatl, void, env, i32, tl)
diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h
index 01aff449bccc..e98fb07bb285 100644
--- a/target/ppc/spr_common.h
+++ b/target/ppc/spr_common.h
@@ -138,7 +138,6 @@ void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn);
void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn);
void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn);
void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn);
-void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn);
void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn);
void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn);
void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn);
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 3ad4273c1649..1e5ba9a1c64b 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -354,16 +354,6 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv)
}
#ifndef CONFIG_USER_ONLY
-void store_40x_sler(CPUPPCState *env, uint32_t val)
-{
- /* XXX: TO BE FIXED */
- if (val != 0x00000000) {
- cpu_abort(env_cpu(env),
- "Little-endian regions are not supported by now\n");
- }
- env->spr[SPR_405_SLER] = val;
-}
-
void check_tlb_flush(CPUPPCState *env, bool global)
{
CPUState *cs = env_cpu(env);
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index f0ca80153b2b..78bb29d441a7 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -404,11 +404,6 @@ void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
/* Bits 28 & 29 affect reset or shutdown. */
store_40x_dbcr0(env, val);
}
-
-void helper_store_40x_sler(CPUPPCState *env, target_ulong val)
-{
- store_40x_sler(env, val);
-}
#endif
/*****************************************************************************/
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 80638ab53597..918bf8f3a0cc 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -967,12 +967,6 @@ void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
ctx->base.is_jmp = DISAS_EXIT_UPDATE;
}
-void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
-{
- translator_io_start(&ctx->base);
- gen_helper_store_40x_sler(tcg_env, cpu_gpr[gprn]);
-}
-
void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
--
2.47.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 5/9] ppc/ppc405: Remove 40x exception model
2025-01-10 14:17 [PATCH 0/9] ppc: Remove 405 CPU family Cédric Le Goater
` (3 preceding siblings ...)
2025-01-10 14:17 ` [PATCH 4/9] ppc/ppc405: Remove storage control (SLER) SPR Cédric Le Goater
@ 2025-01-10 14:17 ` Cédric Le Goater
2025-01-10 14:17 ` [PATCH 6/9] ppc/ppc405: Remove timer support Cédric Le Goater
` (3 subsequent siblings)
8 siblings, 0 replies; 29+ messages in thread
From: Cédric Le Goater @ 2025-01-10 14:17 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, Nicholas Piggin, Daniel Henrique Barboza,
Cédric Le Goater
This exception model was only used by the 405 CPU family which was
removed. The rest of the PPC 4xx CPUs use the BookE exception model.
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
target/ppc/cpu.h | 8 +--
target/ppc/helper.h | 1 -
target/ppc/cpu_init.c | 11 ----
target/ppc/excp_helper.c | 116 ---------------------------------------
target/ppc/translate.c | 14 -----
5 files changed, 1 insertion(+), 149 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 2f3741860076..32423cfb7368 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -196,8 +196,6 @@ typedef enum powerpc_excp_t {
POWERPC_EXCP_UNKNOWN = 0,
/* Standard PowerPC exception model */
POWERPC_EXCP_STD,
- /* PowerPC 40x exception model */
- POWERPC_EXCP_40x,
/* PowerPC 603/604/G2 exception model */
POWERPC_EXCP_6xx,
/* PowerPC 7xx exception model */
@@ -2206,9 +2204,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_403_TBL (0x3DC)
#define SPR_403_TBU (0x3DD)
#define SPR_SEBR (0x3DE)
-#define SPR_40x_SRR2 (0x3DE)
#define SPR_SER (0x3DF)
-#define SPR_40x_SRR3 (0x3DF)
#define SPR_L3OHCR (0x3E8)
#define SPR_L3ITCR1 (0x3E9)
#define SPR_L3ITCR2 (0x3EA)
@@ -2405,8 +2401,6 @@ enum {
/* Embedded PowerPC dedicated instructions */
PPC_WRTEE = 0x0001000000000000ULL,
- /* PowerPC 40x exception model */
- PPC_40x_EXCP = 0x0002000000000000ULL,
/* PowerPC 405 Mac instructions */
PPC_405_MAC = 0x0004000000000000ULL,
/* PowerPC 440 specific instructions */
@@ -2450,7 +2444,7 @@ enum {
| PPC_CACHE_DCBA | PPC_CACHE_LOCK \
| PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
| PPC_40x_TLB | PPC_SEGMENT_64B \
- | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
+ | PPC_SLBI | PPC_WRTEE \
| PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
| PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
| PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 86f3bbc087f6..8272ceb5d7b1 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -12,7 +12,6 @@ DEF_HELPER_4(HASHCHKP, void, env, tl, tl, tl)
DEF_HELPER_2(store_msr, void, env, tl)
DEF_HELPER_1(ppc_maybe_interrupt, void, env)
DEF_HELPER_1(rfi, void, env)
-DEF_HELPER_1(40x_rfci, void, env)
DEF_HELPER_1(rfci, void, env)
DEF_HELPER_1(rfdi, void, env)
DEF_HELPER_1(rfmci, void, env)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index da92dce54624..14573d1d8b92 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7420,17 +7420,6 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
* they can be read with "p $ivor0", "p $ivor1", etc.
*/
break;
- case POWERPC_EXCP_40x:
- qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
- " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
- env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
- env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]);
-
- qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx
- " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
- env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2],
- env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]);
- break;
default:
break;
}
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index fde9912230e9..1a4c0ae5c0f0 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -473,114 +473,6 @@ static void powerpc_mcheck_checkstop(CPUPPCState *env)
#endif
}
-static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
-{
- CPUPPCState *env = &cpu->env;
- target_ulong msr, new_msr, vector;
- int srr0 = SPR_SRR0, srr1 = SPR_SRR1;
-
- /* new srr1 value excluding must-be-zero bits */
- msr = env->msr & ~0x783f0000ULL;
-
- /* new interrupt handler msr preserves ME unless explicitly overridden */
- new_msr = env->msr & (((target_ulong)1 << MSR_ME));
-
- /* HV emu assistance interrupt only exists on server arch 2.05 or later */
- if (excp == POWERPC_EXCP_HV_EMU) {
- excp = POWERPC_EXCP_PROGRAM;
- }
-
- vector = env->excp_vectors[excp];
- if (vector == (target_ulong)-1ULL) {
- cpu_abort(env_cpu(env),
- "Raised an exception without defined vector %d\n", excp);
- }
- vector |= env->excp_prefix;
-
- switch (excp) {
- case POWERPC_EXCP_CRITICAL: /* Critical input */
- srr0 = SPR_40x_SRR2;
- srr1 = SPR_40x_SRR3;
- break;
- case POWERPC_EXCP_MCHECK: /* Machine check exception */
- powerpc_mcheck_checkstop(env);
- /* machine check exceptions don't have ME set */
- new_msr &= ~((target_ulong)1 << MSR_ME);
- srr0 = SPR_40x_SRR2;
- srr1 = SPR_40x_SRR3;
- break;
- case POWERPC_EXCP_DSI: /* Data storage exception */
- trace_ppc_excp_dsi(env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]);
- break;
- case POWERPC_EXCP_ISI: /* Instruction storage exception */
- trace_ppc_excp_isi(msr, env->nip);
- break;
- case POWERPC_EXCP_EXTERNAL: /* External input */
- break;
- case POWERPC_EXCP_ALIGN: /* Alignment exception */
- break;
- case POWERPC_EXCP_PROGRAM: /* Program exception */
- switch (env->error_code & ~0xF) {
- case POWERPC_EXCP_FP:
- if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {
- trace_ppc_excp_fp_ignore();
- powerpc_reset_excp_state(cpu);
- return;
- }
- env->spr[SPR_40x_ESR] = ESR_FP;
- break;
- case POWERPC_EXCP_INVAL:
- trace_ppc_excp_inval(env->nip);
- env->spr[SPR_40x_ESR] = ESR_PIL;
- break;
- case POWERPC_EXCP_PRIV:
- env->spr[SPR_40x_ESR] = ESR_PPR;
- break;
- case POWERPC_EXCP_TRAP:
- env->spr[SPR_40x_ESR] = ESR_PTR;
- break;
- default:
- cpu_abort(env_cpu(env), "Invalid program exception %d. Aborting\n",
- env->error_code);
- break;
- }
- break;
- case POWERPC_EXCP_SYSCALL: /* System call exception */
- dump_syscall(env);
-
- /*
- * We need to correct the NIP which in this case is supposed
- * to point to the next instruction
- */
- env->nip += 4;
- break;
- case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
- trace_ppc_excp_print("FIT");
- break;
- case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
- trace_ppc_excp_print("WDT");
- break;
- case POWERPC_EXCP_DTLB: /* Data TLB error */
- case POWERPC_EXCP_ITLB: /* Instruction TLB error */
- break;
- case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
- trace_ppc_excp_print("PIT");
- break;
- case POWERPC_EXCP_DEBUG: /* Debug interrupt */
- cpu_abort(env_cpu(env), "%s exception not implemented\n",
- powerpc_excp_name(excp));
- break;
- default:
- cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
- excp);
- break;
- }
-
- env->spr[srr0] = env->nip;
- env->spr[srr1] = msr;
- powerpc_set_excp_state(cpu, vector, new_msr);
-}
-
static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
{
CPUPPCState *env = &cpu->env;
@@ -1635,9 +1527,6 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp)
env->excp_stats[excp]++;
switch (env->excp_model) {
- case POWERPC_EXCP_40x:
- powerpc_excp_40x(cpu, excp);
- break;
case POWERPC_EXCP_6xx:
powerpc_excp_6xx(cpu, excp);
break;
@@ -2779,11 +2668,6 @@ void raise_ebb_perfm_exception(CPUPPCState *env)
/*****************************************************************************/
/* Embedded PowerPC specific helpers */
-void helper_40x_rfci(CPUPPCState *env)
-{
- do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3]);
-}
-
void helper_rfci(CPUPPCState *env)
{
do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1]);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 918bf8f3a0cc..0f19949897f4 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5090,19 +5090,6 @@ static void gen_icread(DisasContext *ctx)
/* interpreted as no-op */
}
-/* rfci (supervisor only) */
-static void gen_rfci_40x(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV(ctx);
-#else
- CHK_SV(ctx);
- /* Restore CPU state */
- gen_helper_40x_rfci(tcg_env);
- ctx->base.is_jmp = DISAS_EXIT;
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
static void gen_rfci(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
@@ -5924,7 +5911,6 @@ GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
-GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
--
2.47.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 6/9] ppc/ppc405: Remove timer support
2025-01-10 14:17 [PATCH 0/9] ppc: Remove 405 CPU family Cédric Le Goater
` (4 preceding siblings ...)
2025-01-10 14:17 ` [PATCH 5/9] ppc/ppc405: Remove 40x exception model Cédric Le Goater
@ 2025-01-10 14:17 ` Cédric Le Goater
2025-01-10 14:17 ` [PATCH 7/9] ppc/ppc405: Remove cache handling instructions Cédric Le Goater
` (2 subsequent siblings)
8 siblings, 0 replies; 29+ messages in thread
From: Cédric Le Goater @ 2025-01-10 14:17 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, Nicholas Piggin, Daniel Henrique Barboza,
Cédric Le Goater
Since the 405 CPU family was phased out, these timer models have no
users anymore.
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/ppc/ppc.h | 15 ---
target/ppc/cpu.h | 7 -
target/ppc/helper.h | 4 -
target/ppc/spr_common.h | 4 -
hw/ppc/ppc.c | 251 -----------------------------------
target/ppc/timebase_helper.c | 20 ---
target/ppc/translate.c | 24 ----
hw/ppc/trace-events | 5 -
8 files changed, 330 deletions(-)
diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
index 8a14d623f8ca..18b0492dd198 100644
--- a/include/hw/ppc/ppc.h
+++ b/include/hw/ppc/ppc.h
@@ -8,19 +8,6 @@ PowerPCCPU *ppc_get_vcpu_by_pir(int pir);
int ppc_cpu_pir(PowerPCCPU *cpu);
int ppc_cpu_tir(PowerPCCPU *cpu);
-/* PowerPC hardware exceptions management helpers */
-typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
-typedef struct clk_setup_t clk_setup_t;
-struct clk_setup_t {
- clk_setup_cb cb;
- void *opaque;
-};
-static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
-{
- if (clk->cb != NULL)
- (*clk->cb)(clk->opaque, freq);
-}
-
struct ppc_tb_t {
/* Time base management */
int64_t tb_offset; /* Compensation */
@@ -67,8 +54,6 @@ int ppc_dcr_init (CPUPPCState *env, int (*dcr_read_error)(int dcrn),
int (*dcr_write_error)(int dcrn));
int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
dcr_read_cb drc_read, dcr_write_cb dcr_write);
-clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
- unsigned int decr_excp);
/* Embedded PowerPC reset */
void ppc40x_core_reset(PowerPCCPU *cpu);
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 32423cfb7368..504924f10561 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1615,11 +1615,7 @@ void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
uint64_t cpu_ppc_load_purr(CPUPPCState *env);
void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
#if !defined(CONFIG_USER_ONLY)
-target_ulong load_40x_pit(CPUPPCState *env);
-void store_40x_pit(CPUPPCState *env, target_ulong val);
void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
-void store_40x_tcr(CPUPPCState *env, target_ulong val);
-void store_40x_tsr(CPUPPCState *env, target_ulong val);
void store_booke_tcr(CPUPPCState *env, target_ulong val);
void store_booke_tsr(CPUPPCState *env, target_ulong val);
void ppc_tlb_invalidate_all(CPUPPCState *env);
@@ -2196,11 +2192,8 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_403_CDBCR (0x3D7)
#define SPR_L3ITCR0 (0x3D8)
#define SPR_TCR (0x3D8)
-#define SPR_40x_TSR (0x3D8)
#define SPR_IBR (0x3DA)
-#define SPR_40x_TCR (0x3DA)
#define SPR_ESASRR (0x3DB)
-#define SPR_40x_PIT (0x3DB)
#define SPR_403_TBL (0x3DC)
#define SPR_403_TBU (0x3DD)
#define SPR_SEBR (0x3DE)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 8272ceb5d7b1..025f2b5ac902 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -746,10 +746,6 @@ DEF_HELPER_FLAGS_1(load_hdecr, TCG_CALL_NO_RWG, tl, env)
DEF_HELPER_FLAGS_2(store_hdecr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_vtb, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_tbu40, TCG_CALL_NO_RWG, void, env, tl)
-DEF_HELPER_FLAGS_1(load_40x_pit, TCG_CALL_NO_RWG, tl, env)
-DEF_HELPER_FLAGS_2(store_40x_pit, TCG_CALL_NO_RWG, void, env, tl)
-DEF_HELPER_FLAGS_2(store_40x_tcr, TCG_CALL_NO_RWG, void, env, tl)
-DEF_HELPER_FLAGS_2(store_40x_tsr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_2(store_40x_pid, void, env, tl)
DEF_HELPER_2(store_40x_dbcr0, void, env, tl)
DEF_HELPER_FLAGS_2(store_booke_tcr, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h
index e98fb07bb285..4aab0e5f8291 100644
--- a/target/ppc/spr_common.h
+++ b/target/ppc/spr_common.h
@@ -135,11 +135,7 @@ void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn);
void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn);
void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn);
void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn);
-void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn);
-void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn);
void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn);
-void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn);
-void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn);
void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn);
void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn);
void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn);
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 90e3db5cfeba..2c72c43f6ed3 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -1163,257 +1163,6 @@ void cpu_ppc_hdecr_exit(CPUPPCState *env)
cpu_ppc_hdecr_lower(cpu);
}
-/*****************************************************************************/
-/* PowerPC 40x timers */
-
-/* PIT, FIT & WDT */
-typedef struct ppc40x_timer_t ppc40x_timer_t;
-struct ppc40x_timer_t {
- uint64_t pit_reload; /* PIT auto-reload value */
- uint64_t fit_next; /* Tick for next FIT interrupt */
- QEMUTimer *fit_timer;
- uint64_t wdt_next; /* Tick for next WDT interrupt */
- QEMUTimer *wdt_timer;
-
- /* 405 have the PIT, 440 have a DECR. */
- unsigned int decr_excp;
-};
-
-/* Fixed interval timer */
-static void cpu_4xx_fit_cb (void *opaque)
-{
- PowerPCCPU *cpu = opaque;
- CPUPPCState *env = &cpu->env;
- ppc_tb_t *tb_env;
- ppc40x_timer_t *ppc40x_timer;
- uint64_t now, next;
-
- tb_env = env->tb_env;
- ppc40x_timer = tb_env->opaque;
- now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
- switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
- case 0:
- next = 1 << 9;
- break;
- case 1:
- next = 1 << 13;
- break;
- case 2:
- next = 1 << 17;
- break;
- case 3:
- next = 1 << 21;
- break;
- default:
- /* Cannot occur, but makes gcc happy */
- return;
- }
- next = now + tb_to_ns_round_up(tb_env->tb_freq, next);
- timer_mod(ppc40x_timer->fit_timer, next);
- env->spr[SPR_40x_TSR] |= 1 << 26;
- if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) {
- ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1);
- }
- trace_ppc4xx_fit((int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
- env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
-}
-
-/* Programmable interval timer */
-static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp)
-{
- ppc40x_timer_t *ppc40x_timer;
- uint64_t now, next;
-
- ppc40x_timer = tb_env->opaque;
- if (ppc40x_timer->pit_reload <= 1 ||
- !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
- (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
- /* Stop PIT */
- trace_ppc4xx_pit_stop();
- timer_del(tb_env->decr_timer);
- } else {
- trace_ppc4xx_pit_start(ppc40x_timer->pit_reload);
- now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
-
- if (is_excp) {
- tb_env->decr_next += ppc40x_timer->pit_reload;
- } else {
- tb_env->decr_next = ns_to_tb(tb_env->decr_freq, now)
- + ppc40x_timer->pit_reload;
- }
- next = tb_to_ns_round_up(tb_env->decr_freq, tb_env->decr_next);
- timer_mod(tb_env->decr_timer, next);
- }
-}
-
-static void cpu_4xx_pit_cb (void *opaque)
-{
- PowerPCCPU *cpu = opaque;
- CPUPPCState *env = &cpu->env;
- ppc_tb_t *tb_env;
- ppc40x_timer_t *ppc40x_timer;
-
- tb_env = env->tb_env;
- ppc40x_timer = tb_env->opaque;
- env->spr[SPR_40x_TSR] |= 1 << 27;
- if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) {
- ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1);
- }
- start_stop_pit(env, tb_env, 1);
- trace_ppc4xx_pit((int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
- (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
- env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
- ppc40x_timer->pit_reload);
-}
-
-/* Watchdog timer */
-static void cpu_4xx_wdt_cb (void *opaque)
-{
- PowerPCCPU *cpu = opaque;
- CPUPPCState *env = &cpu->env;
- ppc_tb_t *tb_env;
- ppc40x_timer_t *ppc40x_timer;
- uint64_t now, next;
-
- tb_env = env->tb_env;
- ppc40x_timer = tb_env->opaque;
- now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
- switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
- case 0:
- next = 1 << 17;
- break;
- case 1:
- next = 1 << 21;
- break;
- case 2:
- next = 1 << 25;
- break;
- case 3:
- next = 1 << 29;
- break;
- default:
- /* Cannot occur, but makes gcc happy */
- return;
- }
- next = now + tb_to_ns_round_up(tb_env->decr_freq, next);
- trace_ppc4xx_wdt(env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
- switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
- case 0x0:
- case 0x1:
- timer_mod(ppc40x_timer->wdt_timer, next);
- ppc40x_timer->wdt_next = next;
- env->spr[SPR_40x_TSR] |= 1U << 31;
- break;
- case 0x2:
- timer_mod(ppc40x_timer->wdt_timer, next);
- ppc40x_timer->wdt_next = next;
- env->spr[SPR_40x_TSR] |= 1 << 30;
- if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) {
- ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1);
- }
- break;
- case 0x3:
- env->spr[SPR_40x_TSR] &= ~0x30000000;
- env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
- switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
- case 0x0:
- /* No reset */
- break;
- case 0x1: /* Core reset */
- ppc40x_core_reset(cpu);
- break;
- case 0x2: /* Chip reset */
- ppc40x_chip_reset(cpu);
- break;
- case 0x3: /* System reset */
- ppc40x_system_reset(cpu);
- break;
- }
- }
-}
-
-void store_40x_pit (CPUPPCState *env, target_ulong val)
-{
- ppc_tb_t *tb_env;
- ppc40x_timer_t *ppc40x_timer;
-
- tb_env = env->tb_env;
- ppc40x_timer = tb_env->opaque;
- trace_ppc40x_store_pit(val);
- ppc40x_timer->pit_reload = val;
- start_stop_pit(env, tb_env, 0);
-}
-
-target_ulong load_40x_pit (CPUPPCState *env)
-{
- return cpu_ppc_load_decr(env);
-}
-
-void store_40x_tsr(CPUPPCState *env, target_ulong val)
-{
- PowerPCCPU *cpu = env_archcpu(env);
-
- trace_ppc40x_store_tcr(val);
-
- env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
- if (val & 0x80000000) {
- ppc_set_irq(cpu, PPC_INTERRUPT_PIT, 0);
- }
-}
-
-void store_40x_tcr(CPUPPCState *env, target_ulong val)
-{
- PowerPCCPU *cpu = env_archcpu(env);
- ppc_tb_t *tb_env;
-
- trace_ppc40x_store_tsr(val);
-
- tb_env = env->tb_env;
- env->spr[SPR_40x_TCR] = val & 0xFFC00000;
- start_stop_pit(env, tb_env, 1);
- cpu_4xx_wdt_cb(cpu);
-}
-
-static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq)
-{
- CPUPPCState *env = opaque;
- ppc_tb_t *tb_env = env->tb_env;
-
- trace_ppc40x_set_tb_clk(freq);
- tb_env->tb_freq = freq;
- tb_env->decr_freq = freq;
- /* XXX: we should also update all timers */
-}
-
-clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
- unsigned int decr_excp)
-{
- ppc_tb_t *tb_env;
- ppc40x_timer_t *ppc40x_timer;
- PowerPCCPU *cpu = env_archcpu(env);
-
- trace_ppc40x_timers_init(freq);
-
- tb_env = g_new0(ppc_tb_t, 1);
- ppc40x_timer = g_new0(ppc40x_timer_t, 1);
-
- env->tb_env = tb_env;
- tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
- tb_env->tb_freq = freq;
- tb_env->decr_freq = freq;
- tb_env->opaque = ppc40x_timer;
-
- /* We use decr timer for PIT */
- tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_pit_cb, cpu);
- ppc40x_timer->fit_timer =
- timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_fit_cb, cpu);
- ppc40x_timer->wdt_timer =
- timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_wdt_cb, cpu);
- ppc40x_timer->decr_excp = decr_excp;
-
- return &ppc_40x_set_tb_clk;
-}
-
/*****************************************************************************/
/* Embedded PowerPC Device Control Registers */
typedef struct ppc_dcrn_t ppc_dcrn_t;
diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c
index 73120323b4e6..1eee0a6918d3 100644
--- a/target/ppc/timebase_helper.c
+++ b/target/ppc/timebase_helper.c
@@ -181,26 +181,6 @@ void helper_store_tbu40(CPUPPCState *env, target_ulong val)
}
}
-target_ulong helper_load_40x_pit(CPUPPCState *env)
-{
- return load_40x_pit(env);
-}
-
-void helper_store_40x_pit(CPUPPCState *env, target_ulong val)
-{
- store_40x_pit(env, val);
-}
-
-void helper_store_40x_tcr(CPUPPCState *env, target_ulong val)
-{
- store_40x_tcr(env, val);
-}
-
-void helper_store_40x_tsr(CPUPPCState *env, target_ulong val)
-{
- store_40x_tsr(env, val);
-}
-
void helper_store_booke_tcr(CPUPPCState *env, target_ulong val)
{
store_booke_tcr(env, val);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 0f19949897f4..ea5eff7cf0f8 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -946,18 +946,6 @@ void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
/* PowerPC 40x specific registers */
#if !defined(CONFIG_USER_ONLY)
-void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
-{
- translator_io_start(&ctx->base);
- gen_helper_load_40x_pit(cpu_gpr[gprn], tcg_env);
-}
-
-void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
-{
- translator_io_start(&ctx->base);
- gen_helper_store_40x_pit(tcg_env, cpu_gpr[gprn]);
-}
-
void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
@@ -967,18 +955,6 @@ void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
ctx->base.is_jmp = DISAS_EXIT_UPDATE;
}
-void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn)
-{
- translator_io_start(&ctx->base);
- gen_helper_store_40x_tcr(tcg_env, cpu_gpr[gprn]);
-}
-
-void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn)
-{
- translator_io_start(&ctx->base);
- gen_helper_store_40x_tsr(tcg_env, cpu_gpr[gprn]);
-}
-
void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index 1f125ce84193..d00a81666c82 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -123,16 +123,11 @@ ppc_decr_load(uint64_t tb) "decr 0x%016" PRIx64
ppc_decr_excp(const char *action) "%s decrementer"
ppc_decr_store(uint32_t nr_bits, uint64_t decr, uint64_t value) "%d-bit 0x%016" PRIx64 " => 0x%016" PRIx64
-ppc4xx_fit(uint32_t ir, uint64_t tcr, uint64_t tsr) "ir %d TCR 0x%" PRIx64 " TSR 0x%" PRIx64
ppc4xx_pit_stop(void) ""
ppc4xx_pit_start(uint64_t reload) "PIT 0x%016" PRIx64
-ppc4xx_pit(uint32_t ar, uint32_t ir, uint64_t tcr, uint64_t tsr, uint64_t reload) "ar %d ir %d TCR 0x%" PRIx64 " TSR 0x%" PRIx64 " PIT 0x%016" PRIx64
ppc4xx_wdt(uint64_t tcr, uint64_t tsr) "TCR 0x%" PRIx64 " TSR 0x%" PRIx64
-ppc40x_store_pit(uint64_t value) "val 0x%" PRIx64
ppc40x_store_tcr(uint64_t value) "val 0x%" PRIx64
ppc40x_store_tsr(uint64_t value) "val 0x%" PRIx64
-ppc40x_set_tb_clk(uint32_t value) "new frequency %" PRIu32
-ppc40x_timers_init(uint32_t value) "frequency %" PRIu32
ppc_irq_set(void *env, uint32_t pin, uint32_t level) "env [%p] pin %d level %d"
ppc_irq_set_exit(void *env, uint32_t irq, uint32_t level, uint32_t pending, uint32_t request) "env [%p] irq 0x%05" PRIx32 " level %d => pending 0x%08" PRIx32 " req 0x%08" PRIx32
--
2.47.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 7/9] ppc/ppc405: Remove cache handling instructions
2025-01-10 14:17 [PATCH 0/9] ppc: Remove 405 CPU family Cédric Le Goater
` (5 preceding siblings ...)
2025-01-10 14:17 ` [PATCH 6/9] ppc/ppc405: Remove timer support Cédric Le Goater
@ 2025-01-10 14:17 ` Cédric Le Goater
2025-01-10 16:09 ` Philippe Mathieu-Daudé
2025-01-10 14:17 ` [PATCH 8/9] ppc/ppc405: Remove TLB instructions Cédric Le Goater
2025-01-10 14:18 ` [PATCH 9/9] ppc/ppc405: Remove POWERPC_MMU_SOFT_4xx MMU model Cédric Le Goater
8 siblings, 1 reply; 29+ messages in thread
From: Cédric Le Goater @ 2025-01-10 14:17 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, Nicholas Piggin, Daniel Henrique Barboza,
Cédric Le Goater
Since the 405 CPU family was phased out, these instructions have no
users anymore.
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
target/ppc/cpu.h | 6 +-----
target/ppc/translate.c | 11 -----------
2 files changed, 1 insertion(+), 16 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 504924f10561..f83f01a62a12 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2234,9 +2234,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_L3CR (0x3FA)
#define SPR_750_TDCH (0x3FA)
#define SPR_IABR2 (0x3FA)
-#define SPR_40x_DCCR (0x3FA)
#define SPR_ICTC (0x3FB)
-#define SPR_40x_ICCR (0x3FB)
#define SPR_THRM1 (0x3FC)
#define SPR_403_PBL1 (0x3FC)
#define SPR_SP (0x3FD)
@@ -2408,8 +2406,6 @@ enum {
PPC_TLBIVAX = 0x0080000000000000ULL,
/* PowerPC 4xx dedicated instructions */
PPC_4xx_COMMON = 0x0100000000000000ULL,
- /* PowerPC 40x ibct instructions */
- PPC_40x_ICBT = 0x0200000000000000ULL,
/* rfmci is not implemented in all BookE PowerPC */
PPC_RFMCI = 0x0400000000000000ULL,
/* rfdi instruction */
@@ -2440,7 +2436,7 @@ enum {
| PPC_SLBI | PPC_WRTEE \
| PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
| PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
- | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
+ | PPC_4xx_COMMON | PPC_RFMCI \
| PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_POPCNTWD \
| PPC_CILDST)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index ea5eff7cf0f8..779103c0472d 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5042,16 +5042,6 @@ static void gen_dcread(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-/* icbt */
-static void gen_icbt_40x(DisasContext *ctx)
-{
- /*
- * interpreted as no-op
- * XXX: specification say this is treated as a load by the MMU but
- * does not generate any exception
- */
-}
-
/* iccci */
static void gen_iccci(DisasContext *ctx)
{
@@ -5884,7 +5874,6 @@ GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
-GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
--
2.47.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 7/9] ppc/ppc405: Remove cache handling instructions
2025-01-10 14:17 ` [PATCH 7/9] ppc/ppc405: Remove cache handling instructions Cédric Le Goater
@ 2025-01-10 16:09 ` Philippe Mathieu-Daudé
2025-01-10 16:15 ` Cédric Le Goater
0 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-10 16:09 UTC (permalink / raw)
To: Cédric Le Goater, qemu-devel
Cc: qemu-ppc, Nicholas Piggin, Daniel Henrique Barboza
On 10/1/25 15:17, Cédric Le Goater wrote:
> Since the 405 CPU family was phased out, these instructions have no
> users anymore.
>
> Signed-off-by: Cédric Le Goater <clg@redhat.com>
> ---
> target/ppc/cpu.h | 6 +-----
> target/ppc/translate.c | 11 -----------
> 2 files changed, 1 insertion(+), 16 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 504924f10561..f83f01a62a12 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -2234,9 +2234,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
> #define SPR_L3CR (0x3FA)
> #define SPR_750_TDCH (0x3FA)
> #define SPR_IABR2 (0x3FA)
> -#define SPR_40x_DCCR (0x3FA)
> #define SPR_ICTC (0x3FB)
> -#define SPR_40x_ICCR (0x3FB)
> #define SPR_THRM1 (0x3FC)
> #define SPR_403_PBL1 (0x3FC)
> #define SPR_SP (0x3FD)
Belong to patch #3?
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 7/9] ppc/ppc405: Remove cache handling instructions
2025-01-10 16:09 ` Philippe Mathieu-Daudé
@ 2025-01-10 16:15 ` Cédric Le Goater
0 siblings, 0 replies; 29+ messages in thread
From: Cédric Le Goater @ 2025-01-10 16:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-ppc, Nicholas Piggin, Daniel Henrique Barboza
On 1/10/25 17:09, Philippe Mathieu-Daudé wrote:
> On 10/1/25 15:17, Cédric Le Goater wrote:
>> Since the 405 CPU family was phased out, these instructions have no
>> users anymore.
>>
>> Signed-off-by: Cédric Le Goater <clg@redhat.com>
>> ---
>> target/ppc/cpu.h | 6 +-----
>> target/ppc/translate.c | 11 -----------
>> 2 files changed, 1 insertion(+), 16 deletions(-)
>>
>> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
>> index 504924f10561..f83f01a62a12 100644
>> --- a/target/ppc/cpu.h
>> +++ b/target/ppc/cpu.h
>> @@ -2234,9 +2234,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
>> #define SPR_L3CR (0x3FA)
>> #define SPR_750_TDCH (0x3FA)
>> #define SPR_IABR2 (0x3FA)
>> -#define SPR_40x_DCCR (0x3FA)
>> #define SPR_ICTC (0x3FB)
>> -#define SPR_40x_ICCR (0x3FB)
>> #define SPR_THRM1 (0x3FC)
>> #define SPR_403_PBL1 (0x3FC)
>> #define SPR_SP (0x3FD)
>
> Belong to patch #3?
>
It could. These are the Data and Instruction Cache Cachability
Register, so they could stay in this patch too.
Thanks,
C.
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 8/9] ppc/ppc405: Remove TLB instructions
2025-01-10 14:17 [PATCH 0/9] ppc: Remove 405 CPU family Cédric Le Goater
` (6 preceding siblings ...)
2025-01-10 14:17 ` [PATCH 7/9] ppc/ppc405: Remove cache handling instructions Cédric Le Goater
@ 2025-01-10 14:17 ` Cédric Le Goater
2025-01-10 14:18 ` [PATCH 9/9] ppc/ppc405: Remove POWERPC_MMU_SOFT_4xx MMU model Cédric Le Goater
8 siblings, 0 replies; 29+ messages in thread
From: Cédric Le Goater @ 2025-01-10 14:17 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, Nicholas Piggin, Daniel Henrique Barboza,
Cédric Le Goater
Since the 405 CPU family was phased out, these instructions have no
users anymore.
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
target/ppc/cpu.h | 4 +-
target/ppc/helper.h | 1 -
target/ppc/spr_common.h | 1 -
target/ppc/mmu_helper.c | 2 +-
target/ppc/translate.c | 81 -----------------------------------------
5 files changed, 2 insertions(+), 87 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index f83f01a62a12..6850d67b6875 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2383,8 +2383,6 @@ enum {
PPC_SEGMENT = 0x0000020000000000ULL,
/* PowerPC 6xx TLB management instructions */
PPC_6xx_TLB = 0x0000040000000000ULL,
- /* PowerPC 40x TLB management instructions */
- PPC_40x_TLB = 0x0000100000000000ULL,
/* segment register access instructions for PowerPC 64 "bridge" */
PPC_SEGMENT_64B = 0x0000200000000000ULL,
/* SLB management */
@@ -2432,7 +2430,7 @@ enum {
| PPC_CACHE_DCBZ \
| PPC_CACHE_DCBA | PPC_CACHE_LOCK \
| PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
- | PPC_40x_TLB | PPC_SEGMENT_64B \
+ | PPC_SEGMENT_64B \
| PPC_SLBI | PPC_WRTEE \
| PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
| PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 025f2b5ac902..102f3e8aecf3 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -746,7 +746,6 @@ DEF_HELPER_FLAGS_1(load_hdecr, TCG_CALL_NO_RWG, tl, env)
DEF_HELPER_FLAGS_2(store_hdecr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_vtb, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_tbu40, TCG_CALL_NO_RWG, void, env, tl)
-DEF_HELPER_2(store_40x_pid, void, env, tl)
DEF_HELPER_2(store_40x_dbcr0, void, env, tl)
DEF_HELPER_FLAGS_2(store_booke_tcr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_booke_tsr, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h
index 4aab0e5f8291..7535a016ee6b 100644
--- a/target/ppc/spr_common.h
+++ b/target/ppc/spr_common.h
@@ -136,7 +136,6 @@ void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn);
void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn);
void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn);
void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn);
-void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn);
void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn);
void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn);
void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn);
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index a802bc9c62b0..faa4522ec8b0 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -673,7 +673,7 @@ static inline int booke_page_size_to_tlb(target_ulong page_size)
#define PPC4XX_TLBLO_ATTR_MASK 0x000000FF
#define PPC4XX_TLBLO_RPN_MASK 0xFFFFFC00
-void helper_store_40x_pid(CPUPPCState *env, target_ulong val)
+static void helper_store_40x_pid(CPUPPCState *env, target_ulong val)
{
if (env->spr[SPR_40x_PID] != val) {
env->spr[SPR_40x_PID] = val;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 779103c0472d..997b8647b137 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -955,13 +955,6 @@ void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
ctx->base.is_jmp = DISAS_EXIT_UPDATE;
}
-void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF);
- gen_helper_store_40x_pid(tcg_env, t0);
-}
-
void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
@@ -5096,77 +5089,6 @@ static void gen_rfmci(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-/* TLB management - PowerPC 405 implementation */
-
-/* tlbre */
-static void gen_tlbre_40x(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV(ctx);
-#else
- CHK_SV(ctx);
- switch (rB(ctx->opcode)) {
- case 0:
- gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], tcg_env,
- cpu_gpr[rA(ctx->opcode)]);
- break;
- case 1:
- gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], tcg_env,
- cpu_gpr[rA(ctx->opcode)]);
- break;
- default:
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
- break;
- }
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-/* tlbsx - tlbsx. */
-static void gen_tlbsx_40x(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV(ctx);
-#else
- TCGv t0;
-
- CHK_SV(ctx);
- t0 = tcg_temp_new();
- gen_addr_reg_index(ctx, t0);
- gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], tcg_env, t0);
- if (Rc(ctx->opcode)) {
- TCGLabel *l1 = gen_new_label();
- tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
- tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
- gen_set_label(l1);
- }
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-/* tlbwe */
-static void gen_tlbwe_40x(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV(ctx);
-#else
- CHK_SV(ctx);
-
- switch (rB(ctx->opcode)) {
- case 0:
- gen_helper_4xx_tlbwe_hi(tcg_env, cpu_gpr[rA(ctx->opcode)],
- cpu_gpr[rS(ctx->opcode)]);
- break;
- case 1:
- gen_helper_4xx_tlbwe_lo(tcg_env, cpu_gpr[rA(ctx->opcode)],
- cpu_gpr[rS(ctx->opcode)]);
- break;
- default:
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
- break;
- }
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
/* TLB management - PowerPC 440 implementation */
/* tlbre */
@@ -5879,9 +5801,6 @@ GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
-GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
-GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
-GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
--
2.47.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 9/9] ppc/ppc405: Remove POWERPC_MMU_SOFT_4xx MMU model
2025-01-10 14:17 [PATCH 0/9] ppc: Remove 405 CPU family Cédric Le Goater
` (7 preceding siblings ...)
2025-01-10 14:17 ` [PATCH 8/9] ppc/ppc405: Remove TLB instructions Cédric Le Goater
@ 2025-01-10 14:18 ` Cédric Le Goater
8 siblings, 0 replies; 29+ messages in thread
From: Cédric Le Goater @ 2025-01-10 14:18 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, Nicholas Piggin, Daniel Henrique Barboza,
Cédric Le Goater
Since the 405 CPU family was phased out, this MMU model has no users
anymore.
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
target/ppc/cpu.h | 6 ----
target/ppc/mmu-booke.h | 3 --
target/ppc/excp_helper.c | 3 --
target/ppc/mmu-booke.c | 63 -----------------------------------
target/ppc/mmu_common.c | 71 ----------------------------------------
target/ppc/mmu_helper.c | 16 ---------
6 files changed, 162 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 6850d67b6875..8056c917efb1 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -232,8 +232,6 @@ typedef enum powerpc_mmu_t {
* keywords: tlbld tlbli TLBMISS PTEHI PTELO)
*/
POWERPC_MMU_SOFT_74xx = 0x00000003,
- /* PowerPC 4xx MMU with software TLB */
- POWERPC_MMU_SOFT_4xx = 0x00000004,
/* PowerPC MMU in real mode only */
POWERPC_MMU_REAL = 0x00000006,
/* Freescale MPC8xx MMU model */
@@ -2146,7 +2144,6 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_7XX_UPMC3 (0x3AD)
#define SPR_7XX_UPMC4 (0x3AE)
#define SPR_USDA (0x3AF)
-#define SPR_40x_ZPR (0x3B0)
#define SPR_BOOKE_MAS7 (0x3B0)
#define SPR_74XX_MMCR2 (0x3B0)
#define SPR_7XX_PMC5 (0x3B1)
@@ -2181,13 +2178,10 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_BOOKE_ICDBDR (0x3D3)
#define SPR_TLBMISS (0x3D4)
#define SPR_IMISS (0x3D4)
-#define SPR_40x_ESR (0x3D4)
#define SPR_PTEHI (0x3D5)
#define SPR_ICMP (0x3D5)
-#define SPR_40x_DEAR (0x3D5)
#define SPR_PTELO (0x3D6)
#define SPR_RPA (0x3D6)
-#define SPR_40x_EVPR (0x3D6)
#define SPR_L3PM (0x3D7)
#define SPR_403_CDBCR (0x3D7)
#define SPR_L3ITCR0 (0x3D8)
diff --git a/target/ppc/mmu-booke.h b/target/ppc/mmu-booke.h
index f972843bbb7b..dcbfac2caefe 100644
--- a/target/ppc/mmu-booke.h
+++ b/target/ppc/mmu-booke.h
@@ -4,9 +4,6 @@
#include "cpu.h"
int ppcemb_tlb_search(CPUPPCState *env, target_ulong address, uint32_t pid);
-int mmu40x_get_physical_address(CPUPPCState *env, hwaddr *raddr, int *prot,
- target_ulong address,
- MMUAccessType access_type);
hwaddr booke206_tlb_to_page_size(CPUPPCState *env, ppcmas_tlb_t *tlb);
int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb, hwaddr *raddrp,
target_ulong address, uint32_t pid);
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 1a4c0ae5c0f0..b795d1969d01 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -3040,9 +3040,6 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
insn = ppc_ldl_code(env, env->nip);
switch (env->mmu_model) {
- case POWERPC_MMU_SOFT_4xx:
- env->spr[SPR_40x_DEAR] = vaddr;
- break;
case POWERPC_MMU_BOOKE:
case POWERPC_MMU_BOOKE206:
env->spr[SPR_BOOKE_DEAR] = vaddr;
diff --git a/target/ppc/mmu-booke.c b/target/ppc/mmu-booke.c
index 55e5dd7c6b0c..3bb721c3d2c6 100644
--- a/target/ppc/mmu-booke.c
+++ b/target/ppc/mmu-booke.c
@@ -68,69 +68,6 @@ int ppcemb_tlb_search(CPUPPCState *env, target_ulong address, uint32_t pid)
return -1;
}
-int mmu40x_get_physical_address(CPUPPCState *env, hwaddr *raddr, int *prot,
- target_ulong address,
- MMUAccessType access_type)
-{
- ppcemb_tlb_t *tlb;
- int i, ret, zsel, zpr, pr;
-
- ret = -1;
- pr = FIELD_EX64(env->msr, MSR, PR);
- for (i = 0; i < env->nb_tlb; i++) {
- tlb = &env->tlb.tlbe[i];
- if (!ppcemb_tlb_check(env, tlb, raddr, address,
- env->spr[SPR_40x_PID], i)) {
- continue;
- }
- zsel = (tlb->attr >> 4) & 0xF;
- zpr = (env->spr[SPR_40x_ZPR] >> (30 - (2 * zsel))) & 0x3;
- qemu_log_mask(CPU_LOG_MMU,
- "%s: TLB %d zsel %d zpr %d ty %d attr %08x\n",
- __func__, i, zsel, zpr, access_type, tlb->attr);
- /* Check execute enable bit */
- switch (zpr) {
- case 0x2:
- if (pr != 0) {
- goto check_perms;
- }
- /* fall through */
- case 0x3:
- /* All accesses granted */
- *prot = PAGE_RWX;
- ret = 0;
- break;
-
- case 0x0:
- if (pr != 0) {
- /* Raise Zone protection fault. */
- env->spr[SPR_40x_ESR] = 1 << 22;
- *prot = 0;
- ret = -2;
- break;
- }
- /* fall through */
- case 0x1:
-check_perms:
- /* Check from TLB entry */
- *prot = tlb->prot;
- if (check_prot_access_type(*prot, access_type)) {
- ret = 0;
- } else {
- env->spr[SPR_40x_ESR] = 0;
- ret = -2;
- }
- break;
- }
- }
- qemu_log_mask(CPU_LOG_MMU, "%s: access %s " TARGET_FMT_lx " => "
- HWADDR_FMT_plx " %d %d\n", __func__,
- ret < 0 ? "refused" : "granted", address,
- ret < 0 ? 0 : *raddr, *prot, ret);
-
- return ret;
-}
-
static bool mmubooke_check_pid(CPUPPCState *env, ppcemb_tlb_t *tlb,
hwaddr *raddr, target_ulong addr, int i)
{
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index fb62b947f1d9..1748d088ac15 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -599,74 +599,6 @@ static bool ppc_real_mode_xlate(PowerPCCPU *cpu, vaddr eaddr,
return false;
}
-static bool ppc_40x_xlate(PowerPCCPU *cpu, vaddr eaddr,
- MMUAccessType access_type,
- hwaddr *raddrp, int *psizep, int *protp,
- int mmu_idx, bool guest_visible)
-{
- CPUState *cs = CPU(cpu);
- CPUPPCState *env = &cpu->env;
- int ret;
-
- if (ppc_real_mode_xlate(cpu, eaddr, access_type, raddrp, psizep, protp)) {
- return true;
- }
-
- ret = mmu40x_get_physical_address(env, raddrp, protp, eaddr, access_type);
- if (ret == 0) {
- *psizep = TARGET_PAGE_BITS;
- return true;
- } else if (!guest_visible) {
- return false;
- }
-
- log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
- if (access_type == MMU_INST_FETCH) {
- switch (ret) {
- case -1:
- /* No matches in page tables or TLB */
- cs->exception_index = POWERPC_EXCP_ITLB;
- env->error_code = 0;
- env->spr[SPR_40x_DEAR] = eaddr;
- env->spr[SPR_40x_ESR] = 0x00000000;
- break;
- case -2:
- /* Access rights violation */
- cs->exception_index = POWERPC_EXCP_ISI;
- env->error_code = 0x08000000;
- break;
- default:
- g_assert_not_reached();
- }
- } else {
- switch (ret) {
- case -1:
- /* No matches in page tables or TLB */
- cs->exception_index = POWERPC_EXCP_DTLB;
- env->error_code = 0;
- env->spr[SPR_40x_DEAR] = eaddr;
- if (access_type == MMU_DATA_STORE) {
- env->spr[SPR_40x_ESR] = 0x00800000;
- } else {
- env->spr[SPR_40x_ESR] = 0x00000000;
- }
- break;
- case -2:
- /* Access rights violation */
- cs->exception_index = POWERPC_EXCP_DSI;
- env->error_code = 0;
- env->spr[SPR_40x_DEAR] = eaddr;
- if (access_type == MMU_DATA_STORE) {
- env->spr[SPR_40x_ESR] |= 0x00800000;
- }
- break;
- default:
- g_assert_not_reached();
- }
- }
- return false;
-}
-
static bool ppc_6xx_xlate(PowerPCCPU *cpu, vaddr eaddr,
MMUAccessType access_type,
hwaddr *raddrp, int *psizep, int *protp,
@@ -832,9 +764,6 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
case POWERPC_MMU_BOOKE206:
return ppc_booke_xlate(cpu, eaddr, access_type, raddrp,
psizep, protp, mmu_idx, guest_visible);
- case POWERPC_MMU_SOFT_4xx:
- return ppc_40x_xlate(cpu, eaddr, access_type, raddrp,
- psizep, protp, mmu_idx, guest_visible);
case POWERPC_MMU_SOFT_6xx:
return ppc_6xx_xlate(cpu, eaddr, access_type, raddrp,
psizep, protp, mmu_idx, guest_visible);
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index faa4522ec8b0..36e06de0e36c 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -107,19 +107,6 @@ static void ppc6xx_tlb_store(CPUPPCState *env, target_ulong EPN, int way,
env->last_way = way;
}
-/* Helpers specific to PowerPC 40x implementations */
-static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env)
-{
- ppcemb_tlb_t *tlb;
- int i;
-
- for (i = 0; i < env->nb_tlb; i++) {
- tlb = &env->tlb.tlbe[i];
- tlb->prot &= ~PAGE_VALID;
- }
- tlb_flush(env_cpu(env));
-}
-
static void booke206_flush_tlb(CPUPPCState *env, int flags,
const int check_iprot)
{
@@ -258,9 +245,6 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
case POWERPC_MMU_SOFT_6xx:
ppc6xx_tlb_invalidate_all(env);
break;
- case POWERPC_MMU_SOFT_4xx:
- ppc4xx_tlb_invalidate_all(env);
- break;
case POWERPC_MMU_REAL:
cpu_abort(env_cpu(env), "No TLB for PowerPC 4xx in real mode\n");
break;
--
2.47.1
^ permalink raw reply related [flat|nested] 29+ messages in thread