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From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "yunhui cui" <cuiyunhui@bytedance.com>
Cc: <masahiroy@kernel.org>, <nathan@kernel.org>,
	<nicolas.schier@linux.dev>, <dennis@kernel.org>, <tj@kernel.org>,
	<cl@gentwo.org>, <paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
	<aou@eecs.berkeley.edu>, <alex@ghiti.fr>, <andybnac@gmail.com>,
	<bjorn@rivosinc.com>, <cyrilbur@tenstorrent.com>,
	<rostedt@goodmis.org>, <puranjay@kernel.org>,
	<ben.dooks@codethink.co.uk>, <zhangchunyan@iscas.ac.cn>,
	<ruanjinjie@huawei.com>, <jszhang@kernel.org>,
	<charlie@rivosinc.com>, <cleger@rivosinc.com>,
	<antonb@tenstorrent.com>, <ajones@ventanamicro.com>,
	<debug@rivosinc.com>, <haibo1.xu@intel.com>,
	<samuel.holland@sifive.com>, <linux-kbuild@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-mm@kvack.org>,
	<linux-riscv@lists.infradead.org>,
	"linux-riscv" <linux-riscv-bounces@lists.infradead.org>,
	<wangziang.ok@bytedance.com>
Subject: Re: [External] [PATCH] RISC-V: store percpu offset in CSR_SCRATCH
Date: Wed, 09 Jul 2025 16:20:38 +0200	[thread overview]
Message-ID: <DB7L9ZHZI3AI.36SXWX2SO9OS7@ventanamicro.com> (raw)
In-Reply-To: <CAEEQ3wkoy3Jr0vZk=X4U56KYPq3=5t7Wr4RE6uNby3MS5qzh-g@mail.gmail.com>

2025-07-09T19:42:26+08:00, yunhui cui <cuiyunhui@bytedance.com>:
> Bench platform: Spacemit(R) X60
> No changes:
> 6.77, 6.791, 6.792, 6.826, 6.784, 6.839, 6.776, 6.733, 6.795, 6.763
> Geometric mean: 6.786839305
> Reusing the current scratch:
> 7.085, 7.09, 7.021, 7.089, 7.068, 7.034, 7.06, 7.062, 7.065, 7.051
> Geometric mean: 7.062466876

Great results.

> A degradation of approximately 4.06% is observed. The possible cause
> of the degradation is that the CSR_TVEC register is set every time a
> kernel/user exception occurs.

I assume the same.

> The following is the patch without percpu optimization, which only
> tests the overhead of separating exceptions into kernel and user
> modes.

Is the overhead above with this patch?  And when we then use the
CSR_SCRATCH for percpu, does it degrade even further?

Thanks.

WARNING: multiple messages have this Message-ID (diff)
From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "yunhui cui" <cuiyunhui@bytedance.com>
Cc: <masahiroy@kernel.org>, <nathan@kernel.org>,
	<nicolas.schier@linux.dev>, <dennis@kernel.org>, <tj@kernel.org>,
	<cl@gentwo.org>, <paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
	<aou@eecs.berkeley.edu>, <alex@ghiti.fr>, <andybnac@gmail.com>,
	<bjorn@rivosinc.com>, <cyrilbur@tenstorrent.com>,
	<rostedt@goodmis.org>, <puranjay@kernel.org>,
	<ben.dooks@codethink.co.uk>, <zhangchunyan@iscas.ac.cn>,
	<ruanjinjie@huawei.com>, <jszhang@kernel.org>,
	<charlie@rivosinc.com>, <cleger@rivosinc.com>,
	<antonb@tenstorrent.com>, <ajones@ventanamicro.com>,
	<debug@rivosinc.com>, <haibo1.xu@intel.com>,
	<samuel.holland@sifive.com>, <linux-kbuild@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-mm@kvack.org>,
	<linux-riscv@lists.infradead.org>,
	"linux-riscv" <linux-riscv-bounces@lists.infradead.org>,
	<wangziang.ok@bytedance.com>
Subject: Re: [External] [PATCH] RISC-V: store percpu offset in CSR_SCRATCH
Date: Wed, 09 Jul 2025 16:20:38 +0200	[thread overview]
Message-ID: <DB7L9ZHZI3AI.36SXWX2SO9OS7@ventanamicro.com> (raw)
In-Reply-To: <CAEEQ3wkoy3Jr0vZk=X4U56KYPq3=5t7Wr4RE6uNby3MS5qzh-g@mail.gmail.com>

2025-07-09T19:42:26+08:00, yunhui cui <cuiyunhui@bytedance.com>:
> Bench platform: Spacemit(R) X60
> No changes:
> 6.77, 6.791, 6.792, 6.826, 6.784, 6.839, 6.776, 6.733, 6.795, 6.763
> Geometric mean: 6.786839305
> Reusing the current scratch:
> 7.085, 7.09, 7.021, 7.089, 7.068, 7.034, 7.06, 7.062, 7.065, 7.051
> Geometric mean: 7.062466876

Great results.

> A degradation of approximately 4.06% is observed. The possible cause
> of the degradation is that the CSR_TVEC register is set every time a
> kernel/user exception occurs.

I assume the same.

> The following is the patch without percpu optimization, which only
> tests the overhead of separating exceptions into kernel and user
> modes.

Is the overhead above with this patch?  And when we then use the
CSR_SCRATCH for percpu, does it degrade even further?

Thanks.

_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2025-07-09 14:20 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-04  8:45 [PATCH RFC] RISC-V: Fix a register to store the percpu offset Yunhui Cui
2025-07-04  8:45 ` Yunhui Cui
2025-07-07  7:55 ` Clément Léger
2025-07-07  7:55   ` Clément Léger
2025-07-07 12:50 ` [PATCH] RISC-V: store percpu offset in CSR_SCRATCH Radim Krčmář
2025-07-07 12:50   ` Radim Krčmář
2025-07-08 10:07   ` [External] " yunhui cui
2025-07-08 10:07     ` yunhui cui
2025-07-08 11:10     ` Radim Krčmář
2025-07-08 11:10       ` Radim Krčmář
2025-07-09 11:42       ` yunhui cui
2025-07-09 11:42         ` yunhui cui
2025-07-09 14:20         ` Radim Krčmář [this message]
2025-07-09 14:20           ` Radim Krčmář
2025-07-10  3:45           ` yunhui cui
2025-07-10  3:45             ` yunhui cui
2025-07-10  6:35             ` Radim Krčmář
2025-07-10  6:35               ` Radim Krčmář
2025-07-10 11:47               ` yunhui cui
2025-07-10 11:47                 ` yunhui cui
2025-07-10 16:40                 ` [PATCH] RISC-V: store precomputed percpu_offset in the task struct Radim Krčmář
2025-07-10 16:40                   ` Radim Krčmář

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