* [Intel-xe] [PATCH v2 00/11] Start register cleanup
@ 2023-02-17 0:52 Lucas De Marchi
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 01/11] drm/xe: Remove outdated build workaround Lucas De Marchi
` (11 more replies)
0 siblings, 12 replies; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-17 0:52 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Maarten Lankhorst, Matthew Auld
Start cleaning up the register definitions used in xe.
This removes dependency on the following registers:
- intel_engine_regs.h
- intel_gt_regs.h
- intel_lrc_reg.h
- intel_gpu_commands.h
- i915_reg.h
- intel_mchbar_regs.h
The includes on the display/ part are left as is since there is still
some more work to do to detangle dependencies. Other than from the
display/ files, xe still depends on:
- i915_reg_defs.h
- display/intel_display_core.h
- display/ext/intel_device_info.h
- display/ext/intel_pch.h
The first one are the generic defines used for defining the registers.
They probably can be split and part of them copied to include/drm to be
shared across the drivers. The last 3 are expected to be cleaned up
together with the rest of the display.
This series started by doing it manually with a few greps, migrated in
the middle to do by "remove the include, parse the warnings from the
compile and use that to generate the header" and finished with a small
python script with clang. There may be some inconsistencies how the
first patches and the last ones were done. I can clean that up on next
version.
Lucas De Marchi (11):
drm/xe: Remove outdated build workaround
drm/xe: Sort includes
drm/xe/guc: Remove i915_regs.h include
drm/xe: Remove dependency on intel_engine_regs.h
drm/xe: Remove dependency on intel_gt_regs.h
drm/xe: Remove dependency on intel_lrc_reg.h
drm/xe: Remove dependency on intel_gpu_commands.h
drm/xe: Remove dependency on i915_reg.h
drm/xe/guc_pc: Move gt register to the proper place
drm/xe: Remove dependency on intel_mchbar_regs.h
drm/xe: Use relative includes for i915_reg_defs.h
drivers/gpu/drm/i915/i915_reg_defs.h | 2 +
drivers/gpu/drm/xe/Makefile | 10 +-
drivers/gpu/drm/xe/display/Makefile | 120 ++++++++
drivers/gpu/drm/xe/regs/xe_engine_regs.h | 98 +++++++
drivers/gpu/drm/xe/regs/xe_gpu_commands.h | 96 +++++++
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 289 ++++++++++++++++++++
drivers/gpu/drm/xe/regs/xe_lrc_regs.h | 17 ++
drivers/gpu/drm/xe/regs/xe_regs.h | 111 ++++++++
drivers/gpu/drm/xe/xe_bb.c | 7 +-
drivers/gpu/drm/xe/xe_bo.c | 2 -
drivers/gpu/drm/xe/xe_bo_evict.c | 2 +-
drivers/gpu/drm/xe/xe_debugfs.c | 2 +-
drivers/gpu/drm/xe/xe_device.c | 9 +-
drivers/gpu/drm/xe/xe_device.h | 3 +-
drivers/gpu/drm/xe/xe_display.c | 12 +-
drivers/gpu/drm/xe/xe_dma_buf.c | 8 +-
drivers/gpu/drm/xe/xe_engine.c | 4 +-
drivers/gpu/drm/xe/xe_exec.c | 2 +-
drivers/gpu/drm/xe/xe_execlist.c | 16 +-
drivers/gpu/drm/xe/xe_force_wake.c | 5 +-
drivers/gpu/drm/xe/xe_ggtt.c | 10 +-
drivers/gpu/drm/xe/xe_gt.c | 5 +-
drivers/gpu/drm/xe/xe_gt_clock.c | 7 +-
drivers/gpu/drm/xe/xe_gt_debugfs.c | 2 +-
drivers/gpu/drm/xe/xe_gt_mcr.c | 5 +-
drivers/gpu/drm/xe/xe_gt_mcr.h | 2 +-
drivers/gpu/drm/xe/xe_gt_pagefault.c | 2 +-
drivers/gpu/drm/xe/xe_gt_sysfs.c | 4 +-
drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c | 2 +-
drivers/gpu/drm/xe/xe_gt_topology.c | 2 +-
drivers/gpu/drm/xe/xe_guc.c | 13 +-
drivers/gpu/drm/xe/xe_guc_ads.c | 8 +-
drivers/gpu/drm/xe/xe_guc_ct.c | 4 +-
drivers/gpu/drm/xe/xe_guc_debugfs.c | 2 +-
drivers/gpu/drm/xe/xe_guc_hwconfig.c | 2 +-
drivers/gpu/drm/xe/xe_guc_log.c | 2 +-
drivers/gpu/drm/xe/xe_guc_pc.c | 29 +-
drivers/gpu/drm/xe/xe_guc_reg.h | 2 +-
drivers/gpu/drm/xe/xe_guc_submit.c | 9 +-
drivers/gpu/drm/xe/xe_huc.c | 2 +-
drivers/gpu/drm/xe/xe_huc_debugfs.c | 2 +-
drivers/gpu/drm/xe/xe_hw_engine.c | 8 +-
drivers/gpu/drm/xe/xe_hw_fence.c | 1 -
drivers/gpu/drm/xe/xe_irq.c | 8 +-
drivers/gpu/drm/xe/xe_lrc.c | 14 +-
drivers/gpu/drm/xe/xe_migrate.c | 14 +-
drivers/gpu/drm/xe/xe_mmio.c | 8 +-
drivers/gpu/drm/xe/xe_mocs.c | 7 +-
drivers/gpu/drm/xe/xe_module.c | 1 +
drivers/gpu/drm/xe/xe_pci.c | 8 +-
drivers/gpu/drm/xe/xe_pcode.c | 10 +-
drivers/gpu/drm/xe/xe_pm.c | 4 +-
drivers/gpu/drm/xe/xe_preempt_fence.c | 2 +-
drivers/gpu/drm/xe/xe_pt.c | 4 +-
drivers/gpu/drm/xe/xe_query.c | 11 +-
drivers/gpu/drm/xe/xe_reg_sr.c | 10 +-
drivers/gpu/drm/xe/xe_reg_sr_types.h | 2 -
drivers/gpu/drm/xe/xe_reg_whitelist.c | 8 +-
drivers/gpu/drm/xe/xe_ring_ops.c | 11 +-
drivers/gpu/drm/xe/xe_rtp.c | 1 -
drivers/gpu/drm/xe/xe_rtp.h | 2 -
drivers/gpu/drm/xe/xe_rtp_types.h | 2 -
drivers/gpu/drm/xe/xe_sa.c | 3 +-
drivers/gpu/drm/xe/xe_sched_job.c | 1 -
drivers/gpu/drm/xe/xe_sync.c | 5 +-
drivers/gpu/drm/xe/xe_ttm_gtt_mgr.c | 2 +-
drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 5 +-
drivers/gpu/drm/xe/xe_ttm_vram_mgr.c | 2 +-
drivers/gpu/drm/xe/xe_tuning.c | 5 +-
drivers/gpu/drm/xe/xe_uc.c | 4 +-
drivers/gpu/drm/xe/xe_vm.c | 2 +-
drivers/gpu/drm/xe/xe_vm_madvise.c | 8 +-
drivers/gpu/drm/xe/xe_wa.c | 7 +-
drivers/gpu/drm/xe/xe_wopcm.c | 2 +-
74 files changed, 900 insertions(+), 213 deletions(-)
create mode 100644 drivers/gpu/drm/xe/display/Makefile
create mode 100644 drivers/gpu/drm/xe/regs/xe_engine_regs.h
create mode 100644 drivers/gpu/drm/xe/regs/xe_gpu_commands.h
create mode 100644 drivers/gpu/drm/xe/regs/xe_gt_regs.h
create mode 100644 drivers/gpu/drm/xe/regs/xe_lrc_regs.h
create mode 100644 drivers/gpu/drm/xe/regs/xe_regs.h
--
2.39.0
^ permalink raw reply [flat|nested] 42+ messages in thread
* [Intel-xe] [PATCH v2 01/11] drm/xe: Remove outdated build workaround
2023-02-17 0:52 [Intel-xe] [PATCH v2 00/11] Start register cleanup Lucas De Marchi
@ 2023-02-17 0:52 ` Lucas De Marchi
2023-02-17 20:13 ` Rodrigo Vivi
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 02/11] drm/xe: Sort includes Lucas De Marchi
` (10 subsequent siblings)
11 siblings, 1 reply; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-17 0:52 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Maarten Lankhorst, Matthew Auld
Use the more common "call cc-disable-warning" way to disable warnings.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/Makefile | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index abd804d622e6..18257cd7227d 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -13,14 +13,8 @@
# will most likely get a sudden build breakage... Hopefully we will fix
# new warnings before CI updates!
subdir-ccflags-y := -Wall -Wextra
-# making these call cc-disable-warning breaks when trying to build xe.mod.o
-# by calling make M=drivers/gpu/drm/xe. This doesn't happen in upstream tree,
-# so it was somehow fixed by the changes in the build system. Move it back to
-# $(call cc-disable-warning, ...) after rebase.
-subdir-ccflags-y += -Wno-unused-parameter
-subdir-ccflags-y += -Wno-type-limits
-#subdir-ccflags-y += $(call cc-disable-warning, unused-parameter)
-#subdir-ccflags-y += $(call cc-disable-warning, type-limits)
+subdir-ccflags-y += $(call cc-disable-warning, unused-parameter)
+subdir-ccflags-y += $(call cc-disable-warning, type-limits)
subdir-ccflags-y += $(call cc-disable-warning, missing-field-initializers)
subdir-ccflags-y += $(call cc-disable-warning, unused-but-set-variable)
# clang warnings
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-xe] [PATCH v2 02/11] drm/xe: Sort includes
2023-02-17 0:52 [Intel-xe] [PATCH v2 00/11] Start register cleanup Lucas De Marchi
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 01/11] drm/xe: Remove outdated build workaround Lucas De Marchi
@ 2023-02-17 0:52 ` Lucas De Marchi
2023-02-17 11:20 ` Matthew Auld
2023-02-17 11:39 ` Jani Nikula
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 03/11] drm/xe/guc: Remove i915_regs.h include Lucas De Marchi
` (9 subsequent siblings)
11 siblings, 2 replies; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-17 0:52 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Maarten Lankhorst, Matthew Auld
Sort includes and split them in blocks:
1) .h corresponding to the .c. Example: xe_bb.c should have a "#include
"xe_bb.h" first.
2) #include <linux/...>
3) #include <drm/...>
4) local includes
5) i915 includes
This is accomplished by running
`clang-format --style=file -i --sort-includes drivers/gpu/drm/xe/*.c`
and ignoring all the changes after the includes. There are also some
manual tweaks to split the blocks.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_bb.c | 4 ++--
drivers/gpu/drm/xe/xe_bo.c | 2 --
drivers/gpu/drm/xe/xe_bo_evict.c | 2 +-
drivers/gpu/drm/xe/xe_debugfs.c | 2 +-
drivers/gpu/drm/xe/xe_device.c | 9 ++++-----
drivers/gpu/drm/xe/xe_display.c | 12 ++++++------
drivers/gpu/drm/xe/xe_dma_buf.c | 8 +++-----
drivers/gpu/drm/xe/xe_engine.c | 4 ++--
drivers/gpu/drm/xe/xe_exec.c | 2 +-
drivers/gpu/drm/xe/xe_execlist.c | 9 ++++-----
drivers/gpu/drm/xe/xe_force_wake.c | 4 ++--
drivers/gpu/drm/xe/xe_ggtt.c | 7 +++----
drivers/gpu/drm/xe/xe_gt.c | 2 +-
drivers/gpu/drm/xe/xe_gt_clock.c | 8 ++++----
drivers/gpu/drm/xe/xe_gt_debugfs.c | 2 +-
drivers/gpu/drm/xe/xe_gt_mcr.c | 2 +-
drivers/gpu/drm/xe/xe_gt_pagefault.c | 2 +-
drivers/gpu/drm/xe/xe_gt_sysfs.c | 4 +++-
drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c | 2 +-
drivers/gpu/drm/xe/xe_gt_topology.c | 2 +-
drivers/gpu/drm/xe/xe_guc.c | 13 +++++++------
drivers/gpu/drm/xe/xe_guc_ads.c | 5 +++--
drivers/gpu/drm/xe/xe_guc_ct.c | 4 ++--
drivers/gpu/drm/xe/xe_guc_debugfs.c | 2 +-
drivers/gpu/drm/xe/xe_guc_hwconfig.c | 2 +-
drivers/gpu/drm/xe/xe_guc_log.c | 2 +-
drivers/gpu/drm/xe/xe_guc_pc.c | 12 +++++++-----
drivers/gpu/drm/xe/xe_guc_submit.c | 6 +++---
drivers/gpu/drm/xe/xe_huc.c | 2 +-
drivers/gpu/drm/xe/xe_huc_debugfs.c | 2 +-
drivers/gpu/drm/xe/xe_hw_engine.c | 3 +--
drivers/gpu/drm/xe/xe_hw_fence.c | 1 -
drivers/gpu/drm/xe/xe_irq.c | 5 +++--
drivers/gpu/drm/xe/xe_lrc.c | 7 +++----
drivers/gpu/drm/xe/xe_migrate.c | 11 ++++++-----
drivers/gpu/drm/xe/xe_mmio.c | 3 +--
drivers/gpu/drm/xe/xe_mocs.c | 4 ++--
drivers/gpu/drm/xe/xe_module.c | 1 +
drivers/gpu/drm/xe/xe_pci.c | 5 ++---
drivers/gpu/drm/xe/xe_pcode.c | 10 ++++------
drivers/gpu/drm/xe/xe_pm.c | 4 ++--
drivers/gpu/drm/xe/xe_preempt_fence.c | 2 +-
drivers/gpu/drm/xe/xe_pt.c | 4 ++--
drivers/gpu/drm/xe/xe_query.c | 11 ++++++-----
drivers/gpu/drm/xe/xe_reg_sr.c | 5 ++---
drivers/gpu/drm/xe/xe_reg_whitelist.c | 7 +++----
drivers/gpu/drm/xe/xe_ring_ops.c | 4 ++--
drivers/gpu/drm/xe/xe_rtp.c | 1 -
drivers/gpu/drm/xe/xe_sa.c | 3 ++-
drivers/gpu/drm/xe/xe_sched_job.c | 1 -
drivers/gpu/drm/xe/xe_sync.c | 5 +++--
drivers/gpu/drm/xe/xe_ttm_gtt_mgr.c | 2 +-
drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 2 +-
drivers/gpu/drm/xe/xe_ttm_vram_mgr.c | 2 +-
drivers/gpu/drm/xe/xe_tuning.c | 2 +-
drivers/gpu/drm/xe/xe_uc.c | 4 ++--
drivers/gpu/drm/xe/xe_vm.c | 2 +-
drivers/gpu/drm/xe/xe_vm_madvise.c | 8 +++++---
drivers/gpu/drm/xe/xe_wopcm.c | 2 +-
59 files changed, 128 insertions(+), 132 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_bb.c b/drivers/gpu/drm/xe/xe_bb.c
index 8b9209571fd0..a25079d4e710 100644
--- a/drivers/gpu/drm/xe/xe_bb.c
+++ b/drivers/gpu/drm/xe/xe_bb.c
@@ -2,12 +2,12 @@
/*
* Copyright © 2022 Intel Corporation
*/
-
#include "xe_bb.h"
-#include "xe_sa.h"
+
#include "xe_device.h"
#include "xe_engine_types.h"
#include "xe_hw_fence.h"
+#include "xe_sa.h"
#include "xe_sched_job.h"
#include "xe_vm_types.h"
diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index 9b7b9c8f84be..4d7852efc807 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -2,8 +2,6 @@
/*
* Copyright © 2021 Intel Corporation
*/
-
-
#include "xe_bo.h"
#include <linux/dma-buf.h>
diff --git a/drivers/gpu/drm/xe/xe_bo_evict.c b/drivers/gpu/drm/xe/xe_bo_evict.c
index 3fb3c8c77efa..a594eb6fec03 100644
--- a/drivers/gpu/drm/xe/xe_bo_evict.c
+++ b/drivers/gpu/drm/xe/xe_bo_evict.c
@@ -2,9 +2,9 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_bo_evict.h"
#include "xe_bo.h"
-#include "xe_bo_evict.h"
#include "xe_device.h"
#include "xe_ggtt.h"
#include "xe_gt.h"
diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugfs.c
index b0f8b157ffa3..f4dbaa666575 100644
--- a/drivers/gpu/drm/xe/xe_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_debugfs.c
@@ -2,6 +2,7 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_debugfs.h"
#include <linux/string_helpers.h>
@@ -9,7 +10,6 @@
#include "xe_bo.h"
#include "xe_device.h"
-#include "xe_debugfs.h"
#include "xe_gt_debugfs.h"
#include "xe_step.h"
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index a028efa8eebe..4426ab06b796 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -2,15 +2,14 @@
/*
* Copyright © 2021 Intel Corporation
*/
-
#include "xe_device.h"
-#include <drm/drm_gem_ttm_helper.h>
#include <drm/drm_aperture.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_gem_ttm_helper.h>
#include <drm/drm_ioctl.h>
-#include <drm/xe_drm.h>
#include <drm/drm_managed.h>
-#include <drm/drm_atomic_helper.h>
+#include <drm/xe_drm.h>
#include "xe_bo.h"
#include "xe_debugfs.h"
@@ -21,8 +20,8 @@
#include "xe_exec.h"
#include "xe_gt.h"
#include "xe_irq.h"
-#include "xe_module.h"
#include "xe_mmio.h"
+#include "xe_module.h"
#include "xe_pcode.h"
#include "xe_pm.h"
#include "xe_query.h"
diff --git a/drivers/gpu/drm/xe/xe_display.c b/drivers/gpu/drm/xe/xe_display.c
index 47a16a3f85fa..6e7b6cfce4d9 100644
--- a/drivers/gpu/drm/xe/xe_display.c
+++ b/drivers/gpu/drm/xe/xe_display.c
@@ -6,12 +6,16 @@
#if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
#include "xe_display.h"
-#include "xe_module.h"
+
+#include <linux/fb.h>
#include <drm/drm_aperture.h>
#include <drm/drm_managed.h>
#include <drm/xe_drm.h>
+#include "display/ext/i915_irq.h"
+#include "display/ext/intel_dram.h"
+#include "display/ext/intel_pm.h"
#include "display/intel_acpi.h"
#include "display/intel_audio.h"
#include "display/intel_bw.h"
@@ -22,11 +26,7 @@
#include "display/intel_hdcp.h"
#include "display/intel_hotplug.h"
#include "display/intel_opregion.h"
-#include "display/ext/i915_irq.h"
-#include "display/ext/intel_dram.h"
-#include "display/ext/intel_pm.h"
-
-#include <linux/fb.h>
+#include "xe_module.h"
/* Xe device functions */
diff --git a/drivers/gpu/drm/xe/xe_dma_buf.c b/drivers/gpu/drm/xe/xe_dma_buf.c
index d09ff25bd940..355afe492bd1 100644
--- a/drivers/gpu/drm/xe/xe_dma_buf.c
+++ b/drivers/gpu/drm/xe/xe_dma_buf.c
@@ -2,21 +2,19 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_dma_buf.h"
+#include <kunit/test.h>
#include <linux/dma-buf.h>
+#include <linux/pci-p2pdma.h>
#include <drm/drm_device.h>
#include <drm/drm_prime.h>
-
#include <drm/ttm/ttm_tt.h>
-#include <kunit/test.h>
-#include <linux/pci-p2pdma.h>
-
#include "tests/xe_test.h"
#include "xe_bo.h"
#include "xe_device.h"
-#include "xe_dma_buf.h"
#include "xe_ttm_vram_mgr.h"
#include "xe_vm.h"
diff --git a/drivers/gpu/drm/xe/xe_engine.c b/drivers/gpu/drm/xe/xe_engine.c
index e478d0417e49..7b11602a4249 100644
--- a/drivers/gpu/drm/xe/xe_engine.c
+++ b/drivers/gpu/drm/xe/xe_engine.c
@@ -2,13 +2,13 @@
/*
* Copyright © 2021 Intel Corporation
*/
-
#include "xe_engine.h"
+#include <linux/nospec.h>
+
#include <drm/drm_device.h>
#include <drm/drm_file.h>
#include <drm/xe_drm.h>
-#include <linux/nospec.h>
#include "xe_device.h"
#include "xe_gt.h"
diff --git a/drivers/gpu/drm/xe/xe_exec.c b/drivers/gpu/drm/xe/xe_exec.c
index 00f298acc436..81248b5f232b 100644
--- a/drivers/gpu/drm/xe/xe_exec.c
+++ b/drivers/gpu/drm/xe/xe_exec.c
@@ -2,6 +2,7 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_exec.h"
#include <drm/drm_device.h>
#include <drm/drm_file.h>
@@ -10,7 +11,6 @@
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_engine.h"
-#include "xe_exec.h"
#include "xe_macros.h"
#include "xe_sched_job.h"
#include "xe_sync.h"
diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
index d555d77cbf49..5633259482ed 100644
--- a/drivers/gpu/drm/xe/xe_execlist.c
+++ b/drivers/gpu/drm/xe/xe_execlist.c
@@ -2,16 +2,15 @@
/*
* Copyright © 2021 Intel Corporation
*/
+#include "xe_execlist.h"
#include <drm/drm_managed.h>
-#include "xe_execlist.h"
-
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_engine.h"
-#include "xe_hw_fence.h"
#include "xe_gt.h"
+#include "xe_hw_fence.h"
#include "xe_lrc.h"
#include "xe_macros.h"
#include "xe_mmio.h"
@@ -19,11 +18,11 @@
#include "xe_ring_ops_types.h"
#include "xe_sched_job.h"
-#include "i915_reg.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_gt_regs.h"
#include "gt/intel_lrc_reg.h"
-#include "gt/intel_engine_regs.h"
+#include "i915_reg.h"
#define XE_EXECLIST_HANG_LIMIT 1
diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c
index d2080e6fbe10..188197c3a8fe 100644
--- a/drivers/gpu/drm/xe/xe_force_wake.c
+++ b/drivers/gpu/drm/xe/xe_force_wake.c
@@ -2,14 +2,14 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_force_wake.h"
#include <drm/drm_util.h>
-#include "xe_force_wake.h"
#include "xe_gt.h"
#include "xe_mmio.h"
-#include "gt/intel_gt_regs.h"
+#include "gt/intel_gt_regs.h"
#define XE_FORCE_WAKE_ACK_TIMEOUT_MS 50
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index d5bd9bc18c57..53a1edaee02d 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -2,24 +2,23 @@
/*
* Copyright © 2021 Intel Corporation
*/
-
#include "xe_ggtt.h"
#include <linux/sizes.h>
-#include <drm/i915_drm.h>
#include <drm/drm_managed.h>
+#include <drm/i915_drm.h>
-#include "xe_device.h"
#include "xe_bo.h"
+#include "xe_device.h"
#include "xe_gt.h"
#include "xe_gt_tlb_invalidation.h"
#include "xe_map.h"
#include "xe_mmio.h"
#include "xe_wopcm.h"
-#include "i915_reg.h"
#include "gt/intel_gt_regs.h"
+#include "i915_reg.h"
/* FIXME: Common file, preferably auto-gen */
#define MTL_GGTT_PTE_PAT0 BIT_ULL(52)
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 20dbc08d3685..5c7c2757bb49 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -2,6 +2,7 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_gt.h"
#include <linux/minmax.h>
@@ -14,7 +15,6 @@
#include "xe_execlist.h"
#include "xe_force_wake.h"
#include "xe_ggtt.h"
-#include "xe_gt.h"
#include "xe_gt_clock.h"
#include "xe_gt_mcr.h"
#include "xe_gt_pagefault.h"
diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
index 575433e9718a..e50117103e1e 100644
--- a/drivers/gpu/drm/xe/xe_gt_clock.c
+++ b/drivers/gpu/drm/xe/xe_gt_clock.c
@@ -2,16 +2,16 @@
/*
* Copyright © 2022 Intel Corporation
*/
-
-#include "i915_reg.h"
-#include "gt/intel_gt_regs.h"
+#include "xe_gt_clock.h"
#include "xe_device.h"
#include "xe_gt.h"
-#include "xe_gt_clock.h"
#include "xe_macros.h"
#include "xe_mmio.h"
+#include "gt/intel_gt_regs.h"
+#include "i915_reg.h"
+
static u32 read_reference_ts_freq(struct xe_gt *gt)
{
u32 ts_override = xe_mmio_read32(gt, GEN9_TIMESTAMP_OVERRIDE.reg);
diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.c b/drivers/gpu/drm/xe/xe_gt_debugfs.c
index c320e58810ce..6bd9b8a908ff 100644
--- a/drivers/gpu/drm/xe/xe_gt_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_gt_debugfs.c
@@ -2,6 +2,7 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_gt_debugfs.h"
#include <drm/drm_debugfs.h>
#include <drm/drm_managed.h>
@@ -10,7 +11,6 @@
#include "xe_force_wake.h"
#include "xe_ggtt.h"
#include "xe_gt.h"
-#include "xe_gt_debugfs.h"
#include "xe_gt_mcr.h"
#include "xe_gt_topology.h"
#include "xe_hw_engine.h"
diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index 7617f0340879..43910e48bdc9 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -2,9 +2,9 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_gt_mcr.h"
#include "xe_gt.h"
-#include "xe_gt_mcr.h"
#include "xe_gt_topology.h"
#include "xe_gt_types.h"
#include "xe_mmio.h"
diff --git a/drivers/gpu/drm/xe/xe_gt_pagefault.c b/drivers/gpu/drm/xe/xe_gt_pagefault.c
index ce79eb48feb8..78dcb8b04036 100644
--- a/drivers/gpu/drm/xe/xe_gt_pagefault.c
+++ b/drivers/gpu/drm/xe/xe_gt_pagefault.c
@@ -2,6 +2,7 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_gt_pagefault.h"
#include <linux/circ_buf.h>
@@ -10,7 +11,6 @@
#include "xe_bo.h"
#include "xe_gt.h"
-#include "xe_gt_pagefault.h"
#include "xe_gt_tlb_invalidation.h"
#include "xe_guc.h"
#include "xe_guc_ct.h"
diff --git a/drivers/gpu/drm/xe/xe_gt_sysfs.c b/drivers/gpu/drm/xe/xe_gt_sysfs.c
index 2d966d935b8e..717193671f3c 100644
--- a/drivers/gpu/drm/xe/xe_gt_sysfs.c
+++ b/drivers/gpu/drm/xe/xe_gt_sysfs.c
@@ -2,12 +2,14 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_gt_sysfs.h"
#include <linux/kobject.h>
#include <linux/sysfs.h>
+
#include <drm/drm_managed.h>
+
#include "xe_gt.h"
-#include "xe_gt_sysfs.h"
static void xe_gt_sysfs_kobj_release(struct kobject *kobj)
{
diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
index 2521c8a65690..24cf81aa46e5 100644
--- a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
+++ b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
@@ -2,9 +2,9 @@
/*
* Copyright © 2023 Intel Corporation
*/
+#include "xe_gt_tlb_invalidation.h"
#include "xe_gt.h"
-#include "xe_gt_tlb_invalidation.h"
#include "xe_guc.h"
#include "xe_guc_ct.h"
#include "xe_trace.h"
diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c
index 8e02e362ba27..e3be481ac8be 100644
--- a/drivers/gpu/drm/xe/xe_gt_topology.c
+++ b/drivers/gpu/drm/xe/xe_gt_topology.c
@@ -2,11 +2,11 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_gt_topology.h"
#include <linux/bitmap.h>
#include "xe_gt.h"
-#include "xe_gt_topology.h"
#include "xe_mmio.h"
#define XE_MAX_DSS_FUSE_BITS (32 * XE_MAX_DSS_FUSE_REGS)
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 5cdfdfd0de40..88cc912fa7eb 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -2,25 +2,26 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_guc.h"
#include "xe_bo.h"
#include "xe_device.h"
-#include "xe_guc.h"
+#include "xe_force_wake.h"
+#include "xe_gt.h"
#include "xe_guc_ads.h"
#include "xe_guc_ct.h"
#include "xe_guc_hwconfig.h"
#include "xe_guc_log.h"
-#include "xe_guc_reg.h"
#include "xe_guc_pc.h"
+#include "xe_guc_reg.h"
#include "xe_guc_submit.h"
-#include "xe_gt.h"
+#include "xe_mmio.h"
#include "xe_platform_types.h"
#include "xe_uc_fw.h"
#include "xe_wopcm.h"
-#include "xe_mmio.h"
-#include "xe_force_wake.h"
-#include "i915_reg_defs.h"
+
#include "gt/intel_gt_regs.h"
+#include "i915_reg_defs.h"
/* TODO: move to common file */
#define GUC_PVC_MOCS_INDEX_MASK REG_GENMASK(25, 24)
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 0c08cecaca40..1ea1b25e7170 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -2,21 +2,22 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_guc_ads.h"
#include <drm/drm_managed.h>
#include "xe_bo.h"
#include "xe_gt.h"
#include "xe_guc.h"
-#include "xe_guc_ads.h"
#include "xe_guc_reg.h"
#include "xe_hw_engine.h"
#include "xe_lrc.h"
#include "xe_map.h"
#include "xe_mmio.h"
#include "xe_platform_types.h"
-#include "gt/intel_gt_regs.h"
+
#include "gt/intel_engine_regs.h"
+#include "gt/intel_gt_regs.h"
/* Slack of a few additional entries per engine */
#define ADS_REGSET_EXTRA_MAX 8
diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index 84d4302d4e72..97fd25eea129 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -2,6 +2,7 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_guc_ct.h"
#include <linux/bitfield.h>
#include <linux/circ_buf.h>
@@ -12,10 +13,9 @@
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_gt.h"
-#include "xe_guc.h"
-#include "xe_guc_ct.h"
#include "xe_gt_pagefault.h"
#include "xe_gt_tlb_invalidation.h"
+#include "xe_guc.h"
#include "xe_guc_submit.h"
#include "xe_map.h"
#include "xe_trace.h"
diff --git a/drivers/gpu/drm/xe/xe_guc_debugfs.c b/drivers/gpu/drm/xe/xe_guc_debugfs.c
index 916e9633b322..d19a7f0f8f0b 100644
--- a/drivers/gpu/drm/xe/xe_guc_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_guc_debugfs.c
@@ -2,6 +2,7 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_guc_debugfs.h"
#include <drm/drm_debugfs.h>
#include <drm/drm_managed.h>
@@ -10,7 +11,6 @@
#include "xe_gt.h"
#include "xe_guc.h"
#include "xe_guc_ct.h"
-#include "xe_guc_debugfs.h"
#include "xe_guc_log.h"
#include "xe_macros.h"
diff --git a/drivers/gpu/drm/xe/xe_guc_hwconfig.c b/drivers/gpu/drm/xe/xe_guc_hwconfig.c
index 57640d608787..f6fd3f51fea4 100644
--- a/drivers/gpu/drm/xe/xe_guc_hwconfig.c
+++ b/drivers/gpu/drm/xe/xe_guc_hwconfig.c
@@ -2,6 +2,7 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_guc_hwconfig.h"
#include <drm/drm_managed.h>
@@ -9,7 +10,6 @@
#include "xe_device.h"
#include "xe_gt.h"
#include "xe_guc.h"
-#include "xe_guc_hwconfig.h"
#include "xe_map.h"
static struct xe_gt *
diff --git a/drivers/gpu/drm/xe/xe_guc_log.c b/drivers/gpu/drm/xe/xe_guc_log.c
index 7ec1b2bb1f8e..795e6a955676 100644
--- a/drivers/gpu/drm/xe/xe_guc_log.c
+++ b/drivers/gpu/drm/xe/xe_guc_log.c
@@ -2,12 +2,12 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_guc_log.h"
#include <drm/drm_managed.h>
#include "xe_bo.h"
#include "xe_gt.h"
-#include "xe_guc_log.h"
#include "xe_map.h"
#include "xe_module.h"
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 3ba0c8a35109..1d4ac0c26d3c 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -2,22 +2,24 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_guc_pc.h"
+
+#include <linux/delay.h>
#include <drm/drm_managed.h>
+
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_gt.h"
-#include "xe_gt_types.h"
#include "xe_gt_sysfs.h"
+#include "xe_gt_types.h"
#include "xe_guc_ct.h"
#include "xe_map.h"
#include "xe_mmio.h"
#include "xe_pcode.h"
-#include "i915_reg_defs.h"
-#include "i915_reg.h"
-
-#include <linux/delay.h>
+#include "i915_reg.h"
+#include "i915_reg_defs.h"
#include "intel_mchbar_regs.h"
/* For GEN6_RP_STATE_CAP.reg to be merged when the definition moves to Xe */
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index a54f7f82d04d..305a0e061778 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -2,6 +2,7 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_guc_submit.h"
#include <linux/bitfield.h>
#include <linux/bitmap.h>
@@ -13,12 +14,11 @@
#include "xe_device.h"
#include "xe_engine.h"
+#include "xe_force_wake.h"
+#include "xe_gt.h"
#include "xe_guc.h"
#include "xe_guc_ct.h"
#include "xe_guc_engine_types.h"
-#include "xe_guc_submit.h"
-#include "xe_gt.h"
-#include "xe_force_wake.h"
#include "xe_hw_engine.h"
#include "xe_hw_fence.h"
#include "xe_lrc.h"
diff --git a/drivers/gpu/drm/xe/xe_huc.c b/drivers/gpu/drm/xe/xe_huc.c
index 82e7fb3a6292..b9fdcc623108 100644
--- a/drivers/gpu/drm/xe/xe_huc.c
+++ b/drivers/gpu/drm/xe/xe_huc.c
@@ -2,6 +2,7 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_huc.h"
#include "xe_bo.h"
#include "xe_device.h"
@@ -9,7 +10,6 @@
#include "xe_gt.h"
#include "xe_guc.h"
#include "xe_guc_reg.h"
-#include "xe_huc.h"
#include "xe_mmio.h"
#include "xe_uc_fw.h"
diff --git a/drivers/gpu/drm/xe/xe_huc_debugfs.c b/drivers/gpu/drm/xe/xe_huc_debugfs.c
index 268bac36336a..dc170c35057e 100644
--- a/drivers/gpu/drm/xe/xe_huc_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_huc_debugfs.c
@@ -2,6 +2,7 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_huc_debugfs.h"
#include <drm/drm_debugfs.h>
#include <drm/drm_managed.h>
@@ -9,7 +10,6 @@
#include "xe_device.h"
#include "xe_gt.h"
#include "xe_huc.h"
-#include "xe_huc_debugfs.h"
#include "xe_macros.h"
static struct xe_gt *
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index fd89dd90131c..edc59d9b124f 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -2,7 +2,6 @@
/*
* Copyright © 2021 Intel Corporation
*/
-
#include "xe_hw_engine.h"
#include <drm/drm_managed.h>
@@ -22,8 +21,8 @@
#include "xe_wa.h"
#include "gt/intel_engine_regs.h"
-#include "i915_reg.h"
#include "gt/intel_gt_regs.h"
+#include "i915_reg.h"
#define MAX_MMIO_BASES 3
struct engine_info {
diff --git a/drivers/gpu/drm/xe/xe_hw_fence.c b/drivers/gpu/drm/xe/xe_hw_fence.c
index e56ca2867545..8930135aca1c 100644
--- a/drivers/gpu/drm/xe/xe_hw_fence.c
+++ b/drivers/gpu/drm/xe/xe_hw_fence.c
@@ -2,7 +2,6 @@
/*
* Copyright © 2021 Intel Corporation
*/
-
#include "xe_hw_fence.h"
#include <linux/device.h>
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 7b7ddd11c2b8..f30fd2b14c22 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -2,6 +2,7 @@
/*
* Copyright © 2021 Intel Corporation
*/
+#include "xe_irq.h"
#include <linux/sched/clock.h>
@@ -10,13 +11,13 @@
#include "xe_device.h"
#include "xe_display.h"
#include "xe_drv.h"
-#include "xe_guc.h"
#include "xe_gt.h"
+#include "xe_guc.h"
#include "xe_hw_engine.h"
#include "xe_mmio.h"
-#include "i915_reg.h"
#include "gt/intel_gt_regs.h"
+#include "i915_reg.h"
static void gen3_assert_iir_is_zero(struct xe_gt *gt, i915_reg_t reg)
{
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 347ff9b34494..45503c39240a 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -2,22 +2,21 @@
/*
* Copyright © 2021 Intel Corporation
*/
-
#include "xe_lrc.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_engine_types.h"
#include "xe_gt.h"
-#include "xe_map.h"
#include "xe_hw_fence.h"
+#include "xe_map.h"
#include "xe_vm.h"
-#include "i915_reg.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_gt_regs.h"
#include "gt/intel_lrc_reg.h"
-#include "gt/intel_engine_regs.h"
+#include "i915_reg.h"
#define GEN8_CTX_VALID (1 << 0)
#define GEN8_CTX_L3LLC_COHERENT (1 << 5)
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index cbcc355cd391..3d2f8d04bc3a 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -4,6 +4,12 @@
*/
#include "xe_migrate.h"
+#include <linux/sizes.h>
+
+#include <drm/drm_managed.h>
+#include <drm/ttm/ttm_tt.h>
+#include <drm/xe_drm.h>
+
#include "xe_bb.h"
#include "xe_bo.h"
#include "xe_engine.h"
@@ -20,11 +26,6 @@
#include "xe_trace.h"
#include "xe_vm.h"
-#include <linux/sizes.h>
-#include <drm/drm_managed.h>
-#include <drm/ttm/ttm_tt.h>
-#include <drm/xe_drm.h>
-
#include "gt/intel_gpu_commands.h"
/**
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 8a953df2b468..57788afe206e 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -2,7 +2,6 @@
/*
* Copyright © 2021 Intel Corporation
*/
-
#include "xe_mmio.h"
#include <drm/drm_managed.h>
@@ -14,9 +13,9 @@
#include "xe_macros.h"
#include "xe_module.h"
-#include "i915_reg.h"
#include "gt/intel_engine_regs.h"
#include "gt/intel_gt_regs.h"
+#include "i915_reg.h"
#define XEHP_MTCFG_ADDR _MMIO(0x101800)
#define TILE_COUNT REG_GENMASK(15, 8)
diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
index 86b966fffbe5..99d3cc6c7164 100644
--- a/drivers/gpu/drm/xe/xe_mocs.c
+++ b/drivers/gpu/drm/xe/xe_mocs.c
@@ -2,14 +2,14 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_mocs.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_engine.h"
#include "xe_gt.h"
-#include "xe_platform_types.h"
#include "xe_mmio.h"
-#include "xe_mocs.h"
+#include "xe_platform_types.h"
#include "xe_step_types.h"
#include "gt/intel_gt_regs.h"
diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
index 9cd1663f83f6..314025b54e7d 100644
--- a/drivers/gpu/drm/xe/xe_module.c
+++ b/drivers/gpu/drm/xe/xe_module.c
@@ -2,6 +2,7 @@
/*
* Copyright © 2021 Intel Corporation
*/
+#include "xe_module.h"
#include <linux/init.h>
#include <linux/module.h>
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 25598de3a1fc..b0e5c402190c 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -2,7 +2,6 @@
/*
* Copyright © 2021 Intel Corporation
*/
-
#include "xe_pci.h"
#include <linux/device/driver.h>
@@ -10,12 +9,12 @@
#include <linux/pci.h>
#include <linux/pm_runtime.h>
-#include <drm/drm_drv.h>
#include <drm/drm_color_mgmt.h>
+#include <drm/drm_drv.h>
#include <drm/xe_pciids.h>
-#include "xe_drv.h"
#include "xe_device.h"
+#include "xe_drv.h"
#include "xe_macros.h"
#include "xe_module.h"
#include "xe_pm.h"
diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c
index 1a76fe478853..17c8416b4179 100644
--- a/drivers/gpu/drm/xe/xe_pcode.c
+++ b/drivers/gpu/drm/xe/xe_pcode.c
@@ -2,16 +2,14 @@
/*
* Copyright © 2022 Intel Corporation
*/
-
-#include "xe_pcode_api.h"
#include "xe_pcode.h"
-#include "xe_gt.h"
-#include "xe_mmio.h"
-
+#include <linux/delay.h>
#include <linux/errno.h>
-#include <linux/delay.h>
+#include "xe_gt.h"
+#include "xe_mmio.h"
+#include "xe_pcode_api.h"
/**
* DOC: PCODE
diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c
index 44c38e670587..02a05aa6783e 100644
--- a/drivers/gpu/drm/xe/xe_pm.c
+++ b/drivers/gpu/drm/xe/xe_pm.c
@@ -2,6 +2,7 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_pm.h"
#include <linux/pm_runtime.h>
@@ -11,9 +12,8 @@
#include "xe_bo_evict.h"
#include "xe_device.h"
#include "xe_display.h"
-#include "xe_pm.h"
-#include "xe_gt.h"
#include "xe_ggtt.h"
+#include "xe_gt.h"
#include "xe_irq.h"
#include "xe_pcode.h"
diff --git a/drivers/gpu/drm/xe/xe_preempt_fence.c b/drivers/gpu/drm/xe/xe_preempt_fence.c
index 6ab9ff442766..20ea4f8f0702 100644
--- a/drivers/gpu/drm/xe/xe_preempt_fence.c
+++ b/drivers/gpu/drm/xe/xe_preempt_fence.c
@@ -2,11 +2,11 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_preempt_fence.h"
#include <linux/slab.h>
#include "xe_engine.h"
-#include "xe_preempt_fence.h"
#include "xe_vm.h"
static void preempt_fence_work_func(struct work_struct *w)
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index 435cc30d88c9..a9ed29d06cc1 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -2,6 +2,7 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_pt.h"
#include <drm/drm_pt_walk.h>
@@ -10,12 +11,11 @@
#include "xe_gt.h"
#include "xe_gt_tlb_invalidation.h"
#include "xe_migrate.h"
-#include "xe_pt.h"
#include "xe_pt_types.h"
-#include "xe_vm.h"
#include "xe_res_cursor.h"
#include "xe_trace.h"
#include "xe_ttm_stolen_mgr.h"
+#include "xe_vm.h"
struct xe_pt_dir {
struct xe_pt pt;
diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
index 6e904e97f456..8f241f5625be 100644
--- a/drivers/gpu/drm/xe/xe_query.c
+++ b/drivers/gpu/drm/xe/xe_query.c
@@ -2,18 +2,19 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_query.h"
-#include <drm/xe_drm.h>
-#include <drm/ttm/ttm_placement.h>
#include <linux/nospec.h>
+#include <drm/ttm/ttm_placement.h>
+#include <drm/xe_drm.h>
+
#include "xe_bo.h"
#include "xe_device.h"
-#include "xe_gt.h"
-#include "xe_macros.h"
-#include "xe_query.h"
#include "xe_ggtt.h"
+#include "xe_gt.h"
#include "xe_guc_hwconfig.h"
+#include "xe_macros.h"
static const enum xe_engine_class xe_to_user_engine_class[] = {
[XE_ENGINE_CLASS_RENDER] = DRM_XE_ENGINE_CLASS_RENDER,
diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
index f7eceb84e647..dc96d0e48688 100644
--- a/drivers/gpu/drm/xe/xe_reg_sr.c
+++ b/drivers/gpu/drm/xe/xe_reg_sr.c
@@ -2,23 +2,22 @@
/*
* Copyright © 2022 Intel Corporation
*/
-
#include "xe_reg_sr.h"
#include <linux/align.h>
#include <linux/string_helpers.h>
#include <linux/xarray.h>
-#include <drm/drm_print.h>
#include <drm/drm_managed.h>
+#include <drm/drm_print.h>
-#include "xe_rtp_types.h"
#include "xe_device_types.h"
#include "xe_force_wake.h"
#include "xe_gt.h"
#include "xe_gt_mcr.h"
#include "xe_macros.h"
#include "xe_mmio.h"
+#include "xe_rtp_types.h"
#include "gt/intel_engine_regs.h"
#include "gt/intel_gt_regs.h"
diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index a34617a642ec..3951460307e2 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -2,15 +2,14 @@
/*
* Copyright © 2023 Intel Corporation
*/
-
#include "xe_reg_whitelist.h"
-#include "xe_platform_types.h"
#include "xe_gt_types.h"
+#include "xe_platform_types.h"
#include "xe_rtp.h"
-#include "../i915/gt/intel_engine_regs.h"
-#include "../i915/gt/intel_gt_regs.h"
+#include "gt/intel_engine_regs.h"
+#include "gt/intel_gt_regs.h"
#undef _MMIO
#undef MCR_REG
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index 370ab1e729fa..5049367bc92d 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -2,19 +2,19 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_ring_ops.h"
#include "xe_engine_types.h"
#include "xe_gt.h"
#include "xe_lrc.h"
#include "xe_macros.h"
-#include "xe_ring_ops.h"
#include "xe_sched_job.h"
#include "xe_vm_types.h"
-#include "i915_reg.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_gt_regs.h"
#include "gt/intel_lrc_reg.h"
+#include "i915_reg.h"
static u32 preparser_disable(bool state)
{
diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
index 5b1316b588d8..f2b8a7d46ebc 100644
--- a/drivers/gpu/drm/xe/xe_rtp.c
+++ b/drivers/gpu/drm/xe/xe_rtp.c
@@ -2,7 +2,6 @@
/*
* Copyright © 2022 Intel Corporation
*/
-
#include "xe_rtp.h"
#include <drm/xe_drm.h>
diff --git a/drivers/gpu/drm/xe/xe_sa.c b/drivers/gpu/drm/xe/xe_sa.c
index e432f40b9bfe..b4f76c1caec0 100644
--- a/drivers/gpu/drm/xe/xe_sa.c
+++ b/drivers/gpu/drm/xe/xe_sa.c
@@ -2,15 +2,16 @@
/*
* Copyright © 2022 Intel Corporation
*/
+#include "xe_sa.h"
#include <linux/kernel.h>
+
#include <drm/drm_managed.h>
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_gt.h"
#include "xe_map.h"
-#include "xe_sa.h"
static void xe_sa_bo_manager_fini(struct drm_device *drm, void *arg)
{
diff --git a/drivers/gpu/drm/xe/xe_sched_job.c b/drivers/gpu/drm/xe/xe_sched_job.c
index 2985caa6097b..630d67a3d574 100644
--- a/drivers/gpu/drm/xe/xe_sched_job.c
+++ b/drivers/gpu/drm/xe/xe_sched_job.c
@@ -2,7 +2,6 @@
/*
* Copyright © 2021 Intel Corporation
*/
-
#include "xe_sched_job.h"
#include <linux/dma-fence-array.h>
diff --git a/drivers/gpu/drm/xe/xe_sync.c b/drivers/gpu/drm/xe/xe_sync.c
index 0fbd8d0978cf..99f1ed87196d 100644
--- a/drivers/gpu/drm/xe/xe_sync.c
+++ b/drivers/gpu/drm/xe/xe_sync.c
@@ -8,13 +8,14 @@
#include <linux/kthread.h>
#include <linux/sched/mm.h>
#include <linux/uaccess.h>
-#include <drm/xe_drm.h>
+
#include <drm/drm_print.h>
#include <drm/drm_syncobj.h>
+#include <drm/xe_drm.h>
#include "xe_device_types.h"
-#include "xe_sched_job_types.h"
#include "xe_macros.h"
+#include "xe_sched_job_types.h"
#define SYNC_FLAGS_TYPE_MASK 0x3
#define SYNC_FLAGS_FENCE_INSTALLED 0x10000
diff --git a/drivers/gpu/drm/xe/xe_ttm_gtt_mgr.c b/drivers/gpu/drm/xe/xe_ttm_gtt_mgr.c
index a0ba8bba84d1..8075781070f2 100644
--- a/drivers/gpu/drm/xe/xe_ttm_gtt_mgr.c
+++ b/drivers/gpu/drm/xe/xe_ttm_gtt_mgr.c
@@ -6,8 +6,8 @@
#include <drm/drm_managed.h>
-#include <drm/ttm/ttm_range_manager.h>
#include <drm/ttm/ttm_placement.h>
+#include <drm/ttm/ttm_range_manager.h>
#include <drm/ttm/ttm_tt.h>
#include "xe_bo.h"
diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
index b4e9c88644e4..1c3783becefd 100644
--- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
+++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
@@ -8,8 +8,8 @@
#include <drm/drm_mm.h>
#include <drm/ttm/ttm_device.h>
-#include <drm/ttm/ttm_range_manager.h>
#include <drm/ttm/ttm_placement.h>
+#include <drm/ttm/ttm_range_manager.h>
#include "../i915/i915_reg.h"
diff --git a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c
index c7e21673b8fd..643365b18bc7 100644
--- a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c
+++ b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c
@@ -6,8 +6,8 @@
#include <drm/drm_managed.h>
-#include <drm/ttm/ttm_range_manager.h>
#include <drm/ttm/ttm_placement.h>
+#include <drm/ttm/ttm_range_manager.h>
#include "xe_bo.h"
#include "xe_device.h"
diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index 3cc32e3e7a90..5f8c56baaeba 100644
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -5,8 +5,8 @@
#include "xe_tuning.h"
-#include "xe_platform_types.h"
#include "xe_gt_types.h"
+#include "xe_platform_types.h"
#include "xe_rtp.h"
#include "gt/intel_gt_regs.h"
diff --git a/drivers/gpu/drm/xe/xe_uc.c b/drivers/gpu/drm/xe/xe_uc.c
index 7886c8b85397..a27e6c1a6aff 100644
--- a/drivers/gpu/drm/xe/xe_uc.c
+++ b/drivers/gpu/drm/xe/xe_uc.c
@@ -3,13 +3,13 @@
* Copyright © 2022 Intel Corporation
*/
+#include "xe_uc.h"
#include "xe_device.h"
-#include "xe_huc.h"
#include "xe_gt.h"
#include "xe_guc.h"
#include "xe_guc_pc.h"
#include "xe_guc_submit.h"
-#include "xe_uc.h"
+#include "xe_huc.h"
#include "xe_uc_fw.h"
#include "xe_wopcm.h"
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 7276a375e2e0..a0e35627e45e 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -25,8 +25,8 @@
#include "xe_preempt_fence.h"
#include "xe_pt.h"
#include "xe_res_cursor.h"
-#include "xe_trace.h"
#include "xe_sync.h"
+#include "xe_trace.h"
#define TEST_VM_ASYNC_OPS_ERROR
diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c
index 1e4e3a1b0631..29815852985a 100644
--- a/drivers/gpu/drm/xe/xe_vm_madvise.c
+++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
@@ -3,13 +3,15 @@
* Copyright © 2021 Intel Corporation
*/
-#include <drm/xe_drm.h>
-#include <drm/ttm/ttm_tt.h>
+#include "xe_vm_madvise.h"
+
#include <linux/nospec.h>
+#include <drm/ttm/ttm_tt.h>
+#include <drm/xe_drm.h>
+
#include "xe_bo.h"
#include "xe_vm.h"
-#include "xe_vm_madvise.h"
static int madvise_preferred_mem_class(struct xe_device *xe, struct xe_vm *vm,
struct xe_vma **vmas, int num_vmas,
diff --git a/drivers/gpu/drm/xe/xe_wopcm.c b/drivers/gpu/drm/xe/xe_wopcm.c
index 8fe182afa06c..e9ac560be57f 100644
--- a/drivers/gpu/drm/xe/xe_wopcm.c
+++ b/drivers/gpu/drm/xe/xe_wopcm.c
@@ -3,13 +3,13 @@
* Copyright © 2022 Intel Corporation
*/
+#include "xe_wopcm.h"
#include "xe_device.h"
#include "xe_force_wake.h"
#include "xe_gt.h"
#include "xe_guc_reg.h"
#include "xe_mmio.h"
#include "xe_uc_fw.h"
-#include "xe_wopcm.h"
/**
* DOC: Write Once Protected Content Memory (WOPCM) Layout
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-xe] [PATCH v2 03/11] drm/xe/guc: Remove i915_regs.h include
2023-02-17 0:52 [Intel-xe] [PATCH v2 00/11] Start register cleanup Lucas De Marchi
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 01/11] drm/xe: Remove outdated build workaround Lucas De Marchi
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 02/11] drm/xe: Sort includes Lucas De Marchi
@ 2023-02-17 0:52 ` Lucas De Marchi
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 04/11] drm/xe: Remove dependency on intel_engine_regs.h Lucas De Marchi
` (8 subsequent siblings)
11 siblings, 0 replies; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-17 0:52 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Maarten Lankhorst, Matthew Auld
i915_regs.h is not needed, particularly in a header file. What is needed
is i915_reg_defs.h for use of _MMIO() and similar macros.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/xe/xe_guc_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_guc_reg.h b/drivers/gpu/drm/xe/xe_guc_reg.h
index 1e16a9b76ddc..513a7e0c8a5a 100644
--- a/drivers/gpu/drm/xe/xe_guc_reg.h
+++ b/drivers/gpu/drm/xe/xe_guc_reg.h
@@ -9,7 +9,7 @@
#include <linux/compiler.h>
#include <linux/types.h>
-#include "i915_reg.h"
+#include "i915_reg_defs.h"
/* Definitions of GuC H/W registers, bits, etc */
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-xe] [PATCH v2 04/11] drm/xe: Remove dependency on intel_engine_regs.h
2023-02-17 0:52 [Intel-xe] [PATCH v2 00/11] Start register cleanup Lucas De Marchi
` (2 preceding siblings ...)
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 03/11] drm/xe/guc: Remove i915_regs.h include Lucas De Marchi
@ 2023-02-17 0:52 ` Lucas De Marchi
2023-02-24 18:02 ` Matt Roper
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 05/11] drm/xe: Remove dependency on intel_gt_regs.h Lucas De Marchi
` (7 subsequent siblings)
11 siblings, 1 reply; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-17 0:52 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Maarten Lankhorst, Matthew Auld
Create regs/xe_engine_regs.h file with all the registers and bit
definitions used by the xe driver. Eventually the registers may be
defined in a different way and since xe doesn't supported below gen12,
the number of registers touched is much smaller, so create a new header.
The definitions themselves are direct copy from the
gt/intel_engine_regs.h file, just sorting the registers by address.
Cleaning those up and adhering to a common coding style is left for
later.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/regs/xe_engine_regs.h | 98 ++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_execlist.c | 2 +-
drivers/gpu/drm/xe/xe_guc_ads.c | 5 +-
drivers/gpu/drm/xe/xe_hw_engine.c | 2 +-
drivers/gpu/drm/xe/xe_lrc.c | 2 +-
drivers/gpu/drm/xe/xe_mmio.c | 2 +-
drivers/gpu/drm/xe/xe_reg_sr.c | 2 +-
drivers/gpu/drm/xe/xe_reg_whitelist.c | 2 +-
drivers/gpu/drm/xe/xe_wa.c | 2 +-
9 files changed, 109 insertions(+), 8 deletions(-)
create mode 100644 drivers/gpu/drm/xe/regs/xe_engine_regs.h
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
new file mode 100644
index 000000000000..6dfa3cf2fd43
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _XE_ENGINE_REGS_H_
+#define _XE_ENGINE_REGS_H_
+
+#include <asm/page.h>
+
+#include "i915_reg_defs.h"
+
+#define RING_TAIL(base) _MMIO((base) + 0x30)
+
+#define RING_HEAD(base) _MMIO((base) + 0x34)
+#define HEAD_ADDR 0x001FFFFC
+
+#define RING_START(base) _MMIO((base) + 0x38)
+
+#define RING_CTL(base) _MMIO((base) + 0x3c)
+#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
+#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
+
+#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
+#define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
+#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
+
+#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
+#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60)
+#define RING_IPEIR(base) _MMIO((base) + 0x64)
+#define RING_IPEHR(base) _MMIO((base) + 0x68)
+#define RING_ACTHD(base) _MMIO((base) + 0x74)
+#define RING_DMA_FADD(base) _MMIO((base) + 0x78)
+#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
+#define IPEIR(base) _MMIO((base) + 0x88)
+#define IPEHR(base) _MMIO((base) + 0x8c)
+#define RING_HWSTAM(base) _MMIO((base) + 0x98)
+#define RING_MI_MODE(base) _MMIO((base) + 0x9c)
+#define RING_NOPID(base) _MMIO((base) + 0x94)
+
+#define RING_IMR(base) _MMIO((base) + 0xa8)
+#define RING_MAX_NONPRIV_SLOTS 12
+
+#define RING_EIR(base) _MMIO((base) + 0xb0)
+#define RING_EMR(base) _MMIO((base) + 0xb4)
+#define RING_ESR(base) _MMIO((base) + 0xb8)
+#define RING_BBADDR(base) _MMIO((base) + 0x140)
+#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168)
+#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
+#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
+
+#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
+#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
+#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
+
+#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
+#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
+
+#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
+
+#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
+#define RING_VALID_MASK 0x00000001
+#define RING_VALID 0x00000001
+#define STOP_RING REG_BIT(8)
+#define TAIL_ADDR 0x001FFFF8
+
+#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8)
+
+#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4d0) + (i) * 4)
+#define RING_FORCE_TO_NONPRIV_DENY REG_BIT(30)
+#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
+#define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28)
+#define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
+#define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
+#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
+#define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
+#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0)
+#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
+#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
+#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
+#define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
+#define RING_FORCE_TO_NONPRIV_MASK_VALID (RING_FORCE_TO_NONPRIV_RANGE_MASK | \
+ RING_FORCE_TO_NONPRIV_ACCESS_MASK | \
+ RING_FORCE_TO_NONPRIV_DENY)
+#define RING_MAX_NONPRIV_SLOTS 12
+
+#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
+
+#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
+#define EL_CTRL_LOAD REG_BIT(0)
+
+#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10)
+#define IECPUNIT_CLKGATE_DIS REG_BIT(22)
+
+#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18)
+#define ALNUNIT_CLKGATE_DIS REG_BIT(13)
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
index 5633259482ed..af2fcf1c32f4 100644
--- a/drivers/gpu/drm/xe/xe_execlist.c
+++ b/drivers/gpu/drm/xe/xe_execlist.c
@@ -6,6 +6,7 @@
#include <drm/drm_managed.h>
+#include "regs/xe_engine_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_engine.h"
@@ -18,7 +19,6 @@
#include "xe_ring_ops_types.h"
#include "xe_sched_job.h"
-#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_gt_regs.h"
#include "gt/intel_lrc_reg.h"
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 1ea1b25e7170..bde094388a34 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -4,8 +4,11 @@
*/
#include "xe_guc_ads.h"
+#include "xe_guc_ads.h"
+
#include <drm/drm_managed.h>
+#include "regs/xe_engine_regs.h"
#include "xe_bo.h"
#include "xe_gt.h"
#include "xe_guc.h"
@@ -16,9 +19,9 @@
#include "xe_mmio.h"
#include "xe_platform_types.h"
-#include "gt/intel_engine_regs.h"
#include "gt/intel_gt_regs.h"
+
/* Slack of a few additional entries per engine */
#define ADS_REGSET_EXTRA_MAX 8
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index edc59d9b124f..ce5d6641499f 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -6,6 +6,7 @@
#include <drm/drm_managed.h>
+#include "regs/xe_engine_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_execlist.h"
@@ -20,7 +21,6 @@
#include "xe_sched_job.h"
#include "xe_wa.h"
-#include "gt/intel_engine_regs.h"
#include "gt/intel_gt_regs.h"
#include "i915_reg.h"
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 45503c39240a..60ffe3f80c59 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -4,6 +4,7 @@
*/
#include "xe_lrc.h"
+#include "regs/xe_engine_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_engine_types.h"
@@ -12,7 +13,6 @@
#include "xe_map.h"
#include "xe_vm.h"
-#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_gt_regs.h"
#include "gt/intel_lrc_reg.h"
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 57788afe206e..892008dcbaf4 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -7,13 +7,13 @@
#include <drm/drm_managed.h>
#include <drm/xe_drm.h>
+#include "regs/xe_engine_regs.h"
#include "xe_device.h"
#include "xe_gt.h"
#include "xe_gt_mcr.h"
#include "xe_macros.h"
#include "xe_module.h"
-#include "gt/intel_engine_regs.h"
#include "gt/intel_gt_regs.h"
#include "i915_reg.h"
diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
index dc96d0e48688..bd3b64ad9c26 100644
--- a/drivers/gpu/drm/xe/xe_reg_sr.c
+++ b/drivers/gpu/drm/xe/xe_reg_sr.c
@@ -11,6 +11,7 @@
#include <drm/drm_managed.h>
#include <drm/drm_print.h>
+#include "regs/xe_engine_regs.h"
#include "xe_device_types.h"
#include "xe_force_wake.h"
#include "xe_gt.h"
@@ -19,7 +20,6 @@
#include "xe_mmio.h"
#include "xe_rtp_types.h"
-#include "gt/intel_engine_regs.h"
#include "gt/intel_gt_regs.h"
#define XE_REG_SR_GROW_STEP_DEFAULT 16
diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index 3951460307e2..e2f3f374b856 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -4,11 +4,11 @@
*/
#include "xe_reg_whitelist.h"
+#include "regs/xe_engine_regs.h"
#include "xe_gt_types.h"
#include "xe_platform_types.h"
#include "xe_rtp.h"
-#include "gt/intel_engine_regs.h"
#include "gt/intel_gt_regs.h"
#undef _MMIO
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 9d2e4555091c..92065341c001 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -7,6 +7,7 @@
#include <linux/compiler_types.h>
+#include "regs/xe_engine_regs.h"
#include "xe_device_types.h"
#include "xe_force_wake.h"
#include "xe_gt.h"
@@ -16,7 +17,6 @@
#include "xe_rtp.h"
#include "xe_step.h"
-#include "gt/intel_engine_regs.h"
#include "gt/intel_gt_regs.h"
#include "i915_reg.h"
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-xe] [PATCH v2 05/11] drm/xe: Remove dependency on intel_gt_regs.h
2023-02-17 0:52 [Intel-xe] [PATCH v2 00/11] Start register cleanup Lucas De Marchi
` (3 preceding siblings ...)
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 04/11] drm/xe: Remove dependency on intel_engine_regs.h Lucas De Marchi
@ 2023-02-17 0:52 ` Lucas De Marchi
2023-02-17 20:20 ` Rodrigo Vivi
2023-02-24 18:06 ` Matt Roper
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 06/11] drm/xe: Remove dependency on intel_lrc_reg.h Lucas De Marchi
` (6 subsequent siblings)
11 siblings, 2 replies; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-17 0:52 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Maarten Lankhorst, Matthew Auld
Create regs/xe_gt_regs.h file with all the registers and bit
definitions used by the xe driver. Eventually the registers may be
defined in a different way and since xe doesn't supported below gen12,
the number of registers touched is much smaller, so create a new header.
The definitions themselves are direct copy from the
gt/intel_gt_regs.h file, just sorting the registers by address.
Cleaning those up and adhering to a common coding style is left for
later.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_reg_defs.h | 2 +
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 287 ++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_execlist.c | 2 +-
drivers/gpu/drm/xe/xe_force_wake.c | 3 +-
drivers/gpu/drm/xe/xe_ggtt.c | 2 +-
drivers/gpu/drm/xe/xe_gt.c | 3 +-
drivers/gpu/drm/xe/xe_gt_clock.c | 2 +-
drivers/gpu/drm/xe/xe_gt_mcr.c | 3 +-
drivers/gpu/drm/xe/xe_guc.c | 2 +-
drivers/gpu/drm/xe/xe_guc_ads.c | 4 +-
drivers/gpu/drm/xe/xe_guc_pc.c | 2 +-
drivers/gpu/drm/xe/xe_hw_engine.c | 2 +-
drivers/gpu/drm/xe/xe_irq.c | 2 +-
drivers/gpu/drm/xe/xe_lrc.c | 2 +-
drivers/gpu/drm/xe/xe_mmio.c | 2 +-
drivers/gpu/drm/xe/xe_mocs.c | 3 +-
drivers/gpu/drm/xe/xe_reg_sr.c | 3 +-
drivers/gpu/drm/xe/xe_reg_whitelist.c | 3 +-
drivers/gpu/drm/xe/xe_ring_ops.c | 2 +-
drivers/gpu/drm/xe/xe_tuning.c | 3 +-
drivers/gpu/drm/xe/xe_wa.c | 2 +-
21 files changed, 308 insertions(+), 28 deletions(-)
create mode 100644 drivers/gpu/drm/xe/regs/xe_gt_regs.h
diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
index b5e06b6a9478..a6080c983a77 100644
--- a/drivers/gpu/drm/i915/i915_reg_defs.h
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -136,6 +136,8 @@ typedef struct {
u32 reg;
} i915_mcr_reg_t;
+#define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg = (offset) })
+
#define INVALID_MMIO_REG _MMIO(0)
/*
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
new file mode 100644
index 000000000000..da40133252fb
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -0,0 +1,287 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _XE_GT_REGS_H_
+#define _XE_GT_REGS_H_
+
+#include "i915_reg_defs.h"
+
+/* RPM unit config (Gen8+) */
+#define RPM_CONFIG0 _MMIO(0xd00)
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
+#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
+#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
+
+#define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0xd50 + (n) * 4)
+#define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0xd70 + (n) * 4)
+#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84)
+
+#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
+#define LNCFCMOCS_REG_COUNT 32
+
+#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
+#define MTL_MCR_SELECTOR _MMIO(0xfd4)
+#define SF_MCR_SELECTOR _MMIO(0xfd8)
+#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
+#define GAM_MCR_SELECTOR _MMIO(0xfe0)
+#define GEN11_MCR_MULTICAST REG_BIT(31)
+#define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27)
+#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
+#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
+#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
+#define MTL_MCR_GROUPID REG_GENMASK(11, 8)
+#define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
+
+#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
+#define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
+
+#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
+#define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
+
+#define PS_INVOCATION_COUNT _MMIO(0x2348)
+
+#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
+#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
+#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
+#define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
+#define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
+#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
+#define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
+
+#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
+#define GEN12_GFX_CCS_AUX_NV _MMIO(0x4208)
+
+#define GEN12_VD0_AUX_NV _MMIO(0x4218)
+#define GEN12_VE0_AUX_NV _MMIO(0x4238)
+
+#define GEN12_VE1_AUX_NV _MMIO(0x42b8)
+#define AUX_INV REG_BIT(0)
+
+#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
+#define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900)
+#define XEHP_FLAT_CCS_BASE_ADDR MCR_REG(0x4910)
+
+#define GEN12_FF_MODE2 _MMIO(0x6604)
+#define XEHP_FF_MODE2 MCR_REG(0x6604)
+#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
+#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
+#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
+#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
+
+#define HIZ_CHICKEN _MMIO(0x7018)
+#define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14)
+
+/* GEN7 chicken */
+#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
+
+#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
+#define XEHP_COMMON_SLICE_CHICKEN3 MCR_REG(0x7304)
+#define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
+#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
+#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
+#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
+
+#define XEHP_SQCM MCR_REG(0x8724)
+#define EN_32B_ACCESS REG_BIT(30)
+
+#define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
+#define GEN10_L3BANK_PAIR_COUNT 4
+#define GEN10_L3BANK_MASK 0x0F
+/* on Xe_HP the same fuses indicates mslices instead of L3 banks */
+#define GEN12_MAX_MSLICES 4
+#define GEN12_MEML3_EN_MASK 0x0F
+
+/* Fuse readout registers for GT */
+#define XEHP_FUSE4 _MMIO(0x9114)
+#define GT_L3_EXC_MASK REG_GENMASK(6, 4)
+
+#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
+#define GEN11_GT_VDBOX_DISABLE_MASK 0xff
+#define GEN11_GT_VEBOX_DISABLE_SHIFT 16
+#define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
+
+#define GEN6_GDRST _MMIO(0x941c)
+#define GEN11_GRDOM_GUC REG_BIT(3)
+#define GEN6_GRDOM_FULL (1 << 0)
+#define GEN11_GRDOM_FULL GEN6_GRDOM_FULL
+
+#define GEN7_MISCCPCTL _MMIO(0x9424)
+#define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
+#define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1)
+
+#define UNSLCGCTL9430 _MMIO(0x9430)
+#define MSQDUNIT_CLKGATE_DIS REG_BIT(3)
+
+#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
+#define VFUNIT_CLKGATE_DIS REG_BIT(20)
+#define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */
+#define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */
+#define GAMEDIA_CLKGATE_DIS REG_BIT(11)
+#define HSUNIT_CLKGATE_DIS REG_BIT(8)
+#define VSUNIT_CLKGATE_DIS REG_BIT(3)
+
+#define UNSLCGCTL9440 _MMIO(0x9440)
+#define GAMTLBOACS_CLKGATE_DIS REG_BIT(28)
+#define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27)
+#define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26)
+#define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24)
+#define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23)
+#define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22)
+#define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21)
+#define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17)
+#define GAMTLBKCR_CLKGATE_DIS REG_BIT(16)
+#define GAMTLBGUC_CLKGATE_DIS REG_BIT(15)
+#define GAMTLBBLT_CLKGATE_DIS REG_BIT(14)
+#define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6)
+
+#define UNSLCGCTL9444 _MMIO(0x9444)
+#define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30)
+#define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29)
+#define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28)
+#define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27)
+#define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26)
+#define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25)
+#define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24)
+#define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23)
+#define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22)
+#define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21)
+#define GAMTLBMERT_CLKGATE_DIS REG_BIT(20)
+#define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19)
+#define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18)
+#define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17)
+#define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
+#define LTCDD_CLKGATE_DIS REG_BIT(10)
+
+#define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
+#define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4)
+#define SARBUNIT_CLKGATE_DIS (1 << 5)
+#define RCCUNIT_CLKGATE_DIS (1 << 7)
+#define MSCUNIT_CLKGATE_DIS (1 << 10)
+#define NODEDSS_CLKGATE_DIS REG_BIT(12)
+#define L3_CLKGATE_DIS REG_BIT(16)
+#define L3_CR2X_CLKGATE_DIS REG_BIT(17)
+
+#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
+#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
+#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
+
+#define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x9524)
+#define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
+#define GWUNIT_CLKGATE_DIS REG_BIT(16)
+
+#define SUBSLICE_UNIT_LEVEL_CLKGATE2 MCR_REG(0x9528)
+#define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
+
+#define SSMCGCTL9530 MCR_REG(0x9530)
+#define RTFUNIT_CLKGATE_DIS REG_BIT(18)
+
+#define GEN10_DFR_RATIO_EN_AND_CHICKEN MCR_REG(0x9550)
+#define DFR_DISABLE (1 << 9)
+
+#define GEN6_RPNSWREQ _MMIO(0xa008)
+#define GEN6_RC_CONTROL _MMIO(0xa090)
+#define GEN6_RC_STATE _MMIO(0xa094)
+
+#define GEN6_PMINTRMSK _MMIO(0xa168)
+#define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31)
+#define ARAT_EXPIRED_INTRMSK (1 << 9)
+
+#define FORCEWAKE_GT_GEN9 _MMIO(0xa188)
+
+#define GEN9_PG_ENABLE _MMIO(0xa210)
+
+/* GPM unit config (Gen9+) */
+#define CTC_MODE _MMIO(0xa26c)
+#define CTC_SOURCE_PARAMETER_MASK 1
+#define CTC_SOURCE_CRYSTAL_CLOCK 0
+#define CTC_SOURCE_DIVIDE_LOGIC 1
+#define CTC_SHIFT_PARAMETER_SHIFT 1
+#define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
+
+#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
+#define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4)
+#define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4)
+
+#define GEN10_SAMPLER_MODE MCR_REG(0xe18c)
+#define ENABLE_SMALLPL REG_BIT(15)
+#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
+#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
+
+#define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c)
+#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
+#define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
+#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
+#define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
+#define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4)
+#define THREAD_EX_ARB_MODE REG_GENMASK(3, 2)
+#define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
+
+#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
+#define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
+#define GEN12_DISABLE_EARLY_READ REG_BIT(14)
+#define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
+#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
+#define GEN12_DISABLE_DOP_GATING REG_BIT(0)
+
+#define SARB_CHICKEN1 MCR_REG(0xe90c)
+#define COMP_CKN_IN REG_GENMASK(30, 29)
+
+#define GEN12_RCU_MODE _MMIO(0x14800)
+#define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0)
+
+#define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044)
+#define FORCEWAKE_KERNEL BIT(0)
+#define FORCEWAKE_USER BIT(1)
+#define FORCEWAKE_KERNEL_FALLBACK BIT(15)
+
+#define GEN6_GT_CORE_STATUS _MMIO(0x138060)
+#define GEN6_RC0 0
+#define GEN6_RC6 3
+
+#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
+#define GEN6_GT_GFX_RC6 _MMIO(0x138108)
+
+#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
+#define GFX_FLSH_CNTL_EN (1 << 0)
+
+#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
+
+#define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)
+#define ENGINE1_MASK REG_GENMASK(31, 16)
+#define ENGINE0_MASK REG_GENMASK(15, 0)
+
+#define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
+
+#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
+#define GEN11_INTR_DATA_VALID (1 << 31)
+#define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
+#define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)
+#define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff)
+#define OTHER_GUC_INSTANCE 0
+
+#define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
+#define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
+#define GEN12_CCS_RSVD_INTR_ENABLE _MMIO(0x190048)
+#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
+#define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
+#define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
+#define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
+#define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
+#define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
+#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
+#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
+#define GEN12_CCS0_CCS1_INTR_MASK _MMIO(0x190100)
+#define GEN12_CCS2_CCS3_INTR_MASK _MMIO(0x190104)
+#define XEHPC_BCS1_BCS2_INTR_MASK _MMIO(0x190110)
+#define XEHPC_BCS3_BCS4_INTR_MASK _MMIO(0x190114)
+#define XEHPC_BCS5_BCS6_INTR_MASK _MMIO(0x190118)
+#define XEHPC_BCS7_BCS8_INTR_MASK _MMIO(0x19011c)
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
index af2fcf1c32f4..b426f8000070 100644
--- a/drivers/gpu/drm/xe/xe_execlist.c
+++ b/drivers/gpu/drm/xe/xe_execlist.c
@@ -7,6 +7,7 @@
#include <drm/drm_managed.h>
#include "regs/xe_engine_regs.h"
+#include "regs/xe_gt_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_engine.h"
@@ -20,7 +21,6 @@
#include "xe_sched_job.h"
#include "gt/intel_gpu_commands.h"
-#include "gt/intel_gt_regs.h"
#include "gt/intel_lrc_reg.h"
#include "i915_reg.h"
diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c
index 188197c3a8fe..e1346d18b580 100644
--- a/drivers/gpu/drm/xe/xe_force_wake.c
+++ b/drivers/gpu/drm/xe/xe_force_wake.c
@@ -6,11 +6,10 @@
#include <drm/drm_util.h>
+#include "regs/xe_gt_regs.h"
#include "xe_gt.h"
#include "xe_mmio.h"
-#include "gt/intel_gt_regs.h"
-
#define XE_FORCE_WAKE_ACK_TIMEOUT_MS 50
static struct xe_gt *
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 53a1edaee02d..2c9b2175c5bb 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -9,6 +9,7 @@
#include <drm/drm_managed.h>
#include <drm/i915_drm.h>
+#include "regs/xe_gt_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_gt.h"
@@ -17,7 +18,6 @@
#include "xe_mmio.h"
#include "xe_wopcm.h"
-#include "gt/intel_gt_regs.h"
#include "i915_reg.h"
/* FIXME: Common file, preferably auto-gen */
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 5c7c2757bb49..c195b4b9f9b8 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -8,6 +8,7 @@
#include <drm/drm_managed.h>
+#include "regs/xe_gt_regs.h"
#include "xe_bb.h"
#include "xe_bo.h"
#include "xe_device.h"
@@ -40,8 +41,6 @@
#include "xe_wa.h"
#include "xe_wopcm.h"
-#include "gt/intel_gt_regs.h"
-
struct xe_gt *xe_find_full_gt(struct xe_gt *gt)
{
struct xe_gt *search;
diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
index e50117103e1e..e9aa7c5452af 100644
--- a/drivers/gpu/drm/xe/xe_gt_clock.c
+++ b/drivers/gpu/drm/xe/xe_gt_clock.c
@@ -4,12 +4,12 @@
*/
#include "xe_gt_clock.h"
+#include "regs/xe_gt_regs.h"
#include "xe_device.h"
#include "xe_gt.h"
#include "xe_macros.h"
#include "xe_mmio.h"
-#include "gt/intel_gt_regs.h"
#include "i915_reg.h"
static u32 read_reference_ts_freq(struct xe_gt *gt)
diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index 43910e48bdc9..c4ede7d6d97c 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -4,13 +4,12 @@
*/
#include "xe_gt_mcr.h"
+#include "regs/xe_gt_regs.h"
#include "xe_gt.h"
#include "xe_gt_topology.h"
#include "xe_gt_types.h"
#include "xe_mmio.h"
-#include "gt/intel_gt_regs.h"
-
/**
* DOC: GT Multicast/Replicated (MCR) Register Support
*
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 88cc912fa7eb..a2a124a7fc0b 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -4,6 +4,7 @@
*/
#include "xe_guc.h"
+#include "regs/xe_gt_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_force_wake.h"
@@ -20,7 +21,6 @@
#include "xe_uc_fw.h"
#include "xe_wopcm.h"
-#include "gt/intel_gt_regs.h"
#include "i915_reg_defs.h"
/* TODO: move to common file */
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index bde094388a34..3cf04594f12f 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -9,6 +9,7 @@
#include <drm/drm_managed.h>
#include "regs/xe_engine_regs.h"
+#include "regs/xe_gt_regs.h"
#include "xe_bo.h"
#include "xe_gt.h"
#include "xe_guc.h"
@@ -19,9 +20,6 @@
#include "xe_mmio.h"
#include "xe_platform_types.h"
-#include "gt/intel_gt_regs.h"
-
-
/* Slack of a few additional entries per engine */
#define ADS_REGSET_EXTRA_MAX 8
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 1d4ac0c26d3c..f7aaf4826f00 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -8,6 +8,7 @@
#include <drm/drm_managed.h>
+#include "regs/xe_gt_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_gt.h"
@@ -30,7 +31,6 @@
#define GEN10_FREQ_INFO_REC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
#define RPE_MASK REG_GENMASK(15, 8)
-#include "gt/intel_gt_regs.h"
/* For GEN6_RPNSWREQ.reg to be merged when the definition moves to Xe */
#define REQ_RATIO_MASK REG_GENMASK(31, 23)
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index ce5d6641499f..caae4f897644 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -7,6 +7,7 @@
#include <drm/drm_managed.h>
#include "regs/xe_engine_regs.h"
+#include "regs/xe_gt_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_execlist.h"
@@ -21,7 +22,6 @@
#include "xe_sched_job.h"
#include "xe_wa.h"
-#include "gt/intel_gt_regs.h"
#include "i915_reg.h"
#define MAX_MMIO_BASES 3
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index f30fd2b14c22..d7756c14b4e2 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -8,6 +8,7 @@
#include <drm/drm_managed.h>
+#include "regs/xe_gt_regs.h"
#include "xe_device.h"
#include "xe_display.h"
#include "xe_drv.h"
@@ -16,7 +17,6 @@
#include "xe_hw_engine.h"
#include "xe_mmio.h"
-#include "gt/intel_gt_regs.h"
#include "i915_reg.h"
static void gen3_assert_iir_is_zero(struct xe_gt *gt, i915_reg_t reg)
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 60ffe3f80c59..8e341d11f2e3 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -5,6 +5,7 @@
#include "xe_lrc.h"
#include "regs/xe_engine_regs.h"
+#include "regs/xe_gt_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_engine_types.h"
@@ -14,7 +15,6 @@
#include "xe_vm.h"
#include "gt/intel_gpu_commands.h"
-#include "gt/intel_gt_regs.h"
#include "gt/intel_lrc_reg.h"
#include "i915_reg.h"
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 892008dcbaf4..d0cd9e920d34 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -8,13 +8,13 @@
#include <drm/xe_drm.h>
#include "regs/xe_engine_regs.h"
+#include "regs/xe_gt_regs.h"
#include "xe_device.h"
#include "xe_gt.h"
#include "xe_gt_mcr.h"
#include "xe_macros.h"
#include "xe_module.h"
-#include "gt/intel_gt_regs.h"
#include "i915_reg.h"
#define XEHP_MTCFG_ADDR _MMIO(0x101800)
diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
index 99d3cc6c7164..173f5c4321f5 100644
--- a/drivers/gpu/drm/xe/xe_mocs.c
+++ b/drivers/gpu/drm/xe/xe_mocs.c
@@ -4,6 +4,7 @@
*/
#include "xe_mocs.h"
+#include "regs/xe_gt_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_engine.h"
@@ -12,8 +13,6 @@
#include "xe_platform_types.h"
#include "xe_step_types.h"
-#include "gt/intel_gt_regs.h"
-
#if IS_ENABLED(CONFIG_DRM_XE_DEBUG)
#define mocs_dbg drm_dbg
#else
diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
index bd3b64ad9c26..6519c6648460 100644
--- a/drivers/gpu/drm/xe/xe_reg_sr.c
+++ b/drivers/gpu/drm/xe/xe_reg_sr.c
@@ -12,6 +12,7 @@
#include <drm/drm_print.h>
#include "regs/xe_engine_regs.h"
+#include "regs/xe_gt_regs.h"
#include "xe_device_types.h"
#include "xe_force_wake.h"
#include "xe_gt.h"
@@ -20,8 +21,6 @@
#include "xe_mmio.h"
#include "xe_rtp_types.h"
-#include "gt/intel_gt_regs.h"
-
#define XE_REG_SR_GROW_STEP_DEFAULT 16
static void reg_sr_fini(struct drm_device *drm, void *arg)
diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index e2f3f374b856..66ff9da46070 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -5,12 +5,11 @@
#include "xe_reg_whitelist.h"
#include "regs/xe_engine_regs.h"
+#include "regs/xe_gt_regs.h"
#include "xe_gt_types.h"
#include "xe_platform_types.h"
#include "xe_rtp.h"
-#include "gt/intel_gt_regs.h"
-
#undef _MMIO
#undef MCR_REG
#define _MMIO(x) _XE_RTP_REG(x)
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index 5049367bc92d..a7ab0d4451f0 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -4,6 +4,7 @@
*/
#include "xe_ring_ops.h"
+#include "regs/xe_gt_regs.h"
#include "xe_engine_types.h"
#include "xe_gt.h"
#include "xe_lrc.h"
@@ -12,7 +13,6 @@
#include "xe_vm_types.h"
#include "gt/intel_gpu_commands.h"
-#include "gt/intel_gt_regs.h"
#include "gt/intel_lrc_reg.h"
#include "i915_reg.h"
diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index 5f8c56baaeba..cda2da27f7c6 100644
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -5,12 +5,11 @@
#include "xe_tuning.h"
+#include "regs/xe_gt_regs.h"
#include "xe_gt_types.h"
#include "xe_platform_types.h"
#include "xe_rtp.h"
-#include "gt/intel_gt_regs.h"
-
#undef _MMIO
#undef MCR_REG
#define _MMIO(x) _XE_RTP_REG(x)
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 92065341c001..155cfd1dcc50 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -8,6 +8,7 @@
#include <linux/compiler_types.h>
#include "regs/xe_engine_regs.h"
+#include "regs/xe_gt_regs.h"
#include "xe_device_types.h"
#include "xe_force_wake.h"
#include "xe_gt.h"
@@ -17,7 +18,6 @@
#include "xe_rtp.h"
#include "xe_step.h"
-#include "gt/intel_gt_regs.h"
#include "i915_reg.h"
/**
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-xe] [PATCH v2 06/11] drm/xe: Remove dependency on intel_lrc_reg.h
2023-02-17 0:52 [Intel-xe] [PATCH v2 00/11] Start register cleanup Lucas De Marchi
` (4 preceding siblings ...)
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 05/11] drm/xe: Remove dependency on intel_gt_regs.h Lucas De Marchi
@ 2023-02-17 0:52 ` Lucas De Marchi
2023-02-24 18:20 ` Matt Roper
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 07/11] drm/xe: Remove dependency on intel_gpu_commands.h Lucas De Marchi
` (5 subsequent siblings)
11 siblings, 1 reply; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-17 0:52 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Maarten Lankhorst, Matthew Auld
Create regs/xe_lrc_regs.h file with all the registers used by the xe
driver. Eventually the registers may be defined in a different way and
since xe doesn't supported below gen12, the number of registers touched
is much smaller, so create a new header.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/regs/xe_lrc_regs.h | 17 +++++++++++++++++
drivers/gpu/drm/xe/xe_execlist.c | 2 +-
drivers/gpu/drm/xe/xe_guc_submit.c | 3 +--
drivers/gpu/drm/xe/xe_lrc.c | 2 +-
drivers/gpu/drm/xe/xe_ring_ops.c | 2 +-
5 files changed, 21 insertions(+), 5 deletions(-)
create mode 100644 drivers/gpu/drm/xe/regs/xe_lrc_regs.h
diff --git a/drivers/gpu/drm/xe/regs/xe_lrc_regs.h b/drivers/gpu/drm/xe/regs/xe_lrc_regs.h
new file mode 100644
index 000000000000..e8a13fa6722b
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_lrc_regs.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _XE_LRC_REGS_H_
+#define _XE_LRC_REGS_H_
+
+#define CTX_CONTEXT_CONTROL (0x02 + 1)
+#define CTX_RING_HEAD (0x04 + 1)
+#define CTX_RING_TAIL (0x06 + 1)
+#define CTX_RING_START (0x08 + 1)
+#define CTX_RING_CTL (0x0a + 1)
+#define CTX_PDP0_UDW (0x30 + 1)
+#define CTX_PDP0_LDW (0x32 + 1)
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
index b426f8000070..ea551dc922cc 100644
--- a/drivers/gpu/drm/xe/xe_execlist.c
+++ b/drivers/gpu/drm/xe/xe_execlist.c
@@ -7,6 +7,7 @@
#include <drm/drm_managed.h>
#include "regs/xe_engine_regs.h"
+#include "regs/xe_lrc_regs.h"
#include "regs/xe_gt_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
@@ -21,7 +22,6 @@
#include "xe_sched_job.h"
#include "gt/intel_gpu_commands.h"
-#include "gt/intel_lrc_reg.h"
#include "i915_reg.h"
#define XE_EXECLIST_HANG_LIMIT 1
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index 305a0e061778..451c9e1c43ff 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -12,6 +12,7 @@
#include <drm/drm_managed.h>
+#include "regs/xe_lrc_regs.h"
#include "xe_device.h"
#include "xe_engine.h"
#include "xe_force_wake.h"
@@ -30,8 +31,6 @@
#include "xe_trace.h"
#include "xe_vm.h"
-#include "gt/intel_lrc_reg.h"
-
static struct xe_gt *
guc_to_gt(struct xe_guc *guc)
{
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 8e341d11f2e3..af6fe47a0495 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -5,6 +5,7 @@
#include "xe_lrc.h"
#include "regs/xe_engine_regs.h"
+#include "regs/xe_lrc_regs.h"
#include "regs/xe_gt_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
@@ -15,7 +16,6 @@
#include "xe_vm.h"
#include "gt/intel_gpu_commands.h"
-#include "gt/intel_lrc_reg.h"
#include "i915_reg.h"
#define GEN8_CTX_VALID (1 << 0)
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index a7ab0d4451f0..0a1e32ab9758 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -4,6 +4,7 @@
*/
#include "xe_ring_ops.h"
+#include "regs/xe_lrc_regs.h"
#include "regs/xe_gt_regs.h"
#include "xe_engine_types.h"
#include "xe_gt.h"
@@ -13,7 +14,6 @@
#include "xe_vm_types.h"
#include "gt/intel_gpu_commands.h"
-#include "gt/intel_lrc_reg.h"
#include "i915_reg.h"
static u32 preparser_disable(bool state)
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-xe] [PATCH v2 07/11] drm/xe: Remove dependency on intel_gpu_commands.h
2023-02-17 0:52 [Intel-xe] [PATCH v2 00/11] Start register cleanup Lucas De Marchi
` (5 preceding siblings ...)
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 06/11] drm/xe: Remove dependency on intel_lrc_reg.h Lucas De Marchi
@ 2023-02-17 0:52 ` Lucas De Marchi
2023-02-24 18:26 ` Matt Roper
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 08/11] drm/xe: Remove dependency on i915_reg.h Lucas De Marchi
` (4 subsequent siblings)
11 siblings, 1 reply; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-17 0:52 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Maarten Lankhorst, Matthew Auld
Copy the macros used by xe in intel_gpu_commands.h to
regs/xe_gpu_commands.h.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gpu_commands.h | 96 +++++++++++++++++++++++
drivers/gpu/drm/xe/xe_bb.c | 3 +-
drivers/gpu/drm/xe/xe_device.h | 3 +-
drivers/gpu/drm/xe/xe_execlist.c | 2 +-
drivers/gpu/drm/xe/xe_lrc.c | 2 +-
drivers/gpu/drm/xe/xe_migrate.c | 3 +-
drivers/gpu/drm/xe/xe_ring_ops.c | 2 +-
7 files changed, 102 insertions(+), 9 deletions(-)
create mode 100644 drivers/gpu/drm/xe/regs/xe_gpu_commands.h
diff --git a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
new file mode 100644
index 000000000000..bf6dc1c8563d
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _XE_GPU_COMMANDS_H_
+#define _XE_GPU_COMMANDS_H_
+
+#define INSTR_CLIENT_SHIFT 29
+#define INSTR_MI_CLIENT 0x0
+#define __INSTR(client) ((client) << INSTR_CLIENT_SHIFT)
+
+#define MI_INSTR(opcode, flags) \
+ (__INSTR(INSTR_MI_CLIENT) | (opcode) << 23 | (flags))
+
+#define MI_NOOP MI_INSTR(0, 0)
+#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
+
+#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
+#define MI_ARB_ENABLE (1<<0)
+#define MI_ARB_DISABLE (0<<0)
+
+#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
+#define MI_STORE_DATA_IMM MI_INSTR(0x20, 0)
+
+#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
+#define MI_LRI_LRM_CS_MMIO REG_BIT(19)
+#define MI_LRI_MMIO_REMAP_EN REG_BIT(17)
+#define MI_LRI_FORCE_POSTED (1<<12)
+
+#define MI_FLUSH_DW MI_INSTR(0x26, 1)
+#define MI_FLUSH_DW_STORE_INDEX (1<<21)
+#define MI_INVALIDATE_TLB (1<<18)
+#define MI_FLUSH_DW_CCS (1<<16)
+#define MI_FLUSH_DW_OP_STOREDW (1<<14)
+#define MI_FLUSH_DW_USE_GTT (1<<2)
+
+#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
+
+#define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3)
+#define SRC_ACCESS_TYPE_SHIFT 21
+#define DST_ACCESS_TYPE_SHIFT 20
+#define CCS_SIZE_MASK 0x3FF
+#define CCS_SIZE_SHIFT 8
+#define XY_CTRL_SURF_MOCS_MASK GENMASK(31, 25)
+#define NUM_CCS_BYTES_PER_BLOCK 256
+#define NUM_BYTES_PER_CCS_BYTE 256
+#define NUM_CCS_BLKS_PER_XFER 1024
+
+#define XY_FAST_COLOR_BLT_CMD (2 << 29 | 0x44 << 22)
+#define XY_FAST_COLOR_BLT_DEPTH_32 (2 << 19)
+#define XY_FAST_COLOR_BLT_DW 16
+#define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21)
+#define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31
+
+#define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22)
+#define BLT_DEPTH_32 (3<<24)
+
+#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
+#define PIPE_CONTROL_TILE_CACHE_FLUSH (1<<28)
+#define PIPE_CONTROL_AMFS_FLUSH (1<<25)
+#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24)
+#define PIPE_CONTROL_CS_STALL (1<<20)
+#define PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET (1<<19)
+#define PIPE_CONTROL_PSD_SYNC (1<<17)
+#define PIPE_CONTROL_QW_WRITE (1<<14)
+#define PIPE_CONTROL_DEPTH_STALL (1<<13)
+#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12)
+#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10)
+#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
+#define PIPE_CONTROL_FLUSH_ENABLE (1<<7)
+#define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
+#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
+#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
+#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
+
+#define PIPE_CONTROL_3D_ENGINE_FLAGS (\
+ PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
+ PIPE_CONTROL_TILE_CACHE_FLUSH | \
+ PIPE_CONTROL_DEPTH_STALL | \
+ PIPE_CONTROL_STALL_AT_SCOREBOARD | \
+ PIPE_CONTROL_PSD_SYNC | \
+ PIPE_CONTROL_AMFS_FLUSH | \
+ PIPE_CONTROL_VF_CACHE_INVALIDATE | \
+ PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
+#define PIPE_CONTROL_3D_ARCH_FLAGS ( \
+ PIPE_CONTROL_3D_ENGINE_FLAGS | \
+ PIPE_CONTROL_INDIRECT_STATE_DISABLE | \
+ PIPE_CONTROL_FLUSH_ENABLE | \
+ PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
+ PIPE_CONTROL_DC_FLUSH_ENABLE)
+
+#define MI_ARB_CHECK MI_INSTR(0x05, 0)
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_bb.c b/drivers/gpu/drm/xe/xe_bb.c
index a25079d4e710..742d12023160 100644
--- a/drivers/gpu/drm/xe/xe_bb.c
+++ b/drivers/gpu/drm/xe/xe_bb.c
@@ -4,6 +4,7 @@
*/
#include "xe_bb.h"
+#include "regs/xe_gpu_commands.h"
#include "xe_device.h"
#include "xe_engine_types.h"
#include "xe_hw_fence.h"
@@ -11,8 +12,6 @@
#include "xe_sched_job.h"
#include "xe_vm_types.h"
-#include "gt/intel_gpu_commands.h"
-
struct xe_bb *xe_bb_new(struct xe_gt *gt, u32 dwords, bool usm)
{
struct xe_bb *bb = kmalloc(sizeof(*bb), GFP_KERNEL);
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index 88d55671b068..ee10b6c11e9f 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -11,12 +11,11 @@ struct xe_file;
#include <drm/drm_util.h>
+#include "regs/xe_gpu_commands.h"
#include "xe_device_types.h"
#include "xe_macros.h"
#include "xe_force_wake.h"
-#include "gt/intel_gpu_commands.h"
-
static inline struct xe_device *to_xe_device(const struct drm_device *dev)
{
return container_of(dev, struct xe_device, drm);
diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
index ea551dc922cc..c3c52bdc70b1 100644
--- a/drivers/gpu/drm/xe/xe_execlist.c
+++ b/drivers/gpu/drm/xe/xe_execlist.c
@@ -8,6 +8,7 @@
#include "regs/xe_engine_regs.h"
#include "regs/xe_lrc_regs.h"
+#include "regs/xe_gpu_commands.h"
#include "regs/xe_gt_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
@@ -21,7 +22,6 @@
#include "xe_ring_ops_types.h"
#include "xe_sched_job.h"
-#include "gt/intel_gpu_commands.h"
#include "i915_reg.h"
#define XE_EXECLIST_HANG_LIMIT 1
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index af6fe47a0495..c1df76c2cf78 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -6,6 +6,7 @@
#include "regs/xe_engine_regs.h"
#include "regs/xe_lrc_regs.h"
+#include "regs/xe_gpu_commands.h"
#include "regs/xe_gt_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
@@ -15,7 +16,6 @@
#include "xe_map.h"
#include "xe_vm.h"
-#include "gt/intel_gpu_commands.h"
#include "i915_reg.h"
#define GEN8_CTX_VALID (1 << 0)
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 3d2f8d04bc3a..3c2ed4d9f63d 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -10,6 +10,7 @@
#include <drm/ttm/ttm_tt.h>
#include <drm/xe_drm.h>
+#include "regs/xe_gpu_commands.h"
#include "xe_bb.h"
#include "xe_bo.h"
#include "xe_engine.h"
@@ -26,8 +27,6 @@
#include "xe_trace.h"
#include "xe_vm.h"
-#include "gt/intel_gpu_commands.h"
-
/**
* struct xe_migrate - migrate context.
*/
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index 0a1e32ab9758..104f96658e1f 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -5,6 +5,7 @@
#include "xe_ring_ops.h"
#include "regs/xe_lrc_regs.h"
+#include "regs/xe_gpu_commands.h"
#include "regs/xe_gt_regs.h"
#include "xe_engine_types.h"
#include "xe_gt.h"
@@ -13,7 +14,6 @@
#include "xe_sched_job.h"
#include "xe_vm_types.h"
-#include "gt/intel_gpu_commands.h"
#include "i915_reg.h"
static u32 preparser_disable(bool state)
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-xe] [PATCH v2 08/11] drm/xe: Remove dependency on i915_reg.h
2023-02-17 0:52 [Intel-xe] [PATCH v2 00/11] Start register cleanup Lucas De Marchi
` (6 preceding siblings ...)
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 07/11] drm/xe: Remove dependency on intel_gpu_commands.h Lucas De Marchi
@ 2023-02-17 0:52 ` Lucas De Marchi
2023-02-17 20:27 ` Rodrigo Vivi
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 09/11] drm/xe/guc_pc: Move gt register to the proper place Lucas De Marchi
` (3 subsequent siblings)
11 siblings, 1 reply; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-17 0:52 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Maarten Lankhorst, Matthew Auld
Copy the macros used by xe in i915_reg.h to regs/xe_regs.h. A minimal
cleanup is done while copying so they adhere minimally to the coding
style. Further reordering and cleaning is left for later.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/regs/xe_regs.h | 111 +++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_execlist.c | 3 +-
drivers/gpu/drm/xe/xe_ggtt.c | 3 +-
drivers/gpu/drm/xe/xe_gt_clock.c | 3 +-
drivers/gpu/drm/xe/xe_guc_pc.c | 3 +-
drivers/gpu/drm/xe/xe_hw_engine.c | 3 +-
drivers/gpu/drm/xe/xe_irq.c | 3 +-
drivers/gpu/drm/xe/xe_lrc.c | 3 +-
drivers/gpu/drm/xe/xe_mmio.c | 3 +-
drivers/gpu/drm/xe/xe_pci.c | 3 +-
drivers/gpu/drm/xe/xe_ring_ops.c | 3 +-
drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 3 +-
drivers/gpu/drm/xe/xe_wa.c | 3 +-
13 files changed, 123 insertions(+), 24 deletions(-)
create mode 100644 drivers/gpu/drm/xe/regs/xe_regs.h
diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
new file mode 100644
index 000000000000..53f1ed54fb1c
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+#ifndef _XE_REGS_H_
+#define _XE_REGS_H_
+
+#include "i915_reg_defs.h"
+
+#define GU_CNTL _MMIO(0x101010)
+#define LMEM_INIT REG_BIT(7)
+
+#define RENDER_RING_BASE 0x02000
+#define BSD_RING_BASE 0x04000
+#define GEN6_BSD_RING_BASE 0x12000
+#define GEN8_BSD2_RING_BASE 0x1c000
+#define GEN11_BSD_RING_BASE 0x1c0000
+#define GEN11_BSD2_RING_BASE 0x1c4000
+#define GEN11_BSD3_RING_BASE 0x1d0000
+#define GEN11_BSD4_RING_BASE 0x1d4000
+#define XEHP_BSD5_RING_BASE 0x1e0000
+#define XEHP_BSD6_RING_BASE 0x1e4000
+#define XEHP_BSD7_RING_BASE 0x1f0000
+#define XEHP_BSD8_RING_BASE 0x1f4000
+#define VEBOX_RING_BASE 0x1a000
+#define GEN11_VEBOX_RING_BASE 0x1c8000
+#define GEN11_VEBOX2_RING_BASE 0x1d8000
+#define XEHP_VEBOX3_RING_BASE 0x1e8000
+#define XEHP_VEBOX4_RING_BASE 0x1f8000
+#define GEN12_COMPUTE0_RING_BASE 0x1a000
+#define GEN12_COMPUTE1_RING_BASE 0x1c000
+#define GEN12_COMPUTE2_RING_BASE 0x1e000
+#define GEN12_COMPUTE3_RING_BASE 0x26000
+#define BLT_RING_BASE 0x22000
+#define XEHPC_BCS1_RING_BASE 0x3e0000
+#define XEHPC_BCS2_RING_BASE 0x3e2000
+#define XEHPC_BCS3_RING_BASE 0x3e4000
+#define XEHPC_BCS4_RING_BASE 0x3e6000
+#define XEHPC_BCS5_RING_BASE 0x3e8000
+#define XEHPC_BCS6_RING_BASE 0x3ea000
+#define XEHPC_BCS7_RING_BASE 0x3ec000
+#define XEHPC_BCS8_RING_BASE 0x3ee000
+#define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11)
+#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
+#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
+#define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
+#define GT_RENDER_USER_INTERRUPT (1 << 0)
+
+#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
+#define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
+
+#define PVC_RP_STATE_CAP _MMIO(0x281014)
+#define MTL_RP_STATE_CAP _MMIO(0x138000)
+
+#define MTL_MEDIAP_STATE_CAP _MMIO(0x138020)
+#define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
+#define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
+
+#define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c)
+#define MTL_MPE_FREQUENCY _MMIO(0x13802c)
+#define MTL_RPE_MASK REG_GENMASK(8, 0)
+
+#define TRANSCODER_A_OFFSET 0x60000
+#define TRANSCODER_B_OFFSET 0x61000
+#define TRANSCODER_C_OFFSET 0x62000
+#define TRANSCODER_D_OFFSET 0x63000
+#define TRANSCODER_DSI0_OFFSET 0x6b000
+#define TRANSCODER_DSI1_OFFSET 0x6b800
+#define PIPE_A_OFFSET 0x70000
+#define PIPE_B_OFFSET 0x71000
+#define PIPE_C_OFFSET 0x72000
+#define PIPE_D_OFFSET 0x73000
+#define PIPE_DSI0_OFFSET 0x7b000
+#define PIPE_DSI1_OFFSET 0x7b800
+
+#define GEN8_PCU_ISR _MMIO(0x444e0)
+#define GEN8_PCU_IMR _MMIO(0x444e4)
+#define GEN8_PCU_IIR _MMIO(0x444e8)
+#define GEN8_PCU_IER _MMIO(0x444ec)
+
+#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
+#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
+#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
+#define GEN11_GU_MISC_IER _MMIO(0x444fc)
+#define GEN11_GU_MISC_GSE (1 << 27)
+
+#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
+#define GEN11_MASTER_IRQ (1 << 31)
+#define GEN11_GU_MISC_IRQ (1 << 29)
+#define GEN11_DISPLAY_IRQ (1 << 16)
+#define GEN11_GT_DW_IRQ(x) (1 << (x))
+
+#define DG1_MSTR_TILE_INTR _MMIO(0x190008)
+#define DG1_MSTR_IRQ REG_BIT(31)
+#define DG1_MSTR_TILE(t) REG_BIT(t)
+
+#define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
+#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
+#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
+#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
+#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
+
+#define GGC _MMIO(0x108040)
+#define GMS_MASK REG_GENMASK(15, 8)
+#define GGMS_MASK REG_GENMASK(7, 6)
+
+#define GEN12_GSMBASE _MMIO(0x108100)
+#define GEN12_DSMBASE _MMIO(0x1080C0)
+#define GEN12_BDSM_MASK REG_GENMASK64(63, 20)
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
index c3c52bdc70b1..ad097918b496 100644
--- a/drivers/gpu/drm/xe/xe_execlist.c
+++ b/drivers/gpu/drm/xe/xe_execlist.c
@@ -10,6 +10,7 @@
#include "regs/xe_lrc_regs.h"
#include "regs/xe_gpu_commands.h"
#include "regs/xe_gt_regs.h"
+#include "regs/xe_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_engine.h"
@@ -22,8 +23,6 @@
#include "xe_ring_ops_types.h"
#include "xe_sched_job.h"
-#include "i915_reg.h"
-
#define XE_EXECLIST_HANG_LIMIT 1
#define GEN11_SW_CTX_ID_SHIFT 37
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 2c9b2175c5bb..6674297fa25e 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -10,6 +10,7 @@
#include <drm/i915_drm.h>
#include "regs/xe_gt_regs.h"
+#include "regs/xe_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_gt.h"
@@ -18,8 +19,6 @@
#include "xe_mmio.h"
#include "xe_wopcm.h"
-#include "i915_reg.h"
-
/* FIXME: Common file, preferably auto-gen */
#define MTL_GGTT_PTE_PAT0 BIT_ULL(52)
#define MTL_GGTT_PTE_PAT1 BIT_ULL(53)
diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
index e9aa7c5452af..cbf9c96c142c 100644
--- a/drivers/gpu/drm/xe/xe_gt_clock.c
+++ b/drivers/gpu/drm/xe/xe_gt_clock.c
@@ -5,13 +5,12 @@
#include "xe_gt_clock.h"
#include "regs/xe_gt_regs.h"
+#include "regs/xe_regs.h"
#include "xe_device.h"
#include "xe_gt.h"
#include "xe_macros.h"
#include "xe_mmio.h"
-#include "i915_reg.h"
-
static u32 read_reference_ts_freq(struct xe_gt *gt)
{
u32 ts_override = xe_mmio_read32(gt, GEN9_TIMESTAMP_OVERRIDE.reg);
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index f7aaf4826f00..0df82defa7e4 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -9,6 +9,7 @@
#include <drm/drm_managed.h>
#include "regs/xe_gt_regs.h"
+#include "regs/xe_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_gt.h"
@@ -19,8 +20,6 @@
#include "xe_mmio.h"
#include "xe_pcode.h"
-#include "i915_reg.h"
-#include "i915_reg_defs.h"
#include "intel_mchbar_regs.h"
/* For GEN6_RP_STATE_CAP.reg to be merged when the definition moves to Xe */
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index caae4f897644..2b49ccba0ce9 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -8,6 +8,7 @@
#include "regs/xe_engine_regs.h"
#include "regs/xe_gt_regs.h"
+#include "regs/xe_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_execlist.h"
@@ -22,8 +23,6 @@
#include "xe_sched_job.h"
#include "xe_wa.h"
-#include "i915_reg.h"
-
#define MAX_MMIO_BASES 3
struct engine_info {
const char *name;
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index d7756c14b4e2..f4f84a16dd83 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -9,6 +9,7 @@
#include <drm/drm_managed.h>
#include "regs/xe_gt_regs.h"
+#include "regs/xe_regs.h"
#include "xe_device.h"
#include "xe_display.h"
#include "xe_drv.h"
@@ -17,8 +18,6 @@
#include "xe_hw_engine.h"
#include "xe_mmio.h"
-#include "i915_reg.h"
-
static void gen3_assert_iir_is_zero(struct xe_gt *gt, i915_reg_t reg)
{
u32 val = xe_mmio_read32(gt, reg.reg);
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index c1df76c2cf78..261eabaae369 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -8,6 +8,7 @@
#include "regs/xe_lrc_regs.h"
#include "regs/xe_gpu_commands.h"
#include "regs/xe_gt_regs.h"
+#include "regs/xe_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_engine_types.h"
@@ -16,8 +17,6 @@
#include "xe_map.h"
#include "xe_vm.h"
-#include "i915_reg.h"
-
#define GEN8_CTX_VALID (1 << 0)
#define GEN8_CTX_L3LLC_COHERENT (1 << 5)
#define GEN8_CTX_PRIVILEGE (1 << 8)
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index d0cd9e920d34..262d33e59d26 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -9,14 +9,13 @@
#include "regs/xe_engine_regs.h"
#include "regs/xe_gt_regs.h"
+#include "regs/xe_regs.h"
#include "xe_device.h"
#include "xe_gt.h"
#include "xe_gt_mcr.h"
#include "xe_macros.h"
#include "xe_module.h"
-#include "i915_reg.h"
-
#define XEHP_MTCFG_ADDR _MMIO(0x101800)
#define TILE_COUNT REG_GENMASK(15, 8)
#define GEN12_LMEM_BAR 2
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index b0e5c402190c..4ecde7c2e619 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -13,6 +13,7 @@
#include <drm/drm_drv.h>
#include <drm/xe_pciids.h>
+#include "regs/xe_regs.h"
#include "xe_device.h"
#include "xe_drv.h"
#include "xe_macros.h"
@@ -20,8 +21,6 @@
#include "xe_pm.h"
#include "xe_step.h"
-#include "i915_reg.h"
-
#define DEV_INFO_FOR_EACH_FLAG(func) \
func(require_force_probe); \
func(is_dgfx); \
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index 104f96658e1f..ba3bde117af1 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -7,6 +7,7 @@
#include "regs/xe_lrc_regs.h"
#include "regs/xe_gpu_commands.h"
#include "regs/xe_gt_regs.h"
+#include "regs/xe_regs.h"
#include "xe_engine_types.h"
#include "xe_gt.h"
#include "xe_lrc.h"
@@ -14,8 +15,6 @@
#include "xe_sched_job.h"
#include "xe_vm_types.h"
-#include "i915_reg.h"
-
static u32 preparser_disable(bool state)
{
return MI_ARB_CHECK | BIT(8) | state;
diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
index 1c3783becefd..19828e003283 100644
--- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
+++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
@@ -11,8 +11,7 @@
#include <drm/ttm/ttm_placement.h>
#include <drm/ttm/ttm_range_manager.h>
-#include "../i915/i915_reg.h"
-
+#include "regs/xe_regs.h"
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_gt.h"
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 155cfd1dcc50..df72b15dfeb0 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -9,6 +9,7 @@
#include "regs/xe_engine_regs.h"
#include "regs/xe_gt_regs.h"
+#include "regs/xe_regs.h"
#include "xe_device_types.h"
#include "xe_force_wake.h"
#include "xe_gt.h"
@@ -18,8 +19,6 @@
#include "xe_rtp.h"
#include "xe_step.h"
-#include "i915_reg.h"
-
/**
* DOC: Hardware workarounds
*
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-xe] [PATCH v2 09/11] drm/xe/guc_pc: Move gt register to the proper place
2023-02-17 0:52 [Intel-xe] [PATCH v2 00/11] Start register cleanup Lucas De Marchi
` (7 preceding siblings ...)
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 08/11] drm/xe: Remove dependency on i915_reg.h Lucas De Marchi
@ 2023-02-17 0:52 ` Lucas De Marchi
2023-02-17 20:23 ` Rodrigo Vivi
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 10/11] drm/xe: Remove dependency on intel_mchbar_regs.h Lucas De Marchi
` (2 subsequent siblings)
11 siblings, 1 reply; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-17 0:52 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Maarten Lankhorst, Matthew Auld
Move a few defines from xe_guc_pc.c to the right register, now that
there is one: xe_gt_regs.h.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 ++
drivers/gpu/drm/xe/xe_guc_pc.c | 6 ------
2 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index da40133252fb..ab8c9e51f62e 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -186,6 +186,7 @@
#define DFR_DISABLE (1 << 9)
#define GEN6_RPNSWREQ _MMIO(0xa008)
+#define REQ_RATIO_MASK REG_GENMASK(31, 23)
#define GEN6_RC_CONTROL _MMIO(0xa090)
#define GEN6_RC_STATE _MMIO(0xa094)
@@ -242,6 +243,7 @@
#define FORCEWAKE_KERNEL_FALLBACK BIT(15)
#define GEN6_GT_CORE_STATUS _MMIO(0x138060)
+#define RCN_MASK REG_GENMASK(2, 0)
#define GEN6_RC0 0
#define GEN6_RC6 3
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 0df82defa7e4..3465236b0b49 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -30,12 +30,6 @@
#define GEN10_FREQ_INFO_REC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
#define RPE_MASK REG_GENMASK(15, 8)
-/* For GEN6_RPNSWREQ.reg to be merged when the definition moves to Xe */
-#define REQ_RATIO_MASK REG_GENMASK(31, 23)
-
-/* For GEN6_GT_CORE_STATUS.reg to be merged when the definition moves to Xe */
-#define RCN_MASK REG_GENMASK(2, 0)
-
#define GEN12_RPSTAT1 _MMIO(0x1381b4)
#define GEN12_CAGF_MASK REG_GENMASK(19, 11)
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-xe] [PATCH v2 10/11] drm/xe: Remove dependency on intel_mchbar_regs.h
2023-02-17 0:52 [Intel-xe] [PATCH v2 00/11] Start register cleanup Lucas De Marchi
` (8 preceding siblings ...)
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 09/11] drm/xe/guc_pc: Move gt register to the proper place Lucas De Marchi
@ 2023-02-17 0:52 ` Lucas De Marchi
2023-02-17 20:18 ` Rodrigo Vivi
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 11/11] drm/xe: Use relative includes for i915_reg_defs.h Lucas De Marchi
2023-02-17 6:19 ` [Intel-xe] [PATCH v2 00/11] Start register cleanup Lucas De Marchi
11 siblings, 1 reply; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-17 0:52 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Maarten Lankhorst, Matthew Auld
The only thing really needed is the base offset, MCHBAR_MIRROR_BASE_SNB.
Remove the include and just define it inplace.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_guc_pc.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 3465236b0b49..cc7d1007d942 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -20,12 +20,12 @@
#include "xe_mmio.h"
#include "xe_pcode.h"
-#include "intel_mchbar_regs.h"
+#define MCHBAR_MIRROR_BASE_SNB 0x140000
-/* For GEN6_RP_STATE_CAP.reg to be merged when the definition moves to Xe */
-#define RP0_MASK REG_GENMASK(7, 0)
-#define RP1_MASK REG_GENMASK(15, 8)
-#define RPN_MASK REG_GENMASK(23, 16)
+#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
+#define RP0_MASK REG_GENMASK(7, 0)
+#define RP1_MASK REG_GENMASK(15, 8)
+#define RPN_MASK REG_GENMASK(23, 16)
#define GEN10_FREQ_INFO_REC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
#define RPE_MASK REG_GENMASK(15, 8)
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-xe] [PATCH v2 11/11] drm/xe: Use relative includes for i915_reg_defs.h
2023-02-17 0:52 [Intel-xe] [PATCH v2 00/11] Start register cleanup Lucas De Marchi
` (9 preceding siblings ...)
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 10/11] drm/xe: Remove dependency on intel_mchbar_regs.h Lucas De Marchi
@ 2023-02-17 0:52 ` Lucas De Marchi
2023-02-17 16:33 ` Lucas De Marchi
2023-02-17 20:28 ` Rodrigo Vivi
2023-02-17 6:19 ` [Intel-xe] [PATCH v2 00/11] Start register cleanup Lucas De Marchi
11 siblings, 2 replies; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-17 0:52 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Maarten Lankhorst, Matthew Auld
With the goal of eliminating i915 includes from xe outside of the
display area, it's better to use relative includes for the only shared
header, i915_reg_defs.h. With this the build system can be changed to
stop adding i915 as an include dir.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/display/Makefile | 120 +++++++++++++++++++++++
drivers/gpu/drm/xe/regs/xe_engine_regs.h | 2 +-
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
drivers/gpu/drm/xe/regs/xe_regs.h | 2 +-
drivers/gpu/drm/xe/xe_gt_mcr.h | 2 +-
drivers/gpu/drm/xe/xe_guc.c | 2 -
drivers/gpu/drm/xe/xe_guc_reg.h | 2 +-
drivers/gpu/drm/xe/xe_reg_sr_types.h | 2 -
drivers/gpu/drm/xe/xe_rtp.h | 2 -
drivers/gpu/drm/xe/xe_rtp_types.h | 2 -
10 files changed, 125 insertions(+), 13 deletions(-)
create mode 100644 drivers/gpu/drm/xe/display/Makefile
diff --git a/drivers/gpu/drm/xe/display/Makefile b/drivers/gpu/drm/xe/display/Makefile
new file mode 100644
index 000000000000..eee576972427
--- /dev/null
+++ b/drivers/gpu/drm/xe/display/Makefile
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: GPL-2.0
+
+subdir-ccflags-y += -I$(srctree)/$(src)
+
+# i915 Display compat #defines and #includes
+subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += -I$(srctree)/$(src)/display/ext \
+ -I$(srctree)/drivers/gpu/drm/xe/display/ \
+ -I$(srctree)/drivers/gpu/drm/i915/display/ \
+ -I$(srctree)/drivers/gpu/drm/i915/ \
+ -DBUILD_FOR_XE=1 \
+ -Ddrm_i915_gem_object=xe_bo \
+ -Ddrm_i915_private=xe_device
+
+CFLAGS_display/intel_fbdev.o = $(call cc-disable-warning, override-init)
+
+$(obj)/display/i915_%.o: $(srctree)/drivers/gpu/drm/i915/display/i915_%.c FORCE
+ $(call cmd,force_checksrc)
+ $(call if_changed_rule,cc_o_c)
+
+$(obj)/display/skl_%.o: $(srctree)/drivers/gpu/drm/i915/display/skl_%.c FORCE
+ $(call cmd,force_checksrc)
+ $(call if_changed_rule,cc_o_c)
+
+$(obj)/display/icl_dsi.o: $(srctree)/drivers/gpu/drm/i915/display/icl_dsi.c FORCE
+ $(call cmd,force_checksrc)
+ $(call if_changed_rule,cc_o_c)
+
+$(obj)/display/intel_%.o: $(srctree)/drivers/gpu/drm/i915/display/intel_%.c FORCE
+ $(call cmd,force_checksrc)
+ $(call if_changed_rule,cc_o_c)
+
+# Display..
+xe-$(CONFIG_DRM_XE_DISPLAY) += \
+ xe_display.o \
+ display/icl_dsi.o \
+ display/intel_atomic.o \
+ display/intel_atomic_plane.o \
+ display/intel_audio.o \
+ display/intel_backlight.o \
+ display/intel_bios.o \
+ display/intel_bw.o \
+ display/intel_cdclk.o \
+ display/intel_color.o \
+ display/intel_combo_phy.o \
+ display/intel_connector.o \
+ display/intel_crtc_state_dump.o \
+ display/intel_crtc.o \
+ display/intel_cursor.o \
+ display/intel_ddi_buf_trans.o \
+ display/intel_ddi.o \
+ display/intel_display.o \
+ display/intel_display_debugfs.o \
+ display/intel_display_power.o \
+ display/intel_display_power_map.o \
+ display/intel_display_power_well.o \
+ display/intel_display_trace.o \
+ display/intel_dkl_phy.o \
+ display/intel_dmc.o \
+ display/intel_dp_aux_backlight.o \
+ display/intel_dp_aux.o \
+ display/intel_dp.o \
+ display/intel_dp_hdcp.o \
+ display/intel_dp_link_training.o \
+ display/intel_dpll.o \
+ display/intel_dpll_mgr.o \
+ display/intel_dp_mst.o \
+ display/intel_drrs.o \
+ display/intel_dsb.o \
+ display/intel_dsi.o \
+ display/intel_dsi_dcs_backlight.o \
+ display/intel_dsi_vbt.o \
+ display/intel_fb.o \
+ display/intel_fbc.o \
+ display/intel_fdi.o \
+ display/intel_fifo_underrun.o \
+ display/intel_frontbuffer.o \
+ display/intel_global_state.o \
+ display/intel_gmbus.o \
+ display/intel_hdcp.o \
+ display/intel_hdmi.o \
+ display/intel_hotplug.o \
+ display/intel_hti.o \
+ display/intel_lspcon.o \
+ display/intel_lvds.o \
+ display/intel_modeset_setup.o \
+ display/intel_modeset_verify.o \
+ display/intel_panel.o \
+ display/intel_pipe_crc.o \
+ display/intel_pps.o \
+ display/intel_psr.o \
+ display/intel_qp_tables.o \
+ display/intel_quirks.o \
+ display/intel_snps_phy.o \
+ display/intel_sprite.o \
+ display/intel_tc.o \
+ display/intel_vdsc.o \
+ display/intel_vga.o \
+ display/intel_vrr.o \
+ display/xe_fb_pin.o \
+ display/xe_plane_initial.o \
+ display/skl_scaler.o \
+ display/skl_universal_plane.o \
+ display/skl_watermark.o \
+ display/ext/i915_irq.o \
+ display/ext/intel_device_info.o \
+ display/ext/intel_dram.o \
+ display/ext/intel_pch.o \
+ display/ext/intel_pm.o
+
+ifeq ($(CONFIG_ACPI),y)
+ xe-$(CONFIG_DRM_XE_DISPLAY) += \
+ display/intel_acpi.o \
+ display/intel_opregion.o
+endif
+
+ifeq ($(CONFIG_DRM_FBDEV_EMULATION),y)
+ xe-$(CONFIG_DRM_XE_DISPLAY) += display/intel_fbdev.o
+endif
+
+
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index 6dfa3cf2fd43..a8f48a43b854 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -8,7 +8,7 @@
#include <asm/page.h>
-#include "i915_reg_defs.h"
+#include "../../i915/i915_reg_defs.h"
#define RING_TAIL(base) _MMIO((base) + 0x30)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index ab8c9e51f62e..2a2ebc7baeda 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -6,7 +6,7 @@
#ifndef _XE_GT_REGS_H_
#define _XE_GT_REGS_H_
-#include "i915_reg_defs.h"
+#include "../../i915/i915_reg_defs.h"
/* RPM unit config (Gen8+) */
#define RPM_CONFIG0 _MMIO(0xd00)
diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index 53f1ed54fb1c..f81f537c1ec1 100644
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -5,7 +5,7 @@
#ifndef _XE_REGS_H_
#define _XE_REGS_H_
-#include "i915_reg_defs.h"
+#include "../../i915/i915_reg_defs.h"
#define GU_CNTL _MMIO(0x101010)
#define LMEM_INIT REG_BIT(7)
diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.h b/drivers/gpu/drm/xe/xe_gt_mcr.h
index c31987d2177c..3f76233f88c3 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.h
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.h
@@ -6,7 +6,7 @@
#ifndef _XE_GT_MCR_H_
#define _XE_GT_MCR_H_
-#include "i915_reg_defs.h"
+#include "../i915/i915_reg_defs.h"
struct drm_printer;
struct xe_gt;
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index a2a124a7fc0b..6eefefd80ff9 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -21,8 +21,6 @@
#include "xe_uc_fw.h"
#include "xe_wopcm.h"
-#include "i915_reg_defs.h"
-
/* TODO: move to common file */
#define GUC_PVC_MOCS_INDEX_MASK REG_GENMASK(25, 24)
#define PVC_MOCS_UC_INDEX 1
diff --git a/drivers/gpu/drm/xe/xe_guc_reg.h b/drivers/gpu/drm/xe/xe_guc_reg.h
index 513a7e0c8a5a..234236833239 100644
--- a/drivers/gpu/drm/xe/xe_guc_reg.h
+++ b/drivers/gpu/drm/xe/xe_guc_reg.h
@@ -9,7 +9,7 @@
#include <linux/compiler.h>
#include <linux/types.h>
-#include "i915_reg_defs.h"
+#include "../i915/i915_reg_defs.h"
/* Definitions of GuC H/W registers, bits, etc */
diff --git a/drivers/gpu/drm/xe/xe_reg_sr_types.h b/drivers/gpu/drm/xe/xe_reg_sr_types.h
index 2fa7ff3966ba..8a317ce428a4 100644
--- a/drivers/gpu/drm/xe/xe_reg_sr_types.h
+++ b/drivers/gpu/drm/xe/xe_reg_sr_types.h
@@ -9,8 +9,6 @@
#include <linux/xarray.h>
#include <linux/types.h>
-#include "i915_reg_defs.h"
-
struct xe_reg_sr_entry {
u32 clr_bits;
u32 set_bits;
diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
index 1ac3fd1c0734..099047af89b4 100644
--- a/drivers/gpu/drm/xe/xe_rtp.h
+++ b/drivers/gpu/drm/xe/xe_rtp.h
@@ -11,8 +11,6 @@
#include "xe_rtp_types.h"
-#include "i915_reg_defs.h"
-
/*
* Register table poke infrastructure
*/
diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
index fac0bd6d5b1e..e87f1b280d96 100644
--- a/drivers/gpu/drm/xe/xe_rtp_types.h
+++ b/drivers/gpu/drm/xe/xe_rtp_types.h
@@ -8,8 +8,6 @@
#include <linux/types.h>
-#include "i915_reg_defs.h"
-
struct xe_hw_engine;
struct xe_gt;
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 00/11] Start register cleanup
2023-02-17 0:52 [Intel-xe] [PATCH v2 00/11] Start register cleanup Lucas De Marchi
` (10 preceding siblings ...)
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 11/11] drm/xe: Use relative includes for i915_reg_defs.h Lucas De Marchi
@ 2023-02-17 6:19 ` Lucas De Marchi
11 siblings, 0 replies; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-17 6:19 UTC (permalink / raw)
To: intel-xe; +Cc: Matthew Auld, Maarten Lankhorst
On Thu, Feb 16, 2023 at 04:52:15PM -0800, Lucas De Marchi wrote:
>Start cleaning up the register definitions used in xe.
>This removes dependency on the following registers:
>
> - intel_engine_regs.h
> - intel_gt_regs.h
> - intel_lrc_reg.h
> - intel_gpu_commands.h
> - i915_reg.h
> - intel_mchbar_regs.h
>
>The includes on the display/ part are left as is since there is still
>some more work to do to detangle dependencies. Other than from the
>display/ files, xe still depends on:
>
> - i915_reg_defs.h
> - display/intel_display_core.h
> - display/ext/intel_device_info.h
> - display/ext/intel_pch.h
>
>The first one are the generic defines used for defining the registers.
>They probably can be split and part of them copied to include/drm to be
>shared across the drivers. The last 3 are expected to be cleaned up
>together with the rest of the display.
>
>This series started by doing it manually with a few greps, migrated in
>the middle to do by "remove the include, parse the warnings from the
>compile and use that to generate the header" and finished with a small
>python script with clang. There may be some inconsistencies how the
fwiw this is the quick hack script I used (helper.py only exports a
git() wrapper). It does ~90% of the job -
just couldn't find a way to make it recurse into the macros - we'd need
the preprocessed header, but then the values would not be valid.
------8<------------
#!/usr/bin/python3
import sys
import clang.cindex
import helpers
FILE = sys.argv[1]
file_data = open(FILE, "r").readlines()
macros_instantiated = []
macros = dict()
macros_prereq = []
def is_used_by_xe(macro):
return helpers.git(["grep", "-q", f"\\b{macro}\\b", "--", "drivers/gpu/drm/xe/", ":(exclude)drivers/gpu/drm/xe/display/ext/"], check=False).returncode == 0
def print_source(node):
sline = node.extent.start.line
eline = node.extent.end.line
ecolumn = node.extent.end.column
line = sline
while line < eline:
print(file_data[line - 1].rstrip())
line += 1
print(file_data[line - 1][:ecolumn].rstrip())
def recurse(node):
if node.kind == clang.cindex.CursorKind.MACRO_DEFINITION and str(node.location.file) == FILE:
macros[node.spelling] = node
if is_used_by_xe(node.spelling):
print_source(node)
elif node.kind == clang.cindex.CursorKind.MACRO_INSTANTIATION and str(node.location.file) == FILE:
macros_instantiated.append(node)
for c in node.get_children():
recurse(c)
index = clang.cindex.Index.create()
root = index.parse(FILE,
options=clang.cindex.TranslationUnit.PARSE_DETAILED_PROCESSING_RECORD |
clang.cindex.TranslationUnit.PARSE_INCOMPLETE |
clang.cindex.TranslationUnit.PARSE_SKIP_FUNCTION_BODIES)
recurse(root.cursor)
for node in macros_instantiated:
if node.spelling in macros:
macros_prereq.append(macros[node.spelling])
macros_prereq.sort(key=lambda x: x.location.line)
if len(macros_prereq):
print("\n\n/* move me up */\n\n")
for node in macros_prereq:
print_source(node)
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 02/11] drm/xe: Sort includes
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 02/11] drm/xe: Sort includes Lucas De Marchi
@ 2023-02-17 11:20 ` Matthew Auld
2023-02-17 15:03 ` Lucas De Marchi
2023-02-17 11:39 ` Jani Nikula
1 sibling, 1 reply; 42+ messages in thread
From: Matthew Auld @ 2023-02-17 11:20 UTC (permalink / raw)
To: Lucas De Marchi, intel-xe; +Cc: Maarten Lankhorst
On 17/02/2023 00:52, Lucas De Marchi wrote:
> Sort includes and split them in blocks:
>
> 1) .h corresponding to the .c. Example: xe_bb.c should have a "#include
> "xe_bb.h" first.
> 2) #include <linux/...>
> 3) #include <drm/...>
> 4) local includes
> 5) i915 includes
>
> This is accomplished by running
> `clang-format --style=file -i --sort-includes drivers/gpu/drm/xe/*.c`
Neat.
> and ignoring all the changes after the includes. There are also some
> manual tweaks to split the blocks.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
<snip>
>
> #include "gt/intel_gt_regs.h"
> diff --git a/drivers/gpu/drm/xe/xe_uc.c b/drivers/gpu/drm/xe/xe_uc.c
> index 7886c8b85397..a27e6c1a6aff 100644
> --- a/drivers/gpu/drm/xe/xe_uc.c
> +++ b/drivers/gpu/drm/xe/xe_uc.c
> @@ -3,13 +3,13 @@
> * Copyright © 2022 Intel Corporation
> */
>
> +#include "xe_uc.h"
Needs new block here?
> #include "xe_device.h"
> -#include "xe_huc.h"
> #include "xe_gt.h"
> #include "xe_guc.h"
> #include "xe_guc_pc.h"
> #include "xe_guc_submit.h"
> -#include "xe_uc.h"
> +#include "xe_huc.h"
> #include "xe_uc_fw.h"
> #include "xe_wopcm.h"
>
> diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
> index 7276a375e2e0..a0e35627e45e 100644
> --- a/drivers/gpu/drm/xe/xe_vm.c
> +++ b/drivers/gpu/drm/xe/xe_vm.c
> @@ -25,8 +25,8 @@
> #include "xe_preempt_fence.h"
> #include "xe_pt.h"
> #include "xe_res_cursor.h"
> -#include "xe_trace.h"
> #include "xe_sync.h"
> +#include "xe_trace.h"
>
> #define TEST_VM_ASYNC_OPS_ERROR
>
> diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c
> index 1e4e3a1b0631..29815852985a 100644
> --- a/drivers/gpu/drm/xe/xe_vm_madvise.c
> +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
> @@ -3,13 +3,15 @@
> * Copyright © 2021 Intel Corporation
> */
>
> -#include <drm/xe_drm.h>
> -#include <drm/ttm/ttm_tt.h>
> +#include "xe_vm_madvise.h"
> +
> #include <linux/nospec.h>
>
> +#include <drm/ttm/ttm_tt.h>
> +#include <drm/xe_drm.h>
> +
> #include "xe_bo.h"
> #include "xe_vm.h"
> -#include "xe_vm_madvise.h"
>
> static int madvise_preferred_mem_class(struct xe_device *xe, struct xe_vm *vm,
> struct xe_vma **vmas, int num_vmas,
> diff --git a/drivers/gpu/drm/xe/xe_wopcm.c b/drivers/gpu/drm/xe/xe_wopcm.c
> index 8fe182afa06c..e9ac560be57f 100644
> --- a/drivers/gpu/drm/xe/xe_wopcm.c
> +++ b/drivers/gpu/drm/xe/xe_wopcm.c
> @@ -3,13 +3,13 @@
> * Copyright © 2022 Intel Corporation
> */
>
> +#include "xe_wopcm.h"
And here?
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> #include "xe_device.h"
> #include "xe_force_wake.h"
> #include "xe_gt.h"
> #include "xe_guc_reg.h"
> #include "xe_mmio.h"
> #include "xe_uc_fw.h"
> -#include "xe_wopcm.h"
>
> /**
> * DOC: Write Once Protected Content Memory (WOPCM) Layout
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 02/11] drm/xe: Sort includes
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 02/11] drm/xe: Sort includes Lucas De Marchi
2023-02-17 11:20 ` Matthew Auld
@ 2023-02-17 11:39 ` Jani Nikula
2023-02-17 15:09 ` Lucas De Marchi
1 sibling, 1 reply; 42+ messages in thread
From: Jani Nikula @ 2023-02-17 11:39 UTC (permalink / raw)
To: Lucas De Marchi, intel-xe
Cc: Lucas De Marchi, Matthew Auld, Maarten Lankhorst
On Thu, 16 Feb 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Sort includes and split them in blocks:
>
> 1) .h corresponding to the .c. Example: xe_bb.c should have a "#include
> "xe_bb.h" first.
Personally, I've never liked this, because the local headers could have
stuff that impacts global headers. And if there are conflicts, you kind
of want to have your local one look like the culprit (although modern
compilers are pretty good at showing both sites).
Note that to keep headers self-contained, this is not enough for headers
not associated with a .c, which is why we have the HDRTEST rule in i915.
> 2) #include <linux/...>
> 3) #include <drm/...>
> 4) local includes
> 5) i915 includes
>
> This is accomplished by running
> `clang-format --style=file -i --sort-includes drivers/gpu/drm/xe/*.c`
> and ignoring all the changes after the includes. There are also some
> manual tweaks to split the blocks.
Do you have the style file somewhere?
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/xe/xe_bb.c | 4 ++--
> drivers/gpu/drm/xe/xe_bo.c | 2 --
> drivers/gpu/drm/xe/xe_bo_evict.c | 2 +-
> drivers/gpu/drm/xe/xe_debugfs.c | 2 +-
> drivers/gpu/drm/xe/xe_device.c | 9 ++++-----
> drivers/gpu/drm/xe/xe_display.c | 12 ++++++------
> drivers/gpu/drm/xe/xe_dma_buf.c | 8 +++-----
> drivers/gpu/drm/xe/xe_engine.c | 4 ++--
> drivers/gpu/drm/xe/xe_exec.c | 2 +-
> drivers/gpu/drm/xe/xe_execlist.c | 9 ++++-----
> drivers/gpu/drm/xe/xe_force_wake.c | 4 ++--
> drivers/gpu/drm/xe/xe_ggtt.c | 7 +++----
> drivers/gpu/drm/xe/xe_gt.c | 2 +-
> drivers/gpu/drm/xe/xe_gt_clock.c | 8 ++++----
> drivers/gpu/drm/xe/xe_gt_debugfs.c | 2 +-
> drivers/gpu/drm/xe/xe_gt_mcr.c | 2 +-
> drivers/gpu/drm/xe/xe_gt_pagefault.c | 2 +-
> drivers/gpu/drm/xe/xe_gt_sysfs.c | 4 +++-
> drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c | 2 +-
> drivers/gpu/drm/xe/xe_gt_topology.c | 2 +-
> drivers/gpu/drm/xe/xe_guc.c | 13 +++++++------
> drivers/gpu/drm/xe/xe_guc_ads.c | 5 +++--
> drivers/gpu/drm/xe/xe_guc_ct.c | 4 ++--
> drivers/gpu/drm/xe/xe_guc_debugfs.c | 2 +-
> drivers/gpu/drm/xe/xe_guc_hwconfig.c | 2 +-
> drivers/gpu/drm/xe/xe_guc_log.c | 2 +-
> drivers/gpu/drm/xe/xe_guc_pc.c | 12 +++++++-----
> drivers/gpu/drm/xe/xe_guc_submit.c | 6 +++---
> drivers/gpu/drm/xe/xe_huc.c | 2 +-
> drivers/gpu/drm/xe/xe_huc_debugfs.c | 2 +-
> drivers/gpu/drm/xe/xe_hw_engine.c | 3 +--
> drivers/gpu/drm/xe/xe_hw_fence.c | 1 -
> drivers/gpu/drm/xe/xe_irq.c | 5 +++--
> drivers/gpu/drm/xe/xe_lrc.c | 7 +++----
> drivers/gpu/drm/xe/xe_migrate.c | 11 ++++++-----
> drivers/gpu/drm/xe/xe_mmio.c | 3 +--
> drivers/gpu/drm/xe/xe_mocs.c | 4 ++--
> drivers/gpu/drm/xe/xe_module.c | 1 +
> drivers/gpu/drm/xe/xe_pci.c | 5 ++---
> drivers/gpu/drm/xe/xe_pcode.c | 10 ++++------
> drivers/gpu/drm/xe/xe_pm.c | 4 ++--
> drivers/gpu/drm/xe/xe_preempt_fence.c | 2 +-
> drivers/gpu/drm/xe/xe_pt.c | 4 ++--
> drivers/gpu/drm/xe/xe_query.c | 11 ++++++-----
> drivers/gpu/drm/xe/xe_reg_sr.c | 5 ++---
> drivers/gpu/drm/xe/xe_reg_whitelist.c | 7 +++----
> drivers/gpu/drm/xe/xe_ring_ops.c | 4 ++--
> drivers/gpu/drm/xe/xe_rtp.c | 1 -
> drivers/gpu/drm/xe/xe_sa.c | 3 ++-
> drivers/gpu/drm/xe/xe_sched_job.c | 1 -
> drivers/gpu/drm/xe/xe_sync.c | 5 +++--
> drivers/gpu/drm/xe/xe_ttm_gtt_mgr.c | 2 +-
> drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 2 +-
> drivers/gpu/drm/xe/xe_ttm_vram_mgr.c | 2 +-
> drivers/gpu/drm/xe/xe_tuning.c | 2 +-
> drivers/gpu/drm/xe/xe_uc.c | 4 ++--
> drivers/gpu/drm/xe/xe_vm.c | 2 +-
> drivers/gpu/drm/xe/xe_vm_madvise.c | 8 +++++---
> drivers/gpu/drm/xe/xe_wopcm.c | 2 +-
> 59 files changed, 128 insertions(+), 132 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_bb.c b/drivers/gpu/drm/xe/xe_bb.c
> index 8b9209571fd0..a25079d4e710 100644
> --- a/drivers/gpu/drm/xe/xe_bb.c
> +++ b/drivers/gpu/drm/xe/xe_bb.c
> @@ -2,12 +2,12 @@
> /*
> * Copyright © 2022 Intel Corporation
> */
> -
Nitpick, throughout the series, I would leave a blank line after the
SPDX and copyright boilerplate, regardless of whether it's an #include
or header guard #ifdef that follows. They're not comments about what
follows, which is what it feels like when they're directly attached to
something that follows without a blank line.
> #include "xe_bb.h"
> -#include "xe_sa.h"
> +
> #include "xe_device.h"
> #include "xe_engine_types.h"
> #include "xe_hw_fence.h"
> +#include "xe_sa.h"
> #include "xe_sched_job.h"
> #include "xe_vm_types.h"
>
...
> diff --git a/drivers/gpu/drm/xe/xe_uc.c b/drivers/gpu/drm/xe/xe_uc.c
> index 7886c8b85397..a27e6c1a6aff 100644
> --- a/drivers/gpu/drm/xe/xe_uc.c
> +++ b/drivers/gpu/drm/xe/xe_uc.c
> @@ -3,13 +3,13 @@
> * Copyright © 2022 Intel Corporation
> */
>
> +#include "xe_uc.h"
> #include "xe_device.h"
> -#include "xe_huc.h"
> #include "xe_gt.h"
> #include "xe_guc.h"
> #include "xe_guc_pc.h"
> #include "xe_guc_submit.h"
> -#include "xe_uc.h"
> +#include "xe_huc.h"
> #include "xe_uc_fw.h"
> #include "xe_wopcm.h"
Here, having the .h corresponding to the .c just looks like it's not
properly sorted.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 02/11] drm/xe: Sort includes
2023-02-17 11:20 ` Matthew Auld
@ 2023-02-17 15:03 ` Lucas De Marchi
0 siblings, 0 replies; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-17 15:03 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-xe, Maarten Lankhorst
On Fri, Feb 17, 2023 at 11:20:50AM +0000, Matthew Auld wrote:
>On 17/02/2023 00:52, Lucas De Marchi wrote:
>>Sort includes and split them in blocks:
>>
>>1) .h corresponding to the .c. Example: xe_bb.c should have a "#include
>> "xe_bb.h" first.
>>2) #include <linux/...>
>>3) #include <drm/...>
>>4) local includes
>>5) i915 includes
>>
>>This is accomplished by running
>>`clang-format --style=file -i --sort-includes drivers/gpu/drm/xe/*.c`
>
>Neat.
>
>>and ignoring all the changes after the includes. There are also some
>>manual tweaks to split the blocks.
>>
>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
><snip>
>
>> #include "gt/intel_gt_regs.h"
>>diff --git a/drivers/gpu/drm/xe/xe_uc.c b/drivers/gpu/drm/xe/xe_uc.c
>>index 7886c8b85397..a27e6c1a6aff 100644
>>--- a/drivers/gpu/drm/xe/xe_uc.c
>>+++ b/drivers/gpu/drm/xe/xe_uc.c
>>@@ -3,13 +3,13 @@
>> * Copyright © 2022 Intel Corporation
>> */
>>+#include "xe_uc.h"
>
>Needs new block here?
yep
>
>> #include "xe_device.h"
>>-#include "xe_huc.h"
>> #include "xe_gt.h"
>> #include "xe_guc.h"
>> #include "xe_guc_pc.h"
>> #include "xe_guc_submit.h"
>>-#include "xe_uc.h"
>>+#include "xe_huc.h"
>> #include "xe_uc_fw.h"
>> #include "xe_wopcm.h"
>>diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
>>index 7276a375e2e0..a0e35627e45e 100644
>>--- a/drivers/gpu/drm/xe/xe_vm.c
>>+++ b/drivers/gpu/drm/xe/xe_vm.c
>>@@ -25,8 +25,8 @@
>> #include "xe_preempt_fence.h"
>> #include "xe_pt.h"
>> #include "xe_res_cursor.h"
>>-#include "xe_trace.h"
>> #include "xe_sync.h"
>>+#include "xe_trace.h"
>> #define TEST_VM_ASYNC_OPS_ERROR
>>diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c
>>index 1e4e3a1b0631..29815852985a 100644
>>--- a/drivers/gpu/drm/xe/xe_vm_madvise.c
>>+++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
>>@@ -3,13 +3,15 @@
>> * Copyright © 2021 Intel Corporation
>> */
>>-#include <drm/xe_drm.h>
>>-#include <drm/ttm/ttm_tt.h>
>>+#include "xe_vm_madvise.h"
>>+
>> #include <linux/nospec.h>
>>+#include <drm/ttm/ttm_tt.h>
>>+#include <drm/xe_drm.h>
>>+
>> #include "xe_bo.h"
>> #include "xe_vm.h"
>>-#include "xe_vm_madvise.h"
>> static int madvise_preferred_mem_class(struct xe_device *xe, struct xe_vm *vm,
>> struct xe_vma **vmas, int num_vmas,
>>diff --git a/drivers/gpu/drm/xe/xe_wopcm.c b/drivers/gpu/drm/xe/xe_wopcm.c
>>index 8fe182afa06c..e9ac560be57f 100644
>>--- a/drivers/gpu/drm/xe/xe_wopcm.c
>>+++ b/drivers/gpu/drm/xe/xe_wopcm.c
>>@@ -3,13 +3,13 @@
>> * Copyright © 2022 Intel Corporation
>> */
>>+#include "xe_wopcm.h"
>
>And here?
yep
>
>Reviewed-by: Matthew Auld <matthew.auld@intel.com>
thanks
Lucas De Marchi
>
>> #include "xe_device.h"
>> #include "xe_force_wake.h"
>> #include "xe_gt.h"
>> #include "xe_guc_reg.h"
>> #include "xe_mmio.h"
>> #include "xe_uc_fw.h"
>>-#include "xe_wopcm.h"
>> /**
>> * DOC: Write Once Protected Content Memory (WOPCM) Layout
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 02/11] drm/xe: Sort includes
2023-02-17 11:39 ` Jani Nikula
@ 2023-02-17 15:09 ` Lucas De Marchi
0 siblings, 0 replies; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-17 15:09 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe, Maarten Lankhorst, Matthew Auld
On Fri, Feb 17, 2023 at 01:39:31PM +0200, Jani Nikula wrote:
>On Thu, 16 Feb 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> Sort includes and split them in blocks:
>>
>> 1) .h corresponding to the .c. Example: xe_bb.c should have a "#include
>> "xe_bb.h" first.
>
>Personally, I've never liked this, because the local headers could have
>stuff that impacts global headers. And if there are conflicts, you kind
>of want to have your local one look like the culprit (although modern
>compilers are pretty good at showing both sites).
>
>Note that to keep headers self-contained, this is not enough for headers
>not associated with a .c, which is why we have the HDRTEST rule in i915.
Although I like the hdrtest and wouldn't replace it, I think having a
convention like this is good - it also solves most of the issues
wrt selfcontained headers while not requiring any special setup on dev
side: if every .c/.h follow the same structure, it's easier to maintain
the consistency.
>
>> 2) #include <linux/...>
>> 3) #include <drm/...>
>> 4) local includes
>> 5) i915 includes
>>
>> This is accomplished by running
>> `clang-format --style=file -i --sort-includes drivers/gpu/drm/xe/*.c`
>> and ignoring all the changes after the includes. There are also some
>> manual tweaks to split the blocks.
>
>Do you have the style file somewhere?
.clang-format. It's in the kernel source tree, added in
commit d4ef8d3ff005 ("clang-format: add configuration file")
>
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_bb.c | 4 ++--
>> drivers/gpu/drm/xe/xe_bo.c | 2 --
>> drivers/gpu/drm/xe/xe_bo_evict.c | 2 +-
>> drivers/gpu/drm/xe/xe_debugfs.c | 2 +-
>> drivers/gpu/drm/xe/xe_device.c | 9 ++++-----
>> drivers/gpu/drm/xe/xe_display.c | 12 ++++++------
>> drivers/gpu/drm/xe/xe_dma_buf.c | 8 +++-----
>> drivers/gpu/drm/xe/xe_engine.c | 4 ++--
>> drivers/gpu/drm/xe/xe_exec.c | 2 +-
>> drivers/gpu/drm/xe/xe_execlist.c | 9 ++++-----
>> drivers/gpu/drm/xe/xe_force_wake.c | 4 ++--
>> drivers/gpu/drm/xe/xe_ggtt.c | 7 +++----
>> drivers/gpu/drm/xe/xe_gt.c | 2 +-
>> drivers/gpu/drm/xe/xe_gt_clock.c | 8 ++++----
>> drivers/gpu/drm/xe/xe_gt_debugfs.c | 2 +-
>> drivers/gpu/drm/xe/xe_gt_mcr.c | 2 +-
>> drivers/gpu/drm/xe/xe_gt_pagefault.c | 2 +-
>> drivers/gpu/drm/xe/xe_gt_sysfs.c | 4 +++-
>> drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c | 2 +-
>> drivers/gpu/drm/xe/xe_gt_topology.c | 2 +-
>> drivers/gpu/drm/xe/xe_guc.c | 13 +++++++------
>> drivers/gpu/drm/xe/xe_guc_ads.c | 5 +++--
>> drivers/gpu/drm/xe/xe_guc_ct.c | 4 ++--
>> drivers/gpu/drm/xe/xe_guc_debugfs.c | 2 +-
>> drivers/gpu/drm/xe/xe_guc_hwconfig.c | 2 +-
>> drivers/gpu/drm/xe/xe_guc_log.c | 2 +-
>> drivers/gpu/drm/xe/xe_guc_pc.c | 12 +++++++-----
>> drivers/gpu/drm/xe/xe_guc_submit.c | 6 +++---
>> drivers/gpu/drm/xe/xe_huc.c | 2 +-
>> drivers/gpu/drm/xe/xe_huc_debugfs.c | 2 +-
>> drivers/gpu/drm/xe/xe_hw_engine.c | 3 +--
>> drivers/gpu/drm/xe/xe_hw_fence.c | 1 -
>> drivers/gpu/drm/xe/xe_irq.c | 5 +++--
>> drivers/gpu/drm/xe/xe_lrc.c | 7 +++----
>> drivers/gpu/drm/xe/xe_migrate.c | 11 ++++++-----
>> drivers/gpu/drm/xe/xe_mmio.c | 3 +--
>> drivers/gpu/drm/xe/xe_mocs.c | 4 ++--
>> drivers/gpu/drm/xe/xe_module.c | 1 +
>> drivers/gpu/drm/xe/xe_pci.c | 5 ++---
>> drivers/gpu/drm/xe/xe_pcode.c | 10 ++++------
>> drivers/gpu/drm/xe/xe_pm.c | 4 ++--
>> drivers/gpu/drm/xe/xe_preempt_fence.c | 2 +-
>> drivers/gpu/drm/xe/xe_pt.c | 4 ++--
>> drivers/gpu/drm/xe/xe_query.c | 11 ++++++-----
>> drivers/gpu/drm/xe/xe_reg_sr.c | 5 ++---
>> drivers/gpu/drm/xe/xe_reg_whitelist.c | 7 +++----
>> drivers/gpu/drm/xe/xe_ring_ops.c | 4 ++--
>> drivers/gpu/drm/xe/xe_rtp.c | 1 -
>> drivers/gpu/drm/xe/xe_sa.c | 3 ++-
>> drivers/gpu/drm/xe/xe_sched_job.c | 1 -
>> drivers/gpu/drm/xe/xe_sync.c | 5 +++--
>> drivers/gpu/drm/xe/xe_ttm_gtt_mgr.c | 2 +-
>> drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 2 +-
>> drivers/gpu/drm/xe/xe_ttm_vram_mgr.c | 2 +-
>> drivers/gpu/drm/xe/xe_tuning.c | 2 +-
>> drivers/gpu/drm/xe/xe_uc.c | 4 ++--
>> drivers/gpu/drm/xe/xe_vm.c | 2 +-
>> drivers/gpu/drm/xe/xe_vm_madvise.c | 8 +++++---
>> drivers/gpu/drm/xe/xe_wopcm.c | 2 +-
>> 59 files changed, 128 insertions(+), 132 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_bb.c b/drivers/gpu/drm/xe/xe_bb.c
>> index 8b9209571fd0..a25079d4e710 100644
>> --- a/drivers/gpu/drm/xe/xe_bb.c
>> +++ b/drivers/gpu/drm/xe/xe_bb.c
>> @@ -2,12 +2,12 @@
>> /*
>> * Copyright © 2022 Intel Corporation
>> */
>> -
>
>Nitpick, throughout the series, I would leave a blank line after the
>SPDX and copyright boilerplate, regardless of whether it's an #include
>or header guard #ifdef that follows. They're not comments about what
>follows, which is what it feels like when they're directly attached to
>something that follows without a blank line.
ok
>
>> #include "xe_bb.h"
>> -#include "xe_sa.h"
>> +
>> #include "xe_device.h"
>> #include "xe_engine_types.h"
>> #include "xe_hw_fence.h"
>> +#include "xe_sa.h"
>> #include "xe_sched_job.h"
>> #include "xe_vm_types.h"
>>
>
>...
>
>> diff --git a/drivers/gpu/drm/xe/xe_uc.c b/drivers/gpu/drm/xe/xe_uc.c
>> index 7886c8b85397..a27e6c1a6aff 100644
>> --- a/drivers/gpu/drm/xe/xe_uc.c
>> +++ b/drivers/gpu/drm/xe/xe_uc.c
>> @@ -3,13 +3,13 @@
>> * Copyright © 2022 Intel Corporation
>> */
>>
>> +#include "xe_uc.h"
>> #include "xe_device.h"
>> -#include "xe_huc.h"
>> #include "xe_gt.h"
>> #include "xe_guc.h"
>> #include "xe_guc_pc.h"
>> #include "xe_guc_submit.h"
>> -#include "xe_uc.h"
>> +#include "xe_huc.h"
>> #include "xe_uc_fw.h"
>> #include "xe_wopcm.h"
>
>Here, having the .h corresponding to the .c just looks like it's not
>properly sorted.
just because I failed to split the block as Matt Auld noticed
thanks
Lucas De Marchi
>
>BR,
>Jani.
>
>
>--
>Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 11/11] drm/xe: Use relative includes for i915_reg_defs.h
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 11/11] drm/xe: Use relative includes for i915_reg_defs.h Lucas De Marchi
@ 2023-02-17 16:33 ` Lucas De Marchi
2023-02-17 20:28 ` Rodrigo Vivi
1 sibling, 0 replies; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-17 16:33 UTC (permalink / raw)
To: intel-xe; +Cc: Matthew Auld, Maarten Lankhorst, Rodrigo Vivi
On Thu, Feb 16, 2023 at 04:52:26PM -0800, Lucas De Marchi wrote:
>With the goal of eliminating i915 includes from xe outside of the
>display area, it's better to use relative includes for the only shared
>header, i915_reg_defs.h. With this the build system can be changed to
>stop adding i915 as an include dir.
>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Rodrigo
I know I've previously suggested changing the other way around and avoid
the relative include. However with this cleanup we are very close to
remove the -I for i915. So I think we can first remove the -I and then
decide what to do with the single include that we still want.
Lucas De Marchi
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 01/11] drm/xe: Remove outdated build workaround
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 01/11] drm/xe: Remove outdated build workaround Lucas De Marchi
@ 2023-02-17 20:13 ` Rodrigo Vivi
0 siblings, 0 replies; 42+ messages in thread
From: Rodrigo Vivi @ 2023-02-17 20:13 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe, Maarten Lankhorst, Matthew Auld
On Thu, Feb 16, 2023 at 04:52:16PM -0800, Lucas De Marchi wrote:
> Use the more common "call cc-disable-warning" way to disable warnings.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/xe/Makefile | 10 ++--------
> 1 file changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index abd804d622e6..18257cd7227d 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -13,14 +13,8 @@
> # will most likely get a sudden build breakage... Hopefully we will fix
> # new warnings before CI updates!
> subdir-ccflags-y := -Wall -Wextra
> -# making these call cc-disable-warning breaks when trying to build xe.mod.o
> -# by calling make M=drivers/gpu/drm/xe. This doesn't happen in upstream tree,
> -# so it was somehow fixed by the changes in the build system. Move it back to
> -# $(call cc-disable-warning, ...) after rebase.
> -subdir-ccflags-y += -Wno-unused-parameter
> -subdir-ccflags-y += -Wno-type-limits
> -#subdir-ccflags-y += $(call cc-disable-warning, unused-parameter)
> -#subdir-ccflags-y += $(call cc-disable-warning, type-limits)
> +subdir-ccflags-y += $(call cc-disable-warning, unused-parameter)
> +subdir-ccflags-y += $(call cc-disable-warning, type-limits)
> subdir-ccflags-y += $(call cc-disable-warning, missing-field-initializers)
> subdir-ccflags-y += $(call cc-disable-warning, unused-but-set-variable)
> # clang warnings
> --
> 2.39.0
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 10/11] drm/xe: Remove dependency on intel_mchbar_regs.h
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 10/11] drm/xe: Remove dependency on intel_mchbar_regs.h Lucas De Marchi
@ 2023-02-17 20:18 ` Rodrigo Vivi
0 siblings, 0 replies; 42+ messages in thread
From: Rodrigo Vivi @ 2023-02-17 20:18 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe, Maarten Lankhorst, Matthew Auld
On Thu, Feb 16, 2023 at 04:52:25PM -0800, Lucas De Marchi wrote:
> The only thing really needed is the base offset, MCHBAR_MIRROR_BASE_SNB.
> Remove the include and just define it inplace.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc_pc.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> index 3465236b0b49..cc7d1007d942 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> @@ -20,12 +20,12 @@
> #include "xe_mmio.h"
> #include "xe_pcode.h"
>
> -#include "intel_mchbar_regs.h"
> +#define MCHBAR_MIRROR_BASE_SNB 0x140000
>
> -/* For GEN6_RP_STATE_CAP.reg to be merged when the definition moves to Xe */
> -#define RP0_MASK REG_GENMASK(7, 0)
> -#define RP1_MASK REG_GENMASK(15, 8)
> -#define RPN_MASK REG_GENMASK(23, 16)
> +#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
> +#define RP0_MASK REG_GENMASK(7, 0)
> +#define RP1_MASK REG_GENMASK(15, 8)
> +#define RPN_MASK REG_GENMASK(23, 16)
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> #define GEN10_FREQ_INFO_REC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
> #define RPE_MASK REG_GENMASK(15, 8)
> --
> 2.39.0
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 05/11] drm/xe: Remove dependency on intel_gt_regs.h
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 05/11] drm/xe: Remove dependency on intel_gt_regs.h Lucas De Marchi
@ 2023-02-17 20:20 ` Rodrigo Vivi
2023-02-17 22:08 ` Lucas De Marchi
2023-02-24 18:06 ` Matt Roper
1 sibling, 1 reply; 42+ messages in thread
From: Rodrigo Vivi @ 2023-02-17 20:20 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe, Maarten Lankhorst, Matthew Auld
On Thu, Feb 16, 2023 at 04:52:20PM -0800, Lucas De Marchi wrote:
> Create regs/xe_gt_regs.h file with all the registers and bit
> definitions used by the xe driver. Eventually the registers may be
> defined in a different way and since xe doesn't supported below gen12,
> the number of registers touched is much smaller, so create a new header.
>
> The definitions themselves are direct copy from the
> gt/intel_gt_regs.h file, just sorting the registers by address.
> Cleaning those up and adhering to a common coding style is left for
> later.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg_defs.h | 2 +
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 287 ++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_execlist.c | 2 +-
> drivers/gpu/drm/xe/xe_force_wake.c | 3 +-
> drivers/gpu/drm/xe/xe_ggtt.c | 2 +-
> drivers/gpu/drm/xe/xe_gt.c | 3 +-
> drivers/gpu/drm/xe/xe_gt_clock.c | 2 +-
> drivers/gpu/drm/xe/xe_gt_mcr.c | 3 +-
> drivers/gpu/drm/xe/xe_guc.c | 2 +-
> drivers/gpu/drm/xe/xe_guc_ads.c | 4 +-
> drivers/gpu/drm/xe/xe_guc_pc.c | 2 +-
> drivers/gpu/drm/xe/xe_hw_engine.c | 2 +-
> drivers/gpu/drm/xe/xe_irq.c | 2 +-
> drivers/gpu/drm/xe/xe_lrc.c | 2 +-
> drivers/gpu/drm/xe/xe_mmio.c | 2 +-
> drivers/gpu/drm/xe/xe_mocs.c | 3 +-
> drivers/gpu/drm/xe/xe_reg_sr.c | 3 +-
> drivers/gpu/drm/xe/xe_reg_whitelist.c | 3 +-
> drivers/gpu/drm/xe/xe_ring_ops.c | 2 +-
> drivers/gpu/drm/xe/xe_tuning.c | 3 +-
> drivers/gpu/drm/xe/xe_wa.c | 2 +-
> 21 files changed, 308 insertions(+), 28 deletions(-)
> create mode 100644 drivers/gpu/drm/xe/regs/xe_gt_regs.h
>
> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
> index b5e06b6a9478..a6080c983a77 100644
> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> @@ -136,6 +136,8 @@ typedef struct {
> u32 reg;
> } i915_mcr_reg_t;
>
> +#define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg = (offset) })
> +
> #define INVALID_MMIO_REG _MMIO(0)
>
> /*
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> new file mode 100644
> index 000000000000..da40133252fb
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -0,0 +1,287 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_GT_REGS_H_
> +#define _XE_GT_REGS_H_
> +
> +#include "i915_reg_defs.h"
> +
> +/* RPM unit config (Gen8+) */
> +#define RPM_CONFIG0 _MMIO(0xd00)
> +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/215
https://lore.kernel.org/all/Y9hw0sSC58B32yPg@mdroper-desk1.amr.corp.intel.com/
Matt has asked us to get rid of the GEN stuff...
I believe this is a great opportunity, although I believe it is not
a blocker and could be done later.
> +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
> +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
> +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
> +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2
> +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
> +#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
> +#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
> +
> +#define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0xd50 + (n) * 4)
> +#define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0xd70 + (n) * 4)
> +#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84)
> +
> +#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
> +#define LNCFCMOCS_REG_COUNT 32
> +
> +#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
> +#define MTL_MCR_SELECTOR _MMIO(0xfd4)
> +#define SF_MCR_SELECTOR _MMIO(0xfd8)
> +#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
> +#define GAM_MCR_SELECTOR _MMIO(0xfe0)
> +#define GEN11_MCR_MULTICAST REG_BIT(31)
> +#define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27)
> +#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
> +#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
> +#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
> +#define MTL_MCR_GROUPID REG_GENMASK(11, 8)
> +#define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
> +
> +#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
> +#define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
> +
> +#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
> +#define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
> +
> +#define PS_INVOCATION_COUNT _MMIO(0x2348)
> +
> +#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
> +#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
> +#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
> +#define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
> +#define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
> +#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
> +#define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
> +
> +#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
> +#define GEN12_GFX_CCS_AUX_NV _MMIO(0x4208)
> +
> +#define GEN12_VD0_AUX_NV _MMIO(0x4218)
> +#define GEN12_VE0_AUX_NV _MMIO(0x4238)
> +
> +#define GEN12_VE1_AUX_NV _MMIO(0x42b8)
> +#define AUX_INV REG_BIT(0)
> +
> +#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
> +#define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900)
> +#define XEHP_FLAT_CCS_BASE_ADDR MCR_REG(0x4910)
> +
> +#define GEN12_FF_MODE2 _MMIO(0x6604)
> +#define XEHP_FF_MODE2 MCR_REG(0x6604)
> +#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
> +#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
> +#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
> +#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
> +
> +#define HIZ_CHICKEN _MMIO(0x7018)
> +#define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14)
> +
> +/* GEN7 chicken */
> +#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
> +
> +#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
> +#define XEHP_COMMON_SLICE_CHICKEN3 MCR_REG(0x7304)
> +#define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
> +#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
> +#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
> +#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
> +
> +#define XEHP_SQCM MCR_REG(0x8724)
> +#define EN_32B_ACCESS REG_BIT(30)
> +
> +#define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
> +#define GEN10_L3BANK_PAIR_COUNT 4
> +#define GEN10_L3BANK_MASK 0x0F
> +/* on Xe_HP the same fuses indicates mslices instead of L3 banks */
> +#define GEN12_MAX_MSLICES 4
> +#define GEN12_MEML3_EN_MASK 0x0F
> +
> +/* Fuse readout registers for GT */
> +#define XEHP_FUSE4 _MMIO(0x9114)
> +#define GT_L3_EXC_MASK REG_GENMASK(6, 4)
> +
> +#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
> +#define GEN11_GT_VDBOX_DISABLE_MASK 0xff
> +#define GEN11_GT_VEBOX_DISABLE_SHIFT 16
> +#define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
> +
> +#define GEN6_GDRST _MMIO(0x941c)
> +#define GEN11_GRDOM_GUC REG_BIT(3)
> +#define GEN6_GRDOM_FULL (1 << 0)
> +#define GEN11_GRDOM_FULL GEN6_GRDOM_FULL
> +
> +#define GEN7_MISCCPCTL _MMIO(0x9424)
> +#define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
> +#define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1)
> +
> +#define UNSLCGCTL9430 _MMIO(0x9430)
> +#define MSQDUNIT_CLKGATE_DIS REG_BIT(3)
> +
> +#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
> +#define VFUNIT_CLKGATE_DIS REG_BIT(20)
> +#define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */
> +#define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */
> +#define GAMEDIA_CLKGATE_DIS REG_BIT(11)
> +#define HSUNIT_CLKGATE_DIS REG_BIT(8)
> +#define VSUNIT_CLKGATE_DIS REG_BIT(3)
> +
> +#define UNSLCGCTL9440 _MMIO(0x9440)
> +#define GAMTLBOACS_CLKGATE_DIS REG_BIT(28)
> +#define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27)
> +#define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26)
> +#define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24)
> +#define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23)
> +#define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22)
> +#define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21)
> +#define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17)
> +#define GAMTLBKCR_CLKGATE_DIS REG_BIT(16)
> +#define GAMTLBGUC_CLKGATE_DIS REG_BIT(15)
> +#define GAMTLBBLT_CLKGATE_DIS REG_BIT(14)
> +#define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6)
> +
> +#define UNSLCGCTL9444 _MMIO(0x9444)
> +#define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30)
> +#define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29)
> +#define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28)
> +#define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27)
> +#define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26)
> +#define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25)
> +#define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24)
> +#define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23)
> +#define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22)
> +#define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21)
> +#define GAMTLBMERT_CLKGATE_DIS REG_BIT(20)
> +#define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19)
> +#define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18)
> +#define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17)
> +#define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
> +#define LTCDD_CLKGATE_DIS REG_BIT(10)
> +
> +#define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> +#define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4)
> +#define SARBUNIT_CLKGATE_DIS (1 << 5)
> +#define RCCUNIT_CLKGATE_DIS (1 << 7)
> +#define MSCUNIT_CLKGATE_DIS (1 << 10)
> +#define NODEDSS_CLKGATE_DIS REG_BIT(12)
> +#define L3_CLKGATE_DIS REG_BIT(16)
> +#define L3_CR2X_CLKGATE_DIS REG_BIT(17)
> +
> +#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
> +#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
> +#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
> +
> +#define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x9524)
> +#define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
> +#define GWUNIT_CLKGATE_DIS REG_BIT(16)
> +
> +#define SUBSLICE_UNIT_LEVEL_CLKGATE2 MCR_REG(0x9528)
> +#define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
> +
> +#define SSMCGCTL9530 MCR_REG(0x9530)
> +#define RTFUNIT_CLKGATE_DIS REG_BIT(18)
> +
> +#define GEN10_DFR_RATIO_EN_AND_CHICKEN MCR_REG(0x9550)
> +#define DFR_DISABLE (1 << 9)
> +
> +#define GEN6_RPNSWREQ _MMIO(0xa008)
> +#define GEN6_RC_CONTROL _MMIO(0xa090)
> +#define GEN6_RC_STATE _MMIO(0xa094)
> +
> +#define GEN6_PMINTRMSK _MMIO(0xa168)
> +#define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31)
> +#define ARAT_EXPIRED_INTRMSK (1 << 9)
> +
> +#define FORCEWAKE_GT_GEN9 _MMIO(0xa188)
> +
> +#define GEN9_PG_ENABLE _MMIO(0xa210)
> +
> +/* GPM unit config (Gen9+) */
> +#define CTC_MODE _MMIO(0xa26c)
> +#define CTC_SOURCE_PARAMETER_MASK 1
> +#define CTC_SOURCE_CRYSTAL_CLOCK 0
> +#define CTC_SOURCE_DIVIDE_LOGIC 1
> +#define CTC_SHIFT_PARAMETER_SHIFT 1
> +#define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
> +
> +#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
> +#define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4)
> +#define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4)
> +
> +#define GEN10_SAMPLER_MODE MCR_REG(0xe18c)
> +#define ENABLE_SMALLPL REG_BIT(15)
> +#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> +#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
> +
> +#define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c)
> +#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
> +#define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
> +#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
> +#define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
> +#define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4)
> +#define THREAD_EX_ARB_MODE REG_GENMASK(3, 2)
> +#define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
> +
> +#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
> +#define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
> +#define GEN12_DISABLE_EARLY_READ REG_BIT(14)
> +#define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
> +#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
> +#define GEN12_DISABLE_DOP_GATING REG_BIT(0)
> +
> +#define SARB_CHICKEN1 MCR_REG(0xe90c)
> +#define COMP_CKN_IN REG_GENMASK(30, 29)
> +
> +#define GEN12_RCU_MODE _MMIO(0x14800)
> +#define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0)
> +
> +#define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044)
> +#define FORCEWAKE_KERNEL BIT(0)
> +#define FORCEWAKE_USER BIT(1)
> +#define FORCEWAKE_KERNEL_FALLBACK BIT(15)
> +
> +#define GEN6_GT_CORE_STATUS _MMIO(0x138060)
> +#define GEN6_RC0 0
> +#define GEN6_RC6 3
> +
> +#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
> +#define GEN6_GT_GFX_RC6 _MMIO(0x138108)
> +
> +#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
> +#define GFX_FLSH_CNTL_EN (1 << 0)
> +
> +#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
> +
> +#define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)
> +#define ENGINE1_MASK REG_GENMASK(31, 16)
> +#define ENGINE0_MASK REG_GENMASK(15, 0)
> +
> +#define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
> +
> +#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
> +#define GEN11_INTR_DATA_VALID (1 << 31)
> +#define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
> +#define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)
> +#define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff)
> +#define OTHER_GUC_INSTANCE 0
> +
> +#define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
> +#define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
> +#define GEN12_CCS_RSVD_INTR_ENABLE _MMIO(0x190048)
> +#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
> +#define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
> +#define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
> +#define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
> +#define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
> +#define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
> +#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
> +#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
> +#define GEN12_CCS0_CCS1_INTR_MASK _MMIO(0x190100)
> +#define GEN12_CCS2_CCS3_INTR_MASK _MMIO(0x190104)
> +#define XEHPC_BCS1_BCS2_INTR_MASK _MMIO(0x190110)
> +#define XEHPC_BCS3_BCS4_INTR_MASK _MMIO(0x190114)
> +#define XEHPC_BCS5_BCS6_INTR_MASK _MMIO(0x190118)
> +#define XEHPC_BCS7_BCS8_INTR_MASK _MMIO(0x19011c)
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
> index af2fcf1c32f4..b426f8000070 100644
> --- a/drivers/gpu/drm/xe/xe_execlist.c
> +++ b/drivers/gpu/drm/xe/xe_execlist.c
> @@ -7,6 +7,7 @@
> #include <drm/drm_managed.h>
>
> #include "regs/xe_engine_regs.h"
> +#include "regs/xe_gt_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_engine.h"
> @@ -20,7 +21,6 @@
> #include "xe_sched_job.h"
>
> #include "gt/intel_gpu_commands.h"
> -#include "gt/intel_gt_regs.h"
> #include "gt/intel_lrc_reg.h"
> #include "i915_reg.h"
>
> diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c
> index 188197c3a8fe..e1346d18b580 100644
> --- a/drivers/gpu/drm/xe/xe_force_wake.c
> +++ b/drivers/gpu/drm/xe/xe_force_wake.c
> @@ -6,11 +6,10 @@
>
> #include <drm/drm_util.h>
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_gt.h"
> #include "xe_mmio.h"
>
> -#include "gt/intel_gt_regs.h"
> -
> #define XE_FORCE_WAKE_ACK_TIMEOUT_MS 50
>
> static struct xe_gt *
> diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> index 53a1edaee02d..2c9b2175c5bb 100644
> --- a/drivers/gpu/drm/xe/xe_ggtt.c
> +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> @@ -9,6 +9,7 @@
> #include <drm/drm_managed.h>
> #include <drm/i915_drm.h>
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_gt.h"
> @@ -17,7 +18,6 @@
> #include "xe_mmio.h"
> #include "xe_wopcm.h"
>
> -#include "gt/intel_gt_regs.h"
> #include "i915_reg.h"
>
> /* FIXME: Common file, preferably auto-gen */
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index 5c7c2757bb49..c195b4b9f9b8 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -8,6 +8,7 @@
>
> #include <drm/drm_managed.h>
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_bb.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> @@ -40,8 +41,6 @@
> #include "xe_wa.h"
> #include "xe_wopcm.h"
>
> -#include "gt/intel_gt_regs.h"
> -
> struct xe_gt *xe_find_full_gt(struct xe_gt *gt)
> {
> struct xe_gt *search;
> diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
> index e50117103e1e..e9aa7c5452af 100644
> --- a/drivers/gpu/drm/xe/xe_gt_clock.c
> +++ b/drivers/gpu/drm/xe/xe_gt_clock.c
> @@ -4,12 +4,12 @@
> */
> #include "xe_gt_clock.h"
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_device.h"
> #include "xe_gt.h"
> #include "xe_macros.h"
> #include "xe_mmio.h"
>
> -#include "gt/intel_gt_regs.h"
> #include "i915_reg.h"
>
> static u32 read_reference_ts_freq(struct xe_gt *gt)
> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
> index 43910e48bdc9..c4ede7d6d97c 100644
> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
> @@ -4,13 +4,12 @@
> */
> #include "xe_gt_mcr.h"
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_gt.h"
> #include "xe_gt_topology.h"
> #include "xe_gt_types.h"
> #include "xe_mmio.h"
>
> -#include "gt/intel_gt_regs.h"
> -
> /**
> * DOC: GT Multicast/Replicated (MCR) Register Support
> *
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index 88cc912fa7eb..a2a124a7fc0b 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -4,6 +4,7 @@
> */
> #include "xe_guc.h"
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_force_wake.h"
> @@ -20,7 +21,6 @@
> #include "xe_uc_fw.h"
> #include "xe_wopcm.h"
>
> -#include "gt/intel_gt_regs.h"
> #include "i915_reg_defs.h"
>
> /* TODO: move to common file */
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index bde094388a34..3cf04594f12f 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -9,6 +9,7 @@
> #include <drm/drm_managed.h>
>
> #include "regs/xe_engine_regs.h"
> +#include "regs/xe_gt_regs.h"
> #include "xe_bo.h"
> #include "xe_gt.h"
> #include "xe_guc.h"
> @@ -19,9 +20,6 @@
> #include "xe_mmio.h"
> #include "xe_platform_types.h"
>
> -#include "gt/intel_gt_regs.h"
> -
> -
> /* Slack of a few additional entries per engine */
> #define ADS_REGSET_EXTRA_MAX 8
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> index 1d4ac0c26d3c..f7aaf4826f00 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> @@ -8,6 +8,7 @@
>
> #include <drm/drm_managed.h>
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_gt.h"
> @@ -30,7 +31,6 @@
> #define GEN10_FREQ_INFO_REC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
> #define RPE_MASK REG_GENMASK(15, 8)
>
> -#include "gt/intel_gt_regs.h"
> /* For GEN6_RPNSWREQ.reg to be merged when the definition moves to Xe */
> #define REQ_RATIO_MASK REG_GENMASK(31, 23)
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index ce5d6641499f..caae4f897644 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -7,6 +7,7 @@
> #include <drm/drm_managed.h>
>
> #include "regs/xe_engine_regs.h"
> +#include "regs/xe_gt_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_execlist.h"
> @@ -21,7 +22,6 @@
> #include "xe_sched_job.h"
> #include "xe_wa.h"
>
> -#include "gt/intel_gt_regs.h"
> #include "i915_reg.h"
>
> #define MAX_MMIO_BASES 3
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index f30fd2b14c22..d7756c14b4e2 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -8,6 +8,7 @@
>
> #include <drm/drm_managed.h>
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_device.h"
> #include "xe_display.h"
> #include "xe_drv.h"
> @@ -16,7 +17,6 @@
> #include "xe_hw_engine.h"
> #include "xe_mmio.h"
>
> -#include "gt/intel_gt_regs.h"
> #include "i915_reg.h"
>
> static void gen3_assert_iir_is_zero(struct xe_gt *gt, i915_reg_t reg)
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index 60ffe3f80c59..8e341d11f2e3 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -5,6 +5,7 @@
> #include "xe_lrc.h"
>
> #include "regs/xe_engine_regs.h"
> +#include "regs/xe_gt_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_engine_types.h"
> @@ -14,7 +15,6 @@
> #include "xe_vm.h"
>
> #include "gt/intel_gpu_commands.h"
> -#include "gt/intel_gt_regs.h"
> #include "gt/intel_lrc_reg.h"
> #include "i915_reg.h"
>
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index 892008dcbaf4..d0cd9e920d34 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -8,13 +8,13 @@
> #include <drm/xe_drm.h>
>
> #include "regs/xe_engine_regs.h"
> +#include "regs/xe_gt_regs.h"
> #include "xe_device.h"
> #include "xe_gt.h"
> #include "xe_gt_mcr.h"
> #include "xe_macros.h"
> #include "xe_module.h"
>
> -#include "gt/intel_gt_regs.h"
> #include "i915_reg.h"
>
> #define XEHP_MTCFG_ADDR _MMIO(0x101800)
> diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
> index 99d3cc6c7164..173f5c4321f5 100644
> --- a/drivers/gpu/drm/xe/xe_mocs.c
> +++ b/drivers/gpu/drm/xe/xe_mocs.c
> @@ -4,6 +4,7 @@
> */
> #include "xe_mocs.h"
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_engine.h"
> @@ -12,8 +13,6 @@
> #include "xe_platform_types.h"
> #include "xe_step_types.h"
>
> -#include "gt/intel_gt_regs.h"
> -
> #if IS_ENABLED(CONFIG_DRM_XE_DEBUG)
> #define mocs_dbg drm_dbg
> #else
> diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
> index bd3b64ad9c26..6519c6648460 100644
> --- a/drivers/gpu/drm/xe/xe_reg_sr.c
> +++ b/drivers/gpu/drm/xe/xe_reg_sr.c
> @@ -12,6 +12,7 @@
> #include <drm/drm_print.h>
>
> #include "regs/xe_engine_regs.h"
> +#include "regs/xe_gt_regs.h"
> #include "xe_device_types.h"
> #include "xe_force_wake.h"
> #include "xe_gt.h"
> @@ -20,8 +21,6 @@
> #include "xe_mmio.h"
> #include "xe_rtp_types.h"
>
> -#include "gt/intel_gt_regs.h"
> -
> #define XE_REG_SR_GROW_STEP_DEFAULT 16
>
> static void reg_sr_fini(struct drm_device *drm, void *arg)
> diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> index e2f3f374b856..66ff9da46070 100644
> --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> @@ -5,12 +5,11 @@
> #include "xe_reg_whitelist.h"
>
> #include "regs/xe_engine_regs.h"
> +#include "regs/xe_gt_regs.h"
> #include "xe_gt_types.h"
> #include "xe_platform_types.h"
> #include "xe_rtp.h"
>
> -#include "gt/intel_gt_regs.h"
> -
> #undef _MMIO
> #undef MCR_REG
> #define _MMIO(x) _XE_RTP_REG(x)
> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
> index 5049367bc92d..a7ab0d4451f0 100644
> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> @@ -4,6 +4,7 @@
> */
> #include "xe_ring_ops.h"
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_engine_types.h"
> #include "xe_gt.h"
> #include "xe_lrc.h"
> @@ -12,7 +13,6 @@
> #include "xe_vm_types.h"
>
> #include "gt/intel_gpu_commands.h"
> -#include "gt/intel_gt_regs.h"
> #include "gt/intel_lrc_reg.h"
> #include "i915_reg.h"
>
> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> index 5f8c56baaeba..cda2da27f7c6 100644
> --- a/drivers/gpu/drm/xe/xe_tuning.c
> +++ b/drivers/gpu/drm/xe/xe_tuning.c
> @@ -5,12 +5,11 @@
>
> #include "xe_tuning.h"
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_gt_types.h"
> #include "xe_platform_types.h"
> #include "xe_rtp.h"
>
> -#include "gt/intel_gt_regs.h"
> -
> #undef _MMIO
> #undef MCR_REG
> #define _MMIO(x) _XE_RTP_REG(x)
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index 92065341c001..155cfd1dcc50 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -8,6 +8,7 @@
> #include <linux/compiler_types.h>
>
> #include "regs/xe_engine_regs.h"
> +#include "regs/xe_gt_regs.h"
> #include "xe_device_types.h"
> #include "xe_force_wake.h"
> #include "xe_gt.h"
> @@ -17,7 +18,6 @@
> #include "xe_rtp.h"
> #include "xe_step.h"
>
> -#include "gt/intel_gt_regs.h"
> #include "i915_reg.h"
>
> /**
> --
> 2.39.0
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 09/11] drm/xe/guc_pc: Move gt register to the proper place
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 09/11] drm/xe/guc_pc: Move gt register to the proper place Lucas De Marchi
@ 2023-02-17 20:23 ` Rodrigo Vivi
2023-02-17 22:11 ` Lucas De Marchi
0 siblings, 1 reply; 42+ messages in thread
From: Rodrigo Vivi @ 2023-02-17 20:23 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe, Maarten Lankhorst, Matthew Auld
On Thu, Feb 16, 2023 at 04:52:24PM -0800, Lucas De Marchi wrote:
> Move a few defines from xe_guc_pc.c to the right register, now that
> there is one: xe_gt_regs.h.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 ++
> drivers/gpu/drm/xe/xe_guc_pc.c | 6 ------
> 2 files changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index da40133252fb..ab8c9e51f62e 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -186,6 +186,7 @@
> #define DFR_DISABLE (1 << 9)
>
> #define GEN6_RPNSWREQ _MMIO(0xa008)
> +#define REQ_RATIO_MASK REG_GENMASK(31, 23)
> #define GEN6_RC_CONTROL _MMIO(0xa090)
> #define GEN6_RC_STATE _MMIO(0xa094)
>
> @@ -242,6 +243,7 @@
> #define FORCEWAKE_KERNEL_FALLBACK BIT(15)
>
> #define GEN6_GT_CORE_STATUS _MMIO(0x138060)
> +#define RCN_MASK REG_GENMASK(2, 0)
> #define GEN6_RC0 0
> #define GEN6_RC6 3
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> index 0df82defa7e4..3465236b0b49 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> @@ -30,12 +30,6 @@
> #define GEN10_FREQ_INFO_REC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
> #define RPE_MASK REG_GENMASK(15, 8)
I don't like this getting split from the rest... but I don't have
any quick better recommendation and the movement below at least is correct
by itself. So,
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> -/* For GEN6_RPNSWREQ.reg to be merged when the definition moves to Xe */
> -#define REQ_RATIO_MASK REG_GENMASK(31, 23)
> -
> -/* For GEN6_GT_CORE_STATUS.reg to be merged when the definition moves to Xe */
> -#define RCN_MASK REG_GENMASK(2, 0)
> -
> #define GEN12_RPSTAT1 _MMIO(0x1381b4)
> #define GEN12_CAGF_MASK REG_GENMASK(19, 11)
>
> --
> 2.39.0
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 08/11] drm/xe: Remove dependency on i915_reg.h
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 08/11] drm/xe: Remove dependency on i915_reg.h Lucas De Marchi
@ 2023-02-17 20:27 ` Rodrigo Vivi
2023-02-17 22:22 ` Lucas De Marchi
0 siblings, 1 reply; 42+ messages in thread
From: Rodrigo Vivi @ 2023-02-17 20:27 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe, Maarten Lankhorst, Matthew Auld
On Thu, Feb 16, 2023 at 04:52:23PM -0800, Lucas De Marchi wrote:
> Copy the macros used by xe in i915_reg.h to regs/xe_regs.h. A minimal
> cleanup is done while copying so they adhere minimally to the coding
> style. Further reordering and cleaning is left for later.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_regs.h | 111 +++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_execlist.c | 3 +-
> drivers/gpu/drm/xe/xe_ggtt.c | 3 +-
> drivers/gpu/drm/xe/xe_gt_clock.c | 3 +-
> drivers/gpu/drm/xe/xe_guc_pc.c | 3 +-
> drivers/gpu/drm/xe/xe_hw_engine.c | 3 +-
> drivers/gpu/drm/xe/xe_irq.c | 3 +-
> drivers/gpu/drm/xe/xe_lrc.c | 3 +-
> drivers/gpu/drm/xe/xe_mmio.c | 3 +-
> drivers/gpu/drm/xe/xe_pci.c | 3 +-
> drivers/gpu/drm/xe/xe_ring_ops.c | 3 +-
> drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 3 +-
> drivers/gpu/drm/xe/xe_wa.c | 3 +-
> 13 files changed, 123 insertions(+), 24 deletions(-)
> create mode 100644 drivers/gpu/drm/xe/regs/xe_regs.h
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
> new file mode 100644
> index 000000000000..53f1ed54fb1c
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/regs/xe_regs.h
> @@ -0,0 +1,111 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +#ifndef _XE_REGS_H_
> +#define _XE_REGS_H_
> +
> +#include "i915_reg_defs.h"
> +
> +#define GU_CNTL _MMIO(0x101010)
> +#define LMEM_INIT REG_BIT(7)
> +
> +#define RENDER_RING_BASE 0x02000
> +#define BSD_RING_BASE 0x04000
> +#define GEN6_BSD_RING_BASE 0x12000
> +#define GEN8_BSD2_RING_BASE 0x1c000
> +#define GEN11_BSD_RING_BASE 0x1c0000
> +#define GEN11_BSD2_RING_BASE 0x1c4000
> +#define GEN11_BSD3_RING_BASE 0x1d0000
> +#define GEN11_BSD4_RING_BASE 0x1d4000
> +#define XEHP_BSD5_RING_BASE 0x1e0000
> +#define XEHP_BSD6_RING_BASE 0x1e4000
> +#define XEHP_BSD7_RING_BASE 0x1f0000
> +#define XEHP_BSD8_RING_BASE 0x1f4000
> +#define VEBOX_RING_BASE 0x1a000
> +#define GEN11_VEBOX_RING_BASE 0x1c8000
> +#define GEN11_VEBOX2_RING_BASE 0x1d8000
> +#define XEHP_VEBOX3_RING_BASE 0x1e8000
> +#define XEHP_VEBOX4_RING_BASE 0x1f8000
> +#define GEN12_COMPUTE0_RING_BASE 0x1a000
> +#define GEN12_COMPUTE1_RING_BASE 0x1c000
> +#define GEN12_COMPUTE2_RING_BASE 0x1e000
> +#define GEN12_COMPUTE3_RING_BASE 0x26000
> +#define BLT_RING_BASE 0x22000
> +#define XEHPC_BCS1_RING_BASE 0x3e0000
> +#define XEHPC_BCS2_RING_BASE 0x3e2000
> +#define XEHPC_BCS3_RING_BASE 0x3e4000
> +#define XEHPC_BCS4_RING_BASE 0x3e6000
> +#define XEHPC_BCS5_RING_BASE 0x3e8000
> +#define XEHPC_BCS6_RING_BASE 0x3ea000
> +#define XEHPC_BCS7_RING_BASE 0x3ec000
> +#define XEHPC_BCS8_RING_BASE 0x3ee000
> +#define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11)
> +#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
> +#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
> +#define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
> +#define GT_RENDER_USER_INTERRUPT (1 << 0)
> +
> +#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
> +#define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
> +
> +#define PVC_RP_STATE_CAP _MMIO(0x281014)
> +#define MTL_RP_STATE_CAP _MMIO(0x138000)
> +
> +#define MTL_MEDIAP_STATE_CAP _MMIO(0x138020)
> +#define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
> +#define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
> +
> +#define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c)
> +#define MTL_MPE_FREQUENCY _MMIO(0x13802c)
> +#define MTL_RPE_MASK REG_GENMASK(8, 0)
> +
> +#define TRANSCODER_A_OFFSET 0x60000
> +#define TRANSCODER_B_OFFSET 0x61000
> +#define TRANSCODER_C_OFFSET 0x62000
> +#define TRANSCODER_D_OFFSET 0x63000
> +#define TRANSCODER_DSI0_OFFSET 0x6b000
> +#define TRANSCODER_DSI1_OFFSET 0x6b800
> +#define PIPE_A_OFFSET 0x70000
> +#define PIPE_B_OFFSET 0x71000
> +#define PIPE_C_OFFSET 0x72000
> +#define PIPE_D_OFFSET 0x73000
> +#define PIPE_DSI0_OFFSET 0x7b000
> +#define PIPE_DSI1_OFFSET 0x7b800
> +
> +#define GEN8_PCU_ISR _MMIO(0x444e0)
> +#define GEN8_PCU_IMR _MMIO(0x444e4)
> +#define GEN8_PCU_IIR _MMIO(0x444e8)
> +#define GEN8_PCU_IER _MMIO(0x444ec)
> +
> +#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
> +#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
> +#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
> +#define GEN11_GU_MISC_IER _MMIO(0x444fc)
> +#define GEN11_GU_MISC_GSE (1 << 27)
> +
> +#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
> +#define GEN11_MASTER_IRQ (1 << 31)
> +#define GEN11_GU_MISC_IRQ (1 << 29)
> +#define GEN11_DISPLAY_IRQ (1 << 16)
> +#define GEN11_GT_DW_IRQ(x) (1 << (x))
> +
> +#define DG1_MSTR_TILE_INTR _MMIO(0x190008)
> +#define DG1_MSTR_IRQ REG_BIT(31)
> +#define DG1_MSTR_TILE(t) REG_BIT(t)
> +
> +#define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
> +#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
> +#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
> +#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
> +#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
> +
> +#define GGC _MMIO(0x108040)
> +#define GMS_MASK REG_GENMASK(15, 8)
> +#define GGMS_MASK REG_GENMASK(7, 6)
one of the things that I'm always confused is with these REG_{BIT,GENMASK,FIELD_PREP}.
Why can't we simply use the regular "non-REG_" versions like every other driver
(aside of i915 of course).
> +
> +#define GEN12_GSMBASE _MMIO(0x108100)
> +#define GEN12_DSMBASE _MMIO(0x1080C0)
> +#define GEN12_BDSM_MASK REG_GENMASK64(63, 20)
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
> index c3c52bdc70b1..ad097918b496 100644
> --- a/drivers/gpu/drm/xe/xe_execlist.c
> +++ b/drivers/gpu/drm/xe/xe_execlist.c
> @@ -10,6 +10,7 @@
> #include "regs/xe_lrc_regs.h"
> #include "regs/xe_gpu_commands.h"
> #include "regs/xe_gt_regs.h"
> +#include "regs/xe_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_engine.h"
> @@ -22,8 +23,6 @@
> #include "xe_ring_ops_types.h"
> #include "xe_sched_job.h"
>
> -#include "i915_reg.h"
> -
> #define XE_EXECLIST_HANG_LIMIT 1
>
> #define GEN11_SW_CTX_ID_SHIFT 37
> diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> index 2c9b2175c5bb..6674297fa25e 100644
> --- a/drivers/gpu/drm/xe/xe_ggtt.c
> +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> @@ -10,6 +10,7 @@
> #include <drm/i915_drm.h>
>
> #include "regs/xe_gt_regs.h"
> +#include "regs/xe_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_gt.h"
> @@ -18,8 +19,6 @@
> #include "xe_mmio.h"
> #include "xe_wopcm.h"
>
> -#include "i915_reg.h"
> -
> /* FIXME: Common file, preferably auto-gen */
> #define MTL_GGTT_PTE_PAT0 BIT_ULL(52)
> #define MTL_GGTT_PTE_PAT1 BIT_ULL(53)
> diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
> index e9aa7c5452af..cbf9c96c142c 100644
> --- a/drivers/gpu/drm/xe/xe_gt_clock.c
> +++ b/drivers/gpu/drm/xe/xe_gt_clock.c
> @@ -5,13 +5,12 @@
> #include "xe_gt_clock.h"
>
> #include "regs/xe_gt_regs.h"
> +#include "regs/xe_regs.h"
> #include "xe_device.h"
> #include "xe_gt.h"
> #include "xe_macros.h"
> #include "xe_mmio.h"
>
> -#include "i915_reg.h"
> -
> static u32 read_reference_ts_freq(struct xe_gt *gt)
> {
> u32 ts_override = xe_mmio_read32(gt, GEN9_TIMESTAMP_OVERRIDE.reg);
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> index f7aaf4826f00..0df82defa7e4 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> @@ -9,6 +9,7 @@
> #include <drm/drm_managed.h>
>
> #include "regs/xe_gt_regs.h"
> +#include "regs/xe_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_gt.h"
> @@ -19,8 +20,6 @@
> #include "xe_mmio.h"
> #include "xe_pcode.h"
>
> -#include "i915_reg.h"
> -#include "i915_reg_defs.h"
> #include "intel_mchbar_regs.h"
>
> /* For GEN6_RP_STATE_CAP.reg to be merged when the definition moves to Xe */
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index caae4f897644..2b49ccba0ce9 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -8,6 +8,7 @@
>
> #include "regs/xe_engine_regs.h"
> #include "regs/xe_gt_regs.h"
> +#include "regs/xe_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_execlist.h"
> @@ -22,8 +23,6 @@
> #include "xe_sched_job.h"
> #include "xe_wa.h"
>
> -#include "i915_reg.h"
> -
> #define MAX_MMIO_BASES 3
> struct engine_info {
> const char *name;
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index d7756c14b4e2..f4f84a16dd83 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -9,6 +9,7 @@
> #include <drm/drm_managed.h>
>
> #include "regs/xe_gt_regs.h"
> +#include "regs/xe_regs.h"
> #include "xe_device.h"
> #include "xe_display.h"
> #include "xe_drv.h"
> @@ -17,8 +18,6 @@
> #include "xe_hw_engine.h"
> #include "xe_mmio.h"
>
> -#include "i915_reg.h"
> -
> static void gen3_assert_iir_is_zero(struct xe_gt *gt, i915_reg_t reg)
> {
> u32 val = xe_mmio_read32(gt, reg.reg);
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index c1df76c2cf78..261eabaae369 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -8,6 +8,7 @@
> #include "regs/xe_lrc_regs.h"
> #include "regs/xe_gpu_commands.h"
> #include "regs/xe_gt_regs.h"
> +#include "regs/xe_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_engine_types.h"
> @@ -16,8 +17,6 @@
> #include "xe_map.h"
> #include "xe_vm.h"
>
> -#include "i915_reg.h"
> -
> #define GEN8_CTX_VALID (1 << 0)
> #define GEN8_CTX_L3LLC_COHERENT (1 << 5)
> #define GEN8_CTX_PRIVILEGE (1 << 8)
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index d0cd9e920d34..262d33e59d26 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -9,14 +9,13 @@
>
> #include "regs/xe_engine_regs.h"
> #include "regs/xe_gt_regs.h"
> +#include "regs/xe_regs.h"
> #include "xe_device.h"
> #include "xe_gt.h"
> #include "xe_gt_mcr.h"
> #include "xe_macros.h"
> #include "xe_module.h"
>
> -#include "i915_reg.h"
> -
> #define XEHP_MTCFG_ADDR _MMIO(0x101800)
> #define TILE_COUNT REG_GENMASK(15, 8)
> #define GEN12_LMEM_BAR 2
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index b0e5c402190c..4ecde7c2e619 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -13,6 +13,7 @@
> #include <drm/drm_drv.h>
> #include <drm/xe_pciids.h>
>
> +#include "regs/xe_regs.h"
> #include "xe_device.h"
> #include "xe_drv.h"
> #include "xe_macros.h"
> @@ -20,8 +21,6 @@
> #include "xe_pm.h"
> #include "xe_step.h"
>
> -#include "i915_reg.h"
> -
> #define DEV_INFO_FOR_EACH_FLAG(func) \
> func(require_force_probe); \
> func(is_dgfx); \
> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
> index 104f96658e1f..ba3bde117af1 100644
> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> @@ -7,6 +7,7 @@
> #include "regs/xe_lrc_regs.h"
> #include "regs/xe_gpu_commands.h"
> #include "regs/xe_gt_regs.h"
> +#include "regs/xe_regs.h"
> #include "xe_engine_types.h"
> #include "xe_gt.h"
> #include "xe_lrc.h"
> @@ -14,8 +15,6 @@
> #include "xe_sched_job.h"
> #include "xe_vm_types.h"
>
> -#include "i915_reg.h"
> -
> static u32 preparser_disable(bool state)
> {
> return MI_ARB_CHECK | BIT(8) | state;
> diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
> index 1c3783becefd..19828e003283 100644
> --- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
> +++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
> @@ -11,8 +11,7 @@
> #include <drm/ttm/ttm_placement.h>
> #include <drm/ttm/ttm_range_manager.h>
>
> -#include "../i915/i915_reg.h"
> -
> +#include "regs/xe_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_gt.h"
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index 155cfd1dcc50..df72b15dfeb0 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -9,6 +9,7 @@
>
> #include "regs/xe_engine_regs.h"
> #include "regs/xe_gt_regs.h"
> +#include "regs/xe_regs.h"
> #include "xe_device_types.h"
> #include "xe_force_wake.h"
> #include "xe_gt.h"
> @@ -18,8 +19,6 @@
> #include "xe_rtp.h"
> #include "xe_step.h"
>
> -#include "i915_reg.h"
> -
> /**
> * DOC: Hardware workarounds
> *
> --
> 2.39.0
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 11/11] drm/xe: Use relative includes for i915_reg_defs.h
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 11/11] drm/xe: Use relative includes for i915_reg_defs.h Lucas De Marchi
2023-02-17 16:33 ` Lucas De Marchi
@ 2023-02-17 20:28 ` Rodrigo Vivi
2023-02-17 22:30 ` Lucas De Marchi
1 sibling, 1 reply; 42+ messages in thread
From: Rodrigo Vivi @ 2023-02-17 20:28 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe, Maarten Lankhorst, Matthew Auld
On Thu, Feb 16, 2023 at 04:52:26PM -0800, Lucas De Marchi wrote:
> With the goal of eliminating i915 includes from xe outside of the
> display area, it's better to use relative includes for the only shared
> header, i915_reg_defs.h. With this the build system can be changed to
> stop adding i915 as an include dir.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/xe/display/Makefile | 120 +++++++++++++++++++++++
> drivers/gpu/drm/xe/regs/xe_engine_regs.h | 2 +-
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
> drivers/gpu/drm/xe/regs/xe_regs.h | 2 +-
> drivers/gpu/drm/xe/xe_gt_mcr.h | 2 +-
> drivers/gpu/drm/xe/xe_guc.c | 2 -
> drivers/gpu/drm/xe/xe_guc_reg.h | 2 +-
> drivers/gpu/drm/xe/xe_reg_sr_types.h | 2 -
> drivers/gpu/drm/xe/xe_rtp.h | 2 -
> drivers/gpu/drm/xe/xe_rtp_types.h | 2 -
> 10 files changed, 125 insertions(+), 13 deletions(-)
> create mode 100644 drivers/gpu/drm/xe/display/Makefile
>
> diff --git a/drivers/gpu/drm/xe/display/Makefile b/drivers/gpu/drm/xe/display/Makefile
> new file mode 100644
> index 000000000000..eee576972427
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/display/Makefile
shouldn't this patch also be modifying the drm/xe/Makefile?
> @@ -0,0 +1,120 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +subdir-ccflags-y += -I$(srctree)/$(src)
> +
> +# i915 Display compat #defines and #includes
> +subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += -I$(srctree)/$(src)/display/ext \
> + -I$(srctree)/drivers/gpu/drm/xe/display/ \
> + -I$(srctree)/drivers/gpu/drm/i915/display/ \
> + -I$(srctree)/drivers/gpu/drm/i915/ \
> + -DBUILD_FOR_XE=1 \
> + -Ddrm_i915_gem_object=xe_bo \
> + -Ddrm_i915_private=xe_device
> +
> +CFLAGS_display/intel_fbdev.o = $(call cc-disable-warning, override-init)
> +
> +$(obj)/display/i915_%.o: $(srctree)/drivers/gpu/drm/i915/display/i915_%.c FORCE
> + $(call cmd,force_checksrc)
> + $(call if_changed_rule,cc_o_c)
> +
> +$(obj)/display/skl_%.o: $(srctree)/drivers/gpu/drm/i915/display/skl_%.c FORCE
> + $(call cmd,force_checksrc)
> + $(call if_changed_rule,cc_o_c)
> +
> +$(obj)/display/icl_dsi.o: $(srctree)/drivers/gpu/drm/i915/display/icl_dsi.c FORCE
> + $(call cmd,force_checksrc)
> + $(call if_changed_rule,cc_o_c)
> +
> +$(obj)/display/intel_%.o: $(srctree)/drivers/gpu/drm/i915/display/intel_%.c FORCE
> + $(call cmd,force_checksrc)
> + $(call if_changed_rule,cc_o_c)
> +
> +# Display..
> +xe-$(CONFIG_DRM_XE_DISPLAY) += \
> + xe_display.o \
> + display/icl_dsi.o \
> + display/intel_atomic.o \
> + display/intel_atomic_plane.o \
> + display/intel_audio.o \
> + display/intel_backlight.o \
> + display/intel_bios.o \
> + display/intel_bw.o \
> + display/intel_cdclk.o \
> + display/intel_color.o \
> + display/intel_combo_phy.o \
> + display/intel_connector.o \
> + display/intel_crtc_state_dump.o \
> + display/intel_crtc.o \
> + display/intel_cursor.o \
> + display/intel_ddi_buf_trans.o \
> + display/intel_ddi.o \
> + display/intel_display.o \
> + display/intel_display_debugfs.o \
> + display/intel_display_power.o \
> + display/intel_display_power_map.o \
> + display/intel_display_power_well.o \
> + display/intel_display_trace.o \
> + display/intel_dkl_phy.o \
> + display/intel_dmc.o \
> + display/intel_dp_aux_backlight.o \
> + display/intel_dp_aux.o \
> + display/intel_dp.o \
> + display/intel_dp_hdcp.o \
> + display/intel_dp_link_training.o \
> + display/intel_dpll.o \
> + display/intel_dpll_mgr.o \
> + display/intel_dp_mst.o \
> + display/intel_drrs.o \
> + display/intel_dsb.o \
> + display/intel_dsi.o \
> + display/intel_dsi_dcs_backlight.o \
> + display/intel_dsi_vbt.o \
> + display/intel_fb.o \
> + display/intel_fbc.o \
> + display/intel_fdi.o \
> + display/intel_fifo_underrun.o \
> + display/intel_frontbuffer.o \
> + display/intel_global_state.o \
> + display/intel_gmbus.o \
> + display/intel_hdcp.o \
> + display/intel_hdmi.o \
> + display/intel_hotplug.o \
> + display/intel_hti.o \
> + display/intel_lspcon.o \
> + display/intel_lvds.o \
> + display/intel_modeset_setup.o \
> + display/intel_modeset_verify.o \
> + display/intel_panel.o \
> + display/intel_pipe_crc.o \
> + display/intel_pps.o \
> + display/intel_psr.o \
> + display/intel_qp_tables.o \
> + display/intel_quirks.o \
> + display/intel_snps_phy.o \
> + display/intel_sprite.o \
> + display/intel_tc.o \
> + display/intel_vdsc.o \
> + display/intel_vga.o \
> + display/intel_vrr.o \
> + display/xe_fb_pin.o \
> + display/xe_plane_initial.o \
> + display/skl_scaler.o \
> + display/skl_universal_plane.o \
> + display/skl_watermark.o \
> + display/ext/i915_irq.o \
> + display/ext/intel_device_info.o \
> + display/ext/intel_dram.o \
> + display/ext/intel_pch.o \
> + display/ext/intel_pm.o
> +
> +ifeq ($(CONFIG_ACPI),y)
> + xe-$(CONFIG_DRM_XE_DISPLAY) += \
> + display/intel_acpi.o \
> + display/intel_opregion.o
> +endif
> +
> +ifeq ($(CONFIG_DRM_FBDEV_EMULATION),y)
> + xe-$(CONFIG_DRM_XE_DISPLAY) += display/intel_fbdev.o
> +endif
> +
> +
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index 6dfa3cf2fd43..a8f48a43b854 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -8,7 +8,7 @@
>
> #include <asm/page.h>
>
> -#include "i915_reg_defs.h"
> +#include "../../i915/i915_reg_defs.h"
>
> #define RING_TAIL(base) _MMIO((base) + 0x30)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index ab8c9e51f62e..2a2ebc7baeda 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -6,7 +6,7 @@
> #ifndef _XE_GT_REGS_H_
> #define _XE_GT_REGS_H_
>
> -#include "i915_reg_defs.h"
> +#include "../../i915/i915_reg_defs.h"
>
> /* RPM unit config (Gen8+) */
> #define RPM_CONFIG0 _MMIO(0xd00)
> diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
> index 53f1ed54fb1c..f81f537c1ec1 100644
> --- a/drivers/gpu/drm/xe/regs/xe_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_regs.h
> @@ -5,7 +5,7 @@
> #ifndef _XE_REGS_H_
> #define _XE_REGS_H_
>
> -#include "i915_reg_defs.h"
> +#include "../../i915/i915_reg_defs.h"
>
> #define GU_CNTL _MMIO(0x101010)
> #define LMEM_INIT REG_BIT(7)
> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.h b/drivers/gpu/drm/xe/xe_gt_mcr.h
> index c31987d2177c..3f76233f88c3 100644
> --- a/drivers/gpu/drm/xe/xe_gt_mcr.h
> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.h
> @@ -6,7 +6,7 @@
> #ifndef _XE_GT_MCR_H_
> #define _XE_GT_MCR_H_
>
> -#include "i915_reg_defs.h"
> +#include "../i915/i915_reg_defs.h"
>
> struct drm_printer;
> struct xe_gt;
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index a2a124a7fc0b..6eefefd80ff9 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -21,8 +21,6 @@
> #include "xe_uc_fw.h"
> #include "xe_wopcm.h"
>
> -#include "i915_reg_defs.h"
> -
> /* TODO: move to common file */
> #define GUC_PVC_MOCS_INDEX_MASK REG_GENMASK(25, 24)
> #define PVC_MOCS_UC_INDEX 1
> diff --git a/drivers/gpu/drm/xe/xe_guc_reg.h b/drivers/gpu/drm/xe/xe_guc_reg.h
> index 513a7e0c8a5a..234236833239 100644
> --- a/drivers/gpu/drm/xe/xe_guc_reg.h
> +++ b/drivers/gpu/drm/xe/xe_guc_reg.h
> @@ -9,7 +9,7 @@
> #include <linux/compiler.h>
> #include <linux/types.h>
>
> -#include "i915_reg_defs.h"
> +#include "../i915/i915_reg_defs.h"
>
> /* Definitions of GuC H/W registers, bits, etc */
>
> diff --git a/drivers/gpu/drm/xe/xe_reg_sr_types.h b/drivers/gpu/drm/xe/xe_reg_sr_types.h
> index 2fa7ff3966ba..8a317ce428a4 100644
> --- a/drivers/gpu/drm/xe/xe_reg_sr_types.h
> +++ b/drivers/gpu/drm/xe/xe_reg_sr_types.h
> @@ -9,8 +9,6 @@
> #include <linux/xarray.h>
> #include <linux/types.h>
>
> -#include "i915_reg_defs.h"
> -
> struct xe_reg_sr_entry {
> u32 clr_bits;
> u32 set_bits;
> diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
> index 1ac3fd1c0734..099047af89b4 100644
> --- a/drivers/gpu/drm/xe/xe_rtp.h
> +++ b/drivers/gpu/drm/xe/xe_rtp.h
> @@ -11,8 +11,6 @@
>
> #include "xe_rtp_types.h"
>
> -#include "i915_reg_defs.h"
> -
> /*
> * Register table poke infrastructure
> */
> diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
> index fac0bd6d5b1e..e87f1b280d96 100644
> --- a/drivers/gpu/drm/xe/xe_rtp_types.h
> +++ b/drivers/gpu/drm/xe/xe_rtp_types.h
> @@ -8,8 +8,6 @@
>
> #include <linux/types.h>
>
> -#include "i915_reg_defs.h"
> -
> struct xe_hw_engine;
> struct xe_gt;
>
> --
> 2.39.0
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 05/11] drm/xe: Remove dependency on intel_gt_regs.h
2023-02-17 20:20 ` Rodrigo Vivi
@ 2023-02-17 22:08 ` Lucas De Marchi
0 siblings, 0 replies; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-17 22:08 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-xe, Maarten Lankhorst, Matthew Auld
On Fri, Feb 17, 2023 at 03:20:38PM -0500, Rodrigo Vivi wrote:
>On Thu, Feb 16, 2023 at 04:52:20PM -0800, Lucas De Marchi wrote:
>> Create regs/xe_gt_regs.h file with all the registers and bit
>> definitions used by the xe driver. Eventually the registers may be
>> defined in a different way and since xe doesn't supported below gen12,
>> the number of registers touched is much smaller, so create a new header.
>>
>> The definitions themselves are direct copy from the
>> gt/intel_gt_regs.h file, just sorting the registers by address.
>> Cleaning those up and adhering to a common coding style is left for
>> later.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg_defs.h | 2 +
>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 287 ++++++++++++++++++++++++++
>> drivers/gpu/drm/xe/xe_execlist.c | 2 +-
>> drivers/gpu/drm/xe/xe_force_wake.c | 3 +-
>> drivers/gpu/drm/xe/xe_ggtt.c | 2 +-
>> drivers/gpu/drm/xe/xe_gt.c | 3 +-
>> drivers/gpu/drm/xe/xe_gt_clock.c | 2 +-
>> drivers/gpu/drm/xe/xe_gt_mcr.c | 3 +-
>> drivers/gpu/drm/xe/xe_guc.c | 2 +-
>> drivers/gpu/drm/xe/xe_guc_ads.c | 4 +-
>> drivers/gpu/drm/xe/xe_guc_pc.c | 2 +-
>> drivers/gpu/drm/xe/xe_hw_engine.c | 2 +-
>> drivers/gpu/drm/xe/xe_irq.c | 2 +-
>> drivers/gpu/drm/xe/xe_lrc.c | 2 +-
>> drivers/gpu/drm/xe/xe_mmio.c | 2 +-
>> drivers/gpu/drm/xe/xe_mocs.c | 3 +-
>> drivers/gpu/drm/xe/xe_reg_sr.c | 3 +-
>> drivers/gpu/drm/xe/xe_reg_whitelist.c | 3 +-
>> drivers/gpu/drm/xe/xe_ring_ops.c | 2 +-
>> drivers/gpu/drm/xe/xe_tuning.c | 3 +-
>> drivers/gpu/drm/xe/xe_wa.c | 2 +-
>> 21 files changed, 308 insertions(+), 28 deletions(-)
>> create mode 100644 drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
>> index b5e06b6a9478..a6080c983a77 100644
>> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
>> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
>> @@ -136,6 +136,8 @@ typedef struct {
>> u32 reg;
>> } i915_mcr_reg_t;
>>
>> +#define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg = (offset) })
>> +
>> #define INVALID_MMIO_REG _MMIO(0)
>>
>> /*
>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> new file mode 100644
>> index 000000000000..da40133252fb
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> @@ -0,0 +1,287 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_GT_REGS_H_
>> +#define _XE_GT_REGS_H_
>> +
>> +#include "i915_reg_defs.h"
>> +
>> +/* RPM unit config (Gen8+) */
>> +#define RPM_CONFIG0 _MMIO(0xd00)
>> +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
>
>https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/215
>https://lore.kernel.org/all/Y9hw0sSC58B32yPg@mdroper-desk1.amr.corp.intel.com/
>
>Matt has asked us to get rid of the GEN stuff...
>I believe this is a great opportunity, although I believe it is not
>a blocker and could be done later.
I have that issue assigned to me so I don't forget. However I'd separate
the rather manual movement here from any cleanup. It's too easy to land
regressions because of a typo while converting coding style together
with a big code move like this. From the commit message:
The definitions themselves are direct copy from the
gt/intel_gt_regs.h file, just sorting the registers by address.
Cleaning those up and adhering to a common coding style is left for
later.
thanks
Lucas De Marchi
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 09/11] drm/xe/guc_pc: Move gt register to the proper place
2023-02-17 20:23 ` Rodrigo Vivi
@ 2023-02-17 22:11 ` Lucas De Marchi
0 siblings, 0 replies; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-17 22:11 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-xe, Maarten Lankhorst, Matthew Auld
On Fri, Feb 17, 2023 at 03:23:10PM -0500, Rodrigo Vivi wrote:
>On Thu, Feb 16, 2023 at 04:52:24PM -0800, Lucas De Marchi wrote:
>> Move a few defines from xe_guc_pc.c to the right register, now that
>> there is one: xe_gt_regs.h.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 ++
>> drivers/gpu/drm/xe/xe_guc_pc.c | 6 ------
>> 2 files changed, 2 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> index da40133252fb..ab8c9e51f62e 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> @@ -186,6 +186,7 @@
>> #define DFR_DISABLE (1 << 9)
>>
>> #define GEN6_RPNSWREQ _MMIO(0xa008)
>> +#define REQ_RATIO_MASK REG_GENMASK(31, 23)
>> #define GEN6_RC_CONTROL _MMIO(0xa090)
>> #define GEN6_RC_STATE _MMIO(0xa094)
>>
>> @@ -242,6 +243,7 @@
>> #define FORCEWAKE_KERNEL_FALLBACK BIT(15)
>>
>> #define GEN6_GT_CORE_STATUS _MMIO(0x138060)
>> +#define RCN_MASK REG_GENMASK(2, 0)
>> #define GEN6_RC0 0
>> #define GEN6_RC6 3
>>
>> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
>> index 0df82defa7e4..3465236b0b49 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
>> @@ -30,12 +30,6 @@
>> #define GEN10_FREQ_INFO_REC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
>> #define RPE_MASK REG_GENMASK(15, 8)
>
>I don't like this getting split from the rest... but I don't have
>any quick better recommendation and the movement below at least is correct
>by itself. So,
>
we could add regs/xe_mchbar_regs.h and move these there. Although if
there is single compilation unit that needs that, we may as well leave
it there. Eventually if we agree on autogenerating the headers, then
we'd have everything unders regs/
>
>Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
thanks
Lucas De Marchi
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 08/11] drm/xe: Remove dependency on i915_reg.h
2023-02-17 20:27 ` Rodrigo Vivi
@ 2023-02-17 22:22 ` Lucas De Marchi
2023-02-27 14:19 ` Jani Nikula
0 siblings, 1 reply; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-17 22:22 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-xe, Maarten Lankhorst, Matthew Auld
On Fri, Feb 17, 2023 at 03:27:12PM -0500, Rodrigo Vivi wrote:
>On Thu, Feb 16, 2023 at 04:52:23PM -0800, Lucas De Marchi wrote:
>> Copy the macros used by xe in i915_reg.h to regs/xe_regs.h. A minimal
>> cleanup is done while copying so they adhere minimally to the coding
>> style. Further reordering and cleaning is left for later.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/xe/regs/xe_regs.h | 111 +++++++++++++++++++++++++
>> drivers/gpu/drm/xe/xe_execlist.c | 3 +-
>> drivers/gpu/drm/xe/xe_ggtt.c | 3 +-
>> drivers/gpu/drm/xe/xe_gt_clock.c | 3 +-
>> drivers/gpu/drm/xe/xe_guc_pc.c | 3 +-
>> drivers/gpu/drm/xe/xe_hw_engine.c | 3 +-
>> drivers/gpu/drm/xe/xe_irq.c | 3 +-
>> drivers/gpu/drm/xe/xe_lrc.c | 3 +-
>> drivers/gpu/drm/xe/xe_mmio.c | 3 +-
>> drivers/gpu/drm/xe/xe_pci.c | 3 +-
>> drivers/gpu/drm/xe/xe_ring_ops.c | 3 +-
>> drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 3 +-
>> drivers/gpu/drm/xe/xe_wa.c | 3 +-
>> 13 files changed, 123 insertions(+), 24 deletions(-)
>> create mode 100644 drivers/gpu/drm/xe/regs/xe_regs.h
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
>> new file mode 100644
>> index 000000000000..53f1ed54fb1c
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/regs/xe_regs.h
>> @@ -0,0 +1,111 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +#ifndef _XE_REGS_H_
>> +#define _XE_REGS_H_
>> +
>> +#include "i915_reg_defs.h"
>> +
>> +#define GU_CNTL _MMIO(0x101010)
>> +#define LMEM_INIT REG_BIT(7)
>> +
>> +#define RENDER_RING_BASE 0x02000
>> +#define BSD_RING_BASE 0x04000
>> +#define GEN6_BSD_RING_BASE 0x12000
>> +#define GEN8_BSD2_RING_BASE 0x1c000
>> +#define GEN11_BSD_RING_BASE 0x1c0000
>> +#define GEN11_BSD2_RING_BASE 0x1c4000
>> +#define GEN11_BSD3_RING_BASE 0x1d0000
>> +#define GEN11_BSD4_RING_BASE 0x1d4000
>> +#define XEHP_BSD5_RING_BASE 0x1e0000
>> +#define XEHP_BSD6_RING_BASE 0x1e4000
>> +#define XEHP_BSD7_RING_BASE 0x1f0000
>> +#define XEHP_BSD8_RING_BASE 0x1f4000
>> +#define VEBOX_RING_BASE 0x1a000
>> +#define GEN11_VEBOX_RING_BASE 0x1c8000
>> +#define GEN11_VEBOX2_RING_BASE 0x1d8000
>> +#define XEHP_VEBOX3_RING_BASE 0x1e8000
>> +#define XEHP_VEBOX4_RING_BASE 0x1f8000
>> +#define GEN12_COMPUTE0_RING_BASE 0x1a000
>> +#define GEN12_COMPUTE1_RING_BASE 0x1c000
>> +#define GEN12_COMPUTE2_RING_BASE 0x1e000
>> +#define GEN12_COMPUTE3_RING_BASE 0x26000
>> +#define BLT_RING_BASE 0x22000
>> +#define XEHPC_BCS1_RING_BASE 0x3e0000
>> +#define XEHPC_BCS2_RING_BASE 0x3e2000
>> +#define XEHPC_BCS3_RING_BASE 0x3e4000
>> +#define XEHPC_BCS4_RING_BASE 0x3e6000
>> +#define XEHPC_BCS5_RING_BASE 0x3e8000
>> +#define XEHPC_BCS6_RING_BASE 0x3ea000
>> +#define XEHPC_BCS7_RING_BASE 0x3ec000
>> +#define XEHPC_BCS8_RING_BASE 0x3ee000
>> +#define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11)
>> +#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
>> +#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
>> +#define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
>> +#define GT_RENDER_USER_INTERRUPT (1 << 0)
>> +
>> +#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
>> +#define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
>> +
>> +#define PVC_RP_STATE_CAP _MMIO(0x281014)
>> +#define MTL_RP_STATE_CAP _MMIO(0x138000)
>> +
>> +#define MTL_MEDIAP_STATE_CAP _MMIO(0x138020)
>> +#define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
>> +#define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
>> +
>> +#define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c)
>> +#define MTL_MPE_FREQUENCY _MMIO(0x13802c)
>> +#define MTL_RPE_MASK REG_GENMASK(8, 0)
>> +
>> +#define TRANSCODER_A_OFFSET 0x60000
>> +#define TRANSCODER_B_OFFSET 0x61000
>> +#define TRANSCODER_C_OFFSET 0x62000
>> +#define TRANSCODER_D_OFFSET 0x63000
>> +#define TRANSCODER_DSI0_OFFSET 0x6b000
>> +#define TRANSCODER_DSI1_OFFSET 0x6b800
>> +#define PIPE_A_OFFSET 0x70000
>> +#define PIPE_B_OFFSET 0x71000
>> +#define PIPE_C_OFFSET 0x72000
>> +#define PIPE_D_OFFSET 0x73000
>> +#define PIPE_DSI0_OFFSET 0x7b000
>> +#define PIPE_DSI1_OFFSET 0x7b800
>> +
>> +#define GEN8_PCU_ISR _MMIO(0x444e0)
>> +#define GEN8_PCU_IMR _MMIO(0x444e4)
>> +#define GEN8_PCU_IIR _MMIO(0x444e8)
>> +#define GEN8_PCU_IER _MMIO(0x444ec)
>> +
>> +#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
>> +#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
>> +#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
>> +#define GEN11_GU_MISC_IER _MMIO(0x444fc)
>> +#define GEN11_GU_MISC_GSE (1 << 27)
>> +
>> +#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
>> +#define GEN11_MASTER_IRQ (1 << 31)
>> +#define GEN11_GU_MISC_IRQ (1 << 29)
>> +#define GEN11_DISPLAY_IRQ (1 << 16)
>> +#define GEN11_GT_DW_IRQ(x) (1 << (x))
>> +
>> +#define DG1_MSTR_TILE_INTR _MMIO(0x190008)
>> +#define DG1_MSTR_IRQ REG_BIT(31)
>> +#define DG1_MSTR_TILE(t) REG_BIT(t)
>> +
>> +#define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
>> +#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
>> +#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
>> +#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
>> +#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
>> +
>> +#define GGC _MMIO(0x108040)
>> +#define GMS_MASK REG_GENMASK(15, 8)
>> +#define GGMS_MASK REG_GENMASK(7, 6)
>
>one of the things that I'm always confused is with these REG_{BIT,GENMASK,FIELD_PREP}.
>Why can't we simply use the regular "non-REG_" versions like every other driver
>(aside of i915 of course).
it was some time ago, I didn't remember exactly and was guessing it was
because GENMASK returns a long, while our registers are 32bits.
Indeed, commit 09b434d4f6d2 ("drm/i915: introduce REG_BIT() and
REG_GENMASK() to define register contents"):
We define the above as wrappers to BIT() and GENMASK() respectively to
force u32 type to go with our register size, and to add compile time
checks on the bit numbers.
we may revisit that and maybe generalize GENMASK32/BIT32 that guarantees a
u32 type is returned.
Lucas De Marchi
>
>> +
>> +#define GEN12_GSMBASE _MMIO(0x108100)
>> +#define GEN12_DSMBASE _MMIO(0x1080C0)
>> +#define GEN12_BDSM_MASK REG_GENMASK64(63, 20)
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
>> index c3c52bdc70b1..ad097918b496 100644
>> --- a/drivers/gpu/drm/xe/xe_execlist.c
>> +++ b/drivers/gpu/drm/xe/xe_execlist.c
>> @@ -10,6 +10,7 @@
>> #include "regs/xe_lrc_regs.h"
>> #include "regs/xe_gpu_commands.h"
>> #include "regs/xe_gt_regs.h"
>> +#include "regs/xe_regs.h"
>> #include "xe_bo.h"
>> #include "xe_device.h"
>> #include "xe_engine.h"
>> @@ -22,8 +23,6 @@
>> #include "xe_ring_ops_types.h"
>> #include "xe_sched_job.h"
>>
>> -#include "i915_reg.h"
>> -
>> #define XE_EXECLIST_HANG_LIMIT 1
>>
>> #define GEN11_SW_CTX_ID_SHIFT 37
>> diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
>> index 2c9b2175c5bb..6674297fa25e 100644
>> --- a/drivers/gpu/drm/xe/xe_ggtt.c
>> +++ b/drivers/gpu/drm/xe/xe_ggtt.c
>> @@ -10,6 +10,7 @@
>> #include <drm/i915_drm.h>
>>
>> #include "regs/xe_gt_regs.h"
>> +#include "regs/xe_regs.h"
>> #include "xe_bo.h"
>> #include "xe_device.h"
>> #include "xe_gt.h"
>> @@ -18,8 +19,6 @@
>> #include "xe_mmio.h"
>> #include "xe_wopcm.h"
>>
>> -#include "i915_reg.h"
>> -
>> /* FIXME: Common file, preferably auto-gen */
>> #define MTL_GGTT_PTE_PAT0 BIT_ULL(52)
>> #define MTL_GGTT_PTE_PAT1 BIT_ULL(53)
>> diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
>> index e9aa7c5452af..cbf9c96c142c 100644
>> --- a/drivers/gpu/drm/xe/xe_gt_clock.c
>> +++ b/drivers/gpu/drm/xe/xe_gt_clock.c
>> @@ -5,13 +5,12 @@
>> #include "xe_gt_clock.h"
>>
>> #include "regs/xe_gt_regs.h"
>> +#include "regs/xe_regs.h"
>> #include "xe_device.h"
>> #include "xe_gt.h"
>> #include "xe_macros.h"
>> #include "xe_mmio.h"
>>
>> -#include "i915_reg.h"
>> -
>> static u32 read_reference_ts_freq(struct xe_gt *gt)
>> {
>> u32 ts_override = xe_mmio_read32(gt, GEN9_TIMESTAMP_OVERRIDE.reg);
>> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
>> index f7aaf4826f00..0df82defa7e4 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
>> @@ -9,6 +9,7 @@
>> #include <drm/drm_managed.h>
>>
>> #include "regs/xe_gt_regs.h"
>> +#include "regs/xe_regs.h"
>> #include "xe_bo.h"
>> #include "xe_device.h"
>> #include "xe_gt.h"
>> @@ -19,8 +20,6 @@
>> #include "xe_mmio.h"
>> #include "xe_pcode.h"
>>
>> -#include "i915_reg.h"
>> -#include "i915_reg_defs.h"
>> #include "intel_mchbar_regs.h"
>>
>> /* For GEN6_RP_STATE_CAP.reg to be merged when the definition moves to Xe */
>> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
>> index caae4f897644..2b49ccba0ce9 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
>> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
>> @@ -8,6 +8,7 @@
>>
>> #include "regs/xe_engine_regs.h"
>> #include "regs/xe_gt_regs.h"
>> +#include "regs/xe_regs.h"
>> #include "xe_bo.h"
>> #include "xe_device.h"
>> #include "xe_execlist.h"
>> @@ -22,8 +23,6 @@
>> #include "xe_sched_job.h"
>> #include "xe_wa.h"
>>
>> -#include "i915_reg.h"
>> -
>> #define MAX_MMIO_BASES 3
>> struct engine_info {
>> const char *name;
>> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>> index d7756c14b4e2..f4f84a16dd83 100644
>> --- a/drivers/gpu/drm/xe/xe_irq.c
>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>> @@ -9,6 +9,7 @@
>> #include <drm/drm_managed.h>
>>
>> #include "regs/xe_gt_regs.h"
>> +#include "regs/xe_regs.h"
>> #include "xe_device.h"
>> #include "xe_display.h"
>> #include "xe_drv.h"
>> @@ -17,8 +18,6 @@
>> #include "xe_hw_engine.h"
>> #include "xe_mmio.h"
>>
>> -#include "i915_reg.h"
>> -
>> static void gen3_assert_iir_is_zero(struct xe_gt *gt, i915_reg_t reg)
>> {
>> u32 val = xe_mmio_read32(gt, reg.reg);
>> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
>> index c1df76c2cf78..261eabaae369 100644
>> --- a/drivers/gpu/drm/xe/xe_lrc.c
>> +++ b/drivers/gpu/drm/xe/xe_lrc.c
>> @@ -8,6 +8,7 @@
>> #include "regs/xe_lrc_regs.h"
>> #include "regs/xe_gpu_commands.h"
>> #include "regs/xe_gt_regs.h"
>> +#include "regs/xe_regs.h"
>> #include "xe_bo.h"
>> #include "xe_device.h"
>> #include "xe_engine_types.h"
>> @@ -16,8 +17,6 @@
>> #include "xe_map.h"
>> #include "xe_vm.h"
>>
>> -#include "i915_reg.h"
>> -
>> #define GEN8_CTX_VALID (1 << 0)
>> #define GEN8_CTX_L3LLC_COHERENT (1 << 5)
>> #define GEN8_CTX_PRIVILEGE (1 << 8)
>> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
>> index d0cd9e920d34..262d33e59d26 100644
>> --- a/drivers/gpu/drm/xe/xe_mmio.c
>> +++ b/drivers/gpu/drm/xe/xe_mmio.c
>> @@ -9,14 +9,13 @@
>>
>> #include "regs/xe_engine_regs.h"
>> #include "regs/xe_gt_regs.h"
>> +#include "regs/xe_regs.h"
>> #include "xe_device.h"
>> #include "xe_gt.h"
>> #include "xe_gt_mcr.h"
>> #include "xe_macros.h"
>> #include "xe_module.h"
>>
>> -#include "i915_reg.h"
>> -
>> #define XEHP_MTCFG_ADDR _MMIO(0x101800)
>> #define TILE_COUNT REG_GENMASK(15, 8)
>> #define GEN12_LMEM_BAR 2
>> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>> index b0e5c402190c..4ecde7c2e619 100644
>> --- a/drivers/gpu/drm/xe/xe_pci.c
>> +++ b/drivers/gpu/drm/xe/xe_pci.c
>> @@ -13,6 +13,7 @@
>> #include <drm/drm_drv.h>
>> #include <drm/xe_pciids.h>
>>
>> +#include "regs/xe_regs.h"
>> #include "xe_device.h"
>> #include "xe_drv.h"
>> #include "xe_macros.h"
>> @@ -20,8 +21,6 @@
>> #include "xe_pm.h"
>> #include "xe_step.h"
>>
>> -#include "i915_reg.h"
>> -
>> #define DEV_INFO_FOR_EACH_FLAG(func) \
>> func(require_force_probe); \
>> func(is_dgfx); \
>> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
>> index 104f96658e1f..ba3bde117af1 100644
>> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
>> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
>> @@ -7,6 +7,7 @@
>> #include "regs/xe_lrc_regs.h"
>> #include "regs/xe_gpu_commands.h"
>> #include "regs/xe_gt_regs.h"
>> +#include "regs/xe_regs.h"
>> #include "xe_engine_types.h"
>> #include "xe_gt.h"
>> #include "xe_lrc.h"
>> @@ -14,8 +15,6 @@
>> #include "xe_sched_job.h"
>> #include "xe_vm_types.h"
>>
>> -#include "i915_reg.h"
>> -
>> static u32 preparser_disable(bool state)
>> {
>> return MI_ARB_CHECK | BIT(8) | state;
>> diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
>> index 1c3783becefd..19828e003283 100644
>> --- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
>> +++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
>> @@ -11,8 +11,7 @@
>> #include <drm/ttm/ttm_placement.h>
>> #include <drm/ttm/ttm_range_manager.h>
>>
>> -#include "../i915/i915_reg.h"
>> -
>> +#include "regs/xe_regs.h"
>> #include "xe_bo.h"
>> #include "xe_device.h"
>> #include "xe_gt.h"
>> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
>> index 155cfd1dcc50..df72b15dfeb0 100644
>> --- a/drivers/gpu/drm/xe/xe_wa.c
>> +++ b/drivers/gpu/drm/xe/xe_wa.c
>> @@ -9,6 +9,7 @@
>>
>> #include "regs/xe_engine_regs.h"
>> #include "regs/xe_gt_regs.h"
>> +#include "regs/xe_regs.h"
>> #include "xe_device_types.h"
>> #include "xe_force_wake.h"
>> #include "xe_gt.h"
>> @@ -18,8 +19,6 @@
>> #include "xe_rtp.h"
>> #include "xe_step.h"
>>
>> -#include "i915_reg.h"
>> -
>> /**
>> * DOC: Hardware workarounds
>> *
>> --
>> 2.39.0
>>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 11/11] drm/xe: Use relative includes for i915_reg_defs.h
2023-02-17 20:28 ` Rodrigo Vivi
@ 2023-02-17 22:30 ` Lucas De Marchi
2023-02-21 21:42 ` Rodrigo Vivi
0 siblings, 1 reply; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-17 22:30 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-xe, Maarten Lankhorst, Matthew Auld
On Fri, Feb 17, 2023 at 03:28:24PM -0500, Rodrigo Vivi wrote:
>On Thu, Feb 16, 2023 at 04:52:26PM -0800, Lucas De Marchi wrote:
>> With the goal of eliminating i915 includes from xe outside of the
>> display area, it's better to use relative includes for the only shared
>> header, i915_reg_defs.h. With this the build system can be changed to
>> stop adding i915 as an include dir.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/xe/display/Makefile | 120 +++++++++++++++++++++++
>> drivers/gpu/drm/xe/regs/xe_engine_regs.h | 2 +-
>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
>> drivers/gpu/drm/xe/regs/xe_regs.h | 2 +-
>> drivers/gpu/drm/xe/xe_gt_mcr.h | 2 +-
>> drivers/gpu/drm/xe/xe_guc.c | 2 -
>> drivers/gpu/drm/xe/xe_guc_reg.h | 2 +-
>> drivers/gpu/drm/xe/xe_reg_sr_types.h | 2 -
>> drivers/gpu/drm/xe/xe_rtp.h | 2 -
>> drivers/gpu/drm/xe/xe_rtp_types.h | 2 -
>> 10 files changed, 125 insertions(+), 13 deletions(-)
>> create mode 100644 drivers/gpu/drm/xe/display/Makefile
>>
>> diff --git a/drivers/gpu/drm/xe/display/Makefile b/drivers/gpu/drm/xe/display/Makefile
>> new file mode 100644
>> index 000000000000..eee576972427
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/display/Makefile
>
>shouldn't this patch also be modifying the drm/xe/Makefile?
sorry, while trying to resolve the display situation I squashed this by
mistake here. Next version I'm giving up on the idea in this patch
and I will just create a regs/xe_reg_defs.h. That will be the only file
with the relative include.
Lucas De Marchi
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 11/11] drm/xe: Use relative includes for i915_reg_defs.h
2023-02-17 22:30 ` Lucas De Marchi
@ 2023-02-21 21:42 ` Rodrigo Vivi
2023-02-21 21:50 ` Lucas De Marchi
0 siblings, 1 reply; 42+ messages in thread
From: Rodrigo Vivi @ 2023-02-21 21:42 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe, Maarten Lankhorst, Matthew Auld
On Fri, Feb 17, 2023 at 02:30:07PM -0800, Lucas De Marchi wrote:
> On Fri, Feb 17, 2023 at 03:28:24PM -0500, Rodrigo Vivi wrote:
> > On Thu, Feb 16, 2023 at 04:52:26PM -0800, Lucas De Marchi wrote:
> > > With the goal of eliminating i915 includes from xe outside of the
> > > display area, it's better to use relative includes for the only shared
> > > header, i915_reg_defs.h. With this the build system can be changed to
> > > stop adding i915 as an include dir.
> > >
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > > drivers/gpu/drm/xe/display/Makefile | 120 +++++++++++++++++++++++
> > > drivers/gpu/drm/xe/regs/xe_engine_regs.h | 2 +-
> > > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
> > > drivers/gpu/drm/xe/regs/xe_regs.h | 2 +-
> > > drivers/gpu/drm/xe/xe_gt_mcr.h | 2 +-
> > > drivers/gpu/drm/xe/xe_guc.c | 2 -
> > > drivers/gpu/drm/xe/xe_guc_reg.h | 2 +-
> > > drivers/gpu/drm/xe/xe_reg_sr_types.h | 2 -
> > > drivers/gpu/drm/xe/xe_rtp.h | 2 -
> > > drivers/gpu/drm/xe/xe_rtp_types.h | 2 -
> > > 10 files changed, 125 insertions(+), 13 deletions(-)
> > > create mode 100644 drivers/gpu/drm/xe/display/Makefile
> > >
> > > diff --git a/drivers/gpu/drm/xe/display/Makefile b/drivers/gpu/drm/xe/display/Makefile
> > > new file mode 100644
> > > index 000000000000..eee576972427
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/xe/display/Makefile
> >
> > shouldn't this patch also be modifying the drm/xe/Makefile?
>
> sorry, while trying to resolve the display situation I squashed this by
> mistake here. Next version I'm giving up on the idea in this patch
> and I will just create a regs/xe_reg_defs.h. That will be the only file
> with the relative include.
But does this solve your main concern of the i915 directories getting
included when display build is enabled even for folders that are not
related to display?
>
> Lucas De Marchi
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 11/11] drm/xe: Use relative includes for i915_reg_defs.h
2023-02-21 21:42 ` Rodrigo Vivi
@ 2023-02-21 21:50 ` Lucas De Marchi
0 siblings, 0 replies; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-21 21:50 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-xe, Maarten Lankhorst, Matthew Auld
On Tue, Feb 21, 2023 at 04:42:08PM -0500, Rodrigo Vivi wrote:
>On Fri, Feb 17, 2023 at 02:30:07PM -0800, Lucas De Marchi wrote:
>> On Fri, Feb 17, 2023 at 03:28:24PM -0500, Rodrigo Vivi wrote:
>> > On Thu, Feb 16, 2023 at 04:52:26PM -0800, Lucas De Marchi wrote:
>> > > With the goal of eliminating i915 includes from xe outside of the
>> > > display area, it's better to use relative includes for the only shared
>> > > header, i915_reg_defs.h. With this the build system can be changed to
>> > > stop adding i915 as an include dir.
>> > >
>> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> > > ---
>> > > drivers/gpu/drm/xe/display/Makefile | 120 +++++++++++++++++++++++
>> > > drivers/gpu/drm/xe/regs/xe_engine_regs.h | 2 +-
>> > > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
>> > > drivers/gpu/drm/xe/regs/xe_regs.h | 2 +-
>> > > drivers/gpu/drm/xe/xe_gt_mcr.h | 2 +-
>> > > drivers/gpu/drm/xe/xe_guc.c | 2 -
>> > > drivers/gpu/drm/xe/xe_guc_reg.h | 2 +-
>> > > drivers/gpu/drm/xe/xe_reg_sr_types.h | 2 -
>> > > drivers/gpu/drm/xe/xe_rtp.h | 2 -
>> > > drivers/gpu/drm/xe/xe_rtp_types.h | 2 -
>> > > 10 files changed, 125 insertions(+), 13 deletions(-)
>> > > create mode 100644 drivers/gpu/drm/xe/display/Makefile
>> > >
>> > > diff --git a/drivers/gpu/drm/xe/display/Makefile b/drivers/gpu/drm/xe/display/Makefile
>> > > new file mode 100644
>> > > index 000000000000..eee576972427
>> > > --- /dev/null
>> > > +++ b/drivers/gpu/drm/xe/display/Makefile
>> >
>> > shouldn't this patch also be modifying the drm/xe/Makefile?
>>
>> sorry, while trying to resolve the display situation I squashed this by
>> mistake here. Next version I'm giving up on the idea in this patch
>> and I will just create a regs/xe_reg_defs.h. That will be the only file
>> with the relative include.
>
>But does this solve your main concern of the i915 directories getting
>included when display build is enabled even for folders that are not
>related to display?
no. Without a refactor on the display integration I couldn't find a
easy way - even if we find a way in the build system to pass the cflags
differently, it will break as the rest of the driver need the display
includes.
I think we'd have to introduce an xe_display and then make xe_display be
the "alias" for drm_i915_private instead of xe_device. However doing
this may mean I'm doing some work that conflicts with what other people
in CC are doing. I can try that later if it doesn't really conflict.
So... I decided to keep this cleanup only up to "everything but
display". To make sure this patch series is complete for that goal I
added a hack patch on top removing display. See v3 of this patch series
Lucas De Marchi
>
>>
>> Lucas De Marchi
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 04/11] drm/xe: Remove dependency on intel_engine_regs.h
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 04/11] drm/xe: Remove dependency on intel_engine_regs.h Lucas De Marchi
@ 2023-02-24 18:02 ` Matt Roper
2023-02-24 18:05 ` Lucas De Marchi
0 siblings, 1 reply; 42+ messages in thread
From: Matt Roper @ 2023-02-24 18:02 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe, Maarten Lankhorst, Matthew Auld
On Thu, Feb 16, 2023 at 04:52:19PM -0800, Lucas De Marchi wrote:
> Create regs/xe_engine_regs.h file with all the registers and bit
> definitions used by the xe driver. Eventually the registers may be
> defined in a different way and since xe doesn't supported below gen12,
> the number of registers touched is much smaller, so create a new header.
>
> The definitions themselves are direct copy from the
> gt/intel_engine_regs.h file, just sorting the registers by address.
> Cleaning those up and adhering to a common coding style is left for
> later.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_engine_regs.h | 98 ++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_execlist.c | 2 +-
> drivers/gpu/drm/xe/xe_guc_ads.c | 5 +-
> drivers/gpu/drm/xe/xe_hw_engine.c | 2 +-
> drivers/gpu/drm/xe/xe_lrc.c | 2 +-
> drivers/gpu/drm/xe/xe_mmio.c | 2 +-
> drivers/gpu/drm/xe/xe_reg_sr.c | 2 +-
> drivers/gpu/drm/xe/xe_reg_whitelist.c | 2 +-
> drivers/gpu/drm/xe/xe_wa.c | 2 +-
> 9 files changed, 109 insertions(+), 8 deletions(-)
> create mode 100644 drivers/gpu/drm/xe/regs/xe_engine_regs.h
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> new file mode 100644
> index 000000000000..6dfa3cf2fd43
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -0,0 +1,98 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_ENGINE_REGS_H_
> +#define _XE_ENGINE_REGS_H_
> +
> +#include <asm/page.h>
> +
> +#include "i915_reg_defs.h"
> +
> +#define RING_TAIL(base) _MMIO((base) + 0x30)
> +
> +#define RING_HEAD(base) _MMIO((base) + 0x34)
> +#define HEAD_ADDR 0x001FFFFC
> +
> +#define RING_START(base) _MMIO((base) + 0x38)
> +
> +#define RING_CTL(base) _MMIO((base) + 0x3c)
> +#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
> +#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
> +
> +#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
> +#define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
> +#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
> +
> +#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
> +#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60)
> +#define RING_IPEIR(base) _MMIO((base) + 0x64)
> +#define RING_IPEHR(base) _MMIO((base) + 0x68)
> +#define RING_ACTHD(base) _MMIO((base) + 0x74)
> +#define RING_DMA_FADD(base) _MMIO((base) + 0x78)
> +#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
> +#define IPEIR(base) _MMIO((base) + 0x88)
> +#define IPEHR(base) _MMIO((base) + 0x8c)
> +#define RING_HWSTAM(base) _MMIO((base) + 0x98)
> +#define RING_MI_MODE(base) _MMIO((base) + 0x9c)
> +#define RING_NOPID(base) _MMIO((base) + 0x94)
> +
> +#define RING_IMR(base) _MMIO((base) + 0xa8)
> +#define RING_MAX_NONPRIV_SLOTS 12
> +
> +#define RING_EIR(base) _MMIO((base) + 0xb0)
> +#define RING_EMR(base) _MMIO((base) + 0xb4)
> +#define RING_ESR(base) _MMIO((base) + 0xb8)
> +#define RING_BBADDR(base) _MMIO((base) + 0x140)
> +#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168)
> +#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
> +#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
> +
> +#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
> +#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
> +#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
> +
> +#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
> +#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
> +
> +#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
> +
> +#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
> +#define RING_VALID_MASK 0x00000001
> +#define RING_VALID 0x00000001
> +#define STOP_RING REG_BIT(8)
> +#define TAIL_ADDR 0x001FFFF8
> +
> +#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8)
> +
> +#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4d0) + (i) * 4)
> +#define RING_FORCE_TO_NONPRIV_DENY REG_BIT(30)
> +#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
> +#define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28)
> +#define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
> +#define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
> +#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
> +#define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
> +#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0)
> +#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
> +#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
> +#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
> +#define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
> +#define RING_FORCE_TO_NONPRIV_MASK_VALID (RING_FORCE_TO_NONPRIV_RANGE_MASK | \
> + RING_FORCE_TO_NONPRIV_ACCESS_MASK | \
> + RING_FORCE_TO_NONPRIV_DENY)
> +#define RING_MAX_NONPRIV_SLOTS 12
> +
> +#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
> +
> +#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
> +#define EL_CTRL_LOAD REG_BIT(0)
> +
> +#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10)
> +#define IECPUNIT_CLKGATE_DIS REG_BIT(22)
> +
> +#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18)
> +#define ALNUNIT_CLKGATE_DIS REG_BIT(13)
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
> index 5633259482ed..af2fcf1c32f4 100644
> --- a/drivers/gpu/drm/xe/xe_execlist.c
> +++ b/drivers/gpu/drm/xe/xe_execlist.c
> @@ -6,6 +6,7 @@
>
> #include <drm/drm_managed.h>
>
> +#include "regs/xe_engine_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_engine.h"
> @@ -18,7 +19,6 @@
> #include "xe_ring_ops_types.h"
> #include "xe_sched_job.h"
>
> -#include "gt/intel_engine_regs.h"
> #include "gt/intel_gpu_commands.h"
> #include "gt/intel_gt_regs.h"
> #include "gt/intel_lrc_reg.h"
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index 1ea1b25e7170..bde094388a34 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -4,8 +4,11 @@
> */
> #include "xe_guc_ads.h"
>
> +#include "xe_guc_ads.h"
> +
This duplication looks like an accident?
Aside from that,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> #include <drm/drm_managed.h>
>
> +#include "regs/xe_engine_regs.h"
> #include "xe_bo.h"
> #include "xe_gt.h"
> #include "xe_guc.h"
> @@ -16,9 +19,9 @@
> #include "xe_mmio.h"
> #include "xe_platform_types.h"
>
> -#include "gt/intel_engine_regs.h"
> #include "gt/intel_gt_regs.h"
>
> +
> /* Slack of a few additional entries per engine */
> #define ADS_REGSET_EXTRA_MAX 8
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index edc59d9b124f..ce5d6641499f 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -6,6 +6,7 @@
>
> #include <drm/drm_managed.h>
>
> +#include "regs/xe_engine_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_execlist.h"
> @@ -20,7 +21,6 @@
> #include "xe_sched_job.h"
> #include "xe_wa.h"
>
> -#include "gt/intel_engine_regs.h"
> #include "gt/intel_gt_regs.h"
> #include "i915_reg.h"
>
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index 45503c39240a..60ffe3f80c59 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -4,6 +4,7 @@
> */
> #include "xe_lrc.h"
>
> +#include "regs/xe_engine_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_engine_types.h"
> @@ -12,7 +13,6 @@
> #include "xe_map.h"
> #include "xe_vm.h"
>
> -#include "gt/intel_engine_regs.h"
> #include "gt/intel_gpu_commands.h"
> #include "gt/intel_gt_regs.h"
> #include "gt/intel_lrc_reg.h"
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index 57788afe206e..892008dcbaf4 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -7,13 +7,13 @@
> #include <drm/drm_managed.h>
> #include <drm/xe_drm.h>
>
> +#include "regs/xe_engine_regs.h"
> #include "xe_device.h"
> #include "xe_gt.h"
> #include "xe_gt_mcr.h"
> #include "xe_macros.h"
> #include "xe_module.h"
>
> -#include "gt/intel_engine_regs.h"
> #include "gt/intel_gt_regs.h"
> #include "i915_reg.h"
>
> diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
> index dc96d0e48688..bd3b64ad9c26 100644
> --- a/drivers/gpu/drm/xe/xe_reg_sr.c
> +++ b/drivers/gpu/drm/xe/xe_reg_sr.c
> @@ -11,6 +11,7 @@
> #include <drm/drm_managed.h>
> #include <drm/drm_print.h>
>
> +#include "regs/xe_engine_regs.h"
> #include "xe_device_types.h"
> #include "xe_force_wake.h"
> #include "xe_gt.h"
> @@ -19,7 +20,6 @@
> #include "xe_mmio.h"
> #include "xe_rtp_types.h"
>
> -#include "gt/intel_engine_regs.h"
> #include "gt/intel_gt_regs.h"
>
> #define XE_REG_SR_GROW_STEP_DEFAULT 16
> diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> index 3951460307e2..e2f3f374b856 100644
> --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> @@ -4,11 +4,11 @@
> */
> #include "xe_reg_whitelist.h"
>
> +#include "regs/xe_engine_regs.h"
> #include "xe_gt_types.h"
> #include "xe_platform_types.h"
> #include "xe_rtp.h"
>
> -#include "gt/intel_engine_regs.h"
> #include "gt/intel_gt_regs.h"
>
> #undef _MMIO
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index 9d2e4555091c..92065341c001 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -7,6 +7,7 @@
>
> #include <linux/compiler_types.h>
>
> +#include "regs/xe_engine_regs.h"
> #include "xe_device_types.h"
> #include "xe_force_wake.h"
> #include "xe_gt.h"
> @@ -16,7 +17,6 @@
> #include "xe_rtp.h"
> #include "xe_step.h"
>
> -#include "gt/intel_engine_regs.h"
> #include "gt/intel_gt_regs.h"
> #include "i915_reg.h"
>
> --
> 2.39.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 04/11] drm/xe: Remove dependency on intel_engine_regs.h
2023-02-24 18:02 ` Matt Roper
@ 2023-02-24 18:05 ` Lucas De Marchi
0 siblings, 0 replies; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-24 18:05 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe, Maarten Lankhorst, Matthew Auld
On Fri, Feb 24, 2023 at 10:02:38AM -0800, Matt Roper wrote:
>On Thu, Feb 16, 2023 at 04:52:19PM -0800, Lucas De Marchi wrote:
>> Create regs/xe_engine_regs.h file with all the registers and bit
>> definitions used by the xe driver. Eventually the registers may be
>> defined in a different way and since xe doesn't supported below gen12,
>> the number of registers touched is much smaller, so create a new header.
>>
>> The definitions themselves are direct copy from the
>> gt/intel_engine_regs.h file, just sorting the registers by address.
>> Cleaning those up and adhering to a common coding style is left for
>> later.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/xe/regs/xe_engine_regs.h | 98 ++++++++++++++++++++++++
>> drivers/gpu/drm/xe/xe_execlist.c | 2 +-
>> drivers/gpu/drm/xe/xe_guc_ads.c | 5 +-
>> drivers/gpu/drm/xe/xe_hw_engine.c | 2 +-
>> drivers/gpu/drm/xe/xe_lrc.c | 2 +-
>> drivers/gpu/drm/xe/xe_mmio.c | 2 +-
>> drivers/gpu/drm/xe/xe_reg_sr.c | 2 +-
>> drivers/gpu/drm/xe/xe_reg_whitelist.c | 2 +-
>> drivers/gpu/drm/xe/xe_wa.c | 2 +-
>> 9 files changed, 109 insertions(+), 8 deletions(-)
>> create mode 100644 drivers/gpu/drm/xe/regs/xe_engine_regs.h
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
>> new file mode 100644
>> index 000000000000..6dfa3cf2fd43
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
>> @@ -0,0 +1,98 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_ENGINE_REGS_H_
>> +#define _XE_ENGINE_REGS_H_
>> +
>> +#include <asm/page.h>
>> +
>> +#include "i915_reg_defs.h"
>> +
>> +#define RING_TAIL(base) _MMIO((base) + 0x30)
>> +
>> +#define RING_HEAD(base) _MMIO((base) + 0x34)
>> +#define HEAD_ADDR 0x001FFFFC
>> +
>> +#define RING_START(base) _MMIO((base) + 0x38)
>> +
>> +#define RING_CTL(base) _MMIO((base) + 0x3c)
>> +#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
>> +#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
>> +
>> +#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
>> +#define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
>> +#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
>> +
>> +#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
>> +#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60)
>> +#define RING_IPEIR(base) _MMIO((base) + 0x64)
>> +#define RING_IPEHR(base) _MMIO((base) + 0x68)
>> +#define RING_ACTHD(base) _MMIO((base) + 0x74)
>> +#define RING_DMA_FADD(base) _MMIO((base) + 0x78)
>> +#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
>> +#define IPEIR(base) _MMIO((base) + 0x88)
>> +#define IPEHR(base) _MMIO((base) + 0x8c)
>> +#define RING_HWSTAM(base) _MMIO((base) + 0x98)
>> +#define RING_MI_MODE(base) _MMIO((base) + 0x9c)
>> +#define RING_NOPID(base) _MMIO((base) + 0x94)
>> +
>> +#define RING_IMR(base) _MMIO((base) + 0xa8)
>> +#define RING_MAX_NONPRIV_SLOTS 12
>> +
>> +#define RING_EIR(base) _MMIO((base) + 0xb0)
>> +#define RING_EMR(base) _MMIO((base) + 0xb4)
>> +#define RING_ESR(base) _MMIO((base) + 0xb8)
>> +#define RING_BBADDR(base) _MMIO((base) + 0x140)
>> +#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168)
>> +#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
>> +#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
>> +
>> +#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
>> +#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
>> +#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
>> +
>> +#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
>> +#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
>> +
>> +#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
>> +
>> +#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
>> +#define RING_VALID_MASK 0x00000001
>> +#define RING_VALID 0x00000001
>> +#define STOP_RING REG_BIT(8)
>> +#define TAIL_ADDR 0x001FFFF8
>> +
>> +#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8)
>> +
>> +#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4d0) + (i) * 4)
>> +#define RING_FORCE_TO_NONPRIV_DENY REG_BIT(30)
>> +#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
>> +#define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28)
>> +#define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
>> +#define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
>> +#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
>> +#define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
>> +#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0)
>> +#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
>> +#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
>> +#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
>> +#define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
>> +#define RING_FORCE_TO_NONPRIV_MASK_VALID (RING_FORCE_TO_NONPRIV_RANGE_MASK | \
>> + RING_FORCE_TO_NONPRIV_ACCESS_MASK | \
>> + RING_FORCE_TO_NONPRIV_DENY)
>> +#define RING_MAX_NONPRIV_SLOTS 12
>> +
>> +#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
>> +
>> +#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
>> +#define EL_CTRL_LOAD REG_BIT(0)
>> +
>> +#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10)
>> +#define IECPUNIT_CLKGATE_DIS REG_BIT(22)
>> +
>> +#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18)
>> +#define ALNUNIT_CLKGATE_DIS REG_BIT(13)
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
>> index 5633259482ed..af2fcf1c32f4 100644
>> --- a/drivers/gpu/drm/xe/xe_execlist.c
>> +++ b/drivers/gpu/drm/xe/xe_execlist.c
>> @@ -6,6 +6,7 @@
>>
>> #include <drm/drm_managed.h>
>>
>> +#include "regs/xe_engine_regs.h"
>> #include "xe_bo.h"
>> #include "xe_device.h"
>> #include "xe_engine.h"
>> @@ -18,7 +19,6 @@
>> #include "xe_ring_ops_types.h"
>> #include "xe_sched_job.h"
>>
>> -#include "gt/intel_engine_regs.h"
>> #include "gt/intel_gpu_commands.h"
>> #include "gt/intel_gt_regs.h"
>> #include "gt/intel_lrc_reg.h"
>> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
>> index 1ea1b25e7170..bde094388a34 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
>> @@ -4,8 +4,11 @@
>> */
>> #include "xe_guc_ads.h"
>>
>> +#include "xe_guc_ads.h"
>> +
>
>This duplication looks like an accident?
yep
>
>Aside from that,
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
thanks
Lucas De Marchi
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 05/11] drm/xe: Remove dependency on intel_gt_regs.h
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 05/11] drm/xe: Remove dependency on intel_gt_regs.h Lucas De Marchi
2023-02-17 20:20 ` Rodrigo Vivi
@ 2023-02-24 18:06 ` Matt Roper
2023-02-24 18:29 ` Lucas De Marchi
1 sibling, 1 reply; 42+ messages in thread
From: Matt Roper @ 2023-02-24 18:06 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe, Maarten Lankhorst, Matthew Auld
On Thu, Feb 16, 2023 at 04:52:20PM -0800, Lucas De Marchi wrote:
> Create regs/xe_gt_regs.h file with all the registers and bit
> definitions used by the xe driver. Eventually the registers may be
> defined in a different way and since xe doesn't supported below gen12,
> the number of registers touched is much smaller, so create a new header.
>
> The definitions themselves are direct copy from the
> gt/intel_gt_regs.h file, just sorting the registers by address.
> Cleaning those up and adhering to a common coding style is left for
> later.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg_defs.h | 2 +
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 287 ++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_execlist.c | 2 +-
> drivers/gpu/drm/xe/xe_force_wake.c | 3 +-
> drivers/gpu/drm/xe/xe_ggtt.c | 2 +-
> drivers/gpu/drm/xe/xe_gt.c | 3 +-
> drivers/gpu/drm/xe/xe_gt_clock.c | 2 +-
> drivers/gpu/drm/xe/xe_gt_mcr.c | 3 +-
> drivers/gpu/drm/xe/xe_guc.c | 2 +-
> drivers/gpu/drm/xe/xe_guc_ads.c | 4 +-
> drivers/gpu/drm/xe/xe_guc_pc.c | 2 +-
> drivers/gpu/drm/xe/xe_hw_engine.c | 2 +-
> drivers/gpu/drm/xe/xe_irq.c | 2 +-
> drivers/gpu/drm/xe/xe_lrc.c | 2 +-
> drivers/gpu/drm/xe/xe_mmio.c | 2 +-
> drivers/gpu/drm/xe/xe_mocs.c | 3 +-
> drivers/gpu/drm/xe/xe_reg_sr.c | 3 +-
> drivers/gpu/drm/xe/xe_reg_whitelist.c | 3 +-
> drivers/gpu/drm/xe/xe_ring_ops.c | 2 +-
> drivers/gpu/drm/xe/xe_tuning.c | 3 +-
> drivers/gpu/drm/xe/xe_wa.c | 2 +-
> 21 files changed, 308 insertions(+), 28 deletions(-)
> create mode 100644 drivers/gpu/drm/xe/regs/xe_gt_regs.h
>
> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
> index b5e06b6a9478..a6080c983a77 100644
> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> @@ -136,6 +136,8 @@ typedef struct {
> u32 reg;
> } i915_mcr_reg_t;
>
> +#define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg = (offset) })
Should there be a corresponding removal of this definition from
drivers/gpu/drm/i915/gt/intel_gt_regs.h ?
Aside from that,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> +
> #define INVALID_MMIO_REG _MMIO(0)
>
> /*
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> new file mode 100644
> index 000000000000..da40133252fb
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -0,0 +1,287 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_GT_REGS_H_
> +#define _XE_GT_REGS_H_
> +
> +#include "i915_reg_defs.h"
> +
> +/* RPM unit config (Gen8+) */
> +#define RPM_CONFIG0 _MMIO(0xd00)
> +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
> +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
> +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
> +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
> +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2
> +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
> +#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
> +#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
> +
> +#define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0xd50 + (n) * 4)
> +#define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0xd70 + (n) * 4)
> +#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84)
> +
> +#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
> +#define LNCFCMOCS_REG_COUNT 32
> +
> +#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
> +#define MTL_MCR_SELECTOR _MMIO(0xfd4)
> +#define SF_MCR_SELECTOR _MMIO(0xfd8)
> +#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
> +#define GAM_MCR_SELECTOR _MMIO(0xfe0)
> +#define GEN11_MCR_MULTICAST REG_BIT(31)
> +#define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27)
> +#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
> +#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
> +#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
> +#define MTL_MCR_GROUPID REG_GENMASK(11, 8)
> +#define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
> +
> +#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
> +#define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
> +
> +#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
> +#define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
> +
> +#define PS_INVOCATION_COUNT _MMIO(0x2348)
> +
> +#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
> +#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
> +#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
> +#define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
> +#define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
> +#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
> +#define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
> +
> +#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
> +#define GEN12_GFX_CCS_AUX_NV _MMIO(0x4208)
> +
> +#define GEN12_VD0_AUX_NV _MMIO(0x4218)
> +#define GEN12_VE0_AUX_NV _MMIO(0x4238)
> +
> +#define GEN12_VE1_AUX_NV _MMIO(0x42b8)
> +#define AUX_INV REG_BIT(0)
> +
> +#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
> +#define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900)
> +#define XEHP_FLAT_CCS_BASE_ADDR MCR_REG(0x4910)
> +
> +#define GEN12_FF_MODE2 _MMIO(0x6604)
> +#define XEHP_FF_MODE2 MCR_REG(0x6604)
> +#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
> +#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
> +#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
> +#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
> +
> +#define HIZ_CHICKEN _MMIO(0x7018)
> +#define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14)
> +
> +/* GEN7 chicken */
> +#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
> +
> +#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
> +#define XEHP_COMMON_SLICE_CHICKEN3 MCR_REG(0x7304)
> +#define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
> +#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
> +#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
> +#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
> +
> +#define XEHP_SQCM MCR_REG(0x8724)
> +#define EN_32B_ACCESS REG_BIT(30)
> +
> +#define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
> +#define GEN10_L3BANK_PAIR_COUNT 4
> +#define GEN10_L3BANK_MASK 0x0F
> +/* on Xe_HP the same fuses indicates mslices instead of L3 banks */
> +#define GEN12_MAX_MSLICES 4
> +#define GEN12_MEML3_EN_MASK 0x0F
> +
> +/* Fuse readout registers for GT */
> +#define XEHP_FUSE4 _MMIO(0x9114)
> +#define GT_L3_EXC_MASK REG_GENMASK(6, 4)
> +
> +#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
> +#define GEN11_GT_VDBOX_DISABLE_MASK 0xff
> +#define GEN11_GT_VEBOX_DISABLE_SHIFT 16
> +#define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
> +
> +#define GEN6_GDRST _MMIO(0x941c)
> +#define GEN11_GRDOM_GUC REG_BIT(3)
> +#define GEN6_GRDOM_FULL (1 << 0)
> +#define GEN11_GRDOM_FULL GEN6_GRDOM_FULL
> +
> +#define GEN7_MISCCPCTL _MMIO(0x9424)
> +#define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
> +#define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1)
> +
> +#define UNSLCGCTL9430 _MMIO(0x9430)
> +#define MSQDUNIT_CLKGATE_DIS REG_BIT(3)
> +
> +#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
> +#define VFUNIT_CLKGATE_DIS REG_BIT(20)
> +#define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */
> +#define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */
> +#define GAMEDIA_CLKGATE_DIS REG_BIT(11)
> +#define HSUNIT_CLKGATE_DIS REG_BIT(8)
> +#define VSUNIT_CLKGATE_DIS REG_BIT(3)
> +
> +#define UNSLCGCTL9440 _MMIO(0x9440)
> +#define GAMTLBOACS_CLKGATE_DIS REG_BIT(28)
> +#define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27)
> +#define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26)
> +#define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24)
> +#define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23)
> +#define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22)
> +#define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21)
> +#define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17)
> +#define GAMTLBKCR_CLKGATE_DIS REG_BIT(16)
> +#define GAMTLBGUC_CLKGATE_DIS REG_BIT(15)
> +#define GAMTLBBLT_CLKGATE_DIS REG_BIT(14)
> +#define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6)
> +
> +#define UNSLCGCTL9444 _MMIO(0x9444)
> +#define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30)
> +#define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29)
> +#define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28)
> +#define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27)
> +#define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26)
> +#define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25)
> +#define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24)
> +#define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23)
> +#define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22)
> +#define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21)
> +#define GAMTLBMERT_CLKGATE_DIS REG_BIT(20)
> +#define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19)
> +#define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18)
> +#define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17)
> +#define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
> +#define LTCDD_CLKGATE_DIS REG_BIT(10)
> +
> +#define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> +#define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4)
> +#define SARBUNIT_CLKGATE_DIS (1 << 5)
> +#define RCCUNIT_CLKGATE_DIS (1 << 7)
> +#define MSCUNIT_CLKGATE_DIS (1 << 10)
> +#define NODEDSS_CLKGATE_DIS REG_BIT(12)
> +#define L3_CLKGATE_DIS REG_BIT(16)
> +#define L3_CR2X_CLKGATE_DIS REG_BIT(17)
> +
> +#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
> +#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
> +#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
> +
> +#define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x9524)
> +#define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
> +#define GWUNIT_CLKGATE_DIS REG_BIT(16)
> +
> +#define SUBSLICE_UNIT_LEVEL_CLKGATE2 MCR_REG(0x9528)
> +#define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
> +
> +#define SSMCGCTL9530 MCR_REG(0x9530)
> +#define RTFUNIT_CLKGATE_DIS REG_BIT(18)
> +
> +#define GEN10_DFR_RATIO_EN_AND_CHICKEN MCR_REG(0x9550)
> +#define DFR_DISABLE (1 << 9)
> +
> +#define GEN6_RPNSWREQ _MMIO(0xa008)
> +#define GEN6_RC_CONTROL _MMIO(0xa090)
> +#define GEN6_RC_STATE _MMIO(0xa094)
> +
> +#define GEN6_PMINTRMSK _MMIO(0xa168)
> +#define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31)
> +#define ARAT_EXPIRED_INTRMSK (1 << 9)
> +
> +#define FORCEWAKE_GT_GEN9 _MMIO(0xa188)
> +
> +#define GEN9_PG_ENABLE _MMIO(0xa210)
> +
> +/* GPM unit config (Gen9+) */
> +#define CTC_MODE _MMIO(0xa26c)
> +#define CTC_SOURCE_PARAMETER_MASK 1
> +#define CTC_SOURCE_CRYSTAL_CLOCK 0
> +#define CTC_SOURCE_DIVIDE_LOGIC 1
> +#define CTC_SHIFT_PARAMETER_SHIFT 1
> +#define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
> +
> +#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
> +#define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4)
> +#define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4)
> +
> +#define GEN10_SAMPLER_MODE MCR_REG(0xe18c)
> +#define ENABLE_SMALLPL REG_BIT(15)
> +#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> +#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
> +
> +#define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c)
> +#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
> +#define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
> +#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
> +#define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
> +#define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4)
> +#define THREAD_EX_ARB_MODE REG_GENMASK(3, 2)
> +#define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
> +
> +#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
> +#define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
> +#define GEN12_DISABLE_EARLY_READ REG_BIT(14)
> +#define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
> +#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
> +#define GEN12_DISABLE_DOP_GATING REG_BIT(0)
> +
> +#define SARB_CHICKEN1 MCR_REG(0xe90c)
> +#define COMP_CKN_IN REG_GENMASK(30, 29)
> +
> +#define GEN12_RCU_MODE _MMIO(0x14800)
> +#define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0)
> +
> +#define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044)
> +#define FORCEWAKE_KERNEL BIT(0)
> +#define FORCEWAKE_USER BIT(1)
> +#define FORCEWAKE_KERNEL_FALLBACK BIT(15)
> +
> +#define GEN6_GT_CORE_STATUS _MMIO(0x138060)
> +#define GEN6_RC0 0
> +#define GEN6_RC6 3
> +
> +#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
> +#define GEN6_GT_GFX_RC6 _MMIO(0x138108)
> +
> +#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
> +#define GFX_FLSH_CNTL_EN (1 << 0)
> +
> +#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
> +
> +#define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)
> +#define ENGINE1_MASK REG_GENMASK(31, 16)
> +#define ENGINE0_MASK REG_GENMASK(15, 0)
> +
> +#define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
> +
> +#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
> +#define GEN11_INTR_DATA_VALID (1 << 31)
> +#define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
> +#define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)
> +#define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff)
> +#define OTHER_GUC_INSTANCE 0
> +
> +#define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
> +#define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
> +#define GEN12_CCS_RSVD_INTR_ENABLE _MMIO(0x190048)
> +#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
> +#define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
> +#define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
> +#define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
> +#define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
> +#define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
> +#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
> +#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
> +#define GEN12_CCS0_CCS1_INTR_MASK _MMIO(0x190100)
> +#define GEN12_CCS2_CCS3_INTR_MASK _MMIO(0x190104)
> +#define XEHPC_BCS1_BCS2_INTR_MASK _MMIO(0x190110)
> +#define XEHPC_BCS3_BCS4_INTR_MASK _MMIO(0x190114)
> +#define XEHPC_BCS5_BCS6_INTR_MASK _MMIO(0x190118)
> +#define XEHPC_BCS7_BCS8_INTR_MASK _MMIO(0x19011c)
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
> index af2fcf1c32f4..b426f8000070 100644
> --- a/drivers/gpu/drm/xe/xe_execlist.c
> +++ b/drivers/gpu/drm/xe/xe_execlist.c
> @@ -7,6 +7,7 @@
> #include <drm/drm_managed.h>
>
> #include "regs/xe_engine_regs.h"
> +#include "regs/xe_gt_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_engine.h"
> @@ -20,7 +21,6 @@
> #include "xe_sched_job.h"
>
> #include "gt/intel_gpu_commands.h"
> -#include "gt/intel_gt_regs.h"
> #include "gt/intel_lrc_reg.h"
> #include "i915_reg.h"
>
> diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c
> index 188197c3a8fe..e1346d18b580 100644
> --- a/drivers/gpu/drm/xe/xe_force_wake.c
> +++ b/drivers/gpu/drm/xe/xe_force_wake.c
> @@ -6,11 +6,10 @@
>
> #include <drm/drm_util.h>
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_gt.h"
> #include "xe_mmio.h"
>
> -#include "gt/intel_gt_regs.h"
> -
> #define XE_FORCE_WAKE_ACK_TIMEOUT_MS 50
>
> static struct xe_gt *
> diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> index 53a1edaee02d..2c9b2175c5bb 100644
> --- a/drivers/gpu/drm/xe/xe_ggtt.c
> +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> @@ -9,6 +9,7 @@
> #include <drm/drm_managed.h>
> #include <drm/i915_drm.h>
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_gt.h"
> @@ -17,7 +18,6 @@
> #include "xe_mmio.h"
> #include "xe_wopcm.h"
>
> -#include "gt/intel_gt_regs.h"
> #include "i915_reg.h"
>
> /* FIXME: Common file, preferably auto-gen */
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index 5c7c2757bb49..c195b4b9f9b8 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -8,6 +8,7 @@
>
> #include <drm/drm_managed.h>
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_bb.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> @@ -40,8 +41,6 @@
> #include "xe_wa.h"
> #include "xe_wopcm.h"
>
> -#include "gt/intel_gt_regs.h"
> -
> struct xe_gt *xe_find_full_gt(struct xe_gt *gt)
> {
> struct xe_gt *search;
> diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
> index e50117103e1e..e9aa7c5452af 100644
> --- a/drivers/gpu/drm/xe/xe_gt_clock.c
> +++ b/drivers/gpu/drm/xe/xe_gt_clock.c
> @@ -4,12 +4,12 @@
> */
> #include "xe_gt_clock.h"
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_device.h"
> #include "xe_gt.h"
> #include "xe_macros.h"
> #include "xe_mmio.h"
>
> -#include "gt/intel_gt_regs.h"
> #include "i915_reg.h"
>
> static u32 read_reference_ts_freq(struct xe_gt *gt)
> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
> index 43910e48bdc9..c4ede7d6d97c 100644
> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
> @@ -4,13 +4,12 @@
> */
> #include "xe_gt_mcr.h"
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_gt.h"
> #include "xe_gt_topology.h"
> #include "xe_gt_types.h"
> #include "xe_mmio.h"
>
> -#include "gt/intel_gt_regs.h"
> -
> /**
> * DOC: GT Multicast/Replicated (MCR) Register Support
> *
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index 88cc912fa7eb..a2a124a7fc0b 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -4,6 +4,7 @@
> */
> #include "xe_guc.h"
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_force_wake.h"
> @@ -20,7 +21,6 @@
> #include "xe_uc_fw.h"
> #include "xe_wopcm.h"
>
> -#include "gt/intel_gt_regs.h"
> #include "i915_reg_defs.h"
>
> /* TODO: move to common file */
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index bde094388a34..3cf04594f12f 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -9,6 +9,7 @@
> #include <drm/drm_managed.h>
>
> #include "regs/xe_engine_regs.h"
> +#include "regs/xe_gt_regs.h"
> #include "xe_bo.h"
> #include "xe_gt.h"
> #include "xe_guc.h"
> @@ -19,9 +20,6 @@
> #include "xe_mmio.h"
> #include "xe_platform_types.h"
>
> -#include "gt/intel_gt_regs.h"
> -
> -
> /* Slack of a few additional entries per engine */
> #define ADS_REGSET_EXTRA_MAX 8
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> index 1d4ac0c26d3c..f7aaf4826f00 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> @@ -8,6 +8,7 @@
>
> #include <drm/drm_managed.h>
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_gt.h"
> @@ -30,7 +31,6 @@
> #define GEN10_FREQ_INFO_REC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
> #define RPE_MASK REG_GENMASK(15, 8)
>
> -#include "gt/intel_gt_regs.h"
> /* For GEN6_RPNSWREQ.reg to be merged when the definition moves to Xe */
> #define REQ_RATIO_MASK REG_GENMASK(31, 23)
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index ce5d6641499f..caae4f897644 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -7,6 +7,7 @@
> #include <drm/drm_managed.h>
>
> #include "regs/xe_engine_regs.h"
> +#include "regs/xe_gt_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_execlist.h"
> @@ -21,7 +22,6 @@
> #include "xe_sched_job.h"
> #include "xe_wa.h"
>
> -#include "gt/intel_gt_regs.h"
> #include "i915_reg.h"
>
> #define MAX_MMIO_BASES 3
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index f30fd2b14c22..d7756c14b4e2 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -8,6 +8,7 @@
>
> #include <drm/drm_managed.h>
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_device.h"
> #include "xe_display.h"
> #include "xe_drv.h"
> @@ -16,7 +17,6 @@
> #include "xe_hw_engine.h"
> #include "xe_mmio.h"
>
> -#include "gt/intel_gt_regs.h"
> #include "i915_reg.h"
>
> static void gen3_assert_iir_is_zero(struct xe_gt *gt, i915_reg_t reg)
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index 60ffe3f80c59..8e341d11f2e3 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -5,6 +5,7 @@
> #include "xe_lrc.h"
>
> #include "regs/xe_engine_regs.h"
> +#include "regs/xe_gt_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_engine_types.h"
> @@ -14,7 +15,6 @@
> #include "xe_vm.h"
>
> #include "gt/intel_gpu_commands.h"
> -#include "gt/intel_gt_regs.h"
> #include "gt/intel_lrc_reg.h"
> #include "i915_reg.h"
>
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index 892008dcbaf4..d0cd9e920d34 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -8,13 +8,13 @@
> #include <drm/xe_drm.h>
>
> #include "regs/xe_engine_regs.h"
> +#include "regs/xe_gt_regs.h"
> #include "xe_device.h"
> #include "xe_gt.h"
> #include "xe_gt_mcr.h"
> #include "xe_macros.h"
> #include "xe_module.h"
>
> -#include "gt/intel_gt_regs.h"
> #include "i915_reg.h"
>
> #define XEHP_MTCFG_ADDR _MMIO(0x101800)
> diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
> index 99d3cc6c7164..173f5c4321f5 100644
> --- a/drivers/gpu/drm/xe/xe_mocs.c
> +++ b/drivers/gpu/drm/xe/xe_mocs.c
> @@ -4,6 +4,7 @@
> */
> #include "xe_mocs.h"
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> #include "xe_engine.h"
> @@ -12,8 +13,6 @@
> #include "xe_platform_types.h"
> #include "xe_step_types.h"
>
> -#include "gt/intel_gt_regs.h"
> -
> #if IS_ENABLED(CONFIG_DRM_XE_DEBUG)
> #define mocs_dbg drm_dbg
> #else
> diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
> index bd3b64ad9c26..6519c6648460 100644
> --- a/drivers/gpu/drm/xe/xe_reg_sr.c
> +++ b/drivers/gpu/drm/xe/xe_reg_sr.c
> @@ -12,6 +12,7 @@
> #include <drm/drm_print.h>
>
> #include "regs/xe_engine_regs.h"
> +#include "regs/xe_gt_regs.h"
> #include "xe_device_types.h"
> #include "xe_force_wake.h"
> #include "xe_gt.h"
> @@ -20,8 +21,6 @@
> #include "xe_mmio.h"
> #include "xe_rtp_types.h"
>
> -#include "gt/intel_gt_regs.h"
> -
> #define XE_REG_SR_GROW_STEP_DEFAULT 16
>
> static void reg_sr_fini(struct drm_device *drm, void *arg)
> diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> index e2f3f374b856..66ff9da46070 100644
> --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> @@ -5,12 +5,11 @@
> #include "xe_reg_whitelist.h"
>
> #include "regs/xe_engine_regs.h"
> +#include "regs/xe_gt_regs.h"
> #include "xe_gt_types.h"
> #include "xe_platform_types.h"
> #include "xe_rtp.h"
>
> -#include "gt/intel_gt_regs.h"
> -
> #undef _MMIO
> #undef MCR_REG
> #define _MMIO(x) _XE_RTP_REG(x)
> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
> index 5049367bc92d..a7ab0d4451f0 100644
> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> @@ -4,6 +4,7 @@
> */
> #include "xe_ring_ops.h"
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_engine_types.h"
> #include "xe_gt.h"
> #include "xe_lrc.h"
> @@ -12,7 +13,6 @@
> #include "xe_vm_types.h"
>
> #include "gt/intel_gpu_commands.h"
> -#include "gt/intel_gt_regs.h"
> #include "gt/intel_lrc_reg.h"
> #include "i915_reg.h"
>
> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> index 5f8c56baaeba..cda2da27f7c6 100644
> --- a/drivers/gpu/drm/xe/xe_tuning.c
> +++ b/drivers/gpu/drm/xe/xe_tuning.c
> @@ -5,12 +5,11 @@
>
> #include "xe_tuning.h"
>
> +#include "regs/xe_gt_regs.h"
> #include "xe_gt_types.h"
> #include "xe_platform_types.h"
> #include "xe_rtp.h"
>
> -#include "gt/intel_gt_regs.h"
> -
> #undef _MMIO
> #undef MCR_REG
> #define _MMIO(x) _XE_RTP_REG(x)
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index 92065341c001..155cfd1dcc50 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -8,6 +8,7 @@
> #include <linux/compiler_types.h>
>
> #include "regs/xe_engine_regs.h"
> +#include "regs/xe_gt_regs.h"
> #include "xe_device_types.h"
> #include "xe_force_wake.h"
> #include "xe_gt.h"
> @@ -17,7 +18,6 @@
> #include "xe_rtp.h"
> #include "xe_step.h"
>
> -#include "gt/intel_gt_regs.h"
> #include "i915_reg.h"
>
> /**
> --
> 2.39.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 06/11] drm/xe: Remove dependency on intel_lrc_reg.h
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 06/11] drm/xe: Remove dependency on intel_lrc_reg.h Lucas De Marchi
@ 2023-02-24 18:20 ` Matt Roper
2023-02-24 18:54 ` Lucas De Marchi
0 siblings, 1 reply; 42+ messages in thread
From: Matt Roper @ 2023-02-24 18:20 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe, Maarten Lankhorst, Matthew Auld
On Thu, Feb 16, 2023 at 04:52:21PM -0800, Lucas De Marchi wrote:
> Create regs/xe_lrc_regs.h file with all the registers used by the xe
> driver. Eventually the registers may be defined in a different way and
> since xe doesn't supported below gen12, the number of registers touched
> is much smaller, so create a new header.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_lrc_regs.h | 17 +++++++++++++++++
> drivers/gpu/drm/xe/xe_execlist.c | 2 +-
> drivers/gpu/drm/xe/xe_guc_submit.c | 3 +--
> drivers/gpu/drm/xe/xe_lrc.c | 2 +-
> drivers/gpu/drm/xe/xe_ring_ops.c | 2 +-
> 5 files changed, 21 insertions(+), 5 deletions(-)
> create mode 100644 drivers/gpu/drm/xe/regs/xe_lrc_regs.h
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_lrc_regs.h b/drivers/gpu/drm/xe/regs/xe_lrc_regs.h
> new file mode 100644
> index 000000000000..e8a13fa6722b
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/regs/xe_lrc_regs.h
This file isn't so much about "register definitions" as it is about
"register offsets in the context image." Maybe we should name this a
bit differently to make that clear? E.g., xe_lrc_offsets.h or
xe_lrc_layout.h or something.
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_LRC_REGS_H_
> +#define _XE_LRC_REGS_H_
> +
> +#define CTX_CONTEXT_CONTROL (0x02 + 1)
> +#define CTX_RING_HEAD (0x04 + 1)
> +#define CTX_RING_TAIL (0x06 + 1)
> +#define CTX_RING_START (0x08 + 1)
> +#define CTX_RING_CTL (0x0a + 1)
> +#define CTX_PDP0_UDW (0x30 + 1)
> +#define CTX_PDP0_LDW (0x32 + 1)
I'm wondering if it would be more clear/obvious if we laid this out as a
C structure rather than using defines?
struct tgl_lrc_layout {
u8 _lri1;
u16 CONTEXT_CONTROL;
u16 RING_TAIL;
u16 RING_START;
...
};
and then later just use code like
offsetof(struct tgl_lrc_layout, RING_TAIL);
to find the offsets when needed. This could cover not just the
simple/common subset of registers here, but also stuff like per-platform
stuff like MI_MODE, BB_OFFSET, GPR0, etc. that we have lookup helpers
for in i915.
Anyway, that's something we can think about in the future; no need to
handle it as part of this series.
Matt
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
> index b426f8000070..ea551dc922cc 100644
> --- a/drivers/gpu/drm/xe/xe_execlist.c
> +++ b/drivers/gpu/drm/xe/xe_execlist.c
> @@ -7,6 +7,7 @@
> #include <drm/drm_managed.h>
>
> #include "regs/xe_engine_regs.h"
> +#include "regs/xe_lrc_regs.h"
> #include "regs/xe_gt_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> @@ -21,7 +22,6 @@
> #include "xe_sched_job.h"
>
> #include "gt/intel_gpu_commands.h"
> -#include "gt/intel_lrc_reg.h"
> #include "i915_reg.h"
>
> #define XE_EXECLIST_HANG_LIMIT 1
> diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
> index 305a0e061778..451c9e1c43ff 100644
> --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
> @@ -12,6 +12,7 @@
>
> #include <drm/drm_managed.h>
>
> +#include "regs/xe_lrc_regs.h"
> #include "xe_device.h"
> #include "xe_engine.h"
> #include "xe_force_wake.h"
> @@ -30,8 +31,6 @@
> #include "xe_trace.h"
> #include "xe_vm.h"
>
> -#include "gt/intel_lrc_reg.h"
> -
> static struct xe_gt *
> guc_to_gt(struct xe_guc *guc)
> {
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index 8e341d11f2e3..af6fe47a0495 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -5,6 +5,7 @@
> #include "xe_lrc.h"
>
> #include "regs/xe_engine_regs.h"
> +#include "regs/xe_lrc_regs.h"
> #include "regs/xe_gt_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> @@ -15,7 +16,6 @@
> #include "xe_vm.h"
>
> #include "gt/intel_gpu_commands.h"
> -#include "gt/intel_lrc_reg.h"
> #include "i915_reg.h"
>
> #define GEN8_CTX_VALID (1 << 0)
> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
> index a7ab0d4451f0..0a1e32ab9758 100644
> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> @@ -4,6 +4,7 @@
> */
> #include "xe_ring_ops.h"
>
> +#include "regs/xe_lrc_regs.h"
> #include "regs/xe_gt_regs.h"
> #include "xe_engine_types.h"
> #include "xe_gt.h"
> @@ -13,7 +14,6 @@
> #include "xe_vm_types.h"
>
> #include "gt/intel_gpu_commands.h"
> -#include "gt/intel_lrc_reg.h"
> #include "i915_reg.h"
>
> static u32 preparser_disable(bool state)
> --
> 2.39.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 07/11] drm/xe: Remove dependency on intel_gpu_commands.h
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 07/11] drm/xe: Remove dependency on intel_gpu_commands.h Lucas De Marchi
@ 2023-02-24 18:26 ` Matt Roper
0 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2023-02-24 18:26 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe, Maarten Lankhorst, Matthew Auld
On Thu, Feb 16, 2023 at 04:52:22PM -0800, Lucas De Marchi wrote:
> Copy the macros used by xe in intel_gpu_commands.h to
> regs/xe_gpu_commands.h.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_gpu_commands.h | 96 +++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_bb.c | 3 +-
> drivers/gpu/drm/xe/xe_device.h | 3 +-
> drivers/gpu/drm/xe/xe_execlist.c | 2 +-
> drivers/gpu/drm/xe/xe_lrc.c | 2 +-
> drivers/gpu/drm/xe/xe_migrate.c | 3 +-
> drivers/gpu/drm/xe/xe_ring_ops.c | 2 +-
> 7 files changed, 102 insertions(+), 9 deletions(-)
> create mode 100644 drivers/gpu/drm/xe/regs/xe_gpu_commands.h
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
> new file mode 100644
> index 000000000000..bf6dc1c8563d
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
> @@ -0,0 +1,96 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_GPU_COMMANDS_H_
> +#define _XE_GPU_COMMANDS_H_
> +
> +#define INSTR_CLIENT_SHIFT 29
> +#define INSTR_MI_CLIENT 0x0
> +#define __INSTR(client) ((client) << INSTR_CLIENT_SHIFT)
> +
> +#define MI_INSTR(opcode, flags) \
> + (__INSTR(INSTR_MI_CLIENT) | (opcode) << 23 | (flags))
> +
> +#define MI_NOOP MI_INSTR(0, 0)
> +#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
> +
> +#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
> +#define MI_ARB_ENABLE (1<<0)
> +#define MI_ARB_DISABLE (0<<0)
> +
> +#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
> +#define MI_STORE_DATA_IMM MI_INSTR(0x20, 0)
> +
> +#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
> +#define MI_LRI_LRM_CS_MMIO REG_BIT(19)
> +#define MI_LRI_MMIO_REMAP_EN REG_BIT(17)
> +#define MI_LRI_FORCE_POSTED (1<<12)
> +
> +#define MI_FLUSH_DW MI_INSTR(0x26, 1)
> +#define MI_FLUSH_DW_STORE_INDEX (1<<21)
> +#define MI_INVALIDATE_TLB (1<<18)
> +#define MI_FLUSH_DW_CCS (1<<16)
> +#define MI_FLUSH_DW_OP_STOREDW (1<<14)
> +#define MI_FLUSH_DW_USE_GTT (1<<2)
> +
> +#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
> +
> +#define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3)
> +#define SRC_ACCESS_TYPE_SHIFT 21
> +#define DST_ACCESS_TYPE_SHIFT 20
> +#define CCS_SIZE_MASK 0x3FF
> +#define CCS_SIZE_SHIFT 8
> +#define XY_CTRL_SURF_MOCS_MASK GENMASK(31, 25)
> +#define NUM_CCS_BYTES_PER_BLOCK 256
> +#define NUM_BYTES_PER_CCS_BYTE 256
> +#define NUM_CCS_BLKS_PER_XFER 1024
> +
> +#define XY_FAST_COLOR_BLT_CMD (2 << 29 | 0x44 << 22)
> +#define XY_FAST_COLOR_BLT_DEPTH_32 (2 << 19)
> +#define XY_FAST_COLOR_BLT_DW 16
> +#define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21)
> +#define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31
> +
> +#define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22)
> +#define BLT_DEPTH_32 (3<<24)
> +
> +#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
> +#define PIPE_CONTROL_TILE_CACHE_FLUSH (1<<28)
> +#define PIPE_CONTROL_AMFS_FLUSH (1<<25)
> +#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24)
> +#define PIPE_CONTROL_CS_STALL (1<<20)
> +#define PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET (1<<19)
> +#define PIPE_CONTROL_PSD_SYNC (1<<17)
> +#define PIPE_CONTROL_QW_WRITE (1<<14)
> +#define PIPE_CONTROL_DEPTH_STALL (1<<13)
> +#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12)
> +#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10)
> +#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
> +#define PIPE_CONTROL_FLUSH_ENABLE (1<<7)
> +#define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
> +#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
> +#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
> +#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
> +
> +#define PIPE_CONTROL_3D_ENGINE_FLAGS (\
> + PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
> + PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
> + PIPE_CONTROL_TILE_CACHE_FLUSH | \
> + PIPE_CONTROL_DEPTH_STALL | \
> + PIPE_CONTROL_STALL_AT_SCOREBOARD | \
> + PIPE_CONTROL_PSD_SYNC | \
> + PIPE_CONTROL_AMFS_FLUSH | \
> + PIPE_CONTROL_VF_CACHE_INVALIDATE | \
> + PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
> +#define PIPE_CONTROL_3D_ARCH_FLAGS ( \
> + PIPE_CONTROL_3D_ENGINE_FLAGS | \
> + PIPE_CONTROL_INDIRECT_STATE_DISABLE | \
> + PIPE_CONTROL_FLUSH_ENABLE | \
> + PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
> + PIPE_CONTROL_DC_FLUSH_ENABLE)
These two flag collections are also defined in
drivers/gpu/drm/xe/xe_ring_ops.c right now. Should we either drop them
here or drop them there?
Matt
> +
> +#define MI_ARB_CHECK MI_INSTR(0x05, 0)
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_bb.c b/drivers/gpu/drm/xe/xe_bb.c
> index a25079d4e710..742d12023160 100644
> --- a/drivers/gpu/drm/xe/xe_bb.c
> +++ b/drivers/gpu/drm/xe/xe_bb.c
> @@ -4,6 +4,7 @@
> */
> #include "xe_bb.h"
>
> +#include "regs/xe_gpu_commands.h"
> #include "xe_device.h"
> #include "xe_engine_types.h"
> #include "xe_hw_fence.h"
> @@ -11,8 +12,6 @@
> #include "xe_sched_job.h"
> #include "xe_vm_types.h"
>
> -#include "gt/intel_gpu_commands.h"
> -
> struct xe_bb *xe_bb_new(struct xe_gt *gt, u32 dwords, bool usm)
> {
> struct xe_bb *bb = kmalloc(sizeof(*bb), GFP_KERNEL);
> diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
> index 88d55671b068..ee10b6c11e9f 100644
> --- a/drivers/gpu/drm/xe/xe_device.h
> +++ b/drivers/gpu/drm/xe/xe_device.h
> @@ -11,12 +11,11 @@ struct xe_file;
>
> #include <drm/drm_util.h>
>
> +#include "regs/xe_gpu_commands.h"
> #include "xe_device_types.h"
> #include "xe_macros.h"
> #include "xe_force_wake.h"
>
> -#include "gt/intel_gpu_commands.h"
> -
> static inline struct xe_device *to_xe_device(const struct drm_device *dev)
> {
> return container_of(dev, struct xe_device, drm);
> diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
> index ea551dc922cc..c3c52bdc70b1 100644
> --- a/drivers/gpu/drm/xe/xe_execlist.c
> +++ b/drivers/gpu/drm/xe/xe_execlist.c
> @@ -8,6 +8,7 @@
>
> #include "regs/xe_engine_regs.h"
> #include "regs/xe_lrc_regs.h"
> +#include "regs/xe_gpu_commands.h"
> #include "regs/xe_gt_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> @@ -21,7 +22,6 @@
> #include "xe_ring_ops_types.h"
> #include "xe_sched_job.h"
>
> -#include "gt/intel_gpu_commands.h"
> #include "i915_reg.h"
>
> #define XE_EXECLIST_HANG_LIMIT 1
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index af6fe47a0495..c1df76c2cf78 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -6,6 +6,7 @@
>
> #include "regs/xe_engine_regs.h"
> #include "regs/xe_lrc_regs.h"
> +#include "regs/xe_gpu_commands.h"
> #include "regs/xe_gt_regs.h"
> #include "xe_bo.h"
> #include "xe_device.h"
> @@ -15,7 +16,6 @@
> #include "xe_map.h"
> #include "xe_vm.h"
>
> -#include "gt/intel_gpu_commands.h"
> #include "i915_reg.h"
>
> #define GEN8_CTX_VALID (1 << 0)
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index 3d2f8d04bc3a..3c2ed4d9f63d 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -10,6 +10,7 @@
> #include <drm/ttm/ttm_tt.h>
> #include <drm/xe_drm.h>
>
> +#include "regs/xe_gpu_commands.h"
> #include "xe_bb.h"
> #include "xe_bo.h"
> #include "xe_engine.h"
> @@ -26,8 +27,6 @@
> #include "xe_trace.h"
> #include "xe_vm.h"
>
> -#include "gt/intel_gpu_commands.h"
> -
> /**
> * struct xe_migrate - migrate context.
> */
> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
> index 0a1e32ab9758..104f96658e1f 100644
> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> @@ -5,6 +5,7 @@
> #include "xe_ring_ops.h"
>
> #include "regs/xe_lrc_regs.h"
> +#include "regs/xe_gpu_commands.h"
> #include "regs/xe_gt_regs.h"
> #include "xe_engine_types.h"
> #include "xe_gt.h"
> @@ -13,7 +14,6 @@
> #include "xe_sched_job.h"
> #include "xe_vm_types.h"
>
> -#include "gt/intel_gpu_commands.h"
> #include "i915_reg.h"
>
> static u32 preparser_disable(bool state)
> --
> 2.39.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 05/11] drm/xe: Remove dependency on intel_gt_regs.h
2023-02-24 18:06 ` Matt Roper
@ 2023-02-24 18:29 ` Lucas De Marchi
2023-02-24 18:34 ` Matt Roper
0 siblings, 1 reply; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-24 18:29 UTC (permalink / raw)
To: Matt Roper; +Cc: Rodrigo Vivi, intel-xe, Maarten Lankhorst, Matthew Auld
On Fri, Feb 24, 2023 at 10:06:14AM -0800, Matt Roper wrote:
>On Thu, Feb 16, 2023 at 04:52:20PM -0800, Lucas De Marchi wrote:
>> Create regs/xe_gt_regs.h file with all the registers and bit
>> definitions used by the xe driver. Eventually the registers may be
>> defined in a different way and since xe doesn't supported below gen12,
>> the number of registers touched is much smaller, so create a new header.
>>
>> The definitions themselves are direct copy from the
>> gt/intel_gt_regs.h file, just sorting the registers by address.
>> Cleaning those up and adhering to a common coding style is left for
>> later.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg_defs.h | 2 +
>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 287 ++++++++++++++++++++++++++
>> drivers/gpu/drm/xe/xe_execlist.c | 2 +-
>> drivers/gpu/drm/xe/xe_force_wake.c | 3 +-
>> drivers/gpu/drm/xe/xe_ggtt.c | 2 +-
>> drivers/gpu/drm/xe/xe_gt.c | 3 +-
>> drivers/gpu/drm/xe/xe_gt_clock.c | 2 +-
>> drivers/gpu/drm/xe/xe_gt_mcr.c | 3 +-
>> drivers/gpu/drm/xe/xe_guc.c | 2 +-
>> drivers/gpu/drm/xe/xe_guc_ads.c | 4 +-
>> drivers/gpu/drm/xe/xe_guc_pc.c | 2 +-
>> drivers/gpu/drm/xe/xe_hw_engine.c | 2 +-
>> drivers/gpu/drm/xe/xe_irq.c | 2 +-
>> drivers/gpu/drm/xe/xe_lrc.c | 2 +-
>> drivers/gpu/drm/xe/xe_mmio.c | 2 +-
>> drivers/gpu/drm/xe/xe_mocs.c | 3 +-
>> drivers/gpu/drm/xe/xe_reg_sr.c | 3 +-
>> drivers/gpu/drm/xe/xe_reg_whitelist.c | 3 +-
>> drivers/gpu/drm/xe/xe_ring_ops.c | 2 +-
>> drivers/gpu/drm/xe/xe_tuning.c | 3 +-
>> drivers/gpu/drm/xe/xe_wa.c | 2 +-
>> 21 files changed, 308 insertions(+), 28 deletions(-)
>> create mode 100644 drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
>> index b5e06b6a9478..a6080c983a77 100644
>> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
>> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
>> @@ -136,6 +136,8 @@ typedef struct {
>> u32 reg;
>> } i915_mcr_reg_t;
>>
>> +#define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg = (offset) })
>
>Should there be a corresponding removal of this definition from
>drivers/gpu/drm/i915/gt/intel_gt_regs.h ?
>
>Aside from that,
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
good catch. I was trying not to change the i915 headers, but this
one went unoticed while fixing the build.
I wonder if this should be a separate patch to merge in
drm-intel-next by itself. It's harmless though and we could keep it
in the xe branch, as long as also removing from drivers/gpu/drm/i915/gt/intel_gt_regs.h
Rodrigo / Matt, are you ok with this approach?
Lucas De Marchi
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 05/11] drm/xe: Remove dependency on intel_gt_regs.h
2023-02-24 18:29 ` Lucas De Marchi
@ 2023-02-24 18:34 ` Matt Roper
2023-02-24 19:47 ` Vivi, Rodrigo
0 siblings, 1 reply; 42+ messages in thread
From: Matt Roper @ 2023-02-24 18:34 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: Rodrigo Vivi, intel-xe, Maarten Lankhorst, Matthew Auld
On Fri, Feb 24, 2023 at 10:29:14AM -0800, Lucas De Marchi wrote:
> On Fri, Feb 24, 2023 at 10:06:14AM -0800, Matt Roper wrote:
> > On Thu, Feb 16, 2023 at 04:52:20PM -0800, Lucas De Marchi wrote:
> > > Create regs/xe_gt_regs.h file with all the registers and bit
> > > definitions used by the xe driver. Eventually the registers may be
> > > defined in a different way and since xe doesn't supported below gen12,
> > > the number of registers touched is much smaller, so create a new header.
> > >
> > > The definitions themselves are direct copy from the
> > > gt/intel_gt_regs.h file, just sorting the registers by address.
> > > Cleaning those up and adhering to a common coding style is left for
> > > later.
> > >
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_reg_defs.h | 2 +
> > > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 287 ++++++++++++++++++++++++++
> > > drivers/gpu/drm/xe/xe_execlist.c | 2 +-
> > > drivers/gpu/drm/xe/xe_force_wake.c | 3 +-
> > > drivers/gpu/drm/xe/xe_ggtt.c | 2 +-
> > > drivers/gpu/drm/xe/xe_gt.c | 3 +-
> > > drivers/gpu/drm/xe/xe_gt_clock.c | 2 +-
> > > drivers/gpu/drm/xe/xe_gt_mcr.c | 3 +-
> > > drivers/gpu/drm/xe/xe_guc.c | 2 +-
> > > drivers/gpu/drm/xe/xe_guc_ads.c | 4 +-
> > > drivers/gpu/drm/xe/xe_guc_pc.c | 2 +-
> > > drivers/gpu/drm/xe/xe_hw_engine.c | 2 +-
> > > drivers/gpu/drm/xe/xe_irq.c | 2 +-
> > > drivers/gpu/drm/xe/xe_lrc.c | 2 +-
> > > drivers/gpu/drm/xe/xe_mmio.c | 2 +-
> > > drivers/gpu/drm/xe/xe_mocs.c | 3 +-
> > > drivers/gpu/drm/xe/xe_reg_sr.c | 3 +-
> > > drivers/gpu/drm/xe/xe_reg_whitelist.c | 3 +-
> > > drivers/gpu/drm/xe/xe_ring_ops.c | 2 +-
> > > drivers/gpu/drm/xe/xe_tuning.c | 3 +-
> > > drivers/gpu/drm/xe/xe_wa.c | 2 +-
> > > 21 files changed, 308 insertions(+), 28 deletions(-)
> > > create mode 100644 drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
> > > index b5e06b6a9478..a6080c983a77 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> > > @@ -136,6 +136,8 @@ typedef struct {
> > > u32 reg;
> > > } i915_mcr_reg_t;
> > >
> > > +#define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg = (offset) })
> >
> > Should there be a corresponding removal of this definition from
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h ?
> >
> > Aside from that,
> >
> > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
>
> good catch. I was trying not to change the i915 headers, but this
> one went unoticed while fixing the build.
>
> I wonder if this should be a separate patch to merge in
> drm-intel-next by itself. It's harmless though and we could keep it
> in the xe branch, as long as also removing from drivers/gpu/drm/i915/gt/intel_gt_regs.h
>
> Rodrigo / Matt, are you ok with this approach?
Either way sounds fine to me.
Matt
>
> Lucas De Marchi
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 06/11] drm/xe: Remove dependency on intel_lrc_reg.h
2023-02-24 18:20 ` Matt Roper
@ 2023-02-24 18:54 ` Lucas De Marchi
0 siblings, 0 replies; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-24 18:54 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe, Maarten Lankhorst, Matthew Auld
On Fri, Feb 24, 2023 at 10:20:10AM -0800, Matt Roper wrote:
>On Thu, Feb 16, 2023 at 04:52:21PM -0800, Lucas De Marchi wrote:
>> Create regs/xe_lrc_regs.h file with all the registers used by the xe
>> driver. Eventually the registers may be defined in a different way and
>> since xe doesn't supported below gen12, the number of registers touched
>> is much smaller, so create a new header.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/xe/regs/xe_lrc_regs.h | 17 +++++++++++++++++
>> drivers/gpu/drm/xe/xe_execlist.c | 2 +-
>> drivers/gpu/drm/xe/xe_guc_submit.c | 3 +--
>> drivers/gpu/drm/xe/xe_lrc.c | 2 +-
>> drivers/gpu/drm/xe/xe_ring_ops.c | 2 +-
>> 5 files changed, 21 insertions(+), 5 deletions(-)
>> create mode 100644 drivers/gpu/drm/xe/regs/xe_lrc_regs.h
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_lrc_regs.h b/drivers/gpu/drm/xe/regs/xe_lrc_regs.h
>> new file mode 100644
>> index 000000000000..e8a13fa6722b
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/regs/xe_lrc_regs.h
>
>This file isn't so much about "register definitions" as it is about
>"register offsets in the context image." Maybe we should name this a
>bit differently to make that clear? E.g., xe_lrc_offsets.h or
>xe_lrc_layout.h or something.
yeah, I like xe_lrc_layout.h. I will change to use it.
>
>> @@ -0,0 +1,17 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_LRC_REGS_H_
>> +#define _XE_LRC_REGS_H_
>> +
>> +#define CTX_CONTEXT_CONTROL (0x02 + 1)
>> +#define CTX_RING_HEAD (0x04 + 1)
>> +#define CTX_RING_TAIL (0x06 + 1)
>> +#define CTX_RING_START (0x08 + 1)
>> +#define CTX_RING_CTL (0x0a + 1)
>> +#define CTX_PDP0_UDW (0x30 + 1)
>> +#define CTX_PDP0_LDW (0x32 + 1)
>
>I'm wondering if it would be more clear/obvious if we laid this out as a
>C structure rather than using defines?
>
> struct tgl_lrc_layout {
> u8 _lri1;
> u16 CONTEXT_CONTROL;
> u16 RING_TAIL;
> u16 RING_START;
> ...
> };
>
>and then later just use code like
>
> offsetof(struct tgl_lrc_layout, RING_TAIL);
>
>to find the offsets when needed. This could cover not just the
>simple/common subset of registers here, but also stuff like per-platform
>stuff like MI_MODE, BB_OFFSET, GPR0, etc. that we have lookup helpers
>for in i915.
>
>Anyway, that's something we can think about in the future; no need to
>handle it as part of this series.
yeah... sounds good. I will keep it as is for now since this series is a
prerequisite fro the WAs I'm working on. But changing to a struct layout
IMO would be a very good improvement. Let me also add an issue in
gitlab with that so we don't forget.
thanks
Lucas De Marchi
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 05/11] drm/xe: Remove dependency on intel_gt_regs.h
2023-02-24 18:34 ` Matt Roper
@ 2023-02-24 19:47 ` Vivi, Rodrigo
2023-02-24 20:25 ` Lucas De Marchi
0 siblings, 1 reply; 42+ messages in thread
From: Vivi, Rodrigo @ 2023-02-24 19:47 UTC (permalink / raw)
To: Roper, Matthew D, De Marchi, Lucas
Cc: intel-xe@lists.freedesktop.org, Lankhorst, Maarten, Auld, Matthew
On Fri, 2023-02-24 at 10:34 -0800, Matt Roper wrote:
> On Fri, Feb 24, 2023 at 10:29:14AM -0800, Lucas De Marchi wrote:
> > On Fri, Feb 24, 2023 at 10:06:14AM -0800, Matt Roper wrote:
> > > On Thu, Feb 16, 2023 at 04:52:20PM -0800, Lucas De Marchi wrote:
> > > > Create regs/xe_gt_regs.h file with all the registers and bit
> > > > definitions used by the xe driver. Eventually the registers may
> > > > be
> > > > defined in a different way and since xe doesn't supported below
> > > > gen12,
> > > > the number of registers touched is much smaller, so create a
> > > > new header.
> > > >
> > > > The definitions themselves are direct copy from the
> > > > gt/intel_gt_regs.h file, just sorting the registers by address.
> > > > Cleaning those up and adhering to a common coding style is left
> > > > for
> > > > later.
> > > >
> > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/i915_reg_defs.h | 2 +
> > > > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 287
> > > > ++++++++++++++++++++++++++
> > > > drivers/gpu/drm/xe/xe_execlist.c | 2 +-
> > > > drivers/gpu/drm/xe/xe_force_wake.c | 3 +-
> > > > drivers/gpu/drm/xe/xe_ggtt.c | 2 +-
> > > > drivers/gpu/drm/xe/xe_gt.c | 3 +-
> > > > drivers/gpu/drm/xe/xe_gt_clock.c | 2 +-
> > > > drivers/gpu/drm/xe/xe_gt_mcr.c | 3 +-
> > > > drivers/gpu/drm/xe/xe_guc.c | 2 +-
> > > > drivers/gpu/drm/xe/xe_guc_ads.c | 4 +-
> > > > drivers/gpu/drm/xe/xe_guc_pc.c | 2 +-
> > > > drivers/gpu/drm/xe/xe_hw_engine.c | 2 +-
> > > > drivers/gpu/drm/xe/xe_irq.c | 2 +-
> > > > drivers/gpu/drm/xe/xe_lrc.c | 2 +-
> > > > drivers/gpu/drm/xe/xe_mmio.c | 2 +-
> > > > drivers/gpu/drm/xe/xe_mocs.c | 3 +-
> > > > drivers/gpu/drm/xe/xe_reg_sr.c | 3 +-
> > > > drivers/gpu/drm/xe/xe_reg_whitelist.c | 3 +-
> > > > drivers/gpu/drm/xe/xe_ring_ops.c | 2 +-
> > > > drivers/gpu/drm/xe/xe_tuning.c | 3 +-
> > > > drivers/gpu/drm/xe/xe_wa.c | 2 +-
> > > > 21 files changed, 308 insertions(+), 28 deletions(-)
> > > > create mode 100644 drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
> > > > b/drivers/gpu/drm/i915/i915_reg_defs.h
> > > > index b5e06b6a9478..a6080c983a77 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> > > > @@ -136,6 +136,8 @@ typedef struct {
> > > > u32 reg;
> > > > } i915_mcr_reg_t;
> > > >
> > > > +#define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg =
> > > > (offset) })
> > >
> > > Should there be a corresponding removal of this definition from
> > > drivers/gpu/drm/i915/gt/intel_gt_regs.h ?
> > >
> > > Aside from that,
> > >
> > > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> >
> >
> > good catch. I was trying not to change the i915 headers, but this
> > one went unoticed while fixing the build.
> >
> > I wonder if this should be a separate patch to merge in
> > drm-intel-next by itself. It's harmless though and we could keep it
> > in the xe branch, as long as also removing from
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h
> >
> > Rodrigo / Matt, are you ok with this approach?
yeap, anything touching outside xe needs a separated patch anyway.
and I believe it can already be sent do intel-gfx, right?!
>
> Either way sounds fine to me.
>
>
> Matt
>
> >
> > Lucas De Marchi
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 05/11] drm/xe: Remove dependency on intel_gt_regs.h
2023-02-24 19:47 ` Vivi, Rodrigo
@ 2023-02-24 20:25 ` Lucas De Marchi
2023-02-24 21:22 ` Vivi, Rodrigo
0 siblings, 1 reply; 42+ messages in thread
From: Lucas De Marchi @ 2023-02-24 20:25 UTC (permalink / raw)
To: Vivi, Rodrigo
Cc: Roper, Matthew D, intel-xe@lists.freedesktop.org,
Lankhorst, Maarten, Auld, Matthew
On Fri, Feb 24, 2023 at 07:47:04PM +0000, Rodrigo Vivi wrote:
>On Fri, 2023-02-24 at 10:34 -0800, Matt Roper wrote:
>> On Fri, Feb 24, 2023 at 10:29:14AM -0800, Lucas De Marchi wrote:
>> > On Fri, Feb 24, 2023 at 10:06:14AM -0800, Matt Roper wrote:
>> > > On Thu, Feb 16, 2023 at 04:52:20PM -0800, Lucas De Marchi wrote:
>> > > > Create regs/xe_gt_regs.h file with all the registers and bit
>> > > > definitions used by the xe driver. Eventually the registers may
>> > > > be
>> > > > defined in a different way and since xe doesn't supported below
>> > > > gen12,
>> > > > the number of registers touched is much smaller, so create a
>> > > > new header.
>> > > >
>> > > > The definitions themselves are direct copy from the
>> > > > gt/intel_gt_regs.h file, just sorting the registers by address.
>> > > > Cleaning those up and adhering to a common coding style is left
>> > > > for
>> > > > later.
>> > > >
>> > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> > > > ---
>> > > > drivers/gpu/drm/i915/i915_reg_defs.h | 2 +
>> > > > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 287
>> > > > ++++++++++++++++++++++++++
>> > > > drivers/gpu/drm/xe/xe_execlist.c | 2 +-
>> > > > drivers/gpu/drm/xe/xe_force_wake.c | 3 +-
>> > > > drivers/gpu/drm/xe/xe_ggtt.c | 2 +-
>> > > > drivers/gpu/drm/xe/xe_gt.c | 3 +-
>> > > > drivers/gpu/drm/xe/xe_gt_clock.c | 2 +-
>> > > > drivers/gpu/drm/xe/xe_gt_mcr.c | 3 +-
>> > > > drivers/gpu/drm/xe/xe_guc.c | 2 +-
>> > > > drivers/gpu/drm/xe/xe_guc_ads.c | 4 +-
>> > > > drivers/gpu/drm/xe/xe_guc_pc.c | 2 +-
>> > > > drivers/gpu/drm/xe/xe_hw_engine.c | 2 +-
>> > > > drivers/gpu/drm/xe/xe_irq.c | 2 +-
>> > > > drivers/gpu/drm/xe/xe_lrc.c | 2 +-
>> > > > drivers/gpu/drm/xe/xe_mmio.c | 2 +-
>> > > > drivers/gpu/drm/xe/xe_mocs.c | 3 +-
>> > > > drivers/gpu/drm/xe/xe_reg_sr.c | 3 +-
>> > > > drivers/gpu/drm/xe/xe_reg_whitelist.c | 3 +-
>> > > > drivers/gpu/drm/xe/xe_ring_ops.c | 2 +-
>> > > > drivers/gpu/drm/xe/xe_tuning.c | 3 +-
>> > > > drivers/gpu/drm/xe/xe_wa.c | 2 +-
>> > > > 21 files changed, 308 insertions(+), 28 deletions(-)
>> > > > create mode 100644 drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> > > >
>> > > > diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
>> > > > b/drivers/gpu/drm/i915/i915_reg_defs.h
>> > > > index b5e06b6a9478..a6080c983a77 100644
>> > > > --- a/drivers/gpu/drm/i915/i915_reg_defs.h
>> > > > +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
>> > > > @@ -136,6 +136,8 @@ typedef struct {
>> > > > u32 reg;
>> > > > } i915_mcr_reg_t;
>> > > >
>> > > > +#define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg =
>> > > > (offset) })
>> > >
>> > > Should there be a corresponding removal of this definition from
>> > > drivers/gpu/drm/i915/gt/intel_gt_regs.h ?
>> > >
>> > > Aside from that,
>> > >
>> > > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>> >
>> >
>> > good catch. I was trying not to change the i915 headers, but this
>> > one went unoticed while fixing the build.
>> >
>> > I wonder if this should be a separate patch to merge in
>> > drm-intel-next by itself. It's harmless though and we could keep it
>> > in the xe branch, as long as also removing from
>> > drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> >
>> > Rodrigo / Matt, are you ok with this approach?
>
>yeap, anything touching outside xe needs a separated patch anyway.
>and I believe it can already be sent do intel-gfx, right?!
the problem is to depend on that patch. If we are rebasing the
drm-xe-next branch with a non-ff. Then we could simply have the patch
in both places and handle the conflict. If we are not rebasing, then
is it ok to have the patch in both places and deal with a possible
conflict in a merge (or backmerge if we are not yet in drm-next)?
Lucas De Marchi
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 05/11] drm/xe: Remove dependency on intel_gt_regs.h
2023-02-24 20:25 ` Lucas De Marchi
@ 2023-02-24 21:22 ` Vivi, Rodrigo
0 siblings, 0 replies; 42+ messages in thread
From: Vivi, Rodrigo @ 2023-02-24 21:22 UTC (permalink / raw)
To: De Marchi, Lucas
Cc: Roper, Matthew D, intel-xe@lists.freedesktop.org,
Lankhorst, Maarten, Auld, Matthew
On Fri, 2023-02-24 at 12:25 -0800, Lucas De Marchi wrote:
> On Fri, Feb 24, 2023 at 07:47:04PM +0000, Rodrigo Vivi wrote:
> > On Fri, 2023-02-24 at 10:34 -0800, Matt Roper wrote:
> > > On Fri, Feb 24, 2023 at 10:29:14AM -0800, Lucas De Marchi wrote:
> > > > On Fri, Feb 24, 2023 at 10:06:14AM -0800, Matt Roper wrote:
> > > > > On Thu, Feb 16, 2023 at 04:52:20PM -0800, Lucas De Marchi
> > > > > wrote:
> > > > > > Create regs/xe_gt_regs.h file with all the registers and
> > > > > > bit
> > > > > > definitions used by the xe driver. Eventually the registers
> > > > > > may
> > > > > > be
> > > > > > defined in a different way and since xe doesn't supported
> > > > > > below
> > > > > > gen12,
> > > > > > the number of registers touched is much smaller, so create
> > > > > > a
> > > > > > new header.
> > > > > >
> > > > > > The definitions themselves are direct copy from the
> > > > > > gt/intel_gt_regs.h file, just sorting the registers by
> > > > > > address.
> > > > > > Cleaning those up and adhering to a common coding style is
> > > > > > left
> > > > > > for
> > > > > > later.
> > > > > >
> > > > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/i915_reg_defs.h | 2 +
> > > > > > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 287
> > > > > > ++++++++++++++++++++++++++
> > > > > > drivers/gpu/drm/xe/xe_execlist.c | 2 +-
> > > > > > drivers/gpu/drm/xe/xe_force_wake.c | 3 +-
> > > > > > drivers/gpu/drm/xe/xe_ggtt.c | 2 +-
> > > > > > drivers/gpu/drm/xe/xe_gt.c | 3 +-
> > > > > > drivers/gpu/drm/xe/xe_gt_clock.c | 2 +-
> > > > > > drivers/gpu/drm/xe/xe_gt_mcr.c | 3 +-
> > > > > > drivers/gpu/drm/xe/xe_guc.c | 2 +-
> > > > > > drivers/gpu/drm/xe/xe_guc_ads.c | 4 +-
> > > > > > drivers/gpu/drm/xe/xe_guc_pc.c | 2 +-
> > > > > > drivers/gpu/drm/xe/xe_hw_engine.c | 2 +-
> > > > > > drivers/gpu/drm/xe/xe_irq.c | 2 +-
> > > > > > drivers/gpu/drm/xe/xe_lrc.c | 2 +-
> > > > > > drivers/gpu/drm/xe/xe_mmio.c | 2 +-
> > > > > > drivers/gpu/drm/xe/xe_mocs.c | 3 +-
> > > > > > drivers/gpu/drm/xe/xe_reg_sr.c | 3 +-
> > > > > > drivers/gpu/drm/xe/xe_reg_whitelist.c | 3 +-
> > > > > > drivers/gpu/drm/xe/xe_ring_ops.c | 2 +-
> > > > > > drivers/gpu/drm/xe/xe_tuning.c | 3 +-
> > > > > > drivers/gpu/drm/xe/xe_wa.c | 2 +-
> > > > > > 21 files changed, 308 insertions(+), 28 deletions(-)
> > > > > > create mode 100644 drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
> > > > > > b/drivers/gpu/drm/i915/i915_reg_defs.h
> > > > > > index b5e06b6a9478..a6080c983a77 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> > > > > > +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> > > > > > @@ -136,6 +136,8 @@ typedef struct {
> > > > > > u32 reg;
> > > > > > } i915_mcr_reg_t;
> > > > > >
> > > > > > +#define MCR_REG(offset) ((const i915_mcr_reg_t){
> > > > > > .reg =
> > > > > > (offset) })
> > > > >
> > > > > Should there be a corresponding removal of this definition
> > > > > from
> > > > > drivers/gpu/drm/i915/gt/intel_gt_regs.h ?
> > > > >
> > > > > Aside from that,
> > > > >
> > > > > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> > > >
> > > >
> > > > good catch. I was trying not to change the i915 headers, but
> > > > this
> > > > one went unoticed while fixing the build.
> > > >
> > > > I wonder if this should be a separate patch to merge in
> > > > drm-intel-next by itself. It's harmless though and we could
> > > > keep it
> > > > in the xe branch, as long as also removing from
> > > > drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > > >
> > > > Rodrigo / Matt, are you ok with this approach?
> >
> > yeap, anything touching outside xe needs a separated patch anyway.
> > and I believe it can already be sent do intel-gfx, right?!
>
> the problem is to depend on that patch. If we are rebasing the
> drm-xe-next branch with a non-ff. Then we could simply have the patch
> in both places and handle the conflict. If we are not rebasing, then
> is it ok to have the patch in both places and deal with a possible
> conflict in a merge (or backmerge if we are not yet in drm-next)?
we will have to rebase, so let's add the patch in both places and
deal with the conflicts.
>
> Lucas De Marchi
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-xe] [PATCH v2 08/11] drm/xe: Remove dependency on i915_reg.h
2023-02-17 22:22 ` Lucas De Marchi
@ 2023-02-27 14:19 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2023-02-27 14:19 UTC (permalink / raw)
To: Lucas De Marchi, Rodrigo Vivi; +Cc: intel-xe, Maarten Lankhorst, Matthew Auld
On Fri, 17 Feb 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Fri, Feb 17, 2023 at 03:27:12PM -0500, Rodrigo Vivi wrote:
>>On Thu, Feb 16, 2023 at 04:52:23PM -0800, Lucas De Marchi wrote:
>>> +#define GGC _MMIO(0x108040)
>>> +#define GMS_MASK REG_GENMASK(15, 8)
>>> +#define GGMS_MASK REG_GENMASK(7, 6)
>>
>>one of the things that I'm always confused is with these REG_{BIT,GENMASK,FIELD_PREP}.
>>Why can't we simply use the regular "non-REG_" versions like every other driver
>>(aside of i915 of course).
>
> it was some time ago, I didn't remember exactly and was guessing it was
> because GENMASK returns a long, while our registers are 32bits.
> Indeed, commit 09b434d4f6d2 ("drm/i915: introduce REG_BIT() and
> REG_GENMASK() to define register contents"):
>
> We define the above as wrappers to BIT() and GENMASK() respectively to
> force u32 type to go with our register size, and to add compile time
> checks on the bit numbers.
This, plus FIELD_PREP() doesn't always generate an integer constant
expression making it hard to use in some cases. Which I believe we see
over and over again in i915 gem/gt code that uses FIELD_PREP(). It's
even compiler dependent I think.
> we may revisit that and maybe generalize GENMASK32/BIT32 that guarantees a
> u32 type is returned.
Obviously not a bad idea, but additionally forcing integer constant
expression might not be something everyone wants in generic code.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 42+ messages in thread
end of thread, other threads:[~2023-02-27 14:19 UTC | newest]
Thread overview: 42+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-02-17 0:52 [Intel-xe] [PATCH v2 00/11] Start register cleanup Lucas De Marchi
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 01/11] drm/xe: Remove outdated build workaround Lucas De Marchi
2023-02-17 20:13 ` Rodrigo Vivi
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 02/11] drm/xe: Sort includes Lucas De Marchi
2023-02-17 11:20 ` Matthew Auld
2023-02-17 15:03 ` Lucas De Marchi
2023-02-17 11:39 ` Jani Nikula
2023-02-17 15:09 ` Lucas De Marchi
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 03/11] drm/xe/guc: Remove i915_regs.h include Lucas De Marchi
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 04/11] drm/xe: Remove dependency on intel_engine_regs.h Lucas De Marchi
2023-02-24 18:02 ` Matt Roper
2023-02-24 18:05 ` Lucas De Marchi
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 05/11] drm/xe: Remove dependency on intel_gt_regs.h Lucas De Marchi
2023-02-17 20:20 ` Rodrigo Vivi
2023-02-17 22:08 ` Lucas De Marchi
2023-02-24 18:06 ` Matt Roper
2023-02-24 18:29 ` Lucas De Marchi
2023-02-24 18:34 ` Matt Roper
2023-02-24 19:47 ` Vivi, Rodrigo
2023-02-24 20:25 ` Lucas De Marchi
2023-02-24 21:22 ` Vivi, Rodrigo
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 06/11] drm/xe: Remove dependency on intel_lrc_reg.h Lucas De Marchi
2023-02-24 18:20 ` Matt Roper
2023-02-24 18:54 ` Lucas De Marchi
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 07/11] drm/xe: Remove dependency on intel_gpu_commands.h Lucas De Marchi
2023-02-24 18:26 ` Matt Roper
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 08/11] drm/xe: Remove dependency on i915_reg.h Lucas De Marchi
2023-02-17 20:27 ` Rodrigo Vivi
2023-02-17 22:22 ` Lucas De Marchi
2023-02-27 14:19 ` Jani Nikula
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 09/11] drm/xe/guc_pc: Move gt register to the proper place Lucas De Marchi
2023-02-17 20:23 ` Rodrigo Vivi
2023-02-17 22:11 ` Lucas De Marchi
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 10/11] drm/xe: Remove dependency on intel_mchbar_regs.h Lucas De Marchi
2023-02-17 20:18 ` Rodrigo Vivi
2023-02-17 0:52 ` [Intel-xe] [PATCH v2 11/11] drm/xe: Use relative includes for i915_reg_defs.h Lucas De Marchi
2023-02-17 16:33 ` Lucas De Marchi
2023-02-17 20:28 ` Rodrigo Vivi
2023-02-17 22:30 ` Lucas De Marchi
2023-02-21 21:42 ` Rodrigo Vivi
2023-02-21 21:50 ` Lucas De Marchi
2023-02-17 6:19 ` [Intel-xe] [PATCH v2 00/11] Start register cleanup Lucas De Marchi
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