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From: Chester Lin <clin@suse.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: "Andreas Färber" <afaerber@suse.de>,
	"Rob Herring" <robh@kernel.org>,
	"David S. Miller" <davem@davemloft.net>,
	"Eric Dumazet" <edumazet@google.com>,
	"Jakub Kicinski" <kuba@kernel.org>,
	"Paolo Abeni" <pabeni@redhat.com>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Jan Petrous" <jan.petrous@nxp.com>,
	netdev@vger.kernel.org, s32@nxp.com, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	"Matthias Brugger" <mbrugger@suse.com>,
	"Chester Lin" <clin@suse.com>
Subject: Re: [PATCH 2/5] dt-bindings: net: add schema for NXP S32CC dwmac glue driver
Date: Fri, 4 Nov 2022 19:39:43 +0800	[thread overview]
Message-ID: <Y2T5/w8CvZH5ZlE2@linux-8mug> (raw)
In-Reply-To: <Y2Q7KtYkvpRz76tn@lunn.ch>

Hi Andrew and Andreas,

On Thu, Nov 03, 2022 at 11:05:30PM +0100, Andrew Lunn wrote:
> > > > +      - description: Main GMAC clock
> > > > +      - description: Peripheral registers clock
> > > > +      - description: Transmit SGMII clock
> > > > +      - description: Transmit RGMII clock
> > > > +      - description: Transmit RMII clock
> > > > +      - description: Transmit MII clock
> > > > +      - description: Receive SGMII clock
> > > > +      - description: Receive RGMII clock
> > > > +      - description: Receive RMII clock
> > > > +      - description: Receive MII clock
> > > > +      - description:
> > > > +          PTP reference clock. This clock is used for programming the
> > > > +          Timestamp Addend Register. If not passed then the system
> > > > +          clock will be used.
> 
> > Not clear to me has been whether the PHY mode can be switched at runtime
> > (like DPAA2 on Layerscape allows for SFPs) or whether this is fixed by board
> > design.
> 
> Does the hardware support 1000BaseX? Often the hardware implementing
> SGMII can also do 1000BaseX, since SGMII is an extended/hacked up
> 1000BaseX.
> 
> If you have an SFP connected to the SERDES, a fibre module will want
> 1000BaseX and a copper module will want SGMII. phylink will tell you
> what phy-mode you need to use depending on what module is in the
> socket. This however might be a mute point, since both of these are
> probably using the SGMII clocks.
> 
> Of the other MII modes listed, it is very unlikely a runtime swap will
> occur.
> 
> 	Andrew

Here I just focus on GMAC since there are other LAN interfaces that S32 family
uses [e.g. PFE]. According to the public GMACSUBSYS ref manual rev2[1] provided
on NXP website, theoretically GMAC can run SGMII in 1000Mbps and 2500Mbps so I
assume that supporting 1000BASE-X could be achievable. I'm not sure if any S32
board variant might have SFP ports but RJ-45 [1000BASE-T] should be the major
type used on S32G-EVB and S32G-RDB2.

@NXP, please feel free to correct me if anything wrong.

Thanks,
Chester

[1] https://www.nxp.com/webapp/Download?colCode=GMACSUBSYSRM -> Membership
subscription is required although it's free IIRC.

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WARNING: multiple messages have this Message-ID (diff)
From: Chester Lin <clin@suse.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: "Andreas Färber" <afaerber@suse.de>,
	"Rob Herring" <robh@kernel.org>,
	"David S. Miller" <davem@davemloft.net>,
	"Eric Dumazet" <edumazet@google.com>,
	"Jakub Kicinski" <kuba@kernel.org>,
	"Paolo Abeni" <pabeni@redhat.com>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Jan Petrous" <jan.petrous@nxp.com>,
	netdev@vger.kernel.org, s32@nxp.com, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	"Matthias Brugger" <mbrugger@suse.com>,
	"Chester Lin" <clin@suse.com>
Subject: Re: [PATCH 2/5] dt-bindings: net: add schema for NXP S32CC dwmac glue driver
Date: Fri, 4 Nov 2022 19:39:43 +0800	[thread overview]
Message-ID: <Y2T5/w8CvZH5ZlE2@linux-8mug> (raw)
In-Reply-To: <Y2Q7KtYkvpRz76tn@lunn.ch>

Hi Andrew and Andreas,

On Thu, Nov 03, 2022 at 11:05:30PM +0100, Andrew Lunn wrote:
> > > > +      - description: Main GMAC clock
> > > > +      - description: Peripheral registers clock
> > > > +      - description: Transmit SGMII clock
> > > > +      - description: Transmit RGMII clock
> > > > +      - description: Transmit RMII clock
> > > > +      - description: Transmit MII clock
> > > > +      - description: Receive SGMII clock
> > > > +      - description: Receive RGMII clock
> > > > +      - description: Receive RMII clock
> > > > +      - description: Receive MII clock
> > > > +      - description:
> > > > +          PTP reference clock. This clock is used for programming the
> > > > +          Timestamp Addend Register. If not passed then the system
> > > > +          clock will be used.
> 
> > Not clear to me has been whether the PHY mode can be switched at runtime
> > (like DPAA2 on Layerscape allows for SFPs) or whether this is fixed by board
> > design.
> 
> Does the hardware support 1000BaseX? Often the hardware implementing
> SGMII can also do 1000BaseX, since SGMII is an extended/hacked up
> 1000BaseX.
> 
> If you have an SFP connected to the SERDES, a fibre module will want
> 1000BaseX and a copper module will want SGMII. phylink will tell you
> what phy-mode you need to use depending on what module is in the
> socket. This however might be a mute point, since both of these are
> probably using the SGMII clocks.
> 
> Of the other MII modes listed, it is very unlikely a runtime swap will
> occur.
> 
> 	Andrew

Here I just focus on GMAC since there are other LAN interfaces that S32 family
uses [e.g. PFE]. According to the public GMACSUBSYS ref manual rev2[1] provided
on NXP website, theoretically GMAC can run SGMII in 1000Mbps and 2500Mbps so I
assume that supporting 1000BASE-X could be achievable. I'm not sure if any S32
board variant might have SFP ports but RJ-45 [1000BASE-T] should be the major
type used on S32G-EVB and S32G-RDB2.

@NXP, please feel free to correct me if anything wrong.

Thanks,
Chester

[1] https://www.nxp.com/webapp/Download?colCode=GMACSUBSYSRM -> Membership
subscription is required although it's free IIRC.

  reply	other threads:[~2022-11-04 11:41 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-31 10:10 [PATCH 0/5] Add GMAC support for S32 SoC family Chester Lin
2022-10-31 10:10 ` Chester Lin
2022-10-31 10:10 ` [PATCH 1/5] dt-bindings: net: snps, dwmac: add NXP S32CC support Chester Lin
2022-10-31 10:10   ` Chester Lin
2022-10-31 10:10 ` [PATCH 2/5] dt-bindings: net: add schema for NXP S32CC dwmac glue driver Chester Lin
2022-10-31 10:10   ` Chester Lin
2022-11-02 15:55   ` Rob Herring
2022-11-02 15:55     ` Rob Herring
2022-11-02 17:13     ` Andreas Färber
2022-11-02 17:13       ` Andreas Färber
2022-11-02 21:44       ` Rob Herring
2022-11-02 21:44         ` Rob Herring
2022-11-04 10:11         ` Chester Lin
2022-11-04 10:11           ` Chester Lin
2022-11-03 22:05       ` Andrew Lunn
2022-11-03 22:05         ` Andrew Lunn
2022-11-04 11:39         ` Chester Lin [this message]
2022-11-04 11:39           ` Chester Lin
2022-11-04 13:30           ` Andrew Lunn
2022-11-04 13:30             ` Andrew Lunn
2022-11-09  8:09             ` Chester Lin
2022-11-09  8:09               ` Chester Lin
2022-11-09 22:55           ` [EXT] " Jan Petrous
2022-11-09 22:55             ` Jan Petrous
2022-11-09 23:00             ` Andrew Lunn
2022-11-09 23:00               ` Andrew Lunn
2022-11-10  8:51               ` Jan Petrous
2022-11-10  8:51                 ` Jan Petrous
2022-11-10 13:04                 ` Andrew Lunn
2022-11-10 13:04                   ` Andrew Lunn
2022-11-09 22:55       ` Jan Petrous
2022-11-09 22:55         ` Jan Petrous
2022-10-31 10:10 ` [PATCH 3/5] net: stmmac: Add CSR clock 500Mhz/800Mhz support Chester Lin
2022-10-31 10:10   ` Chester Lin
2022-10-31 10:10 ` [PATCH 4/5] net: stmmac: Add AXI4 ACE control support Chester Lin
2022-10-31 10:10   ` Chester Lin
2022-10-31 10:10 ` [PATCH 5/5] net: stmmac: Add NXP S32 SoC family support Chester Lin
2022-10-31 10:10   ` Chester Lin
2022-10-31 13:27   ` Andrew Lunn
2022-10-31 13:27     ` Andrew Lunn

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