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From: Chester Lin <clin@suse.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: "Andreas Färber" <afaerber@suse.de>,
	"Rob Herring" <robh@kernel.org>,
	"David S. Miller" <davem@davemloft.net>,
	"Eric Dumazet" <edumazet@google.com>,
	"Jakub Kicinski" <kuba@kernel.org>,
	"Paolo Abeni" <pabeni@redhat.com>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Jan Petrous" <jan.petrous@nxp.com>,
	netdev@vger.kernel.org, s32@nxp.com, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	"Matthias Brugger" <mbrugger@suse.com>,
	"Chester Lin" <clin@suse.com>
Subject: Re: [PATCH 2/5] dt-bindings: net: add schema for NXP S32CC dwmac glue driver
Date: Wed, 9 Nov 2022 16:09:01 +0800	[thread overview]
Message-ID: <Y2tgHYT+rV1+fxTm@linux-8mug> (raw)
In-Reply-To: <Y2UT4yIqk0pV6FHA@lunn.ch>

Hi Andrew,

On Fri, Nov 04, 2022 at 02:30:11PM +0100, Andrew Lunn wrote:
> > Here I just focus on GMAC since there are other LAN interfaces that S32 family
> > uses [e.g. PFE]. According to the public GMACSUBSYS ref manual rev2[1] provided
> > on NXP website, theoretically GMAC can run SGMII in 1000Mbps and 2500Mbps so I
> > assume that supporting 1000BASE-X could be achievable. I'm not sure if any S32
> > board variant might have SFP ports but RJ-45 [1000BASE-T] should be the major
> > type used on S32G-EVB and S32G-RDB2.
> 
> SGMII at 2500Mbps does not exist. Lots of people get this wrong. It
> will be 2500Base-X.
> 

Thanks for your correction.

> Does the clock need to change in order to support 2500Base-X? If i

Since I'm not a hardware designer from NXP and I can't find any board that
S32G2 CPUs could integrate SFP, so I am not able to tell how the clock could
be configured while supporting 2500Base-X.

> understand you correctly, Linux does not control the clocks, and so
> cannot change the clocks? So that probably means you cannot actually

To be more precise, the SCMI clock protocol in ATF [ARM Trusted Firmware]
doesn't design any interface to get/set parents of a clock so that re-parenting
clocks via the SCMI clk driver [clk-scmi.c] in Linux Kernel is impossible
for this case. That means, if any board design allows run-time swap on different
phys, the dedicated clks which represent each phy-mode are required in order
to trigger clock re-parenting in ATF since different phy connections would
need different clock sources.

> support 2500Base-X? Once you have Linux actually controlling the
> hardware, you can then make use of an SFP or a copper PHY which
> supports 2.5G. The PHY will swap its host side between SGMII and
> 2500Base-X depending on what the line side negotiates, 1000Base-T or
> 2500Base-T. The MAC driver then needs to change its configuration to
> suite.
> 
> 	Andrew

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Chester Lin <clin@suse.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: "Andreas Färber" <afaerber@suse.de>,
	"Rob Herring" <robh@kernel.org>,
	"David S. Miller" <davem@davemloft.net>,
	"Eric Dumazet" <edumazet@google.com>,
	"Jakub Kicinski" <kuba@kernel.org>,
	"Paolo Abeni" <pabeni@redhat.com>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Jan Petrous" <jan.petrous@nxp.com>,
	netdev@vger.kernel.org, s32@nxp.com, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	"Matthias Brugger" <mbrugger@suse.com>,
	"Chester Lin" <clin@suse.com>
Subject: Re: [PATCH 2/5] dt-bindings: net: add schema for NXP S32CC dwmac glue driver
Date: Wed, 9 Nov 2022 16:09:01 +0800	[thread overview]
Message-ID: <Y2tgHYT+rV1+fxTm@linux-8mug> (raw)
In-Reply-To: <Y2UT4yIqk0pV6FHA@lunn.ch>

Hi Andrew,

On Fri, Nov 04, 2022 at 02:30:11PM +0100, Andrew Lunn wrote:
> > Here I just focus on GMAC since there are other LAN interfaces that S32 family
> > uses [e.g. PFE]. According to the public GMACSUBSYS ref manual rev2[1] provided
> > on NXP website, theoretically GMAC can run SGMII in 1000Mbps and 2500Mbps so I
> > assume that supporting 1000BASE-X could be achievable. I'm not sure if any S32
> > board variant might have SFP ports but RJ-45 [1000BASE-T] should be the major
> > type used on S32G-EVB and S32G-RDB2.
> 
> SGMII at 2500Mbps does not exist. Lots of people get this wrong. It
> will be 2500Base-X.
> 

Thanks for your correction.

> Does the clock need to change in order to support 2500Base-X? If i

Since I'm not a hardware designer from NXP and I can't find any board that
S32G2 CPUs could integrate SFP, so I am not able to tell how the clock could
be configured while supporting 2500Base-X.

> understand you correctly, Linux does not control the clocks, and so
> cannot change the clocks? So that probably means you cannot actually

To be more precise, the SCMI clock protocol in ATF [ARM Trusted Firmware]
doesn't design any interface to get/set parents of a clock so that re-parenting
clocks via the SCMI clk driver [clk-scmi.c] in Linux Kernel is impossible
for this case. That means, if any board design allows run-time swap on different
phys, the dedicated clks which represent each phy-mode are required in order
to trigger clock re-parenting in ATF since different phy connections would
need different clock sources.

> support 2500Base-X? Once you have Linux actually controlling the
> hardware, you can then make use of an SFP or a copper PHY which
> supports 2.5G. The PHY will swap its host side between SGMII and
> 2500Base-X depending on what the line side negotiates, 1000Base-T or
> 2500Base-T. The MAC driver then needs to change its configuration to
> suite.
> 
> 	Andrew

  reply	other threads:[~2022-11-09  8:11 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-31 10:10 [PATCH 0/5] Add GMAC support for S32 SoC family Chester Lin
2022-10-31 10:10 ` Chester Lin
2022-10-31 10:10 ` [PATCH 1/5] dt-bindings: net: snps, dwmac: add NXP S32CC support Chester Lin
2022-10-31 10:10   ` Chester Lin
2022-10-31 10:10 ` [PATCH 2/5] dt-bindings: net: add schema for NXP S32CC dwmac glue driver Chester Lin
2022-10-31 10:10   ` Chester Lin
2022-11-02 15:55   ` Rob Herring
2022-11-02 15:55     ` Rob Herring
2022-11-02 17:13     ` Andreas Färber
2022-11-02 17:13       ` Andreas Färber
2022-11-02 21:44       ` Rob Herring
2022-11-02 21:44         ` Rob Herring
2022-11-04 10:11         ` Chester Lin
2022-11-04 10:11           ` Chester Lin
2022-11-03 22:05       ` Andrew Lunn
2022-11-03 22:05         ` Andrew Lunn
2022-11-04 11:39         ` Chester Lin
2022-11-04 11:39           ` Chester Lin
2022-11-04 13:30           ` Andrew Lunn
2022-11-04 13:30             ` Andrew Lunn
2022-11-09  8:09             ` Chester Lin [this message]
2022-11-09  8:09               ` Chester Lin
2022-11-09 22:55           ` [EXT] " Jan Petrous
2022-11-09 22:55             ` Jan Petrous
2022-11-09 23:00             ` Andrew Lunn
2022-11-09 23:00               ` Andrew Lunn
2022-11-10  8:51               ` Jan Petrous
2022-11-10  8:51                 ` Jan Petrous
2022-11-10 13:04                 ` Andrew Lunn
2022-11-10 13:04                   ` Andrew Lunn
2022-11-09 22:55       ` Jan Petrous
2022-11-09 22:55         ` Jan Petrous
2022-10-31 10:10 ` [PATCH 3/5] net: stmmac: Add CSR clock 500Mhz/800Mhz support Chester Lin
2022-10-31 10:10   ` Chester Lin
2022-10-31 10:10 ` [PATCH 4/5] net: stmmac: Add AXI4 ACE control support Chester Lin
2022-10-31 10:10   ` Chester Lin
2022-10-31 10:10 ` [PATCH 5/5] net: stmmac: Add NXP S32 SoC family support Chester Lin
2022-10-31 10:10   ` Chester Lin
2022-10-31 13:27   ` Andrew Lunn
2022-10-31 13:27     ` Andrew Lunn

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