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From: Catalin Marinas <catalin.marinas@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: kernel-team@android.com, Will Deacon <will@kernel.org>,
	marcan@marcan.st, kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] KVM: arm64: vgic-v3: List M1 Pro/Max as requiring the SEIS workaround
Date: Sun, 15 May 2022 10:46:03 +0100	[thread overview]
Message-ID: <YoDL2xsqFxOPo46p@arm.com> (raw)
In-Reply-To: <20220514102524.3188730-1-maz@kernel.org>

On Sat, May 14, 2022 at 11:25:24AM +0100, Marc Zyngier wrote:
> Unsusprisingly, Apple M1 Pro/Max have the exact same defect as the
> original M1 and generate random SErrors in the host when a guest
> tickles the GICv3 CPU interface the wrong way.
> 
> Add the part numbers for both the CPU types found in these two
> new implementations, and add them to the hall of shame. This also
> applies to the Ultra version, as it is composed of 2 Max SoCs.
> 
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
>  arch/arm64/include/asm/cputype.h | 8 ++++++++
>  arch/arm64/kvm/vgic/vgic-v3.c    | 4 ++++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> index ff8f4511df71..60647bdc0b09 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -118,6 +118,10 @@
>  
>  #define APPLE_CPU_PART_M1_ICESTORM	0x022
>  #define APPLE_CPU_PART_M1_FIRESTORM	0x023
> +#define APPLE_CPU_PART_M1_ICESTORM_PRO	0x024
> +#define APPLE_CPU_PART_M1_FIRESTORM_PRO	0x025
> +#define APPLE_CPU_PART_M1_ICESTORM_MAX	0x028
> +#define APPLE_CPU_PART_M1_FIRESTORM_MAX	0x029
>  
>  #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
>  #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
> @@ -164,6 +168,10 @@
>  #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
>  #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
>  #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
> +#define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)
> +#define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO)
> +#define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX)
> +#define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX)

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	Will Deacon <will@kernel.org>,
	marcan@marcan.st, kernel-team@android.com
Subject: Re: [PATCH] KVM: arm64: vgic-v3: List M1 Pro/Max as requiring the SEIS workaround
Date: Sun, 15 May 2022 10:46:03 +0100	[thread overview]
Message-ID: <YoDL2xsqFxOPo46p@arm.com> (raw)
In-Reply-To: <20220514102524.3188730-1-maz@kernel.org>

On Sat, May 14, 2022 at 11:25:24AM +0100, Marc Zyngier wrote:
> Unsusprisingly, Apple M1 Pro/Max have the exact same defect as the
> original M1 and generate random SErrors in the host when a guest
> tickles the GICv3 CPU interface the wrong way.
> 
> Add the part numbers for both the CPU types found in these two
> new implementations, and add them to the hall of shame. This also
> applies to the Ultra version, as it is composed of 2 Max SoCs.
> 
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
>  arch/arm64/include/asm/cputype.h | 8 ++++++++
>  arch/arm64/kvm/vgic/vgic-v3.c    | 4 ++++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> index ff8f4511df71..60647bdc0b09 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -118,6 +118,10 @@
>  
>  #define APPLE_CPU_PART_M1_ICESTORM	0x022
>  #define APPLE_CPU_PART_M1_FIRESTORM	0x023
> +#define APPLE_CPU_PART_M1_ICESTORM_PRO	0x024
> +#define APPLE_CPU_PART_M1_FIRESTORM_PRO	0x025
> +#define APPLE_CPU_PART_M1_ICESTORM_MAX	0x028
> +#define APPLE_CPU_PART_M1_FIRESTORM_MAX	0x029
>  
>  #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
>  #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
> @@ -164,6 +168,10 @@
>  #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
>  #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
>  #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
> +#define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)
> +#define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO)
> +#define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX)
> +#define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX)

Acked-by: Catalin Marinas <catalin.marinas@arm.com>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-05-15  9:46 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-14 10:25 [PATCH] KVM: arm64: vgic-v3: List M1 Pro/Max as requiring the SEIS workaround Marc Zyngier
2022-05-14 10:25 ` Marc Zyngier
2022-05-15  9:46 ` Catalin Marinas [this message]
2022-05-15  9:46   ` Catalin Marinas
2022-05-15 10:57 ` Marc Zyngier
2022-05-15 10:57   ` Marc Zyngier

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