* [PATCH] KVM: arm64: vgic-v3: List M1 Pro/Max as requiring the SEIS workaround
@ 2022-05-14 10:25 ` Marc Zyngier
0 siblings, 0 replies; 6+ messages in thread
From: Marc Zyngier @ 2022-05-14 10:25 UTC (permalink / raw)
To: kvmarm, linux-arm-kernel
Cc: kernel-team, Will Deacon, Catalin Marinas, marcan
Unsusprisingly, Apple M1 Pro/Max have the exact same defect as the
original M1 and generate random SErrors in the host when a guest
tickles the GICv3 CPU interface the wrong way.
Add the part numbers for both the CPU types found in these two
new implementations, and add them to the hall of shame. This also
applies to the Ultra version, as it is composed of 2 Max SoCs.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/include/asm/cputype.h | 8 ++++++++
arch/arm64/kvm/vgic/vgic-v3.c | 4 ++++
2 files changed, 12 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index ff8f4511df71..60647bdc0b09 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -118,6 +118,10 @@
#define APPLE_CPU_PART_M1_ICESTORM 0x022
#define APPLE_CPU_PART_M1_FIRESTORM 0x023
+#define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024
+#define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025
+#define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028
+#define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029
#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
@@ -164,6 +168,10 @@
#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
+#define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)
+#define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO)
+#define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX)
+#define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX)
/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c
index b549af8b1dc2..826ff6f2a4e7 100644
--- a/arch/arm64/kvm/vgic/vgic-v3.c
+++ b/arch/arm64/kvm/vgic/vgic-v3.c
@@ -612,6 +612,10 @@ early_param("kvm-arm.vgic_v4_enable", early_gicv4_enable);
static const struct midr_range broken_seis[] = {
MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM),
MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM),
+ MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO),
+ MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO),
+ MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX),
+ MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX),
{},
};
--
2.34.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] KVM: arm64: vgic-v3: List M1 Pro/Max as requiring the SEIS workaround
@ 2022-05-14 10:25 ` Marc Zyngier
0 siblings, 0 replies; 6+ messages in thread
From: Marc Zyngier @ 2022-05-14 10:25 UTC (permalink / raw)
To: kvmarm, linux-arm-kernel
Cc: James Morse, Suzuki K Poulose, Alexandru Elisei, Will Deacon,
Catalin Marinas, marcan, kernel-team
Unsusprisingly, Apple M1 Pro/Max have the exact same defect as the
original M1 and generate random SErrors in the host when a guest
tickles the GICv3 CPU interface the wrong way.
Add the part numbers for both the CPU types found in these two
new implementations, and add them to the hall of shame. This also
applies to the Ultra version, as it is composed of 2 Max SoCs.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/include/asm/cputype.h | 8 ++++++++
arch/arm64/kvm/vgic/vgic-v3.c | 4 ++++
2 files changed, 12 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index ff8f4511df71..60647bdc0b09 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -118,6 +118,10 @@
#define APPLE_CPU_PART_M1_ICESTORM 0x022
#define APPLE_CPU_PART_M1_FIRESTORM 0x023
+#define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024
+#define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025
+#define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028
+#define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029
#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
@@ -164,6 +168,10 @@
#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
+#define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)
+#define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO)
+#define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX)
+#define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX)
/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c
index b549af8b1dc2..826ff6f2a4e7 100644
--- a/arch/arm64/kvm/vgic/vgic-v3.c
+++ b/arch/arm64/kvm/vgic/vgic-v3.c
@@ -612,6 +612,10 @@ early_param("kvm-arm.vgic_v4_enable", early_gicv4_enable);
static const struct midr_range broken_seis[] = {
MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM),
MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM),
+ MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO),
+ MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO),
+ MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX),
+ MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX),
{},
};
--
2.34.1
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] KVM: arm64: vgic-v3: List M1 Pro/Max as requiring the SEIS workaround
2022-05-14 10:25 ` Marc Zyngier
@ 2022-05-15 9:46 ` Catalin Marinas
-1 siblings, 0 replies; 6+ messages in thread
From: Catalin Marinas @ 2022-05-15 9:46 UTC (permalink / raw)
To: Marc Zyngier; +Cc: kernel-team, Will Deacon, marcan, kvmarm, linux-arm-kernel
On Sat, May 14, 2022 at 11:25:24AM +0100, Marc Zyngier wrote:
> Unsusprisingly, Apple M1 Pro/Max have the exact same defect as the
> original M1 and generate random SErrors in the host when a guest
> tickles the GICv3 CPU interface the wrong way.
>
> Add the part numbers for both the CPU types found in these two
> new implementations, and add them to the hall of shame. This also
> applies to the Ultra version, as it is composed of 2 Max SoCs.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> arch/arm64/include/asm/cputype.h | 8 ++++++++
> arch/arm64/kvm/vgic/vgic-v3.c | 4 ++++
> 2 files changed, 12 insertions(+)
>
> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> index ff8f4511df71..60647bdc0b09 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -118,6 +118,10 @@
>
> #define APPLE_CPU_PART_M1_ICESTORM 0x022
> #define APPLE_CPU_PART_M1_FIRESTORM 0x023
> +#define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024
> +#define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025
> +#define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028
> +#define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029
>
> #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
> #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
> @@ -164,6 +168,10 @@
> #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
> #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
> #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
> +#define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)
> +#define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO)
> +#define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX)
> +#define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX)
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] KVM: arm64: vgic-v3: List M1 Pro/Max as requiring the SEIS workaround
@ 2022-05-15 9:46 ` Catalin Marinas
0 siblings, 0 replies; 6+ messages in thread
From: Catalin Marinas @ 2022-05-15 9:46 UTC (permalink / raw)
To: Marc Zyngier
Cc: kvmarm, linux-arm-kernel, James Morse, Suzuki K Poulose,
Alexandru Elisei, Will Deacon, marcan, kernel-team
On Sat, May 14, 2022 at 11:25:24AM +0100, Marc Zyngier wrote:
> Unsusprisingly, Apple M1 Pro/Max have the exact same defect as the
> original M1 and generate random SErrors in the host when a guest
> tickles the GICv3 CPU interface the wrong way.
>
> Add the part numbers for both the CPU types found in these two
> new implementations, and add them to the hall of shame. This also
> applies to the Ultra version, as it is composed of 2 Max SoCs.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> arch/arm64/include/asm/cputype.h | 8 ++++++++
> arch/arm64/kvm/vgic/vgic-v3.c | 4 ++++
> 2 files changed, 12 insertions(+)
>
> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> index ff8f4511df71..60647bdc0b09 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -118,6 +118,10 @@
>
> #define APPLE_CPU_PART_M1_ICESTORM 0x022
> #define APPLE_CPU_PART_M1_FIRESTORM 0x023
> +#define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024
> +#define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025
> +#define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028
> +#define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029
>
> #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
> #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
> @@ -164,6 +168,10 @@
> #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
> #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
> #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
> +#define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)
> +#define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO)
> +#define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX)
> +#define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX)
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] KVM: arm64: vgic-v3: List M1 Pro/Max as requiring the SEIS workaround
2022-05-14 10:25 ` Marc Zyngier
@ 2022-05-15 10:57 ` Marc Zyngier
-1 siblings, 0 replies; 6+ messages in thread
From: Marc Zyngier @ 2022-05-15 10:57 UTC (permalink / raw)
To: Marc Zyngier, linux-arm-kernel, kvmarm
Cc: Catalin Marinas, marcan, kernel-team, Will Deacon
On Sat, 14 May 2022 11:25:24 +0100, Marc Zyngier wrote:
> Unsusprisingly, Apple M1 Pro/Max have the exact same defect as the
> original M1 and generate random SErrors in the host when a guest
> tickles the GICv3 CPU interface the wrong way.
>
> Add the part numbers for both the CPU types found in these two
> new implementations, and add them to the hall of shame. This also
> applies to the Ultra version, as it is composed of 2 Max SoCs.
Applied to next, thanks!
[1/1] KVM: arm64: vgic-v3: List M1 Pro/Max as requiring the SEIS workaround
commit: cae889302ebf5a9b22ca3580996118b8d20b3ae6
Cheers,
M.
--
Without deviation from the norm, progress is not possible.
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] KVM: arm64: vgic-v3: List M1 Pro/Max as requiring the SEIS workaround
@ 2022-05-15 10:57 ` Marc Zyngier
0 siblings, 0 replies; 6+ messages in thread
From: Marc Zyngier @ 2022-05-15 10:57 UTC (permalink / raw)
To: Marc Zyngier, linux-arm-kernel, kvmarm
Cc: kernel-team, marcan, Catalin Marinas, Will Deacon
On Sat, 14 May 2022 11:25:24 +0100, Marc Zyngier wrote:
> Unsusprisingly, Apple M1 Pro/Max have the exact same defect as the
> original M1 and generate random SErrors in the host when a guest
> tickles the GICv3 CPU interface the wrong way.
>
> Add the part numbers for both the CPU types found in these two
> new implementations, and add them to the hall of shame. This also
> applies to the Ultra version, as it is composed of 2 Max SoCs.
Applied to next, thanks!
[1/1] KVM: arm64: vgic-v3: List M1 Pro/Max as requiring the SEIS workaround
commit: cae889302ebf5a9b22ca3580996118b8d20b3ae6
Cheers,
M.
--
Without deviation from the norm, progress is not possible.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-05-15 10:58 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2022-05-14 10:25 [PATCH] KVM: arm64: vgic-v3: List M1 Pro/Max as requiring the SEIS workaround Marc Zyngier
2022-05-14 10:25 ` Marc Zyngier
2022-05-15 9:46 ` Catalin Marinas
2022-05-15 9:46 ` Catalin Marinas
2022-05-15 10:57 ` Marc Zyngier
2022-05-15 10:57 ` Marc Zyngier
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