From: Deepak Gupta <debug@rivosinc.com>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Shuah Khan <shuah@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org,
Samuel Holland <samuel.holland@sifive.com>
Subject: Re: [PATCH v2 01/15] riscv: add Firmware Feature (FWFT) SBI extensions definitions
Date: Mon, 10 Feb 2025 20:06:12 -0800 [thread overview]
Message-ID: <Z6rMtBud/hsKYYIw@debug.ba.rivosinc.com> (raw)
In-Reply-To: <20250210213549.1867704-2-cleger@rivosinc.com>
On Mon, Feb 10, 2025 at 10:35:34PM +0100, Clément Léger wrote:
>The Firmware Features extension (FWFT) was added as part of the SBI 3.0
>specification. Add SBI definitions to use this extension.
>
>Signed-off-by: Clément Léger <cleger@rivosinc.com>
>Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
>Tested-by: Samuel Holland <samuel.holland@sifive.com>
>---
> arch/riscv/include/asm/sbi.h | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
>diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
>index 3d250824178b..d373b5c08039 100644
>--- a/arch/riscv/include/asm/sbi.h
>+++ b/arch/riscv/include/asm/sbi.h
>@@ -35,6 +35,7 @@ enum sbi_ext_id {
> SBI_EXT_DBCN = 0x4442434E,
> SBI_EXT_STA = 0x535441,
> SBI_EXT_NACL = 0x4E41434C,
>+ SBI_EXT_FWFT = 0x46574654,
>
> /* Experimentals extensions must lie within this range */
> SBI_EXT_EXPERIMENTAL_START = 0x08000000,
>@@ -402,6 +403,33 @@ enum sbi_ext_nacl_feature {
> #define SBI_NACL_SHMEM_SRET_X(__i) ((__riscv_xlen / 8) * (__i))
> #define SBI_NACL_SHMEM_SRET_X_LAST 31
>
>+/* SBI function IDs for FW feature extension */
>+#define SBI_EXT_FWFT_SET 0x0
>+#define SBI_EXT_FWFT_GET 0x1
>+
>+enum sbi_fwft_feature_t {
>+ SBI_FWFT_MISALIGNED_EXC_DELEG = 0x0,
>+ SBI_FWFT_LANDING_PAD = 0x1,
>+ SBI_FWFT_SHADOW_STACK = 0x2,
>+ SBI_FWFT_DOUBLE_TRAP = 0x3,
>+ SBI_FWFT_PTE_AD_HW_UPDATING = 0x4,
>+ SBI_FWFT_POINTER_MASKING_PMLEN = 0x5,
>+ SBI_FWFT_LOCAL_RESERVED_START = 0x6,
>+ SBI_FWFT_LOCAL_RESERVED_END = 0x3fffffff,
>+ SBI_FWFT_LOCAL_PLATFORM_START = 0x40000000,
>+ SBI_FWFT_LOCAL_PLATFORM_END = 0x7fffffff,
>+
>+ SBI_FWFT_GLOBAL_RESERVED_START = 0x80000000,
>+ SBI_FWFT_GLOBAL_RESERVED_END = 0xbfffffff,
>+ SBI_FWFT_GLOBAL_PLATFORM_START = 0xc0000000,
>+ SBI_FWFT_GLOBAL_PLATFORM_END = 0xffffffff,
>+};
>+
>+#define SBI_FWFT_PLATFORM_FEATURE_BIT (1 << 30)
>+#define SBI_FWFT_GLOBAL_FEATURE_BIT (1 << 31)
>+
>+#define SBI_FWFT_SET_FLAG_LOCK (1 << 0)
>+
> /* SBI spec version fields */
> #define SBI_SPEC_VERSION_DEFAULT 0x1
> #define SBI_SPEC_VERSION_MAJOR_SHIFT 24
>@@ -419,6 +447,11 @@ enum sbi_ext_nacl_feature {
> #define SBI_ERR_ALREADY_STARTED -7
> #define SBI_ERR_ALREADY_STOPPED -8
> #define SBI_ERR_NO_SHMEM -9
>+#define SBI_ERR_INVALID_STATE -10
>+#define SBI_ERR_BAD_RANGE -11
>+#define SBI_ERR_TIMEOUT -12
nit: Space mis-aligned(^) ^
otherwise
Reviewed-by: Deepak Gupta <debug@rivosinc.com>
>+#define SBI_ERR_IO -13
>+#define SBI_ERR_DENIED_LOCKED -14
>
> extern unsigned long sbi_spec_version;
> struct sbiret {
>--
>2.47.2
>
>
--
kvm-riscv mailing list
kvm-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kvm-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Deepak Gupta <debug@rivosinc.com>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Shuah Khan <shuah@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org,
Samuel Holland <samuel.holland@sifive.com>
Subject: Re: [PATCH v2 01/15] riscv: add Firmware Feature (FWFT) SBI extensions definitions
Date: Mon, 10 Feb 2025 20:06:12 -0800 [thread overview]
Message-ID: <Z6rMtBud/hsKYYIw@debug.ba.rivosinc.com> (raw)
In-Reply-To: <20250210213549.1867704-2-cleger@rivosinc.com>
On Mon, Feb 10, 2025 at 10:35:34PM +0100, Clément Léger wrote:
>The Firmware Features extension (FWFT) was added as part of the SBI 3.0
>specification. Add SBI definitions to use this extension.
>
>Signed-off-by: Clément Léger <cleger@rivosinc.com>
>Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
>Tested-by: Samuel Holland <samuel.holland@sifive.com>
>---
> arch/riscv/include/asm/sbi.h | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
>diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
>index 3d250824178b..d373b5c08039 100644
>--- a/arch/riscv/include/asm/sbi.h
>+++ b/arch/riscv/include/asm/sbi.h
>@@ -35,6 +35,7 @@ enum sbi_ext_id {
> SBI_EXT_DBCN = 0x4442434E,
> SBI_EXT_STA = 0x535441,
> SBI_EXT_NACL = 0x4E41434C,
>+ SBI_EXT_FWFT = 0x46574654,
>
> /* Experimentals extensions must lie within this range */
> SBI_EXT_EXPERIMENTAL_START = 0x08000000,
>@@ -402,6 +403,33 @@ enum sbi_ext_nacl_feature {
> #define SBI_NACL_SHMEM_SRET_X(__i) ((__riscv_xlen / 8) * (__i))
> #define SBI_NACL_SHMEM_SRET_X_LAST 31
>
>+/* SBI function IDs for FW feature extension */
>+#define SBI_EXT_FWFT_SET 0x0
>+#define SBI_EXT_FWFT_GET 0x1
>+
>+enum sbi_fwft_feature_t {
>+ SBI_FWFT_MISALIGNED_EXC_DELEG = 0x0,
>+ SBI_FWFT_LANDING_PAD = 0x1,
>+ SBI_FWFT_SHADOW_STACK = 0x2,
>+ SBI_FWFT_DOUBLE_TRAP = 0x3,
>+ SBI_FWFT_PTE_AD_HW_UPDATING = 0x4,
>+ SBI_FWFT_POINTER_MASKING_PMLEN = 0x5,
>+ SBI_FWFT_LOCAL_RESERVED_START = 0x6,
>+ SBI_FWFT_LOCAL_RESERVED_END = 0x3fffffff,
>+ SBI_FWFT_LOCAL_PLATFORM_START = 0x40000000,
>+ SBI_FWFT_LOCAL_PLATFORM_END = 0x7fffffff,
>+
>+ SBI_FWFT_GLOBAL_RESERVED_START = 0x80000000,
>+ SBI_FWFT_GLOBAL_RESERVED_END = 0xbfffffff,
>+ SBI_FWFT_GLOBAL_PLATFORM_START = 0xc0000000,
>+ SBI_FWFT_GLOBAL_PLATFORM_END = 0xffffffff,
>+};
>+
>+#define SBI_FWFT_PLATFORM_FEATURE_BIT (1 << 30)
>+#define SBI_FWFT_GLOBAL_FEATURE_BIT (1 << 31)
>+
>+#define SBI_FWFT_SET_FLAG_LOCK (1 << 0)
>+
> /* SBI spec version fields */
> #define SBI_SPEC_VERSION_DEFAULT 0x1
> #define SBI_SPEC_VERSION_MAJOR_SHIFT 24
>@@ -419,6 +447,11 @@ enum sbi_ext_nacl_feature {
> #define SBI_ERR_ALREADY_STARTED -7
> #define SBI_ERR_ALREADY_STOPPED -8
> #define SBI_ERR_NO_SHMEM -9
>+#define SBI_ERR_INVALID_STATE -10
>+#define SBI_ERR_BAD_RANGE -11
>+#define SBI_ERR_TIMEOUT -12
nit: Space mis-aligned(^) ^
otherwise
Reviewed-by: Deepak Gupta <debug@rivosinc.com>
>+#define SBI_ERR_IO -13
>+#define SBI_ERR_DENIED_LOCKED -14
>
> extern unsigned long sbi_spec_version;
> struct sbiret {
>--
>2.47.2
>
>
WARNING: multiple messages have this Message-ID (diff)
From: Deepak Gupta <debug@rivosinc.com>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Shuah Khan <shuah@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org,
Samuel Holland <samuel.holland@sifive.com>
Subject: Re: [PATCH v2 01/15] riscv: add Firmware Feature (FWFT) SBI extensions definitions
Date: Mon, 10 Feb 2025 20:06:12 -0800 [thread overview]
Message-ID: <Z6rMtBud/hsKYYIw@debug.ba.rivosinc.com> (raw)
In-Reply-To: <20250210213549.1867704-2-cleger@rivosinc.com>
On Mon, Feb 10, 2025 at 10:35:34PM +0100, Clément Léger wrote:
>The Firmware Features extension (FWFT) was added as part of the SBI 3.0
>specification. Add SBI definitions to use this extension.
>
>Signed-off-by: Clément Léger <cleger@rivosinc.com>
>Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
>Tested-by: Samuel Holland <samuel.holland@sifive.com>
>---
> arch/riscv/include/asm/sbi.h | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
>diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
>index 3d250824178b..d373b5c08039 100644
>--- a/arch/riscv/include/asm/sbi.h
>+++ b/arch/riscv/include/asm/sbi.h
>@@ -35,6 +35,7 @@ enum sbi_ext_id {
> SBI_EXT_DBCN = 0x4442434E,
> SBI_EXT_STA = 0x535441,
> SBI_EXT_NACL = 0x4E41434C,
>+ SBI_EXT_FWFT = 0x46574654,
>
> /* Experimentals extensions must lie within this range */
> SBI_EXT_EXPERIMENTAL_START = 0x08000000,
>@@ -402,6 +403,33 @@ enum sbi_ext_nacl_feature {
> #define SBI_NACL_SHMEM_SRET_X(__i) ((__riscv_xlen / 8) * (__i))
> #define SBI_NACL_SHMEM_SRET_X_LAST 31
>
>+/* SBI function IDs for FW feature extension */
>+#define SBI_EXT_FWFT_SET 0x0
>+#define SBI_EXT_FWFT_GET 0x1
>+
>+enum sbi_fwft_feature_t {
>+ SBI_FWFT_MISALIGNED_EXC_DELEG = 0x0,
>+ SBI_FWFT_LANDING_PAD = 0x1,
>+ SBI_FWFT_SHADOW_STACK = 0x2,
>+ SBI_FWFT_DOUBLE_TRAP = 0x3,
>+ SBI_FWFT_PTE_AD_HW_UPDATING = 0x4,
>+ SBI_FWFT_POINTER_MASKING_PMLEN = 0x5,
>+ SBI_FWFT_LOCAL_RESERVED_START = 0x6,
>+ SBI_FWFT_LOCAL_RESERVED_END = 0x3fffffff,
>+ SBI_FWFT_LOCAL_PLATFORM_START = 0x40000000,
>+ SBI_FWFT_LOCAL_PLATFORM_END = 0x7fffffff,
>+
>+ SBI_FWFT_GLOBAL_RESERVED_START = 0x80000000,
>+ SBI_FWFT_GLOBAL_RESERVED_END = 0xbfffffff,
>+ SBI_FWFT_GLOBAL_PLATFORM_START = 0xc0000000,
>+ SBI_FWFT_GLOBAL_PLATFORM_END = 0xffffffff,
>+};
>+
>+#define SBI_FWFT_PLATFORM_FEATURE_BIT (1 << 30)
>+#define SBI_FWFT_GLOBAL_FEATURE_BIT (1 << 31)
>+
>+#define SBI_FWFT_SET_FLAG_LOCK (1 << 0)
>+
> /* SBI spec version fields */
> #define SBI_SPEC_VERSION_DEFAULT 0x1
> #define SBI_SPEC_VERSION_MAJOR_SHIFT 24
>@@ -419,6 +447,11 @@ enum sbi_ext_nacl_feature {
> #define SBI_ERR_ALREADY_STARTED -7
> #define SBI_ERR_ALREADY_STOPPED -8
> #define SBI_ERR_NO_SHMEM -9
>+#define SBI_ERR_INVALID_STATE -10
>+#define SBI_ERR_BAD_RANGE -11
>+#define SBI_ERR_TIMEOUT -12
nit: Space mis-aligned(^) ^
otherwise
Reviewed-by: Deepak Gupta <debug@rivosinc.com>
>+#define SBI_ERR_IO -13
>+#define SBI_ERR_DENIED_LOCKED -14
>
> extern unsigned long sbi_spec_version;
> struct sbiret {
>--
>2.47.2
>
>
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2025-02-11 4:06 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-10 21:35 [PATCH v2 00/15] riscv: add SBI FWFT misaligned exception delegation support Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 01/15] riscv: add Firmware Feature (FWFT) SBI extensions definitions Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-11 4:06 ` Deepak Gupta [this message]
2025-02-11 4:06 ` Deepak Gupta
2025-02-11 4:06 ` Deepak Gupta
2025-02-11 4:31 ` Samuel Holland
2025-02-11 4:31 ` Samuel Holland
2025-02-11 4:31 ` Samuel Holland
2025-02-10 21:35 ` [PATCH v2 02/15] riscv: misaligned: request misaligned exception from SBI Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 03/15] riscv: misaligned: use on_each_cpu() for scalar misaligned access probing Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 04/15] riscv: misaligned: use correct CONFIG_ ifdef for misaligned_access_speed Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 05/15] riscv: misaligned: move emulated access uniformity check in a function Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 06/15] riscv: misaligned: add a function to check misalign trap delegability Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 07/15] riscv: misaligned: factorize trap handling Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 08/15] riscv: misaligned: enable IRQs while handling misaligned accesses Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 09/15] riscv: misaligned: use get_user() instead of __get_user() Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 10/15] Documentation/sysctl: add riscv to unaligned-trap supported archs Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 11/15] selftests: riscv: add misaligned access testing Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 12/15] RISC-V: KVM: add SBI extension init()/deinit() functions Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 13/15] RISC-V: KVM: add SBI extension reset callback Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 14/15] RISC-V: KVM: add support for FWFT SBI extension Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-11 5:43 ` Deepak Gupta
2025-02-11 5:43 ` Deepak Gupta
2025-02-11 5:43 ` Deepak Gupta
2025-02-11 10:31 ` Clément Léger
2025-02-11 10:31 ` Clément Léger
2025-02-11 10:31 ` Clément Léger
2025-02-11 16:08 ` Deepak Gupta
2025-02-11 16:08 ` Deepak Gupta
2025-02-11 16:08 ` Deepak Gupta
2025-02-11 5:57 ` Deepak Gupta
2025-02-11 5:57 ` Deepak Gupta
2025-02-11 5:57 ` Deepak Gupta
2025-02-14 13:55 ` Clément Léger
2025-02-14 13:55 ` Clément Léger
2025-02-14 13:55 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 15/15] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-11 6:05 ` Deepak Gupta
2025-02-11 6:05 ` Deepak Gupta
2025-02-11 6:05 ` Deepak Gupta
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