From: Deepak Gupta <debug@rivosinc.com>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Shuah Khan <shuah@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org,
Samuel Holland <samuel.holland@sifive.com>
Subject: Re: [PATCH v2 15/15] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG
Date: Mon, 10 Feb 2025 22:05:46 -0800 [thread overview]
Message-ID: <Z6roumtGyFOfoOiw@debug.ba.rivosinc.com> (raw)
In-Reply-To: <20250210213549.1867704-16-cleger@rivosinc.com>
On Mon, Feb 10, 2025 at 10:35:48PM +0100, Clément Léger wrote:
>SBI_FWFT_MISALIGNED_DELEG needs hedeleg to be modified to delegate
>misaligned load/store exceptions. Save and restore it during CPU
>load/put.
>
>Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Deepak Gupta <debug@rivosinc.com>
>---
> arch/riscv/kvm/vcpu.c | 3 +++
> arch/riscv/kvm/vcpu_sbi_fwft.c | 39 ++++++++++++++++++++++++++++++++++
> 2 files changed, 42 insertions(+)
>
>diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
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WARNING: multiple messages have this Message-ID (diff)
From: Deepak Gupta <debug@rivosinc.com>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Shuah Khan <shuah@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org,
Samuel Holland <samuel.holland@sifive.com>
Subject: Re: [PATCH v2 15/15] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG
Date: Mon, 10 Feb 2025 22:05:46 -0800 [thread overview]
Message-ID: <Z6roumtGyFOfoOiw@debug.ba.rivosinc.com> (raw)
In-Reply-To: <20250210213549.1867704-16-cleger@rivosinc.com>
On Mon, Feb 10, 2025 at 10:35:48PM +0100, Clément Léger wrote:
>SBI_FWFT_MISALIGNED_DELEG needs hedeleg to be modified to delegate
>misaligned load/store exceptions. Save and restore it during CPU
>load/put.
>
>Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Deepak Gupta <debug@rivosinc.com>
>---
> arch/riscv/kvm/vcpu.c | 3 +++
> arch/riscv/kvm/vcpu_sbi_fwft.c | 39 ++++++++++++++++++++++++++++++++++
> 2 files changed, 42 insertions(+)
>
>diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
WARNING: multiple messages have this Message-ID (diff)
From: Deepak Gupta <debug@rivosinc.com>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Shuah Khan <shuah@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org,
Samuel Holland <samuel.holland@sifive.com>
Subject: Re: [PATCH v2 15/15] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG
Date: Mon, 10 Feb 2025 22:05:46 -0800 [thread overview]
Message-ID: <Z6roumtGyFOfoOiw@debug.ba.rivosinc.com> (raw)
In-Reply-To: <20250210213549.1867704-16-cleger@rivosinc.com>
On Mon, Feb 10, 2025 at 10:35:48PM +0100, Clément Léger wrote:
>SBI_FWFT_MISALIGNED_DELEG needs hedeleg to be modified to delegate
>misaligned load/store exceptions. Save and restore it during CPU
>load/put.
>
>Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Deepak Gupta <debug@rivosinc.com>
>---
> arch/riscv/kvm/vcpu.c | 3 +++
> arch/riscv/kvm/vcpu_sbi_fwft.c | 39 ++++++++++++++++++++++++++++++++++
> 2 files changed, 42 insertions(+)
>
>diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
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next prev parent reply other threads:[~2025-02-11 6:05 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-10 21:35 [PATCH v2 00/15] riscv: add SBI FWFT misaligned exception delegation support Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 01/15] riscv: add Firmware Feature (FWFT) SBI extensions definitions Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-11 4:06 ` Deepak Gupta
2025-02-11 4:06 ` Deepak Gupta
2025-02-11 4:06 ` Deepak Gupta
2025-02-11 4:31 ` Samuel Holland
2025-02-11 4:31 ` Samuel Holland
2025-02-11 4:31 ` Samuel Holland
2025-02-10 21:35 ` [PATCH v2 02/15] riscv: misaligned: request misaligned exception from SBI Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 03/15] riscv: misaligned: use on_each_cpu() for scalar misaligned access probing Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 04/15] riscv: misaligned: use correct CONFIG_ ifdef for misaligned_access_speed Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 05/15] riscv: misaligned: move emulated access uniformity check in a function Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 06/15] riscv: misaligned: add a function to check misalign trap delegability Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 07/15] riscv: misaligned: factorize trap handling Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 08/15] riscv: misaligned: enable IRQs while handling misaligned accesses Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 09/15] riscv: misaligned: use get_user() instead of __get_user() Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 10/15] Documentation/sysctl: add riscv to unaligned-trap supported archs Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 11/15] selftests: riscv: add misaligned access testing Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 12/15] RISC-V: KVM: add SBI extension init()/deinit() functions Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 13/15] RISC-V: KVM: add SBI extension reset callback Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 14/15] RISC-V: KVM: add support for FWFT SBI extension Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-11 5:43 ` Deepak Gupta
2025-02-11 5:43 ` Deepak Gupta
2025-02-11 5:43 ` Deepak Gupta
2025-02-11 10:31 ` Clément Léger
2025-02-11 10:31 ` Clément Léger
2025-02-11 10:31 ` Clément Léger
2025-02-11 16:08 ` Deepak Gupta
2025-02-11 16:08 ` Deepak Gupta
2025-02-11 16:08 ` Deepak Gupta
2025-02-11 5:57 ` Deepak Gupta
2025-02-11 5:57 ` Deepak Gupta
2025-02-11 5:57 ` Deepak Gupta
2025-02-14 13:55 ` Clément Léger
2025-02-14 13:55 ` Clément Léger
2025-02-14 13:55 ` Clément Léger
2025-02-10 21:35 ` [PATCH v2 15/15] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-10 21:35 ` Clément Léger
2025-02-11 6:05 ` Deepak Gupta [this message]
2025-02-11 6:05 ` Deepak Gupta
2025-02-11 6:05 ` Deepak Gupta
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