* [PATCH 00/19] DSC misc fixes
@ 2023-07-13 10:33 ` Ankit Nautiyal
0 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
This series is an attempt to address multiple issues with DSC,
scattered in separate existing series.
Patches 1-3 are DSC fixes from series to Handle BPC for HDMI2.1 PCON
https://patchwork.freedesktop.org/series/107550/
Patches 4-5 are from series DSC fixes for Bigjoiner:
https://patchwork.freedesktop.org/series/115773/
Patches 6-12 are from series to add DSC fractional BPP support:
https://patchwork.freedesktop.org/series/111391/
Patch 13 is to fix compressed bpc for MST DSC, from Stan's series :
https://patchwork.freedesktop.org/series/116179/
Rev2: Addressed review comments from Stan, Ville.
Rev3: Split larger patches. Separate out common helpers.
Rev4: Rebased, fixed checkpatch warnings.
Ankit Nautiyal (18):
drm/i915/dp: Consider output_format while computing dsc bpp
drm/i915/dp: Move compressed bpp check with 420 format inside the
helper
drm/i915/dp_mst: Use output_format to get the final link bpp
drm/i915/dp: Use consistent name for link bpp and compressed bpp
drm/i915/dp: Update Bigjoiner interface bits for computing compressed
bpp
drm/i915/display: Account for DSC not split case while computing cdclk
drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck
drm/i915/dp: Remove extra logs for printing DSC info
drm/display/dp: Fix the DP DSC Receiver cap size
drm/i915/dp: Avoid forcing DSC BPC for MST case
drm/i915/dp: Add functions to get min/max src input bpc with DSC
drm/i915/dp: Check min bpc DSC limits for dsc_force_bpc also
drm/i915/dp: Avoid left shift of DSC output bpp by 4
drm/i915/dp: Rename helper to get DSC max pipe_bpp
drm/i915/dp: Separate out functions for edp/DP for computing DSC bpp
drm/i915/dp: Add DSC BPC/BPP constraints while selecting pipe bpp with
DSC
drm/i915/dp: Separate out function to get compressed bpp with joiner
drm/i915/dp: Get optimal link config to have best compressed bpp
Stanislav Lisovskiy (1):
drm/i915: Query compressed bpp properly using correct DPCD and DP Spec
info
drivers/gpu/drm/i915/display/intel_cdclk.c | 63 +-
drivers/gpu/drm/i915/display/intel_dp.c | 611 ++++++++++++++----
drivers/gpu/drm/i915/display/intel_dp.h | 20 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 80 +--
drivers/gpu/drm/i915/display/intel_vdsc.c | 12 +
drivers/gpu/drm/i915/display/intel_vdsc.h | 2 +
.../drm/i915/display/skl_universal_plane.c | 4 +-
include/drm/display/drm_dp.h | 2 +-
8 files changed, 603 insertions(+), 191 deletions(-)
--
2.40.1
^ permalink raw reply [flat|nested] 72+ messages in thread* [Intel-gfx] [PATCH 01/19] drm/i915/dp: Consider output_format while computing dsc bpp
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-13 10:33 ` Ankit Nautiyal
-1 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel
While using DSC the compressed bpp is computed assuming RGB output
format. Consider the output_format and compute the compressed bpp
during mode valid and compute config steps.
For DP-MST we currently use RGB output format only, so continue
using RGB while computing compressed bpp for MST case.
v2: Use output_bpp instead for pipe_bpp to clamp compressed_bpp. (Ville)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 19 +++++++++++++++++--
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 03675620e3ea..e0d9618fccab 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -744,6 +744,7 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
bool bigjoiner,
+ enum intel_output_format output_format,
u32 pipe_bpp,
u32 timeslots)
{
@@ -768,6 +769,10 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
bits_per_pixel = ((link_clock * lane_count) * timeslots) /
(intel_dp_mode_to_fec_clock(mode_clock) * 8);
+ /* Bandwidth required for 420 is half, that of 444 format */
+ if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ bits_per_pixel *= 2;
+
drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
"total bw %u pixel clock %u\n",
bits_per_pixel, timeslots,
@@ -1161,11 +1166,16 @@ intel_dp_mode_valid(struct drm_connector *_connector,
if (HAS_DSC(dev_priv) &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+ enum intel_output_format sink_format, output_format;
+ int pipe_bpp;
+
+ sink_format = intel_dp_sink_format(connector, mode);
+ output_format = intel_dp_output_format(connector, sink_format);
/*
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be picked
*/
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
/*
* Output bpp is stored in 6.4 format so right shift by 4 to get the
@@ -1185,6 +1195,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
target_clock,
mode->hdisplay,
bigjoiner,
+ output_format,
pipe_bpp, 64) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
@@ -1724,6 +1735,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
adjusted_mode->crtc_clock,
adjusted_mode->crtc_hdisplay,
pipe_config->bigjoiner_pipes,
+ pipe_config->output_format,
pipe_bpp,
timeslots);
/*
@@ -1759,9 +1771,12 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
* calculation procedure is bit different for MST case.
*/
if (compute_pipe_bpp) {
+ u16 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
+ pipe_config->pipe_bpp);
+
pipe_config->dsc.compressed_bpp = min_t(u16,
dsc_max_output_bpp >> 4,
- pipe_config->pipe_bpp);
+ output_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n",
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 22099de3ca45..bb4f976af296 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -111,6 +111,7 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
bool bigjoiner,
+ enum intel_output_format output_format,
u32 pipe_bpp,
u32 timeslots);
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index e3f176a093d2..aa8d9d570626 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -973,6 +973,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
target_clock,
mode->hdisplay,
bigjoiner,
+ INTEL_OUTPUT_FORMAT_RGB,
pipe_bpp, 64) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH 01/19] drm/i915/dp: Consider output_format while computing dsc bpp
@ 2023-07-13 10:33 ` Ankit Nautiyal
0 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
While using DSC the compressed bpp is computed assuming RGB output
format. Consider the output_format and compute the compressed bpp
during mode valid and compute config steps.
For DP-MST we currently use RGB output format only, so continue
using RGB while computing compressed bpp for MST case.
v2: Use output_bpp instead for pipe_bpp to clamp compressed_bpp. (Ville)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 19 +++++++++++++++++--
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 03675620e3ea..e0d9618fccab 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -744,6 +744,7 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
bool bigjoiner,
+ enum intel_output_format output_format,
u32 pipe_bpp,
u32 timeslots)
{
@@ -768,6 +769,10 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
bits_per_pixel = ((link_clock * lane_count) * timeslots) /
(intel_dp_mode_to_fec_clock(mode_clock) * 8);
+ /* Bandwidth required for 420 is half, that of 444 format */
+ if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ bits_per_pixel *= 2;
+
drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
"total bw %u pixel clock %u\n",
bits_per_pixel, timeslots,
@@ -1161,11 +1166,16 @@ intel_dp_mode_valid(struct drm_connector *_connector,
if (HAS_DSC(dev_priv) &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+ enum intel_output_format sink_format, output_format;
+ int pipe_bpp;
+
+ sink_format = intel_dp_sink_format(connector, mode);
+ output_format = intel_dp_output_format(connector, sink_format);
/*
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be picked
*/
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
/*
* Output bpp is stored in 6.4 format so right shift by 4 to get the
@@ -1185,6 +1195,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
target_clock,
mode->hdisplay,
bigjoiner,
+ output_format,
pipe_bpp, 64) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
@@ -1724,6 +1735,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
adjusted_mode->crtc_clock,
adjusted_mode->crtc_hdisplay,
pipe_config->bigjoiner_pipes,
+ pipe_config->output_format,
pipe_bpp,
timeslots);
/*
@@ -1759,9 +1771,12 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
* calculation procedure is bit different for MST case.
*/
if (compute_pipe_bpp) {
+ u16 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
+ pipe_config->pipe_bpp);
+
pipe_config->dsc.compressed_bpp = min_t(u16,
dsc_max_output_bpp >> 4,
- pipe_config->pipe_bpp);
+ output_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n",
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 22099de3ca45..bb4f976af296 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -111,6 +111,7 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
bool bigjoiner,
+ enum intel_output_format output_format,
u32 pipe_bpp,
u32 timeslots);
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index e3f176a093d2..aa8d9d570626 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -973,6 +973,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
target_clock,
mode->hdisplay,
bigjoiner,
+ INTEL_OUTPUT_FORMAT_RGB,
pipe_bpp, 64) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [Intel-gfx] [PATCH 02/19] drm/i915/dp: Move compressed bpp check with 420 format inside the helper
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-13 10:33 ` Ankit Nautiyal
-1 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel
Move the check for limiting compressed bite_per_pixel for 420,422
formats in the helper to compute bits_per_pixel.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e0d9618fccab..d1db457fb17c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -773,6 +773,15 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
bits_per_pixel *= 2;
+ /*
+ * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
+ * supported PPS value can be 63.9375 and with the further
+ * mention that for 420, 422 formats, bpp should be programmed double
+ * the target bpp restricting our target bpp to be 31.9375 at max.
+ */
+ if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ bits_per_pixel = min_t(u32, bits_per_pixel, 31);
+
drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
"total bw %u pixel clock %u\n",
bits_per_pixel, timeslots,
@@ -1738,15 +1747,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->output_format,
pipe_bpp,
timeslots);
- /*
- * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
- * supported PPS value can be 63.9375 and with the further
- * mention that bpp should be programmed double the target bpp
- * restricting our target bpp to be 31.9375 at max
- */
- if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
- dsc_max_output_bpp = min_t(u16, dsc_max_output_bpp, 31 << 4);
-
if (!dsc_max_output_bpp) {
drm_dbg_kms(&dev_priv->drm,
"Compressed BPP not supported\n");
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH 02/19] drm/i915/dp: Move compressed bpp check with 420 format inside the helper
@ 2023-07-13 10:33 ` Ankit Nautiyal
0 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
Move the check for limiting compressed bite_per_pixel for 420,422
formats in the helper to compute bits_per_pixel.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e0d9618fccab..d1db457fb17c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -773,6 +773,15 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
bits_per_pixel *= 2;
+ /*
+ * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
+ * supported PPS value can be 63.9375 and with the further
+ * mention that for 420, 422 formats, bpp should be programmed double
+ * the target bpp restricting our target bpp to be 31.9375 at max.
+ */
+ if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ bits_per_pixel = min_t(u32, bits_per_pixel, 31);
+
drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
"total bw %u pixel clock %u\n",
bits_per_pixel, timeslots,
@@ -1738,15 +1747,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->output_format,
pipe_bpp,
timeslots);
- /*
- * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
- * supported PPS value can be 63.9375 and with the further
- * mention that bpp should be programmed double the target bpp
- * restricting our target bpp to be 31.9375 at max
- */
- if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
- dsc_max_output_bpp = min_t(u16, dsc_max_output_bpp, 31 << 4);
-
if (!dsc_max_output_bpp) {
drm_dbg_kms(&dev_priv->drm,
"Compressed BPP not supported\n");
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* Re: [Intel-gfx] [PATCH 02/19] drm/i915/dp: Move compressed bpp check with 420 format inside the helper
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-14 3:23 ` Murthy, Arun R
-1 siblings, 0 replies; 72+ messages in thread
From: Murthy, Arun R @ 2023-07-14 3:23 UTC (permalink / raw)
To: Nautiyal, Ankit K, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ankit
> Nautiyal
> Sent: Thursday, July 13, 2023 4:03 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 02/19] drm/i915/dp: Move compressed bpp check
> with 420 format inside the helper
>
> Move the check for limiting compressed bite_per_pixel for 420,422 formats
> in the helper to compute bits_per_pixel.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
Looks good!
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
> drivers/gpu/drm/i915/display/intel_dp.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index e0d9618fccab..d1db457fb17c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -773,6 +773,15 @@ u16 intel_dp_dsc_get_output_bpp(struct
> drm_i915_private *i915,
> if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> bits_per_pixel *= 2;
>
> + /*
> + * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
> + * supported PPS value can be 63.9375 and with the further
> + * mention that for 420, 422 formats, bpp should be programmed
> double
> + * the target bpp restricting our target bpp to be 31.9375 at max.
> + */
> + if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> + bits_per_pixel = min_t(u32, bits_per_pixel, 31);
> +
> drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
> "total bw %u pixel clock %u\n",
> bits_per_pixel, timeslots,
> @@ -1738,15 +1747,6 @@ int intel_dp_dsc_compute_config(struct intel_dp
> *intel_dp,
> pipe_config-
> >output_format,
> pipe_bpp,
> timeslots);
> - /*
> - * According to DSC 1.2a Section 4.1.1 Table 4.1 the
> maximum
> - * supported PPS value can be 63.9375 and with the
> further
> - * mention that bpp should be programmed double
> the target bpp
> - * restricting our target bpp to be 31.9375 at max
> - */
> - if (pipe_config->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420)
> - dsc_max_output_bpp = min_t(u16,
> dsc_max_output_bpp, 31 << 4);
> -
> if (!dsc_max_output_bpp) {
> drm_dbg_kms(&dev_priv->drm,
> "Compressed BPP not
> supported\n");
> --
> 2.40.1
^ permalink raw reply [flat|nested] 72+ messages in thread* RE: [Intel-gfx] [PATCH 02/19] drm/i915/dp: Move compressed bpp check with 420 format inside the helper
@ 2023-07-14 3:23 ` Murthy, Arun R
0 siblings, 0 replies; 72+ messages in thread
From: Murthy, Arun R @ 2023-07-14 3:23 UTC (permalink / raw)
To: Nautiyal, Ankit K, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ankit
> Nautiyal
> Sent: Thursday, July 13, 2023 4:03 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 02/19] drm/i915/dp: Move compressed bpp check
> with 420 format inside the helper
>
> Move the check for limiting compressed bite_per_pixel for 420,422 formats
> in the helper to compute bits_per_pixel.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
Looks good!
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
> drivers/gpu/drm/i915/display/intel_dp.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index e0d9618fccab..d1db457fb17c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -773,6 +773,15 @@ u16 intel_dp_dsc_get_output_bpp(struct
> drm_i915_private *i915,
> if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> bits_per_pixel *= 2;
>
> + /*
> + * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
> + * supported PPS value can be 63.9375 and with the further
> + * mention that for 420, 422 formats, bpp should be programmed
> double
> + * the target bpp restricting our target bpp to be 31.9375 at max.
> + */
> + if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> + bits_per_pixel = min_t(u32, bits_per_pixel, 31);
> +
> drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
> "total bw %u pixel clock %u\n",
> bits_per_pixel, timeslots,
> @@ -1738,15 +1747,6 @@ int intel_dp_dsc_compute_config(struct intel_dp
> *intel_dp,
> pipe_config-
> >output_format,
> pipe_bpp,
> timeslots);
> - /*
> - * According to DSC 1.2a Section 4.1.1 Table 4.1 the
> maximum
> - * supported PPS value can be 63.9375 and with the
> further
> - * mention that bpp should be programmed double
> the target bpp
> - * restricting our target bpp to be 31.9375 at max
> - */
> - if (pipe_config->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420)
> - dsc_max_output_bpp = min_t(u16,
> dsc_max_output_bpp, 31 << 4);
> -
> if (!dsc_max_output_bpp) {
> drm_dbg_kms(&dev_priv->drm,
> "Compressed BPP not
> supported\n");
> --
> 2.40.1
^ permalink raw reply [flat|nested] 72+ messages in thread
* [Intel-gfx] [PATCH 03/19] drm/i915/dp_mst: Use output_format to get the final link bpp
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-13 10:33 ` Ankit Nautiyal
-1 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel
The final link bpp used to calculate the m_n values depend on the
output_format. Though the output_format is set to RGB for MST case and
the link bpp will be same as the pipe bpp, for the sake of semantics,
lets calculate the m_n values with the link bpp, instead of pipe_bpp.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++++-
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d1db457fb17c..eb158efdb414 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -965,7 +965,7 @@ int intel_dp_min_bpp(enum intel_output_format output_format)
return 8 * 3;
}
-static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
+int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
{
/*
* bpp value was assumed to RGB format. And YCbCr 4:2:0 output
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index bb4f976af296..7dd015385054 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -144,5 +144,6 @@ void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
void intel_dp_phy_test(struct intel_encoder *encoder);
void intel_dp_wait_source_oui(struct intel_dp *intel_dp);
+int intel_dp_output_bpp(enum intel_output_format output_format, int bpp);
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index aa8d9d570626..ef5375eb923e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -155,6 +155,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
int slots = -EINVAL;
+ int link_bpp;
slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, limits->max_bpp,
limits->min_bpp, limits,
@@ -163,7 +164,9 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
if (slots < 0)
return slots;
- intel_link_compute_m_n(crtc_state->pipe_bpp,
+ link_bpp = intel_dp_output_bpp(crtc_state->output_format, crtc_state->pipe_bpp);
+
+ intel_link_compute_m_n(link_bpp,
crtc_state->lane_count,
adjusted_mode->crtc_clock,
crtc_state->port_clock,
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH 03/19] drm/i915/dp_mst: Use output_format to get the final link bpp
@ 2023-07-13 10:33 ` Ankit Nautiyal
0 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
The final link bpp used to calculate the m_n values depend on the
output_format. Though the output_format is set to RGB for MST case and
the link bpp will be same as the pipe bpp, for the sake of semantics,
lets calculate the m_n values with the link bpp, instead of pipe_bpp.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++++-
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d1db457fb17c..eb158efdb414 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -965,7 +965,7 @@ int intel_dp_min_bpp(enum intel_output_format output_format)
return 8 * 3;
}
-static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
+int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
{
/*
* bpp value was assumed to RGB format. And YCbCr 4:2:0 output
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index bb4f976af296..7dd015385054 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -144,5 +144,6 @@ void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
void intel_dp_phy_test(struct intel_encoder *encoder);
void intel_dp_wait_source_oui(struct intel_dp *intel_dp);
+int intel_dp_output_bpp(enum intel_output_format output_format, int bpp);
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index aa8d9d570626..ef5375eb923e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -155,6 +155,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
int slots = -EINVAL;
+ int link_bpp;
slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, limits->max_bpp,
limits->min_bpp, limits,
@@ -163,7 +164,9 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
if (slots < 0)
return slots;
- intel_link_compute_m_n(crtc_state->pipe_bpp,
+ link_bpp = intel_dp_output_bpp(crtc_state->output_format, crtc_state->pipe_bpp);
+
+ intel_link_compute_m_n(link_bpp,
crtc_state->lane_count,
adjusted_mode->crtc_clock,
crtc_state->port_clock,
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [Intel-gfx] [PATCH 04/19] drm/i915/dp: Use consistent name for link bpp and compressed bpp
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-13 10:33 ` Ankit Nautiyal
-1 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel
Currently there are many places where we use output_bpp for link bpp and
compressed bpp.
Lets use consistent naming:
output_bpp : The intermediate value taking into account the
output_format chroma subsampling.
compressed_bpp : target bpp for the DSC encoder.
link_bpp : final bpp used in the link.
For 444 sampling without DSC:
link_bpp = output_bpp = pipe_bpp
For 420 sampling without DSC:
output_bpp = pipe_bpp / 2
link_bpp = output_bpp
For 444 sampling with DSC:
output_bpp = pipe_bpp
link_bpp = compressed_bpp, computed with output_bpp (i.e. pipe_bpp in
this case)
For 420 sampling with DSC:
output_bpp = pipe_bpp/2
link_bpp = compressed_bpp, computed with output_bpp
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 84 ++++++++++-----------
drivers/gpu/drm/i915/display/intel_dp.h | 14 ++--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +++---
3 files changed, 60 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index eb158efdb414..19768ac658ba 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -740,13 +740,13 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p
return bits_per_pixel;
}
-u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- enum intel_output_format output_format,
- u32 pipe_bpp,
- u32 timeslots)
+u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ enum intel_output_format output_format,
+ u32 pipe_bpp,
+ u32 timeslots)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
@@ -1136,7 +1136,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
int target_clock = mode->clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
int max_dotclk = dev_priv->max_dotclk_freq;
- u16 dsc_max_output_bpp = 0;
+ u16 dsc_max_compressed_bpp = 0;
u8 dsc_slice_count = 0;
enum drm_mode_status status;
bool dsc = false, bigjoiner = false;
@@ -1191,21 +1191,21 @@ intel_dp_mode_valid(struct drm_connector *_connector,
* integer value since we support only integer values of bpp.
*/
if (intel_dp_is_edp(intel_dp)) {
- dsc_max_output_bpp =
+ dsc_max_compressed_bpp =
drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
dsc_slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
- dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- max_link_clock,
- max_lanes,
- target_clock,
- mode->hdisplay,
- bigjoiner,
- output_format,
- pipe_bpp, 64) >> 4;
+ dsc_max_compressed_bpp =
+ intel_dp_dsc_get_max_compressed_bpp(dev_priv,
+ max_link_clock,
+ max_lanes,
+ target_clock,
+ mode->hdisplay,
+ bigjoiner,
+ output_format,
+ pipe_bpp, 64) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1213,7 +1213,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
bigjoiner);
}
- dsc = dsc_max_output_bpp && dsc_slice_count;
+ dsc = dsc_max_compressed_bpp && dsc_slice_count;
}
/*
@@ -1502,9 +1502,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
int mode_rate, link_rate, link_avail;
for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
- int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
+ int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
- mode_rate = intel_dp_link_required(clock, output_bpp);
+ mode_rate = intel_dp_link_required(clock, link_bpp);
for (i = 0; i < intel_dp->num_common_rates; i++) {
link_rate = intel_dp_common_rate(intel_dp, i);
@@ -1733,21 +1733,21 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return -EINVAL;
}
} else {
- u16 dsc_max_output_bpp = 0;
+ u16 dsc_max_compressed_bpp = 0;
u8 dsc_dp_slice_count;
if (compute_pipe_bpp) {
- dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- pipe_config->port_clock,
- pipe_config->lane_count,
- adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay,
- pipe_config->bigjoiner_pipes,
- pipe_config->output_format,
- pipe_bpp,
- timeslots);
- if (!dsc_max_output_bpp) {
+ dsc_max_compressed_bpp =
+ intel_dp_dsc_get_max_compressed_bpp(dev_priv,
+ pipe_config->port_clock,
+ pipe_config->lane_count,
+ adjusted_mode->crtc_clock,
+ adjusted_mode->crtc_hdisplay,
+ pipe_config->bigjoiner_pipes,
+ pipe_config->output_format,
+ pipe_bpp,
+ timeslots);
+ if (!dsc_max_compressed_bpp) {
drm_dbg_kms(&dev_priv->drm,
"Compressed BPP not supported\n");
return -EINVAL;
@@ -1775,7 +1775,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->pipe_bpp);
pipe_config->dsc.compressed_bpp = min_t(u16,
- dsc_max_output_bpp >> 4,
+ dsc_max_compressed_bpp >> 4,
output_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
@@ -2151,7 +2151,7 @@ static bool can_enable_drrs(struct intel_connector *connector,
static void
intel_dp_drrs_compute_config(struct intel_connector *connector,
struct intel_crtc_state *pipe_config,
- int output_bpp)
+ int link_bpp)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
const struct drm_display_mode *downclock_mode =
@@ -2176,7 +2176,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
if (pipe_config->splitter.enable)
pixel_clock /= pipe_config->splitter.link_count;
- intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
+ intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock,
pipe_config->port_clock, &pipe_config->dp_m2_n2,
pipe_config->fec_enable);
@@ -2274,7 +2274,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
const struct drm_display_mode *fixed_mode;
struct intel_connector *connector = intel_dp->attached_connector;
- int ret = 0, output_bpp;
+ int ret = 0, link_bpp;
if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
pipe_config->has_pch_encoder = true;
@@ -2324,10 +2324,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_dp_limited_color_range(pipe_config, conn_state);
if (pipe_config->dsc.compression_enable)
- output_bpp = pipe_config->dsc.compressed_bpp;
+ link_bpp = pipe_config->dsc.compressed_bpp;
else
- output_bpp = intel_dp_output_bpp(pipe_config->output_format,
- pipe_config->pipe_bpp);
+ link_bpp = intel_dp_output_bpp(pipe_config->output_format,
+ pipe_config->pipe_bpp);
if (intel_dp->mso_link_count) {
int n = intel_dp->mso_link_count;
@@ -2351,7 +2351,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
- intel_link_compute_m_n(output_bpp,
+ intel_link_compute_m_n(link_bpp,
pipe_config->lane_count,
adjusted_mode->crtc_clock,
pipe_config->port_clock,
@@ -2367,7 +2367,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_vrr_compute_config(pipe_config, conn_state);
intel_psr_compute_config(intel_dp, pipe_config, conn_state);
- intel_dp_drrs_compute_config(connector, pipe_config, output_bpp);
+ intel_dp_drrs_compute_config(connector, pipe_config, link_bpp);
intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 7dd015385054..6fd423463f5c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -107,13 +107,13 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
unsigned int type);
bool intel_digital_port_connected(struct intel_encoder *encoder);
int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
-u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- enum intel_output_format output_format,
- u32 pipe_bpp,
- u32 timeslots);
+u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ enum intel_output_format output_format,
+ u32 pipe_bpp,
+ u32 timeslots);
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
int mode_clock, int mode_hdisplay,
bool bigjoiner);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index ef5375eb923e..1f00713fb1ad 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -915,7 +915,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
int max_rate, mode_rate, max_lanes, max_link_clock;
int ret;
bool dsc = false, bigjoiner = false;
- u16 dsc_max_output_bpp = 0;
+ u16 dsc_max_compressed_bpp = 0;
u8 dsc_slice_count = 0;
int target_clock = mode->clock;
@@ -969,15 +969,15 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
- dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- max_link_clock,
- max_lanes,
- target_clock,
- mode->hdisplay,
- bigjoiner,
- INTEL_OUTPUT_FORMAT_RGB,
- pipe_bpp, 64) >> 4;
+ dsc_max_compressed_bpp =
+ intel_dp_dsc_get_max_compressed_bpp(dev_priv,
+ max_link_clock,
+ max_lanes,
+ target_clock,
+ mode->hdisplay,
+ bigjoiner,
+ INTEL_OUTPUT_FORMAT_RGB,
+ pipe_bpp, 64) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -985,7 +985,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
bigjoiner);
}
- dsc = dsc_max_output_bpp && dsc_slice_count;
+ dsc = dsc_max_compressed_bpp && dsc_slice_count;
}
/*
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH 04/19] drm/i915/dp: Use consistent name for link bpp and compressed bpp
@ 2023-07-13 10:33 ` Ankit Nautiyal
0 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
Currently there are many places where we use output_bpp for link bpp and
compressed bpp.
Lets use consistent naming:
output_bpp : The intermediate value taking into account the
output_format chroma subsampling.
compressed_bpp : target bpp for the DSC encoder.
link_bpp : final bpp used in the link.
For 444 sampling without DSC:
link_bpp = output_bpp = pipe_bpp
For 420 sampling without DSC:
output_bpp = pipe_bpp / 2
link_bpp = output_bpp
For 444 sampling with DSC:
output_bpp = pipe_bpp
link_bpp = compressed_bpp, computed with output_bpp (i.e. pipe_bpp in
this case)
For 420 sampling with DSC:
output_bpp = pipe_bpp/2
link_bpp = compressed_bpp, computed with output_bpp
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 84 ++++++++++-----------
drivers/gpu/drm/i915/display/intel_dp.h | 14 ++--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +++---
3 files changed, 60 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index eb158efdb414..19768ac658ba 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -740,13 +740,13 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p
return bits_per_pixel;
}
-u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- enum intel_output_format output_format,
- u32 pipe_bpp,
- u32 timeslots)
+u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ enum intel_output_format output_format,
+ u32 pipe_bpp,
+ u32 timeslots)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
@@ -1136,7 +1136,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
int target_clock = mode->clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
int max_dotclk = dev_priv->max_dotclk_freq;
- u16 dsc_max_output_bpp = 0;
+ u16 dsc_max_compressed_bpp = 0;
u8 dsc_slice_count = 0;
enum drm_mode_status status;
bool dsc = false, bigjoiner = false;
@@ -1191,21 +1191,21 @@ intel_dp_mode_valid(struct drm_connector *_connector,
* integer value since we support only integer values of bpp.
*/
if (intel_dp_is_edp(intel_dp)) {
- dsc_max_output_bpp =
+ dsc_max_compressed_bpp =
drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
dsc_slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
- dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- max_link_clock,
- max_lanes,
- target_clock,
- mode->hdisplay,
- bigjoiner,
- output_format,
- pipe_bpp, 64) >> 4;
+ dsc_max_compressed_bpp =
+ intel_dp_dsc_get_max_compressed_bpp(dev_priv,
+ max_link_clock,
+ max_lanes,
+ target_clock,
+ mode->hdisplay,
+ bigjoiner,
+ output_format,
+ pipe_bpp, 64) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1213,7 +1213,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
bigjoiner);
}
- dsc = dsc_max_output_bpp && dsc_slice_count;
+ dsc = dsc_max_compressed_bpp && dsc_slice_count;
}
/*
@@ -1502,9 +1502,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
int mode_rate, link_rate, link_avail;
for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
- int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
+ int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
- mode_rate = intel_dp_link_required(clock, output_bpp);
+ mode_rate = intel_dp_link_required(clock, link_bpp);
for (i = 0; i < intel_dp->num_common_rates; i++) {
link_rate = intel_dp_common_rate(intel_dp, i);
@@ -1733,21 +1733,21 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return -EINVAL;
}
} else {
- u16 dsc_max_output_bpp = 0;
+ u16 dsc_max_compressed_bpp = 0;
u8 dsc_dp_slice_count;
if (compute_pipe_bpp) {
- dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- pipe_config->port_clock,
- pipe_config->lane_count,
- adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay,
- pipe_config->bigjoiner_pipes,
- pipe_config->output_format,
- pipe_bpp,
- timeslots);
- if (!dsc_max_output_bpp) {
+ dsc_max_compressed_bpp =
+ intel_dp_dsc_get_max_compressed_bpp(dev_priv,
+ pipe_config->port_clock,
+ pipe_config->lane_count,
+ adjusted_mode->crtc_clock,
+ adjusted_mode->crtc_hdisplay,
+ pipe_config->bigjoiner_pipes,
+ pipe_config->output_format,
+ pipe_bpp,
+ timeslots);
+ if (!dsc_max_compressed_bpp) {
drm_dbg_kms(&dev_priv->drm,
"Compressed BPP not supported\n");
return -EINVAL;
@@ -1775,7 +1775,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->pipe_bpp);
pipe_config->dsc.compressed_bpp = min_t(u16,
- dsc_max_output_bpp >> 4,
+ dsc_max_compressed_bpp >> 4,
output_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
@@ -2151,7 +2151,7 @@ static bool can_enable_drrs(struct intel_connector *connector,
static void
intel_dp_drrs_compute_config(struct intel_connector *connector,
struct intel_crtc_state *pipe_config,
- int output_bpp)
+ int link_bpp)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
const struct drm_display_mode *downclock_mode =
@@ -2176,7 +2176,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
if (pipe_config->splitter.enable)
pixel_clock /= pipe_config->splitter.link_count;
- intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
+ intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock,
pipe_config->port_clock, &pipe_config->dp_m2_n2,
pipe_config->fec_enable);
@@ -2274,7 +2274,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
const struct drm_display_mode *fixed_mode;
struct intel_connector *connector = intel_dp->attached_connector;
- int ret = 0, output_bpp;
+ int ret = 0, link_bpp;
if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
pipe_config->has_pch_encoder = true;
@@ -2324,10 +2324,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_dp_limited_color_range(pipe_config, conn_state);
if (pipe_config->dsc.compression_enable)
- output_bpp = pipe_config->dsc.compressed_bpp;
+ link_bpp = pipe_config->dsc.compressed_bpp;
else
- output_bpp = intel_dp_output_bpp(pipe_config->output_format,
- pipe_config->pipe_bpp);
+ link_bpp = intel_dp_output_bpp(pipe_config->output_format,
+ pipe_config->pipe_bpp);
if (intel_dp->mso_link_count) {
int n = intel_dp->mso_link_count;
@@ -2351,7 +2351,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
- intel_link_compute_m_n(output_bpp,
+ intel_link_compute_m_n(link_bpp,
pipe_config->lane_count,
adjusted_mode->crtc_clock,
pipe_config->port_clock,
@@ -2367,7 +2367,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_vrr_compute_config(pipe_config, conn_state);
intel_psr_compute_config(intel_dp, pipe_config, conn_state);
- intel_dp_drrs_compute_config(connector, pipe_config, output_bpp);
+ intel_dp_drrs_compute_config(connector, pipe_config, link_bpp);
intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 7dd015385054..6fd423463f5c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -107,13 +107,13 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
unsigned int type);
bool intel_digital_port_connected(struct intel_encoder *encoder);
int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
-u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- enum intel_output_format output_format,
- u32 pipe_bpp,
- u32 timeslots);
+u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ enum intel_output_format output_format,
+ u32 pipe_bpp,
+ u32 timeslots);
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
int mode_clock, int mode_hdisplay,
bool bigjoiner);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index ef5375eb923e..1f00713fb1ad 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -915,7 +915,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
int max_rate, mode_rate, max_lanes, max_link_clock;
int ret;
bool dsc = false, bigjoiner = false;
- u16 dsc_max_output_bpp = 0;
+ u16 dsc_max_compressed_bpp = 0;
u8 dsc_slice_count = 0;
int target_clock = mode->clock;
@@ -969,15 +969,15 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
- dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- max_link_clock,
- max_lanes,
- target_clock,
- mode->hdisplay,
- bigjoiner,
- INTEL_OUTPUT_FORMAT_RGB,
- pipe_bpp, 64) >> 4;
+ dsc_max_compressed_bpp =
+ intel_dp_dsc_get_max_compressed_bpp(dev_priv,
+ max_link_clock,
+ max_lanes,
+ target_clock,
+ mode->hdisplay,
+ bigjoiner,
+ INTEL_OUTPUT_FORMAT_RGB,
+ pipe_bpp, 64) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -985,7 +985,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
bigjoiner);
}
- dsc = dsc_max_output_bpp && dsc_slice_count;
+ dsc = dsc_max_compressed_bpp && dsc_slice_count;
}
/*
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [Intel-gfx] [PATCH 05/19] drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-13 10:33 ` Ankit Nautiyal
-1 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel
In Bigjoiner check for DSC, bigjoiner interface bits for DP for
DISPLAY > 13 is 36 (Bspec: 49259).
v2: Corrected Display ver to 13.
v3: Follow convention for conditional statement. (Ville)
v4: Fix check for display ver. (Ville)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 19768ac658ba..c1fd448d80e1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -802,8 +802,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
if (bigjoiner) {
+ int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
u32 max_bpp_bigjoiner =
- i915->display.cdclk.max_cdclk_freq * 48 /
+ i915->display.cdclk.max_cdclk_freq * 2 * bigjoiner_interface_bits /
intel_dp_mode_to_fec_clock(mode_clock);
bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH 05/19] drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp
@ 2023-07-13 10:33 ` Ankit Nautiyal
0 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
In Bigjoiner check for DSC, bigjoiner interface bits for DP for
DISPLAY > 13 is 36 (Bspec: 49259).
v2: Corrected Display ver to 13.
v3: Follow convention for conditional statement. (Ville)
v4: Fix check for display ver. (Ville)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 19768ac658ba..c1fd448d80e1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -802,8 +802,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
if (bigjoiner) {
+ int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
u32 max_bpp_bigjoiner =
- i915->display.cdclk.max_cdclk_freq * 48 /
+ i915->display.cdclk.max_cdclk_freq * 2 * bigjoiner_interface_bits /
intel_dp_mode_to_fec_clock(mode_clock);
bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* Re: [Intel-gfx] [PATCH 05/19] drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-20 9:29 ` Lisovskiy, Stanislav
-1 siblings, 0 replies; 72+ messages in thread
From: Lisovskiy, Stanislav @ 2023-07-20 9:29 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, dri-devel
On Thu, Jul 13, 2023 at 04:03:32PM +0530, Ankit Nautiyal wrote:
> In Bigjoiner check for DSC, bigjoiner interface bits for DP for
> DISPLAY > 13 is 36 (Bspec: 49259).
>
> v2: Corrected Display ver to 13.
>
> v3: Follow convention for conditional statement. (Ville)
>
> v4: Fix check for display ver. (Ville)
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 19768ac658ba..c1fd448d80e1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -802,8 +802,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
> bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
>
> if (bigjoiner) {
> + int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
> u32 max_bpp_bigjoiner =
> - i915->display.cdclk.max_cdclk_freq * 48 /
> + i915->display.cdclk.max_cdclk_freq * 2 * bigjoiner_interface_bits /
Probably "num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);" again,
instead of "2"?
With that clarified,
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> intel_dp_mode_to_fec_clock(mode_clock);
>
> bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 72+ messages in thread* Re: [PATCH 05/19] drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp
@ 2023-07-20 9:29 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 72+ messages in thread
From: Lisovskiy, Stanislav @ 2023-07-20 9:29 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, anusha.srivatsa, dri-devel, navaremanasi
On Thu, Jul 13, 2023 at 04:03:32PM +0530, Ankit Nautiyal wrote:
> In Bigjoiner check for DSC, bigjoiner interface bits for DP for
> DISPLAY > 13 is 36 (Bspec: 49259).
>
> v2: Corrected Display ver to 13.
>
> v3: Follow convention for conditional statement. (Ville)
>
> v4: Fix check for display ver. (Ville)
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 19768ac658ba..c1fd448d80e1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -802,8 +802,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
> bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
>
> if (bigjoiner) {
> + int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
> u32 max_bpp_bigjoiner =
> - i915->display.cdclk.max_cdclk_freq * 48 /
> + i915->display.cdclk.max_cdclk_freq * 2 * bigjoiner_interface_bits /
Probably "num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);" again,
instead of "2"?
With that clarified,
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> intel_dp_mode_to_fec_clock(mode_clock);
>
> bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 72+ messages in thread* Re: [Intel-gfx] [PATCH 05/19] drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp
2023-07-20 9:29 ` Lisovskiy, Stanislav
@ 2023-07-24 12:19 ` Nautiyal, Ankit K
-1 siblings, 0 replies; 72+ messages in thread
From: Nautiyal, Ankit K @ 2023-07-24 12:19 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx, dri-devel
Hi Stan,
Thanks for the reviews ans suggestions. Please my response inline:
On 7/20/2023 2:59 PM, Lisovskiy, Stanislav wrote:
> On Thu, Jul 13, 2023 at 04:03:32PM +0530, Ankit Nautiyal wrote:
>> In Bigjoiner check for DSC, bigjoiner interface bits for DP for
>> DISPLAY > 13 is 36 (Bspec: 49259).
>>
>> v2: Corrected Display ver to 13.
>>
>> v3: Follow convention for conditional statement. (Ville)
>>
>> v4: Fix check for display ver. (Ville)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 19768ac658ba..c1fd448d80e1 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -802,8 +802,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
>> bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
>>
>> if (bigjoiner) {
>> + int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
>> u32 max_bpp_bigjoiner =
>> - i915->display.cdclk.max_cdclk_freq * 48 /
>> + i915->display.cdclk.max_cdclk_freq * 2 * bigjoiner_interface_bits /
> Probably "num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);" again,
> instead of "2"?
Currently intel_dsc_get_num_vdsc_instances will give total number of
vdsc_engines including joined pipes.
So with bigjoiner the function will return 4.
This was good to calculate Pipe BW check: (Pixel clock < PPC * CDCLK
frequency * Number of pipes joined
as we get PPC * number of pipes joined from
intel_dsc_get_num_vdsc_instances)
Or to calculate DSC_PIC_WIDTH PPS parameter.
But here we perhaps need intel_dsc_get_vdsc_engines_per_pipe that will
just return 2 if dsc_split 1 otherwise.
Thanks & Regards,
Ankit
>
> With that clarified,
>
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
>> intel_dp_mode_to_fec_clock(mode_clock);
>>
>> bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
>> --
>> 2.40.1
>>
^ permalink raw reply [flat|nested] 72+ messages in thread* Re: [PATCH 05/19] drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp
@ 2023-07-24 12:19 ` Nautiyal, Ankit K
0 siblings, 0 replies; 72+ messages in thread
From: Nautiyal, Ankit K @ 2023-07-24 12:19 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx, anusha.srivatsa, dri-devel, navaremanasi
Hi Stan,
Thanks for the reviews ans suggestions. Please my response inline:
On 7/20/2023 2:59 PM, Lisovskiy, Stanislav wrote:
> On Thu, Jul 13, 2023 at 04:03:32PM +0530, Ankit Nautiyal wrote:
>> In Bigjoiner check for DSC, bigjoiner interface bits for DP for
>> DISPLAY > 13 is 36 (Bspec: 49259).
>>
>> v2: Corrected Display ver to 13.
>>
>> v3: Follow convention for conditional statement. (Ville)
>>
>> v4: Fix check for display ver. (Ville)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 19768ac658ba..c1fd448d80e1 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -802,8 +802,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
>> bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
>>
>> if (bigjoiner) {
>> + int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
>> u32 max_bpp_bigjoiner =
>> - i915->display.cdclk.max_cdclk_freq * 48 /
>> + i915->display.cdclk.max_cdclk_freq * 2 * bigjoiner_interface_bits /
> Probably "num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);" again,
> instead of "2"?
Currently intel_dsc_get_num_vdsc_instances will give total number of
vdsc_engines including joined pipes.
So with bigjoiner the function will return 4.
This was good to calculate Pipe BW check: (Pixel clock < PPC * CDCLK
frequency * Number of pipes joined
as we get PPC * number of pipes joined from
intel_dsc_get_num_vdsc_instances)
Or to calculate DSC_PIC_WIDTH PPS parameter.
But here we perhaps need intel_dsc_get_vdsc_engines_per_pipe that will
just return 2 if dsc_split 1 otherwise.
Thanks & Regards,
Ankit
>
> With that clarified,
>
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
>> intel_dp_mode_to_fec_clock(mode_clock);
>>
>> bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
>> --
>> 2.40.1
>>
^ permalink raw reply [flat|nested] 72+ messages in thread* Re: [Intel-gfx] [PATCH 05/19] drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp
2023-07-24 12:19 ` Nautiyal, Ankit K
@ 2023-07-25 10:13 ` Lisovskiy, Stanislav
-1 siblings, 0 replies; 72+ messages in thread
From: Lisovskiy, Stanislav @ 2023-07-25 10:13 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-gfx, dri-devel
On Mon, Jul 24, 2023 at 05:49:11PM +0530, Nautiyal, Ankit K wrote:
> Hi Stan,
>
> Thanks for the reviews ans suggestions. Please my response inline:
>
>
> On 7/20/2023 2:59 PM, Lisovskiy, Stanislav wrote:
> > On Thu, Jul 13, 2023 at 04:03:32PM +0530, Ankit Nautiyal wrote:
> > > In Bigjoiner check for DSC, bigjoiner interface bits for DP for
> > > DISPLAY > 13 is 36 (Bspec: 49259).
> > >
> > > v2: Corrected Display ver to 13.
> > >
> > > v3: Follow convention for conditional statement. (Ville)
> > >
> > > v4: Fix check for display ver. (Ville)
> > >
> > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
> > > 1 file changed, 2 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 19768ac658ba..c1fd448d80e1 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -802,8 +802,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
> > > bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
> > > if (bigjoiner) {
> > > + int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
> > > u32 max_bpp_bigjoiner =
> > > - i915->display.cdclk.max_cdclk_freq * 48 /
> > > + i915->display.cdclk.max_cdclk_freq * 2 * bigjoiner_interface_bits /
> > Probably "num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);" again,
> > instead of "2"?
>
> Currently intel_dsc_get_num_vdsc_instances will give total number of
> vdsc_engines including joined pipes.
>
> So with bigjoiner the function will return 4.
>
> This was good to calculate Pipe BW check: (Pixel clock < PPC * CDCLK
> frequency * Number of pipes joined
>
> as we get PPC * number of pipes joined from
> intel_dsc_get_num_vdsc_instances)
>
> Or to calculate DSC_PIC_WIDTH PPS parameter.
>
> But here we perhaps need intel_dsc_get_vdsc_engines_per_pipe that will just
> return 2 if dsc_split 1 otherwise.
>
> Thanks & Regards,
>
> Ankit
Yes, I agree, unfortunately not applicable here.
May be yeah we need some function like that and then refactor
also the intel_dsc_get_num_vdsc_instances to use that one..
Stan
>
> >
> > With that clarified,
> >
> > Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> >
> > > intel_dp_mode_to_fec_clock(mode_clock);
> > > bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
> > > --
> > > 2.40.1
> > >
^ permalink raw reply [flat|nested] 72+ messages in thread* Re: [PATCH 05/19] drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp
@ 2023-07-25 10:13 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 72+ messages in thread
From: Lisovskiy, Stanislav @ 2023-07-25 10:13 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-gfx, anusha.srivatsa, dri-devel, navaremanasi
On Mon, Jul 24, 2023 at 05:49:11PM +0530, Nautiyal, Ankit K wrote:
> Hi Stan,
>
> Thanks for the reviews ans suggestions. Please my response inline:
>
>
> On 7/20/2023 2:59 PM, Lisovskiy, Stanislav wrote:
> > On Thu, Jul 13, 2023 at 04:03:32PM +0530, Ankit Nautiyal wrote:
> > > In Bigjoiner check for DSC, bigjoiner interface bits for DP for
> > > DISPLAY > 13 is 36 (Bspec: 49259).
> > >
> > > v2: Corrected Display ver to 13.
> > >
> > > v3: Follow convention for conditional statement. (Ville)
> > >
> > > v4: Fix check for display ver. (Ville)
> > >
> > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
> > > 1 file changed, 2 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 19768ac658ba..c1fd448d80e1 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -802,8 +802,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
> > > bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
> > > if (bigjoiner) {
> > > + int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
> > > u32 max_bpp_bigjoiner =
> > > - i915->display.cdclk.max_cdclk_freq * 48 /
> > > + i915->display.cdclk.max_cdclk_freq * 2 * bigjoiner_interface_bits /
> > Probably "num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);" again,
> > instead of "2"?
>
> Currently intel_dsc_get_num_vdsc_instances will give total number of
> vdsc_engines including joined pipes.
>
> So with bigjoiner the function will return 4.
>
> This was good to calculate Pipe BW check: (Pixel clock < PPC * CDCLK
> frequency * Number of pipes joined
>
> as we get PPC * number of pipes joined from
> intel_dsc_get_num_vdsc_instances)
>
> Or to calculate DSC_PIC_WIDTH PPS parameter.
>
> But here we perhaps need intel_dsc_get_vdsc_engines_per_pipe that will just
> return 2 if dsc_split 1 otherwise.
>
> Thanks & Regards,
>
> Ankit
Yes, I agree, unfortunately not applicable here.
May be yeah we need some function like that and then refactor
also the intel_dsc_get_num_vdsc_instances to use that one..
Stan
>
> >
> > With that clarified,
> >
> > Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> >
> > > intel_dp_mode_to_fec_clock(mode_clock);
> > > bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
> > > --
> > > 2.40.1
> > >
^ permalink raw reply [flat|nested] 72+ messages in thread* Re: [Intel-gfx] [PATCH 05/19] drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp
2023-07-25 10:13 ` Lisovskiy, Stanislav
@ 2023-07-25 11:19 ` Nautiyal, Ankit K
-1 siblings, 0 replies; 72+ messages in thread
From: Nautiyal, Ankit K @ 2023-07-25 11:19 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx, dri-devel
On 7/25/2023 3:43 PM, Lisovskiy, Stanislav wrote:
> On Mon, Jul 24, 2023 at 05:49:11PM +0530, Nautiyal, Ankit K wrote:
>> Hi Stan,
>>
>> Thanks for the reviews ans suggestions. Please my response inline:
>>
>>
>> On 7/20/2023 2:59 PM, Lisovskiy, Stanislav wrote:
>>> On Thu, Jul 13, 2023 at 04:03:32PM +0530, Ankit Nautiyal wrote:
>>>> In Bigjoiner check for DSC, bigjoiner interface bits for DP for
>>>> DISPLAY > 13 is 36 (Bspec: 49259).
>>>>
>>>> v2: Corrected Display ver to 13.
>>>>
>>>> v3: Follow convention for conditional statement. (Ville)
>>>>
>>>> v4: Fix check for display ver. (Ville)
>>>>
>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
>>>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> index 19768ac658ba..c1fd448d80e1 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> @@ -802,8 +802,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
>>>> bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
>>>> if (bigjoiner) {
>>>> + int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
>>>> u32 max_bpp_bigjoiner =
>>>> - i915->display.cdclk.max_cdclk_freq * 48 /
>>>> + i915->display.cdclk.max_cdclk_freq * 2 * bigjoiner_interface_bits /
>>> Probably "num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);" again,
>>> instead of "2"?
>> Currently intel_dsc_get_num_vdsc_instances will give total number of
>> vdsc_engines including joined pipes.
>>
>> So with bigjoiner the function will return 4.
>>
>> This was good to calculate Pipe BW check: (Pixel clock < PPC * CDCLK
>> frequency * Number of pipes joined
>>
>> as we get PPC * number of pipes joined from
>> intel_dsc_get_num_vdsc_instances)
>>
>> Or to calculate DSC_PIC_WIDTH PPS parameter.
>>
>> But here we perhaps need intel_dsc_get_vdsc_engines_per_pipe that will just
>> return 2 if dsc_split 1 otherwise.
>>
>> Thanks & Regards,
>>
>> Ankit
> Yes, I agree, unfortunately not applicable here.
> May be yeah we need some function like that and then refactor
> also the intel_dsc_get_num_vdsc_instances to use that one..
>
> Stan
Alright, let me make the change in a separate patch and add to this series.
Thanks & Regards,
Ankit
>
>>> With that clarified,
>>>
>>> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>>>
>>>> intel_dp_mode_to_fec_clock(mode_clock);
>>>> bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
>>>> --
>>>> 2.40.1
>>>>
^ permalink raw reply [flat|nested] 72+ messages in thread* Re: [PATCH 05/19] drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp
@ 2023-07-25 11:19 ` Nautiyal, Ankit K
0 siblings, 0 replies; 72+ messages in thread
From: Nautiyal, Ankit K @ 2023-07-25 11:19 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx, anusha.srivatsa, dri-devel, navaremanasi
On 7/25/2023 3:43 PM, Lisovskiy, Stanislav wrote:
> On Mon, Jul 24, 2023 at 05:49:11PM +0530, Nautiyal, Ankit K wrote:
>> Hi Stan,
>>
>> Thanks for the reviews ans suggestions. Please my response inline:
>>
>>
>> On 7/20/2023 2:59 PM, Lisovskiy, Stanislav wrote:
>>> On Thu, Jul 13, 2023 at 04:03:32PM +0530, Ankit Nautiyal wrote:
>>>> In Bigjoiner check for DSC, bigjoiner interface bits for DP for
>>>> DISPLAY > 13 is 36 (Bspec: 49259).
>>>>
>>>> v2: Corrected Display ver to 13.
>>>>
>>>> v3: Follow convention for conditional statement. (Ville)
>>>>
>>>> v4: Fix check for display ver. (Ville)
>>>>
>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
>>>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> index 19768ac658ba..c1fd448d80e1 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> @@ -802,8 +802,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
>>>> bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
>>>> if (bigjoiner) {
>>>> + int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
>>>> u32 max_bpp_bigjoiner =
>>>> - i915->display.cdclk.max_cdclk_freq * 48 /
>>>> + i915->display.cdclk.max_cdclk_freq * 2 * bigjoiner_interface_bits /
>>> Probably "num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);" again,
>>> instead of "2"?
>> Currently intel_dsc_get_num_vdsc_instances will give total number of
>> vdsc_engines including joined pipes.
>>
>> So with bigjoiner the function will return 4.
>>
>> This was good to calculate Pipe BW check: (Pixel clock < PPC * CDCLK
>> frequency * Number of pipes joined
>>
>> as we get PPC * number of pipes joined from
>> intel_dsc_get_num_vdsc_instances)
>>
>> Or to calculate DSC_PIC_WIDTH PPS parameter.
>>
>> But here we perhaps need intel_dsc_get_vdsc_engines_per_pipe that will just
>> return 2 if dsc_split 1 otherwise.
>>
>> Thanks & Regards,
>>
>> Ankit
> Yes, I agree, unfortunately not applicable here.
> May be yeah we need some function like that and then refactor
> also the intel_dsc_get_num_vdsc_instances to use that one..
>
> Stan
Alright, let me make the change in a separate patch and add to this series.
Thanks & Regards,
Ankit
>
>>> With that clarified,
>>>
>>> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>>>
>>>> intel_dp_mode_to_fec_clock(mode_clock);
>>>> bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
>>>> --
>>>> 2.40.1
>>>>
^ permalink raw reply [flat|nested] 72+ messages in thread* Re: [Intel-gfx] [PATCH 05/19] drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp
2023-07-25 11:19 ` Nautiyal, Ankit K
@ 2023-07-28 4:18 ` Nautiyal, Ankit K
-1 siblings, 0 replies; 72+ messages in thread
From: Nautiyal, Ankit K @ 2023-07-28 4:18 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx, dri-devel
On 7/25/2023 4:49 PM, Nautiyal, Ankit K wrote:
>
> On 7/25/2023 3:43 PM, Lisovskiy, Stanislav wrote:
>> On Mon, Jul 24, 2023 at 05:49:11PM +0530, Nautiyal, Ankit K wrote:
>>> Hi Stan,
>>>
>>> Thanks for the reviews ans suggestions. Please my response inline:
>>>
>>>
>>> On 7/20/2023 2:59 PM, Lisovskiy, Stanislav wrote:
>>>> On Thu, Jul 13, 2023 at 04:03:32PM +0530, Ankit Nautiyal wrote:
>>>>> In Bigjoiner check for DSC, bigjoiner interface bits for DP for
>>>>> DISPLAY > 13 is 36 (Bspec: 49259).
>>>>>
>>>>> v2: Corrected Display ver to 13.
>>>>>
>>>>> v3: Follow convention for conditional statement. (Ville)
>>>>>
>>>>> v4: Fix check for display ver. (Ville)
>>>>>
>>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>>> ---
>>>>> drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
>>>>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>>>>> b/drivers/gpu/drm/i915/display/intel_dp.c
>>>>> index 19768ac658ba..c1fd448d80e1 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>>>> @@ -802,8 +802,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct
>>>>> drm_i915_private *i915,
>>>>> bits_per_pixel = min(bits_per_pixel,
>>>>> max_bpp_small_joiner_ram);
>>>>> if (bigjoiner) {
>>>>> + int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ?
>>>>> 36 : 24;
>>>>> u32 max_bpp_bigjoiner =
>>>>> - i915->display.cdclk.max_cdclk_freq * 48 /
>>>>> + i915->display.cdclk.max_cdclk_freq * 2 *
>>>>> bigjoiner_interface_bits /
>>>> Probably "num_vdsc_instances =
>>>> intel_dsc_get_num_vdsc_instances(crtc_state);" again,
>>>> instead of "2"?
>>> Currently intel_dsc_get_num_vdsc_instances will give total number of
>>> vdsc_engines including joined pipes.
>>>
>>> So with bigjoiner the function will return 4.
>>>
>>> This was good to calculate Pipe BW check: (Pixel clock < PPC * CDCLK
>>> frequency * Number of pipes joined
>>>
>>> as we get PPC * number of pipes joined from
>>> intel_dsc_get_num_vdsc_instances)
>>>
>>> Or to calculate DSC_PIC_WIDTH PPS parameter.
>>>
>>> But here we perhaps need intel_dsc_get_vdsc_engines_per_pipe that
>>> will just
>>> return 2 if dsc_split 1 otherwise.
>>>
>>> Thanks & Regards,
>>>
>>> Ankit
>> Yes, I agree, unfortunately not applicable here.
>> May be yeah we need some function like that and then refactor
>> also the intel_dsc_get_num_vdsc_instances to use that one..
>>
>> Stan
>
> Alright, let me make the change in a separate patch and add to this
> series.
>
> Thanks & Regards,
>
> Ankit
>
>
Since we call this function during mode valid too, so cannot directly
use intel_dsc_get_num_vdsc_instance,
so I have put a comment for clarification about PPC in the latest version.
Regard,
Ankit
>>
>>>> With that clarified,
>>>>
>>>> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>>>>
>>>>> intel_dp_mode_to_fec_clock(mode_clock);
>>>>> bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
>>>>> --
>>>>> 2.40.1
>>>>>
^ permalink raw reply [flat|nested] 72+ messages in thread* Re: [PATCH 05/19] drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp
@ 2023-07-28 4:18 ` Nautiyal, Ankit K
0 siblings, 0 replies; 72+ messages in thread
From: Nautiyal, Ankit K @ 2023-07-28 4:18 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx, anusha.srivatsa, navaremanasi, dri-devel
On 7/25/2023 4:49 PM, Nautiyal, Ankit K wrote:
>
> On 7/25/2023 3:43 PM, Lisovskiy, Stanislav wrote:
>> On Mon, Jul 24, 2023 at 05:49:11PM +0530, Nautiyal, Ankit K wrote:
>>> Hi Stan,
>>>
>>> Thanks for the reviews ans suggestions. Please my response inline:
>>>
>>>
>>> On 7/20/2023 2:59 PM, Lisovskiy, Stanislav wrote:
>>>> On Thu, Jul 13, 2023 at 04:03:32PM +0530, Ankit Nautiyal wrote:
>>>>> In Bigjoiner check for DSC, bigjoiner interface bits for DP for
>>>>> DISPLAY > 13 is 36 (Bspec: 49259).
>>>>>
>>>>> v2: Corrected Display ver to 13.
>>>>>
>>>>> v3: Follow convention for conditional statement. (Ville)
>>>>>
>>>>> v4: Fix check for display ver. (Ville)
>>>>>
>>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>>> ---
>>>>> drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
>>>>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>>>>> b/drivers/gpu/drm/i915/display/intel_dp.c
>>>>> index 19768ac658ba..c1fd448d80e1 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>>>> @@ -802,8 +802,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct
>>>>> drm_i915_private *i915,
>>>>> bits_per_pixel = min(bits_per_pixel,
>>>>> max_bpp_small_joiner_ram);
>>>>> if (bigjoiner) {
>>>>> + int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ?
>>>>> 36 : 24;
>>>>> u32 max_bpp_bigjoiner =
>>>>> - i915->display.cdclk.max_cdclk_freq * 48 /
>>>>> + i915->display.cdclk.max_cdclk_freq * 2 *
>>>>> bigjoiner_interface_bits /
>>>> Probably "num_vdsc_instances =
>>>> intel_dsc_get_num_vdsc_instances(crtc_state);" again,
>>>> instead of "2"?
>>> Currently intel_dsc_get_num_vdsc_instances will give total number of
>>> vdsc_engines including joined pipes.
>>>
>>> So with bigjoiner the function will return 4.
>>>
>>> This was good to calculate Pipe BW check: (Pixel clock < PPC * CDCLK
>>> frequency * Number of pipes joined
>>>
>>> as we get PPC * number of pipes joined from
>>> intel_dsc_get_num_vdsc_instances)
>>>
>>> Or to calculate DSC_PIC_WIDTH PPS parameter.
>>>
>>> But here we perhaps need intel_dsc_get_vdsc_engines_per_pipe that
>>> will just
>>> return 2 if dsc_split 1 otherwise.
>>>
>>> Thanks & Regards,
>>>
>>> Ankit
>> Yes, I agree, unfortunately not applicable here.
>> May be yeah we need some function like that and then refactor
>> also the intel_dsc_get_num_vdsc_instances to use that one..
>>
>> Stan
>
> Alright, let me make the change in a separate patch and add to this
> series.
>
> Thanks & Regards,
>
> Ankit
>
>
Since we call this function during mode valid too, so cannot directly
use intel_dsc_get_num_vdsc_instance,
so I have put a comment for clarification about PPC in the latest version.
Regard,
Ankit
>>
>>>> With that clarified,
>>>>
>>>> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>>>>
>>>>> intel_dp_mode_to_fec_clock(mode_clock);
>>>>> bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
>>>>> --
>>>>> 2.40.1
>>>>>
^ permalink raw reply [flat|nested] 72+ messages in thread
* [Intel-gfx] [PATCH 06/19] drm/i915/display: Account for DSC not split case while computing cdclk
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-13 10:33 ` Ankit Nautiyal
-1 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel
Currently we assume 2 Pixels Per Clock (PPC) while computing
plane cdclk and min_cdlck. In cases where DSC single engine
is used the throughput is 1 PPC.
So account for the above case, while computing cdclk.
v2: Use helper to get the adjusted pixel rate.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 12 ++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.h | 2 ++
drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
4 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index dcc1f6941b60..701909966545 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2508,7 +2508,7 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
int pixel_rate = crtc_state->pixel_rate;
if (DISPLAY_VER(dev_priv) >= 10)
- return DIV_ROUND_UP(pixel_rate, 2);
+ return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
else if (DISPLAY_VER(dev_priv) == 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
return pixel_rate;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 9d76c2756784..bbfdbf06da68 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -1038,3 +1038,15 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
out:
intel_display_power_put(dev_priv, power_domain, wakeref);
}
+
+int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate)
+{
+ /*
+ * If single VDSC engine is used, it uses one pixel per clock
+ * otherwise we use two pixels per clock.
+ */
+ if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split)
+ return pixel_rate;
+
+ return DIV_ROUND_UP(pixel_rate, 2);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index 2cc41ff08909..3bb4b1980b6b 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -28,4 +28,6 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
+int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate);
+
#endif /* __INTEL_VDSC_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 6b01a0b68b97..9eeb25ec4be9 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -17,6 +17,7 @@
#include "intel_fb.h"
#include "intel_fbc.h"
#include "intel_psr.h"
+#include "intel_vdsc.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
#include "skl_watermark.h"
@@ -263,8 +264,7 @@ static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
{
unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
- /* two pixels per clock */
- return DIV_ROUND_UP(pixel_rate, 2);
+ return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
}
static void
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH 06/19] drm/i915/display: Account for DSC not split case while computing cdclk
@ 2023-07-13 10:33 ` Ankit Nautiyal
0 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
Currently we assume 2 Pixels Per Clock (PPC) while computing
plane cdclk and min_cdlck. In cases where DSC single engine
is used the throughput is 1 PPC.
So account for the above case, while computing cdclk.
v2: Use helper to get the adjusted pixel rate.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 12 ++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.h | 2 ++
drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
4 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index dcc1f6941b60..701909966545 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2508,7 +2508,7 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
int pixel_rate = crtc_state->pixel_rate;
if (DISPLAY_VER(dev_priv) >= 10)
- return DIV_ROUND_UP(pixel_rate, 2);
+ return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
else if (DISPLAY_VER(dev_priv) == 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
return pixel_rate;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 9d76c2756784..bbfdbf06da68 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -1038,3 +1038,15 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
out:
intel_display_power_put(dev_priv, power_domain, wakeref);
}
+
+int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate)
+{
+ /*
+ * If single VDSC engine is used, it uses one pixel per clock
+ * otherwise we use two pixels per clock.
+ */
+ if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split)
+ return pixel_rate;
+
+ return DIV_ROUND_UP(pixel_rate, 2);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index 2cc41ff08909..3bb4b1980b6b 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -28,4 +28,6 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
+int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate);
+
#endif /* __INTEL_VDSC_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 6b01a0b68b97..9eeb25ec4be9 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -17,6 +17,7 @@
#include "intel_fb.h"
#include "intel_fbc.h"
#include "intel_psr.h"
+#include "intel_vdsc.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
#include "skl_watermark.h"
@@ -263,8 +264,7 @@ static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
{
unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
- /* two pixels per clock */
- return DIV_ROUND_UP(pixel_rate, 2);
+ return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
}
static void
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* Re: [Intel-gfx] [PATCH 06/19] drm/i915/display: Account for DSC not split case while computing cdclk
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-20 9:16 ` Lisovskiy, Stanislav
-1 siblings, 0 replies; 72+ messages in thread
From: Lisovskiy, Stanislav @ 2023-07-20 9:16 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, dri-devel
On Thu, Jul 13, 2023 at 04:03:33PM +0530, Ankit Nautiyal wrote:
> Currently we assume 2 Pixels Per Clock (PPC) while computing
> plane cdclk and min_cdlck. In cases where DSC single engine
> is used the throughput is 1 PPC.
>
> So account for the above case, while computing cdclk.
>
> v2: Use helper to get the adjusted pixel rate.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
> drivers/gpu/drm/i915/display/intel_vdsc.c | 12 ++++++++++++
> drivers/gpu/drm/i915/display/intel_vdsc.h | 2 ++
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
> 4 files changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index dcc1f6941b60..701909966545 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2508,7 +2508,7 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
> int pixel_rate = crtc_state->pixel_rate;
>
> if (DISPLAY_VER(dev_priv) >= 10)
> - return DIV_ROUND_UP(pixel_rate, 2);
> + return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
> else if (DISPLAY_VER(dev_priv) == 9 ||
> IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> return pixel_rate;
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 9d76c2756784..bbfdbf06da68 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -1038,3 +1038,15 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
> out:
> intel_display_power_put(dev_priv, power_domain, wakeref);
> }
> +
> +int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate)
> +{
> + /*
> + * If single VDSC engine is used, it uses one pixel per clock
> + * otherwise we use two pixels per clock.
> + */
> + if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split)
> + return pixel_rate;
> +
> + return DIV_ROUND_UP(pixel_rate, 2);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
> index 2cc41ff08909..3bb4b1980b6b 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> @@ -28,4 +28,6 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
> void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
>
> +int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate);
> +
> #endif /* __INTEL_VDSC_H__ */
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 6b01a0b68b97..9eeb25ec4be9 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -17,6 +17,7 @@
> #include "intel_fb.h"
> #include "intel_fbc.h"
> #include "intel_psr.h"
> +#include "intel_vdsc.h"
> #include "skl_scaler.h"
> #include "skl_universal_plane.h"
> #include "skl_watermark.h"
> @@ -263,8 +264,7 @@ static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
> {
> unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
>
> - /* two pixels per clock */
> - return DIV_ROUND_UP(pixel_rate, 2);
> + return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
Hi Ankit,
I think the thing what you are taking of is already handled here in intel_cdclk.c:
/*
* When we decide to use only one VDSC engine, since
* each VDSC operates with 1 ppc throughput, pixel clock
* cannot be higher than the VDSC clock (cdclk)
* If there 2 VDSC engines, then pixel clock can't be higher than
* VDSC clock(cdclk) * 2 and so on.
*/
if (crtc_state->dsc.compression_enable) {
int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
min_cdclk = max_t(int, min_cdclk,
DIV_ROUND_UP(crtc_state->pixel_rate,
num_vdsc_instances));
}
Also even if something still have to be done here, I think we should preferrably
deal with anything related to DSC in a single place, to prevent any kind of
confusion(when those checks are scattered in different places, it is way more easy to forget/not notice something)
I think intel_pixel_rate_to_cdclk isn't supposed to know anything about DSC or any other specifics like audio checks and etc - it is
just dealing with the "default" uncompressed case.
Any other additional limitations or checks we apply after those, as there are
quite many anyway.
Stan
> }
>
> static void
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 72+ messages in thread* Re: [PATCH 06/19] drm/i915/display: Account for DSC not split case while computing cdclk
@ 2023-07-20 9:16 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 72+ messages in thread
From: Lisovskiy, Stanislav @ 2023-07-20 9:16 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, anusha.srivatsa, dri-devel, navaremanasi
On Thu, Jul 13, 2023 at 04:03:33PM +0530, Ankit Nautiyal wrote:
> Currently we assume 2 Pixels Per Clock (PPC) while computing
> plane cdclk and min_cdlck. In cases where DSC single engine
> is used the throughput is 1 PPC.
>
> So account for the above case, while computing cdclk.
>
> v2: Use helper to get the adjusted pixel rate.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
> drivers/gpu/drm/i915/display/intel_vdsc.c | 12 ++++++++++++
> drivers/gpu/drm/i915/display/intel_vdsc.h | 2 ++
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
> 4 files changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index dcc1f6941b60..701909966545 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2508,7 +2508,7 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
> int pixel_rate = crtc_state->pixel_rate;
>
> if (DISPLAY_VER(dev_priv) >= 10)
> - return DIV_ROUND_UP(pixel_rate, 2);
> + return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
> else if (DISPLAY_VER(dev_priv) == 9 ||
> IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> return pixel_rate;
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 9d76c2756784..bbfdbf06da68 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -1038,3 +1038,15 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
> out:
> intel_display_power_put(dev_priv, power_domain, wakeref);
> }
> +
> +int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate)
> +{
> + /*
> + * If single VDSC engine is used, it uses one pixel per clock
> + * otherwise we use two pixels per clock.
> + */
> + if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split)
> + return pixel_rate;
> +
> + return DIV_ROUND_UP(pixel_rate, 2);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
> index 2cc41ff08909..3bb4b1980b6b 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> @@ -28,4 +28,6 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
> void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
>
> +int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate);
> +
> #endif /* __INTEL_VDSC_H__ */
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 6b01a0b68b97..9eeb25ec4be9 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -17,6 +17,7 @@
> #include "intel_fb.h"
> #include "intel_fbc.h"
> #include "intel_psr.h"
> +#include "intel_vdsc.h"
> #include "skl_scaler.h"
> #include "skl_universal_plane.h"
> #include "skl_watermark.h"
> @@ -263,8 +264,7 @@ static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
> {
> unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
>
> - /* two pixels per clock */
> - return DIV_ROUND_UP(pixel_rate, 2);
> + return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
Hi Ankit,
I think the thing what you are taking of is already handled here in intel_cdclk.c:
/*
* When we decide to use only one VDSC engine, since
* each VDSC operates with 1 ppc throughput, pixel clock
* cannot be higher than the VDSC clock (cdclk)
* If there 2 VDSC engines, then pixel clock can't be higher than
* VDSC clock(cdclk) * 2 and so on.
*/
if (crtc_state->dsc.compression_enable) {
int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
min_cdclk = max_t(int, min_cdclk,
DIV_ROUND_UP(crtc_state->pixel_rate,
num_vdsc_instances));
}
Also even if something still have to be done here, I think we should preferrably
deal with anything related to DSC in a single place, to prevent any kind of
confusion(when those checks are scattered in different places, it is way more easy to forget/not notice something)
I think intel_pixel_rate_to_cdclk isn't supposed to know anything about DSC or any other specifics like audio checks and etc - it is
just dealing with the "default" uncompressed case.
Any other additional limitations or checks we apply after those, as there are
quite many anyway.
Stan
> }
>
> static void
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 72+ messages in thread* Re: [Intel-gfx] [PATCH 06/19] drm/i915/display: Account for DSC not split case while computing cdclk
2023-07-20 9:16 ` Lisovskiy, Stanislav
@ 2023-07-25 5:52 ` Nautiyal, Ankit K
-1 siblings, 0 replies; 72+ messages in thread
From: Nautiyal, Ankit K @ 2023-07-25 5:52 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx, dri-devel
On 7/20/2023 2:46 PM, Lisovskiy, Stanislav wrote:
> On Thu, Jul 13, 2023 at 04:03:33PM +0530, Ankit Nautiyal wrote:
>> Currently we assume 2 Pixels Per Clock (PPC) while computing
>> plane cdclk and min_cdlck. In cases where DSC single engine
>> is used the throughput is 1 PPC.
>>
>> So account for the above case, while computing cdclk.
>>
>> v2: Use helper to get the adjusted pixel rate.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
>> drivers/gpu/drm/i915/display/intel_vdsc.c | 12 ++++++++++++
>> drivers/gpu/drm/i915/display/intel_vdsc.h | 2 ++
>> drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
>> 4 files changed, 17 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index dcc1f6941b60..701909966545 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -2508,7 +2508,7 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
>> int pixel_rate = crtc_state->pixel_rate;
>>
>> if (DISPLAY_VER(dev_priv) >= 10)
>> - return DIV_ROUND_UP(pixel_rate, 2);
>> + return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
>> else if (DISPLAY_VER(dev_priv) == 9 ||
>> IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
>> return pixel_rate;
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> index 9d76c2756784..bbfdbf06da68 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> @@ -1038,3 +1038,15 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
>> out:
>> intel_display_power_put(dev_priv, power_domain, wakeref);
>> }
>> +
>> +int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate)
>> +{
>> + /*
>> + * If single VDSC engine is used, it uses one pixel per clock
>> + * otherwise we use two pixels per clock.
>> + */
>> + if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split)
>> + return pixel_rate;
>> +
>> + return DIV_ROUND_UP(pixel_rate, 2);
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
>> index 2cc41ff08909..3bb4b1980b6b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
>> @@ -28,4 +28,6 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
>> void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
>> const struct intel_crtc_state *crtc_state);
>>
>> +int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate);
>> +
>> #endif /* __INTEL_VDSC_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> index 6b01a0b68b97..9eeb25ec4be9 100644
>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> @@ -17,6 +17,7 @@
>> #include "intel_fb.h"
>> #include "intel_fbc.h"
>> #include "intel_psr.h"
>> +#include "intel_vdsc.h"
>> #include "skl_scaler.h"
>> #include "skl_universal_plane.h"
>> #include "skl_watermark.h"
>> @@ -263,8 +264,7 @@ static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
>> {
>> unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
>>
>> - /* two pixels per clock */
>> - return DIV_ROUND_UP(pixel_rate, 2);
>> + return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
> Hi Ankit,
>
> I think the thing what you are taking of is already handled here in intel_cdclk.c:
>
> /*
> * When we decide to use only one VDSC engine, since
> * each VDSC operates with 1 ppc throughput, pixel clock
> * cannot be higher than the VDSC clock (cdclk)
> * If there 2 VDSC engines, then pixel clock can't be higher than
> * VDSC clock(cdclk) * 2 and so on.
> */
> if (crtc_state->dsc.compression_enable) {
> int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
>
> min_cdclk = max_t(int, min_cdclk,
> DIV_ROUND_UP(crtc_state->pixel_rate,
> num_vdsc_instances));
> }
As far as I understand this condition is coming from the pixel clock
limitation as an input to the splitter (Bspec: 49259):
Pipe BW check:
Pixel clock < PPC * CDCLK frequency * Number of pipes joined
PPC = 1 or 2 depending on number of DSC engines used within the pipe.
So it implies CDCLK frequency > Pixel clock / (PPC * Number of pipes joined)
num_vdsc_instances is actually giving us (PPC * number of pipes joined).
I completely agree that there will be no effect of the change on the
min_cdclk that gets computed in any case, whether DSC, 1 engine, 2
engine, bigjoiner or no DSC.
Only thing is for the case where 1 DSC engine is used, what
intel_pixel_rate_to_cdclk return will be different, and its due to the
fact that pipe is driven with 1PPC.
But as I said, the min_cdclk computed will be same as without patch. So
we can certainly do away with this change, and I can drop this from the
patch.
But in case of icl_plane_min_cdclk, currently we are dividing the
plane_pixel_rate by 2, citing that we use 2 pixel per clock, to get the
plane_min_cdclk.
Should this not be 1 PPC in case where single DSC engine is used? In
that case plane_min_cdclk will be double. Should we keep the change only
for plane_min_cdclk then?
Regards,
Ankit
>
> Also even if something still have to be done here, I think we should preferrably
> deal with anything related to DSC in a single place, to prevent any kind of
> confusion(when those checks are scattered in different places, it is way more easy to forget/not notice something)
>
> I think intel_pixel_rate_to_cdclk isn't supposed to know anything about DSC or any other specifics like audio checks and etc - it is
> just dealing with the "default" uncompressed case.
> Any other additional limitations or checks we apply after those, as there are
> quite many anyway.
>
> Stan
>
>
>> }
>>
>> static void
>> --
>> 2.40.1
>>
^ permalink raw reply [flat|nested] 72+ messages in thread* Re: [PATCH 06/19] drm/i915/display: Account for DSC not split case while computing cdclk
@ 2023-07-25 5:52 ` Nautiyal, Ankit K
0 siblings, 0 replies; 72+ messages in thread
From: Nautiyal, Ankit K @ 2023-07-25 5:52 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx, anusha.srivatsa, dri-devel, navaremanasi
On 7/20/2023 2:46 PM, Lisovskiy, Stanislav wrote:
> On Thu, Jul 13, 2023 at 04:03:33PM +0530, Ankit Nautiyal wrote:
>> Currently we assume 2 Pixels Per Clock (PPC) while computing
>> plane cdclk and min_cdlck. In cases where DSC single engine
>> is used the throughput is 1 PPC.
>>
>> So account for the above case, while computing cdclk.
>>
>> v2: Use helper to get the adjusted pixel rate.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
>> drivers/gpu/drm/i915/display/intel_vdsc.c | 12 ++++++++++++
>> drivers/gpu/drm/i915/display/intel_vdsc.h | 2 ++
>> drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
>> 4 files changed, 17 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index dcc1f6941b60..701909966545 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -2508,7 +2508,7 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
>> int pixel_rate = crtc_state->pixel_rate;
>>
>> if (DISPLAY_VER(dev_priv) >= 10)
>> - return DIV_ROUND_UP(pixel_rate, 2);
>> + return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
>> else if (DISPLAY_VER(dev_priv) == 9 ||
>> IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
>> return pixel_rate;
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> index 9d76c2756784..bbfdbf06da68 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> @@ -1038,3 +1038,15 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
>> out:
>> intel_display_power_put(dev_priv, power_domain, wakeref);
>> }
>> +
>> +int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate)
>> +{
>> + /*
>> + * If single VDSC engine is used, it uses one pixel per clock
>> + * otherwise we use two pixels per clock.
>> + */
>> + if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split)
>> + return pixel_rate;
>> +
>> + return DIV_ROUND_UP(pixel_rate, 2);
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
>> index 2cc41ff08909..3bb4b1980b6b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
>> @@ -28,4 +28,6 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
>> void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
>> const struct intel_crtc_state *crtc_state);
>>
>> +int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate);
>> +
>> #endif /* __INTEL_VDSC_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> index 6b01a0b68b97..9eeb25ec4be9 100644
>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> @@ -17,6 +17,7 @@
>> #include "intel_fb.h"
>> #include "intel_fbc.h"
>> #include "intel_psr.h"
>> +#include "intel_vdsc.h"
>> #include "skl_scaler.h"
>> #include "skl_universal_plane.h"
>> #include "skl_watermark.h"
>> @@ -263,8 +264,7 @@ static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
>> {
>> unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
>>
>> - /* two pixels per clock */
>> - return DIV_ROUND_UP(pixel_rate, 2);
>> + return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
> Hi Ankit,
>
> I think the thing what you are taking of is already handled here in intel_cdclk.c:
>
> /*
> * When we decide to use only one VDSC engine, since
> * each VDSC operates with 1 ppc throughput, pixel clock
> * cannot be higher than the VDSC clock (cdclk)
> * If there 2 VDSC engines, then pixel clock can't be higher than
> * VDSC clock(cdclk) * 2 and so on.
> */
> if (crtc_state->dsc.compression_enable) {
> int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
>
> min_cdclk = max_t(int, min_cdclk,
> DIV_ROUND_UP(crtc_state->pixel_rate,
> num_vdsc_instances));
> }
As far as I understand this condition is coming from the pixel clock
limitation as an input to the splitter (Bspec: 49259):
Pipe BW check:
Pixel clock < PPC * CDCLK frequency * Number of pipes joined
PPC = 1 or 2 depending on number of DSC engines used within the pipe.
So it implies CDCLK frequency > Pixel clock / (PPC * Number of pipes joined)
num_vdsc_instances is actually giving us (PPC * number of pipes joined).
I completely agree that there will be no effect of the change on the
min_cdclk that gets computed in any case, whether DSC, 1 engine, 2
engine, bigjoiner or no DSC.
Only thing is for the case where 1 DSC engine is used, what
intel_pixel_rate_to_cdclk return will be different, and its due to the
fact that pipe is driven with 1PPC.
But as I said, the min_cdclk computed will be same as without patch. So
we can certainly do away with this change, and I can drop this from the
patch.
But in case of icl_plane_min_cdclk, currently we are dividing the
plane_pixel_rate by 2, citing that we use 2 pixel per clock, to get the
plane_min_cdclk.
Should this not be 1 PPC in case where single DSC engine is used? In
that case plane_min_cdclk will be double. Should we keep the change only
for plane_min_cdclk then?
Regards,
Ankit
>
> Also even if something still have to be done here, I think we should preferrably
> deal with anything related to DSC in a single place, to prevent any kind of
> confusion(when those checks are scattered in different places, it is way more easy to forget/not notice something)
>
> I think intel_pixel_rate_to_cdclk isn't supposed to know anything about DSC or any other specifics like audio checks and etc - it is
> just dealing with the "default" uncompressed case.
> Any other additional limitations or checks we apply after those, as there are
> quite many anyway.
>
> Stan
>
>
>> }
>>
>> static void
>> --
>> 2.40.1
>>
^ permalink raw reply [flat|nested] 72+ messages in thread* Re: [Intel-gfx] [PATCH 06/19] drm/i915/display: Account for DSC not split case while computing cdclk
2023-07-25 5:52 ` Nautiyal, Ankit K
@ 2023-07-25 10:10 ` Lisovskiy, Stanislav
-1 siblings, 0 replies; 72+ messages in thread
From: Lisovskiy, Stanislav @ 2023-07-25 10:10 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-gfx, dri-devel
On Tue, Jul 25, 2023 at 11:22:52AM +0530, Nautiyal, Ankit K wrote:
>
> On 7/20/2023 2:46 PM, Lisovskiy, Stanislav wrote:
> > On Thu, Jul 13, 2023 at 04:03:33PM +0530, Ankit Nautiyal wrote:
> > > Currently we assume 2 Pixels Per Clock (PPC) while computing
> > > plane cdclk and min_cdlck. In cases where DSC single engine
> > > is used the throughput is 1 PPC.
> > >
> > > So account for the above case, while computing cdclk.
> > >
> > > v2: Use helper to get the adjusted pixel rate.
> > >
> > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
> > > drivers/gpu/drm/i915/display/intel_vdsc.c | 12 ++++++++++++
> > > drivers/gpu/drm/i915/display/intel_vdsc.h | 2 ++
> > > drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
> > > 4 files changed, 17 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > index dcc1f6941b60..701909966545 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > @@ -2508,7 +2508,7 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
> > > int pixel_rate = crtc_state->pixel_rate;
> > > if (DISPLAY_VER(dev_priv) >= 10)
> > > - return DIV_ROUND_UP(pixel_rate, 2);
> > > + return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
> > > else if (DISPLAY_VER(dev_priv) == 9 ||
> > > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> > > return pixel_rate;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > index 9d76c2756784..bbfdbf06da68 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > @@ -1038,3 +1038,15 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
> > > out:
> > > intel_display_power_put(dev_priv, power_domain, wakeref);
> > > }
> > > +
> > > +int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate)
> > > +{
> > > + /*
> > > + * If single VDSC engine is used, it uses one pixel per clock
> > > + * otherwise we use two pixels per clock.
> > > + */
> > > + if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split)
> > > + return pixel_rate;
> > > +
> > > + return DIV_ROUND_UP(pixel_rate, 2);
> > > +}
> > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
> > > index 2cc41ff08909..3bb4b1980b6b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> > > @@ -28,4 +28,6 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
> > > void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
> > > const struct intel_crtc_state *crtc_state);
> > > +int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate);
> > > +
> > > #endif /* __INTEL_VDSC_H__ */
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > index 6b01a0b68b97..9eeb25ec4be9 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > @@ -17,6 +17,7 @@
> > > #include "intel_fb.h"
> > > #include "intel_fbc.h"
> > > #include "intel_psr.h"
> > > +#include "intel_vdsc.h"
> > > #include "skl_scaler.h"
> > > #include "skl_universal_plane.h"
> > > #include "skl_watermark.h"
> > > @@ -263,8 +264,7 @@ static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
> > > {
> > > unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
> > > - /* two pixels per clock */
> > > - return DIV_ROUND_UP(pixel_rate, 2);
> > > + return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
> > Hi Ankit,
> >
> > I think the thing what you are taking of is already handled here in intel_cdclk.c:
> >
> > /*
> > * When we decide to use only one VDSC engine, since
> > * each VDSC operates with 1 ppc throughput, pixel clock
> > * cannot be higher than the VDSC clock (cdclk)
> > * If there 2 VDSC engines, then pixel clock can't be higher than
> > * VDSC clock(cdclk) * 2 and so on.
> > */
> > if (crtc_state->dsc.compression_enable) {
> > int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
> >
> > min_cdclk = max_t(int, min_cdclk,
> > DIV_ROUND_UP(crtc_state->pixel_rate,
> > num_vdsc_instances));
> > }
>
> As far as I understand this condition is coming from the pixel clock
> limitation as an input to the splitter (Bspec: 49259):
>
> Pipe BW check:
>
> Pixel clock < PPC * CDCLK frequency * Number of pipes joined
>
> PPC = 1 or 2 depending on number of DSC engines used within the pipe.
>
> So it implies CDCLK frequency > Pixel clock / (PPC * Number of pipes joined)
>
> num_vdsc_instances is actually giving us (PPC * number of pipes joined).
>
>
> I completely agree that there will be no effect of the change on the
> min_cdclk that gets computed in any case, whether DSC, 1 engine, 2 engine,
> bigjoiner or no DSC.
>
> Only thing is for the case where 1 DSC engine is used, what
> intel_pixel_rate_to_cdclk return will be different, and its due to the fact
> that pipe is driven with 1PPC.
>
> But as I said, the min_cdclk computed will be same as without patch. So we
> can certainly do away with this change, and I can drop this from the patch.
>
>
> But in case of icl_plane_min_cdclk, currently we are dividing the
> plane_pixel_rate by 2, citing that we use 2 pixel per clock, to get the
> plane_min_cdclk.
>
> Should this not be 1 PPC in case where single DSC engine is used? In that
> case plane_min_cdclk will be double. Should we keep the change only for
> plane_min_cdclk then?
Those are different cases:
1) When we are not using DSC, we are always processing
2 pixels per CDCLK, starting from gen 10. It is reflected in both intel_pixel_rate_to_cdclk
and icl_plane_min_cdclk(which is a bit of a tautology I agree, but anyways we always take
all limitations and use max(worst case) of them)
2) When we are using DSC. In that case we could use 1 or VDSC engines, which would set PPC to
1 or 2 correspondently. So whenever we happen to use DSC that condition will take max of
the CDCLK obtained by other requirements and that formula.
However in non-compressed case when there is no DSC, we should even be insterested in querying
how many VDSC instances we have, amount of pixels processed per CDCLK isn't related to this in
that case.
Stan
>
>
> Regards,
>
> Ankit
>
>
> >
> > Also even if something still have to be done here, I think we should preferrably
> > deal with anything related to DSC in a single place, to prevent any kind of
> > confusion(when those checks are scattered in different places, it is way more easy to forget/not notice something)
> >
> > I think intel_pixel_rate_to_cdclk isn't supposed to know anything about DSC or any other specifics like audio checks and etc - it is
> > just dealing with the "default" uncompressed case.
> > Any other additional limitations or checks we apply after those, as there are
> > quite many anyway.
> >
> > Stan
> >
> >
> > > }
> > > static void
> > > --
> > > 2.40.1
> > >
^ permalink raw reply [flat|nested] 72+ messages in thread* Re: [PATCH 06/19] drm/i915/display: Account for DSC not split case while computing cdclk
@ 2023-07-25 10:10 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 72+ messages in thread
From: Lisovskiy, Stanislav @ 2023-07-25 10:10 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-gfx, anusha.srivatsa, dri-devel, navaremanasi
On Tue, Jul 25, 2023 at 11:22:52AM +0530, Nautiyal, Ankit K wrote:
>
> On 7/20/2023 2:46 PM, Lisovskiy, Stanislav wrote:
> > On Thu, Jul 13, 2023 at 04:03:33PM +0530, Ankit Nautiyal wrote:
> > > Currently we assume 2 Pixels Per Clock (PPC) while computing
> > > plane cdclk and min_cdlck. In cases where DSC single engine
> > > is used the throughput is 1 PPC.
> > >
> > > So account for the above case, while computing cdclk.
> > >
> > > v2: Use helper to get the adjusted pixel rate.
> > >
> > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
> > > drivers/gpu/drm/i915/display/intel_vdsc.c | 12 ++++++++++++
> > > drivers/gpu/drm/i915/display/intel_vdsc.h | 2 ++
> > > drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
> > > 4 files changed, 17 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > index dcc1f6941b60..701909966545 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > @@ -2508,7 +2508,7 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
> > > int pixel_rate = crtc_state->pixel_rate;
> > > if (DISPLAY_VER(dev_priv) >= 10)
> > > - return DIV_ROUND_UP(pixel_rate, 2);
> > > + return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
> > > else if (DISPLAY_VER(dev_priv) == 9 ||
> > > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> > > return pixel_rate;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > index 9d76c2756784..bbfdbf06da68 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > @@ -1038,3 +1038,15 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
> > > out:
> > > intel_display_power_put(dev_priv, power_domain, wakeref);
> > > }
> > > +
> > > +int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate)
> > > +{
> > > + /*
> > > + * If single VDSC engine is used, it uses one pixel per clock
> > > + * otherwise we use two pixels per clock.
> > > + */
> > > + if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split)
> > > + return pixel_rate;
> > > +
> > > + return DIV_ROUND_UP(pixel_rate, 2);
> > > +}
> > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
> > > index 2cc41ff08909..3bb4b1980b6b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> > > @@ -28,4 +28,6 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
> > > void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
> > > const struct intel_crtc_state *crtc_state);
> > > +int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate);
> > > +
> > > #endif /* __INTEL_VDSC_H__ */
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > index 6b01a0b68b97..9eeb25ec4be9 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > @@ -17,6 +17,7 @@
> > > #include "intel_fb.h"
> > > #include "intel_fbc.h"
> > > #include "intel_psr.h"
> > > +#include "intel_vdsc.h"
> > > #include "skl_scaler.h"
> > > #include "skl_universal_plane.h"
> > > #include "skl_watermark.h"
> > > @@ -263,8 +264,7 @@ static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
> > > {
> > > unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
> > > - /* two pixels per clock */
> > > - return DIV_ROUND_UP(pixel_rate, 2);
> > > + return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
> > Hi Ankit,
> >
> > I think the thing what you are taking of is already handled here in intel_cdclk.c:
> >
> > /*
> > * When we decide to use only one VDSC engine, since
> > * each VDSC operates with 1 ppc throughput, pixel clock
> > * cannot be higher than the VDSC clock (cdclk)
> > * If there 2 VDSC engines, then pixel clock can't be higher than
> > * VDSC clock(cdclk) * 2 and so on.
> > */
> > if (crtc_state->dsc.compression_enable) {
> > int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
> >
> > min_cdclk = max_t(int, min_cdclk,
> > DIV_ROUND_UP(crtc_state->pixel_rate,
> > num_vdsc_instances));
> > }
>
> As far as I understand this condition is coming from the pixel clock
> limitation as an input to the splitter (Bspec: 49259):
>
> Pipe BW check:
>
> Pixel clock < PPC * CDCLK frequency * Number of pipes joined
>
> PPC = 1 or 2 depending on number of DSC engines used within the pipe.
>
> So it implies CDCLK frequency > Pixel clock / (PPC * Number of pipes joined)
>
> num_vdsc_instances is actually giving us (PPC * number of pipes joined).
>
>
> I completely agree that there will be no effect of the change on the
> min_cdclk that gets computed in any case, whether DSC, 1 engine, 2 engine,
> bigjoiner or no DSC.
>
> Only thing is for the case where 1 DSC engine is used, what
> intel_pixel_rate_to_cdclk return will be different, and its due to the fact
> that pipe is driven with 1PPC.
>
> But as I said, the min_cdclk computed will be same as without patch. So we
> can certainly do away with this change, and I can drop this from the patch.
>
>
> But in case of icl_plane_min_cdclk, currently we are dividing the
> plane_pixel_rate by 2, citing that we use 2 pixel per clock, to get the
> plane_min_cdclk.
>
> Should this not be 1 PPC in case where single DSC engine is used? In that
> case plane_min_cdclk will be double. Should we keep the change only for
> plane_min_cdclk then?
Those are different cases:
1) When we are not using DSC, we are always processing
2 pixels per CDCLK, starting from gen 10. It is reflected in both intel_pixel_rate_to_cdclk
and icl_plane_min_cdclk(which is a bit of a tautology I agree, but anyways we always take
all limitations and use max(worst case) of them)
2) When we are using DSC. In that case we could use 1 or VDSC engines, which would set PPC to
1 or 2 correspondently. So whenever we happen to use DSC that condition will take max of
the CDCLK obtained by other requirements and that formula.
However in non-compressed case when there is no DSC, we should even be insterested in querying
how many VDSC instances we have, amount of pixels processed per CDCLK isn't related to this in
that case.
Stan
>
>
> Regards,
>
> Ankit
>
>
> >
> > Also even if something still have to be done here, I think we should preferrably
> > deal with anything related to DSC in a single place, to prevent any kind of
> > confusion(when those checks are scattered in different places, it is way more easy to forget/not notice something)
> >
> > I think intel_pixel_rate_to_cdclk isn't supposed to know anything about DSC or any other specifics like audio checks and etc - it is
> > just dealing with the "default" uncompressed case.
> > Any other additional limitations or checks we apply after those, as there are
> > quite many anyway.
> >
> > Stan
> >
> >
> > > }
> > > static void
> > > --
> > > 2.40.1
> > >
^ permalink raw reply [flat|nested] 72+ messages in thread* Re: [Intel-gfx] [PATCH 06/19] drm/i915/display: Account for DSC not split case while computing cdclk
2023-07-25 10:10 ` Lisovskiy, Stanislav
@ 2023-07-25 11:22 ` Nautiyal, Ankit K
-1 siblings, 0 replies; 72+ messages in thread
From: Nautiyal, Ankit K @ 2023-07-25 11:22 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx, dri-devel
On 7/25/2023 3:40 PM, Lisovskiy, Stanislav wrote:
> On Tue, Jul 25, 2023 at 11:22:52AM +0530, Nautiyal, Ankit K wrote:
>> On 7/20/2023 2:46 PM, Lisovskiy, Stanislav wrote:
>>> On Thu, Jul 13, 2023 at 04:03:33PM +0530, Ankit Nautiyal wrote:
>>>> Currently we assume 2 Pixels Per Clock (PPC) while computing
>>>> plane cdclk and min_cdlck. In cases where DSC single engine
>>>> is used the throughput is 1 PPC.
>>>>
>>>> So account for the above case, while computing cdclk.
>>>>
>>>> v2: Use helper to get the adjusted pixel rate.
>>>>
>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
>>>> drivers/gpu/drm/i915/display/intel_vdsc.c | 12 ++++++++++++
>>>> drivers/gpu/drm/i915/display/intel_vdsc.h | 2 ++
>>>> drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
>>>> 4 files changed, 17 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>>>> index dcc1f6941b60..701909966545 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>>>> @@ -2508,7 +2508,7 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
>>>> int pixel_rate = crtc_state->pixel_rate;
>>>> if (DISPLAY_VER(dev_priv) >= 10)
>>>> - return DIV_ROUND_UP(pixel_rate, 2);
>>>> + return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
>>>> else if (DISPLAY_VER(dev_priv) == 9 ||
>>>> IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
>>>> return pixel_rate;
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> index 9d76c2756784..bbfdbf06da68 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> @@ -1038,3 +1038,15 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
>>>> out:
>>>> intel_display_power_put(dev_priv, power_domain, wakeref);
>>>> }
>>>> +
>>>> +int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate)
>>>> +{
>>>> + /*
>>>> + * If single VDSC engine is used, it uses one pixel per clock
>>>> + * otherwise we use two pixels per clock.
>>>> + */
>>>> + if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split)
>>>> + return pixel_rate;
>>>> +
>>>> + return DIV_ROUND_UP(pixel_rate, 2);
>>>> +}
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
>>>> index 2cc41ff08909..3bb4b1980b6b 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
>>>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
>>>> @@ -28,4 +28,6 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
>>>> void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
>>>> const struct intel_crtc_state *crtc_state);
>>>> +int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate);
>>>> +
>>>> #endif /* __INTEL_VDSC_H__ */
>>>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>> index 6b01a0b68b97..9eeb25ec4be9 100644
>>>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>> @@ -17,6 +17,7 @@
>>>> #include "intel_fb.h"
>>>> #include "intel_fbc.h"
>>>> #include "intel_psr.h"
>>>> +#include "intel_vdsc.h"
>>>> #include "skl_scaler.h"
>>>> #include "skl_universal_plane.h"
>>>> #include "skl_watermark.h"
>>>> @@ -263,8 +264,7 @@ static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
>>>> {
>>>> unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
>>>> - /* two pixels per clock */
>>>> - return DIV_ROUND_UP(pixel_rate, 2);
>>>> + return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
>>> Hi Ankit,
>>>
>>> I think the thing what you are taking of is already handled here in intel_cdclk.c:
>>>
>>> /*
>>> * When we decide to use only one VDSC engine, since
>>> * each VDSC operates with 1 ppc throughput, pixel clock
>>> * cannot be higher than the VDSC clock (cdclk)
>>> * If there 2 VDSC engines, then pixel clock can't be higher than
>>> * VDSC clock(cdclk) * 2 and so on.
>>> */
>>> if (crtc_state->dsc.compression_enable) {
>>> int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
>>>
>>> min_cdclk = max_t(int, min_cdclk,
>>> DIV_ROUND_UP(crtc_state->pixel_rate,
>>> num_vdsc_instances));
>>> }
>> As far as I understand this condition is coming from the pixel clock
>> limitation as an input to the splitter (Bspec: 49259):
>>
>> Pipe BW check:
>>
>> Pixel clock < PPC * CDCLK frequency * Number of pipes joined
>>
>> PPC = 1 or 2 depending on number of DSC engines used within the pipe.
>>
>> So it implies CDCLK frequency > Pixel clock / (PPC * Number of pipes joined)
>>
>> num_vdsc_instances is actually giving us (PPC * number of pipes joined).
>>
>>
>> I completely agree that there will be no effect of the change on the
>> min_cdclk that gets computed in any case, whether DSC, 1 engine, 2 engine,
>> bigjoiner or no DSC.
>>
>> Only thing is for the case where 1 DSC engine is used, what
>> intel_pixel_rate_to_cdclk return will be different, and its due to the fact
>> that pipe is driven with 1PPC.
>>
>> But as I said, the min_cdclk computed will be same as without patch. So we
>> can certainly do away with this change, and I can drop this from the patch.
>>
>>
>> But in case of icl_plane_min_cdclk, currently we are dividing the
>> plane_pixel_rate by 2, citing that we use 2 pixel per clock, to get the
>> plane_min_cdclk.
>>
>> Should this not be 1 PPC in case where single DSC engine is used? In that
>> case plane_min_cdclk will be double. Should we keep the change only for
>> plane_min_cdclk then?
> Those are different cases:
>
>
> 1) When we are not using DSC, we are always processing
> 2 pixels per CDCLK, starting from gen 10. It is reflected in both intel_pixel_rate_to_cdclk
> and icl_plane_min_cdclk(which is a bit of a tautology I agree, but anyways we always take
> all limitations and use max(worst case) of them)
>
> 2) When we are using DSC. In that case we could use 1 or VDSC engines, which would set PPC to
> 1 or 2 correspondently. So whenever we happen to use DSC that condition will take max of
> the CDCLK obtained by other requirements and that formula.
> However in non-compressed case when there is no DSC, we should even be insterested in querying
> how many VDSC instances we have, amount of pixels processed per CDCLK isn't related to this in
> that case.
>
> Stan
Alright then I'll drop this change. The existing checks seem sufficient
to take care of the cdclk for DSC case.
Regards,
Ankit
>>
>> Regards,
>>
>> Ankit
>>
>>
>>> Also even if something still have to be done here, I think we should preferrably
>>> deal with anything related to DSC in a single place, to prevent any kind of
>>> confusion(when those checks are scattered in different places, it is way more easy to forget/not notice something)
>>>
>>> I think intel_pixel_rate_to_cdclk isn't supposed to know anything about DSC or any other specifics like audio checks and etc - it is
>>> just dealing with the "default" uncompressed case.
>>> Any other additional limitations or checks we apply after those, as there are
>>> quite many anyway.
>>>
>>> Stan
>>>
>>>
>>>> }
>>>> static void
>>>> --
>>>> 2.40.1
>>>>
^ permalink raw reply [flat|nested] 72+ messages in thread* Re: [PATCH 06/19] drm/i915/display: Account for DSC not split case while computing cdclk
@ 2023-07-25 11:22 ` Nautiyal, Ankit K
0 siblings, 0 replies; 72+ messages in thread
From: Nautiyal, Ankit K @ 2023-07-25 11:22 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx, anusha.srivatsa, dri-devel, navaremanasi
On 7/25/2023 3:40 PM, Lisovskiy, Stanislav wrote:
> On Tue, Jul 25, 2023 at 11:22:52AM +0530, Nautiyal, Ankit K wrote:
>> On 7/20/2023 2:46 PM, Lisovskiy, Stanislav wrote:
>>> On Thu, Jul 13, 2023 at 04:03:33PM +0530, Ankit Nautiyal wrote:
>>>> Currently we assume 2 Pixels Per Clock (PPC) while computing
>>>> plane cdclk and min_cdlck. In cases where DSC single engine
>>>> is used the throughput is 1 PPC.
>>>>
>>>> So account for the above case, while computing cdclk.
>>>>
>>>> v2: Use helper to get the adjusted pixel rate.
>>>>
>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
>>>> drivers/gpu/drm/i915/display/intel_vdsc.c | 12 ++++++++++++
>>>> drivers/gpu/drm/i915/display/intel_vdsc.h | 2 ++
>>>> drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
>>>> 4 files changed, 17 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>>>> index dcc1f6941b60..701909966545 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>>>> @@ -2508,7 +2508,7 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
>>>> int pixel_rate = crtc_state->pixel_rate;
>>>> if (DISPLAY_VER(dev_priv) >= 10)
>>>> - return DIV_ROUND_UP(pixel_rate, 2);
>>>> + return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
>>>> else if (DISPLAY_VER(dev_priv) == 9 ||
>>>> IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
>>>> return pixel_rate;
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> index 9d76c2756784..bbfdbf06da68 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> @@ -1038,3 +1038,15 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
>>>> out:
>>>> intel_display_power_put(dev_priv, power_domain, wakeref);
>>>> }
>>>> +
>>>> +int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate)
>>>> +{
>>>> + /*
>>>> + * If single VDSC engine is used, it uses one pixel per clock
>>>> + * otherwise we use two pixels per clock.
>>>> + */
>>>> + if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split)
>>>> + return pixel_rate;
>>>> +
>>>> + return DIV_ROUND_UP(pixel_rate, 2);
>>>> +}
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
>>>> index 2cc41ff08909..3bb4b1980b6b 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
>>>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
>>>> @@ -28,4 +28,6 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
>>>> void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
>>>> const struct intel_crtc_state *crtc_state);
>>>> +int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate);
>>>> +
>>>> #endif /* __INTEL_VDSC_H__ */
>>>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>> index 6b01a0b68b97..9eeb25ec4be9 100644
>>>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>> @@ -17,6 +17,7 @@
>>>> #include "intel_fb.h"
>>>> #include "intel_fbc.h"
>>>> #include "intel_psr.h"
>>>> +#include "intel_vdsc.h"
>>>> #include "skl_scaler.h"
>>>> #include "skl_universal_plane.h"
>>>> #include "skl_watermark.h"
>>>> @@ -263,8 +264,7 @@ static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
>>>> {
>>>> unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
>>>> - /* two pixels per clock */
>>>> - return DIV_ROUND_UP(pixel_rate, 2);
>>>> + return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate);
>>> Hi Ankit,
>>>
>>> I think the thing what you are taking of is already handled here in intel_cdclk.c:
>>>
>>> /*
>>> * When we decide to use only one VDSC engine, since
>>> * each VDSC operates with 1 ppc throughput, pixel clock
>>> * cannot be higher than the VDSC clock (cdclk)
>>> * If there 2 VDSC engines, then pixel clock can't be higher than
>>> * VDSC clock(cdclk) * 2 and so on.
>>> */
>>> if (crtc_state->dsc.compression_enable) {
>>> int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
>>>
>>> min_cdclk = max_t(int, min_cdclk,
>>> DIV_ROUND_UP(crtc_state->pixel_rate,
>>> num_vdsc_instances));
>>> }
>> As far as I understand this condition is coming from the pixel clock
>> limitation as an input to the splitter (Bspec: 49259):
>>
>> Pipe BW check:
>>
>> Pixel clock < PPC * CDCLK frequency * Number of pipes joined
>>
>> PPC = 1 or 2 depending on number of DSC engines used within the pipe.
>>
>> So it implies CDCLK frequency > Pixel clock / (PPC * Number of pipes joined)
>>
>> num_vdsc_instances is actually giving us (PPC * number of pipes joined).
>>
>>
>> I completely agree that there will be no effect of the change on the
>> min_cdclk that gets computed in any case, whether DSC, 1 engine, 2 engine,
>> bigjoiner or no DSC.
>>
>> Only thing is for the case where 1 DSC engine is used, what
>> intel_pixel_rate_to_cdclk return will be different, and its due to the fact
>> that pipe is driven with 1PPC.
>>
>> But as I said, the min_cdclk computed will be same as without patch. So we
>> can certainly do away with this change, and I can drop this from the patch.
>>
>>
>> But in case of icl_plane_min_cdclk, currently we are dividing the
>> plane_pixel_rate by 2, citing that we use 2 pixel per clock, to get the
>> plane_min_cdclk.
>>
>> Should this not be 1 PPC in case where single DSC engine is used? In that
>> case plane_min_cdclk will be double. Should we keep the change only for
>> plane_min_cdclk then?
> Those are different cases:
>
>
> 1) When we are not using DSC, we are always processing
> 2 pixels per CDCLK, starting from gen 10. It is reflected in both intel_pixel_rate_to_cdclk
> and icl_plane_min_cdclk(which is a bit of a tautology I agree, but anyways we always take
> all limitations and use max(worst case) of them)
>
> 2) When we are using DSC. In that case we could use 1 or VDSC engines, which would set PPC to
> 1 or 2 correspondently. So whenever we happen to use DSC that condition will take max of
> the CDCLK obtained by other requirements and that formula.
> However in non-compressed case when there is no DSC, we should even be insterested in querying
> how many VDSC instances we have, amount of pixels processed per CDCLK isn't related to this in
> that case.
>
> Stan
Alright then I'll drop this change. The existing checks seem sufficient
to take care of the cdclk for DSC case.
Regards,
Ankit
>>
>> Regards,
>>
>> Ankit
>>
>>
>>> Also even if something still have to be done here, I think we should preferrably
>>> deal with anything related to DSC in a single place, to prevent any kind of
>>> confusion(when those checks are scattered in different places, it is way more easy to forget/not notice something)
>>>
>>> I think intel_pixel_rate_to_cdclk isn't supposed to know anything about DSC or any other specifics like audio checks and etc - it is
>>> just dealing with the "default" uncompressed case.
>>> Any other additional limitations or checks we apply after those, as there are
>>> quite many anyway.
>>>
>>> Stan
>>>
>>>
>>>> }
>>>> static void
>>>> --
>>>> 2.40.1
>>>>
^ permalink raw reply [flat|nested] 72+ messages in thread
* [Intel-gfx] [PATCH 07/19] drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-13 10:33 ` Ankit Nautiyal
-1 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel
As per Bsepc:49259, Bigjoiner BW check puts restriction on the
compressed bpp for a given CDCLK, pixelclock in cases where
Bigjoiner + DSC are used.
Currently compressed bpp is computed first, and it is ensured that
the bpp will work at least with the max CDCLK freq.
Since the CDCLK is computed later, lets account for Bigjoiner BW
check while calculating Min CDCLK.
v2: Use pixel clock in the bw calculations. (Ville)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 61 +++++++++++++++++-----
1 file changed, 47 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 701909966545..788dba576294 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2533,6 +2533,51 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
return min_cdclk;
}
+static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
+ int min_cdclk = 0;
+
+ /*
+ * When we decide to use only one VDSC engine, since
+ * each VDSC operates with 1 ppc throughput, pixel clock
+ * cannot be higher than the VDSC clock (cdclk)
+ * If there 2 VDSC engines, then pixel clock can't be higher than
+ * VDSC clock(cdclk) * 2 and so on.
+ */
+ min_cdclk = max_t(int, min_cdclk,
+ DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances));
+
+ if (crtc_state->bigjoiner_pipes) {
+ int pixel_clock = crtc_state->hw.adjusted_mode.clock;
+
+ /*
+ * According to Bigjoiner bw check:
+ * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
+ *
+ * We have already computed compressed_bpp, so now compute the min CDCLK that
+ * is required to support this compressed_bpp.
+ *
+ * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
+ *
+ * Since PPC = 2 with bigjoiner
+ * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
+ *
+ * #TODO Bspec mentions to account for FEC overhead while using pixel clock.
+ * Check if we need to use FEC overhead in the above calculations.
+ */
+ int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
+ int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) /
+ (2 * bigjoiner_interface_bits);
+
+ min_cdclk = max(min_cdclk, min_cdclk_bj);
+ }
+
+ return min_cdclk;
+}
+
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv =
@@ -2604,20 +2649,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
/* Account for additional needs from the planes */
min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
- /*
- * When we decide to use only one VDSC engine, since
- * each VDSC operates with 1 ppc throughput, pixel clock
- * cannot be higher than the VDSC clock (cdclk)
- * If there 2 VDSC engines, then pixel clock can't be higher than
- * VDSC clock(cdclk) * 2 and so on.
- */
- if (crtc_state->dsc.compression_enable) {
- int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
-
- min_cdclk = max_t(int, min_cdclk,
- DIV_ROUND_UP(crtc_state->pixel_rate,
- num_vdsc_instances));
- }
+ if (crtc_state->dsc.compression_enable)
+ min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
/*
* HACK. Currently for TGL/DG2 platforms we calculate
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH 07/19] drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck
@ 2023-07-13 10:33 ` Ankit Nautiyal
0 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
As per Bsepc:49259, Bigjoiner BW check puts restriction on the
compressed bpp for a given CDCLK, pixelclock in cases where
Bigjoiner + DSC are used.
Currently compressed bpp is computed first, and it is ensured that
the bpp will work at least with the max CDCLK freq.
Since the CDCLK is computed later, lets account for Bigjoiner BW
check while calculating Min CDCLK.
v2: Use pixel clock in the bw calculations. (Ville)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 61 +++++++++++++++++-----
1 file changed, 47 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 701909966545..788dba576294 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2533,6 +2533,51 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
return min_cdclk;
}
+static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
+ int min_cdclk = 0;
+
+ /*
+ * When we decide to use only one VDSC engine, since
+ * each VDSC operates with 1 ppc throughput, pixel clock
+ * cannot be higher than the VDSC clock (cdclk)
+ * If there 2 VDSC engines, then pixel clock can't be higher than
+ * VDSC clock(cdclk) * 2 and so on.
+ */
+ min_cdclk = max_t(int, min_cdclk,
+ DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances));
+
+ if (crtc_state->bigjoiner_pipes) {
+ int pixel_clock = crtc_state->hw.adjusted_mode.clock;
+
+ /*
+ * According to Bigjoiner bw check:
+ * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
+ *
+ * We have already computed compressed_bpp, so now compute the min CDCLK that
+ * is required to support this compressed_bpp.
+ *
+ * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
+ *
+ * Since PPC = 2 with bigjoiner
+ * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
+ *
+ * #TODO Bspec mentions to account for FEC overhead while using pixel clock.
+ * Check if we need to use FEC overhead in the above calculations.
+ */
+ int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
+ int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) /
+ (2 * bigjoiner_interface_bits);
+
+ min_cdclk = max(min_cdclk, min_cdclk_bj);
+ }
+
+ return min_cdclk;
+}
+
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv =
@@ -2604,20 +2649,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
/* Account for additional needs from the planes */
min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
- /*
- * When we decide to use only one VDSC engine, since
- * each VDSC operates with 1 ppc throughput, pixel clock
- * cannot be higher than the VDSC clock (cdclk)
- * If there 2 VDSC engines, then pixel clock can't be higher than
- * VDSC clock(cdclk) * 2 and so on.
- */
- if (crtc_state->dsc.compression_enable) {
- int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
-
- min_cdclk = max_t(int, min_cdclk,
- DIV_ROUND_UP(crtc_state->pixel_rate,
- num_vdsc_instances));
- }
+ if (crtc_state->dsc.compression_enable)
+ min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
/*
* HACK. Currently for TGL/DG2 platforms we calculate
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* Re: [Intel-gfx] [PATCH 07/19] drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-20 9:24 ` Lisovskiy, Stanislav
-1 siblings, 0 replies; 72+ messages in thread
From: Lisovskiy, Stanislav @ 2023-07-20 9:24 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, dri-devel
On Thu, Jul 13, 2023 at 04:03:34PM +0530, Ankit Nautiyal wrote:
> As per Bsepc:49259, Bigjoiner BW check puts restriction on the
> compressed bpp for a given CDCLK, pixelclock in cases where
> Bigjoiner + DSC are used.
>
> Currently compressed bpp is computed first, and it is ensured that
> the bpp will work at least with the max CDCLK freq.
>
> Since the CDCLK is computed later, lets account for Bigjoiner BW
> check while calculating Min CDCLK.
>
> v2: Use pixel clock in the bw calculations. (Ville)
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 61 +++++++++++++++++-----
> 1 file changed, 47 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 701909966545..788dba576294 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2533,6 +2533,51 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
> return min_cdclk;
> }
>
> +static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
> + int min_cdclk = 0;
> +
> + /*
> + * When we decide to use only one VDSC engine, since
> + * each VDSC operates with 1 ppc throughput, pixel clock
> + * cannot be higher than the VDSC clock (cdclk)
> + * If there 2 VDSC engines, then pixel clock can't be higher than
> + * VDSC clock(cdclk) * 2 and so on.
> + */
> + min_cdclk = max_t(int, min_cdclk,
> + DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances));
> +
> + if (crtc_state->bigjoiner_pipes) {
> + int pixel_clock = crtc_state->hw.adjusted_mode.clock;
> +
> + /*
> + * According to Bigjoiner bw check:
> + * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
> + *
> + * We have already computed compressed_bpp, so now compute the min CDCLK that
> + * is required to support this compressed_bpp.
> + *
> + * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
> + *
> + * Since PPC = 2 with bigjoiner
> + * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
> + *
> + * #TODO Bspec mentions to account for FEC overhead while using pixel clock.
> + * Check if we need to use FEC overhead in the above calculations.
There is already some function used in intel_dp.c:
intel_dp_mode_to_fec_clock(mode_clock) => Should you may be just use that one, to account FEC
overhead?
> + */
> + int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
> + int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) /
> + (2 * bigjoiner_interface_bits);
I would use "num_vdsc_instances" instead of 2, since we even get those explicitly.
> +
> + min_cdclk = max(min_cdclk, min_cdclk_bj);
> + }
> +
> + return min_cdclk;
> +}
> +
> int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv =
> @@ -2604,20 +2649,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> /* Account for additional needs from the planes */
> min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
>
> - /*
> - * When we decide to use only one VDSC engine, since
> - * each VDSC operates with 1 ppc throughput, pixel clock
> - * cannot be higher than the VDSC clock (cdclk)
> - * If there 2 VDSC engines, then pixel clock can't be higher than
> - * VDSC clock(cdclk) * 2 and so on.
> - */
> - if (crtc_state->dsc.compression_enable) {
> - int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
> -
> - min_cdclk = max_t(int, min_cdclk,
> - DIV_ROUND_UP(crtc_state->pixel_rate,
> - num_vdsc_instances));
> - }
> + if (crtc_state->dsc.compression_enable)
> + min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
With notes above taken care of:
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> /*
> * HACK. Currently for TGL/DG2 platforms we calculate
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 72+ messages in thread* Re: [PATCH 07/19] drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck
@ 2023-07-20 9:24 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 72+ messages in thread
From: Lisovskiy, Stanislav @ 2023-07-20 9:24 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, anusha.srivatsa, dri-devel, navaremanasi
On Thu, Jul 13, 2023 at 04:03:34PM +0530, Ankit Nautiyal wrote:
> As per Bsepc:49259, Bigjoiner BW check puts restriction on the
> compressed bpp for a given CDCLK, pixelclock in cases where
> Bigjoiner + DSC are used.
>
> Currently compressed bpp is computed first, and it is ensured that
> the bpp will work at least with the max CDCLK freq.
>
> Since the CDCLK is computed later, lets account for Bigjoiner BW
> check while calculating Min CDCLK.
>
> v2: Use pixel clock in the bw calculations. (Ville)
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 61 +++++++++++++++++-----
> 1 file changed, 47 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 701909966545..788dba576294 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2533,6 +2533,51 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
> return min_cdclk;
> }
>
> +static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
> + int min_cdclk = 0;
> +
> + /*
> + * When we decide to use only one VDSC engine, since
> + * each VDSC operates with 1 ppc throughput, pixel clock
> + * cannot be higher than the VDSC clock (cdclk)
> + * If there 2 VDSC engines, then pixel clock can't be higher than
> + * VDSC clock(cdclk) * 2 and so on.
> + */
> + min_cdclk = max_t(int, min_cdclk,
> + DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances));
> +
> + if (crtc_state->bigjoiner_pipes) {
> + int pixel_clock = crtc_state->hw.adjusted_mode.clock;
> +
> + /*
> + * According to Bigjoiner bw check:
> + * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
> + *
> + * We have already computed compressed_bpp, so now compute the min CDCLK that
> + * is required to support this compressed_bpp.
> + *
> + * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
> + *
> + * Since PPC = 2 with bigjoiner
> + * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
> + *
> + * #TODO Bspec mentions to account for FEC overhead while using pixel clock.
> + * Check if we need to use FEC overhead in the above calculations.
There is already some function used in intel_dp.c:
intel_dp_mode_to_fec_clock(mode_clock) => Should you may be just use that one, to account FEC
overhead?
> + */
> + int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
> + int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) /
> + (2 * bigjoiner_interface_bits);
I would use "num_vdsc_instances" instead of 2, since we even get those explicitly.
> +
> + min_cdclk = max(min_cdclk, min_cdclk_bj);
> + }
> +
> + return min_cdclk;
> +}
> +
> int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv =
> @@ -2604,20 +2649,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> /* Account for additional needs from the planes */
> min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
>
> - /*
> - * When we decide to use only one VDSC engine, since
> - * each VDSC operates with 1 ppc throughput, pixel clock
> - * cannot be higher than the VDSC clock (cdclk)
> - * If there 2 VDSC engines, then pixel clock can't be higher than
> - * VDSC clock(cdclk) * 2 and so on.
> - */
> - if (crtc_state->dsc.compression_enable) {
> - int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
> -
> - min_cdclk = max_t(int, min_cdclk,
> - DIV_ROUND_UP(crtc_state->pixel_rate,
> - num_vdsc_instances));
> - }
> + if (crtc_state->dsc.compression_enable)
> + min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
With notes above taken care of:
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> /*
> * HACK. Currently for TGL/DG2 platforms we calculate
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 72+ messages in thread* Re: [Intel-gfx] [PATCH 07/19] drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck
2023-07-20 9:24 ` Lisovskiy, Stanislav
@ 2023-07-25 6:01 ` Nautiyal, Ankit K
-1 siblings, 0 replies; 72+ messages in thread
From: Nautiyal, Ankit K @ 2023-07-25 6:01 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx, dri-devel
On 7/20/2023 2:54 PM, Lisovskiy, Stanislav wrote:
> On Thu, Jul 13, 2023 at 04:03:34PM +0530, Ankit Nautiyal wrote:
>> As per Bsepc:49259, Bigjoiner BW check puts restriction on the
>> compressed bpp for a given CDCLK, pixelclock in cases where
>> Bigjoiner + DSC are used.
>>
>> Currently compressed bpp is computed first, and it is ensured that
>> the bpp will work at least with the max CDCLK freq.
>>
>> Since the CDCLK is computed later, lets account for Bigjoiner BW
>> check while calculating Min CDCLK.
>>
>> v2: Use pixel clock in the bw calculations. (Ville)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_cdclk.c | 61 +++++++++++++++++-----
>> 1 file changed, 47 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index 701909966545..788dba576294 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -2533,6 +2533,51 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
>> return min_cdclk;
>> }
>>
>> +static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
>> +{
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> + int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
>> + int min_cdclk = 0;
>> +
>> + /*
>> + * When we decide to use only one VDSC engine, since
>> + * each VDSC operates with 1 ppc throughput, pixel clock
>> + * cannot be higher than the VDSC clock (cdclk)
>> + * If there 2 VDSC engines, then pixel clock can't be higher than
>> + * VDSC clock(cdclk) * 2 and so on.
>> + */
>> + min_cdclk = max_t(int, min_cdclk,
>> + DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances));
>> +
>> + if (crtc_state->bigjoiner_pipes) {
>> + int pixel_clock = crtc_state->hw.adjusted_mode.clock;
>> +
>> + /*
>> + * According to Bigjoiner bw check:
>> + * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
>> + *
>> + * We have already computed compressed_bpp, so now compute the min CDCLK that
>> + * is required to support this compressed_bpp.
>> + *
>> + * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
>> + *
>> + * Since PPC = 2 with bigjoiner
>> + * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
>> + *
>> + * #TODO Bspec mentions to account for FEC overhead while using pixel clock.
>> + * Check if we need to use FEC overhead in the above calculations.
> There is already some function used in intel_dp.c:
>
> intel_dp_mode_to_fec_clock(mode_clock) => Should you may be just use that one, to account FEC
> overhead?
Hmm right I agree, I can use that here, thanks!
>
>> + */
>> + int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
>> + int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) /
>> + (2 * bigjoiner_interface_bits);
> I would use "num_vdsc_instances" instead of 2, since we even get those explicitly.
Currently for the bigjoiner case, the num_vdsc_instances returns 4 for
the pipes. Should we have a function to have num_vdsc_instances_per_pipe?
Or perhaps one function for just getting the PPC which will be 2 for
Display>=10 and when dsc_split is used, and 1 otherwise?
Thanks & Regards,
Ankit
>
>> +
>> + min_cdclk = max(min_cdclk, min_cdclk_bj);
>> + }
>> +
>> + return min_cdclk;
>> +}
>> +
>> int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>> {
>> struct drm_i915_private *dev_priv =
>> @@ -2604,20 +2649,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>> /* Account for additional needs from the planes */
>> min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
>>
>> - /*
>> - * When we decide to use only one VDSC engine, since
>> - * each VDSC operates with 1 ppc throughput, pixel clock
>> - * cannot be higher than the VDSC clock (cdclk)
>> - * If there 2 VDSC engines, then pixel clock can't be higher than
>> - * VDSC clock(cdclk) * 2 and so on.
>> - */
>> - if (crtc_state->dsc.compression_enable) {
>> - int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
>> -
>> - min_cdclk = max_t(int, min_cdclk,
>> - DIV_ROUND_UP(crtc_state->pixel_rate,
>> - num_vdsc_instances));
>> - }
>> + if (crtc_state->dsc.compression_enable)
>> + min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
>
> With notes above taken care of:
>
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
>>
>> /*
>> * HACK. Currently for TGL/DG2 platforms we calculate
>> --
>> 2.40.1
>>
^ permalink raw reply [flat|nested] 72+ messages in thread* Re: [PATCH 07/19] drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck
@ 2023-07-25 6:01 ` Nautiyal, Ankit K
0 siblings, 0 replies; 72+ messages in thread
From: Nautiyal, Ankit K @ 2023-07-25 6:01 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx, anusha.srivatsa, dri-devel, navaremanasi
On 7/20/2023 2:54 PM, Lisovskiy, Stanislav wrote:
> On Thu, Jul 13, 2023 at 04:03:34PM +0530, Ankit Nautiyal wrote:
>> As per Bsepc:49259, Bigjoiner BW check puts restriction on the
>> compressed bpp for a given CDCLK, pixelclock in cases where
>> Bigjoiner + DSC are used.
>>
>> Currently compressed bpp is computed first, and it is ensured that
>> the bpp will work at least with the max CDCLK freq.
>>
>> Since the CDCLK is computed later, lets account for Bigjoiner BW
>> check while calculating Min CDCLK.
>>
>> v2: Use pixel clock in the bw calculations. (Ville)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_cdclk.c | 61 +++++++++++++++++-----
>> 1 file changed, 47 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index 701909966545..788dba576294 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -2533,6 +2533,51 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
>> return min_cdclk;
>> }
>>
>> +static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
>> +{
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> + int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
>> + int min_cdclk = 0;
>> +
>> + /*
>> + * When we decide to use only one VDSC engine, since
>> + * each VDSC operates with 1 ppc throughput, pixel clock
>> + * cannot be higher than the VDSC clock (cdclk)
>> + * If there 2 VDSC engines, then pixel clock can't be higher than
>> + * VDSC clock(cdclk) * 2 and so on.
>> + */
>> + min_cdclk = max_t(int, min_cdclk,
>> + DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances));
>> +
>> + if (crtc_state->bigjoiner_pipes) {
>> + int pixel_clock = crtc_state->hw.adjusted_mode.clock;
>> +
>> + /*
>> + * According to Bigjoiner bw check:
>> + * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
>> + *
>> + * We have already computed compressed_bpp, so now compute the min CDCLK that
>> + * is required to support this compressed_bpp.
>> + *
>> + * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
>> + *
>> + * Since PPC = 2 with bigjoiner
>> + * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
>> + *
>> + * #TODO Bspec mentions to account for FEC overhead while using pixel clock.
>> + * Check if we need to use FEC overhead in the above calculations.
> There is already some function used in intel_dp.c:
>
> intel_dp_mode_to_fec_clock(mode_clock) => Should you may be just use that one, to account FEC
> overhead?
Hmm right I agree, I can use that here, thanks!
>
>> + */
>> + int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
>> + int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) /
>> + (2 * bigjoiner_interface_bits);
> I would use "num_vdsc_instances" instead of 2, since we even get those explicitly.
Currently for the bigjoiner case, the num_vdsc_instances returns 4 for
the pipes. Should we have a function to have num_vdsc_instances_per_pipe?
Or perhaps one function for just getting the PPC which will be 2 for
Display>=10 and when dsc_split is used, and 1 otherwise?
Thanks & Regards,
Ankit
>
>> +
>> + min_cdclk = max(min_cdclk, min_cdclk_bj);
>> + }
>> +
>> + return min_cdclk;
>> +}
>> +
>> int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>> {
>> struct drm_i915_private *dev_priv =
>> @@ -2604,20 +2649,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>> /* Account for additional needs from the planes */
>> min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
>>
>> - /*
>> - * When we decide to use only one VDSC engine, since
>> - * each VDSC operates with 1 ppc throughput, pixel clock
>> - * cannot be higher than the VDSC clock (cdclk)
>> - * If there 2 VDSC engines, then pixel clock can't be higher than
>> - * VDSC clock(cdclk) * 2 and so on.
>> - */
>> - if (crtc_state->dsc.compression_enable) {
>> - int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
>> -
>> - min_cdclk = max_t(int, min_cdclk,
>> - DIV_ROUND_UP(crtc_state->pixel_rate,
>> - num_vdsc_instances));
>> - }
>> + if (crtc_state->dsc.compression_enable)
>> + min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
>
> With notes above taken care of:
>
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
>>
>> /*
>> * HACK. Currently for TGL/DG2 platforms we calculate
>> --
>> 2.40.1
>>
^ permalink raw reply [flat|nested] 72+ messages in thread
* [Intel-gfx] [PATCH 08/19] drm/i915/dp: Remove extra logs for printing DSC info
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-13 10:33 ` Ankit Nautiyal
-1 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel
DSC compressed bpp and slice counts are already getting printed at the
end of dsc compute config. Remove extra logs.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c1fd448d80e1..23ede846202c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1780,9 +1780,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
output_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
- drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n",
- pipe_config->dsc.compressed_bpp,
- pipe_config->dsc.slice_count);
}
/*
* VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH 08/19] drm/i915/dp: Remove extra logs for printing DSC info
@ 2023-07-13 10:33 ` Ankit Nautiyal
0 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
DSC compressed bpp and slice counts are already getting printed at the
end of dsc compute config. Remove extra logs.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c1fd448d80e1..23ede846202c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1780,9 +1780,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
output_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
- drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n",
- pipe_config->dsc.compressed_bpp,
- pipe_config->dsc.slice_count);
}
/*
* VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [Intel-gfx] [PATCH 08/19] drm/i915/dp: Remove extra logs for printing DSC info
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-14 3:28 ` Murthy, Arun R
-1 siblings, 0 replies; 72+ messages in thread
From: Murthy, Arun R @ 2023-07-14 3:28 UTC (permalink / raw)
To: Nautiyal, Ankit K, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ankit
> Nautiyal
> Sent: Thursday, July 13, 2023 4:04 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 08/19] drm/i915/dp: Remove extra logs for
> printing DSC info
>
> DSC compressed bpp and slice counts are already getting printed at the end
> of dsc compute config. Remove extra logs.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
> drivers/gpu/drm/i915/display/intel_dp.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index c1fd448d80e1..23ede846202c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1780,9 +1780,6 @@ int intel_dp_dsc_compute_config(struct intel_dp
> *intel_dp,
> output_bpp);
> }
> pipe_config->dsc.slice_count = dsc_dp_slice_count;
> - drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d
> slice count %d\n",
> - pipe_config->dsc.compressed_bpp,
> - pipe_config->dsc.slice_count);
> }
> /*
> * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
> --
> 2.40.1
^ permalink raw reply [flat|nested] 72+ messages in thread
* RE: [Intel-gfx] [PATCH 08/19] drm/i915/dp: Remove extra logs for printing DSC info
@ 2023-07-14 3:28 ` Murthy, Arun R
0 siblings, 0 replies; 72+ messages in thread
From: Murthy, Arun R @ 2023-07-14 3:28 UTC (permalink / raw)
To: Nautiyal, Ankit K, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ankit
> Nautiyal
> Sent: Thursday, July 13, 2023 4:04 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 08/19] drm/i915/dp: Remove extra logs for
> printing DSC info
>
> DSC compressed bpp and slice counts are already getting printed at the end
> of dsc compute config. Remove extra logs.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
> drivers/gpu/drm/i915/display/intel_dp.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index c1fd448d80e1..23ede846202c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1780,9 +1780,6 @@ int intel_dp_dsc_compute_config(struct intel_dp
> *intel_dp,
> output_bpp);
> }
> pipe_config->dsc.slice_count = dsc_dp_slice_count;
> - drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d
> slice count %d\n",
> - pipe_config->dsc.compressed_bpp,
> - pipe_config->dsc.slice_count);
> }
> /*
> * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
> --
> 2.40.1
^ permalink raw reply [flat|nested] 72+ messages in thread
* [Intel-gfx] [PATCH 09/19] drm/display/dp: Fix the DP DSC Receiver cap size
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-13 10:33 ` Ankit Nautiyal
-1 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel
DP DSC Receiver Capabilities are exposed via DPCD 60h-6Fh.
Fix the DSC RECEIVER CAP SIZE accordingly.
Fixes: ffddc4363c28 ("drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT")
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: <stable@vger.kernel.org> # v5.0+
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
include/drm/display/drm_dp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 02f2ac4dd2df..e69cece404b3 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1537,7 +1537,7 @@ enum drm_dp_phy {
#define DP_BRANCH_OUI_HEADER_SIZE 0xc
#define DP_RECEIVER_CAP_SIZE 0xf
-#define DP_DSC_RECEIVER_CAP_SIZE 0xf
+#define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */
#define EDP_PSR_RECEIVER_CAP_SIZE 2
#define EDP_DISPLAY_CTL_CAP_SIZE 3
#define DP_LTTPR_COMMON_CAP_SIZE 8
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH 09/19] drm/display/dp: Fix the DP DSC Receiver cap size
@ 2023-07-13 10:33 ` Ankit Nautiyal
0 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
DP DSC Receiver Capabilities are exposed via DPCD 60h-6Fh.
Fix the DSC RECEIVER CAP SIZE accordingly.
Fixes: ffddc4363c28 ("drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT")
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: <stable@vger.kernel.org> # v5.0+
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
include/drm/display/drm_dp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 02f2ac4dd2df..e69cece404b3 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1537,7 +1537,7 @@ enum drm_dp_phy {
#define DP_BRANCH_OUI_HEADER_SIZE 0xc
#define DP_RECEIVER_CAP_SIZE 0xf
-#define DP_DSC_RECEIVER_CAP_SIZE 0xf
+#define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */
#define EDP_PSR_RECEIVER_CAP_SIZE 2
#define EDP_DISPLAY_CTL_CAP_SIZE 3
#define DP_LTTPR_COMMON_CAP_SIZE 8
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [Intel-gfx] [PATCH 10/19] drm/i915/dp: Avoid forcing DSC BPC for MST case
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-13 10:33 ` Ankit Nautiyal
-1 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel
For MST the bpc is hardcoded to 8, and pipe bpp to 24.
So avoid forcing DSC bpc for MST case.
v2: Warn and ignore the debug flag than to bail out. (Jani)
v3: Fix dbg message to mention forced bpc instead of bpp.
v4: Fix checkpatch longline warning.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++++
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 23ede846202c..11e54e6ee985 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1695,14 +1695,14 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
return -EINVAL;
- if (compute_pipe_bpp)
+ if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
+ pipe_bpp = intel_dp->force_dsc_bpc * 3;
+ drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
+ intel_dp->force_dsc_bpc);
+ } else if (compute_pipe_bpp) {
pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
- else
+ } else {
pipe_bpp = pipe_config->pipe_bpp;
-
- if (intel_dp->force_dsc_bpc) {
- pipe_bpp = intel_dp->force_dsc_bpc * 3;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
}
/* Min Input BPC for ICL+ is 8 */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 1f00713fb1ad..dff4717edbd0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -361,6 +361,11 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
/* enable compression if the mode doesn't fit available BW */
drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
if (ret || intel_dp->force_dsc_en) {
+ /*
+ * FIXME: As bpc is hardcoded to 8, as mentioned above,
+ * WARN and ignore the debug flag force_dsc_bpc for now.
+ */
+ drm_WARN(&dev_priv->drm, intel_dp->force_dsc_bpc, "Cannot Force BPC for MST\n");
/*
* Try to get at least some timeslots and then see, if
* we can fit there with DSC.
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH 10/19] drm/i915/dp: Avoid forcing DSC BPC for MST case
@ 2023-07-13 10:33 ` Ankit Nautiyal
0 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
For MST the bpc is hardcoded to 8, and pipe bpp to 24.
So avoid forcing DSC bpc for MST case.
v2: Warn and ignore the debug flag than to bail out. (Jani)
v3: Fix dbg message to mention forced bpc instead of bpp.
v4: Fix checkpatch longline warning.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++++
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 23ede846202c..11e54e6ee985 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1695,14 +1695,14 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
return -EINVAL;
- if (compute_pipe_bpp)
+ if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
+ pipe_bpp = intel_dp->force_dsc_bpc * 3;
+ drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
+ intel_dp->force_dsc_bpc);
+ } else if (compute_pipe_bpp) {
pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
- else
+ } else {
pipe_bpp = pipe_config->pipe_bpp;
-
- if (intel_dp->force_dsc_bpc) {
- pipe_bpp = intel_dp->force_dsc_bpc * 3;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
}
/* Min Input BPC for ICL+ is 8 */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 1f00713fb1ad..dff4717edbd0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -361,6 +361,11 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
/* enable compression if the mode doesn't fit available BW */
drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
if (ret || intel_dp->force_dsc_en) {
+ /*
+ * FIXME: As bpc is hardcoded to 8, as mentioned above,
+ * WARN and ignore the debug flag force_dsc_bpc for now.
+ */
+ drm_WARN(&dev_priv->drm, intel_dp->force_dsc_bpc, "Cannot Force BPC for MST\n");
/*
* Try to get at least some timeslots and then see, if
* we can fit there with DSC.
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [Intel-gfx] [PATCH 11/19] drm/i915/dp: Add functions to get min/max src input bpc with DSC
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-13 10:33 ` Ankit Nautiyal
-1 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel
Separate out functions for getting maximum and minimum input BPC based
on platforms, when DSC is used.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 38 +++++++++++++++++++------
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 11e54e6ee985..5cc62c51372d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1533,6 +1533,18 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
return -EINVAL;
}
+static
+u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
+{
+ /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
+ if (DISPLAY_VER(i915) >= 12)
+ return 12;
+ if (DISPLAY_VER(i915) == 11)
+ return 10;
+
+ return 0;
+}
+
int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -1540,11 +1552,12 @@ int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
u8 dsc_bpc[3] = {0};
u8 dsc_max_bpc;
- /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
- if (DISPLAY_VER(i915) >= 12)
- dsc_max_bpc = min_t(u8, 12, max_req_bpc);
- else
- dsc_max_bpc = min_t(u8, 10, max_req_bpc);
+ dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
+
+ if (!dsc_max_bpc)
+ return dsc_max_bpc;
+
+ dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
dsc_bpc);
@@ -1672,6 +1685,16 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
}
+static
+u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
+{
+ /* Min DSC Input BPC for ICL+ is 8 */
+ if (DISPLAY_VER(i915) >= 11)
+ return 8;
+
+ return 0;
+}
+
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1705,10 +1728,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_bpp = pipe_config->pipe_bpp;
}
- /* Min Input BPC for ICL+ is 8 */
- if (pipe_bpp < 8 * 3) {
+ if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) {
drm_dbg_kms(&dev_priv->drm,
- "No DSC support for less than 8bpc\n");
+ "Computed BPC less than min supported by source for DSC\n");
return -EINVAL;
}
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH 11/19] drm/i915/dp: Add functions to get min/max src input bpc with DSC
@ 2023-07-13 10:33 ` Ankit Nautiyal
0 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
Separate out functions for getting maximum and minimum input BPC based
on platforms, when DSC is used.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 38 +++++++++++++++++++------
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 11e54e6ee985..5cc62c51372d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1533,6 +1533,18 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
return -EINVAL;
}
+static
+u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
+{
+ /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
+ if (DISPLAY_VER(i915) >= 12)
+ return 12;
+ if (DISPLAY_VER(i915) == 11)
+ return 10;
+
+ return 0;
+}
+
int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -1540,11 +1552,12 @@ int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
u8 dsc_bpc[3] = {0};
u8 dsc_max_bpc;
- /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
- if (DISPLAY_VER(i915) >= 12)
- dsc_max_bpc = min_t(u8, 12, max_req_bpc);
- else
- dsc_max_bpc = min_t(u8, 10, max_req_bpc);
+ dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
+
+ if (!dsc_max_bpc)
+ return dsc_max_bpc;
+
+ dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
dsc_bpc);
@@ -1672,6 +1685,16 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
}
+static
+u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
+{
+ /* Min DSC Input BPC for ICL+ is 8 */
+ if (DISPLAY_VER(i915) >= 11)
+ return 8;
+
+ return 0;
+}
+
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1705,10 +1728,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_bpp = pipe_config->pipe_bpp;
}
- /* Min Input BPC for ICL+ is 8 */
- if (pipe_bpp < 8 * 3) {
+ if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) {
drm_dbg_kms(&dev_priv->drm,
- "No DSC support for less than 8bpc\n");
+ "Computed BPC less than min supported by source for DSC\n");
return -EINVAL;
}
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [Intel-gfx] [PATCH 12/19] drm/i915/dp: Check min bpc DSC limits for dsc_force_bpc also
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-13 10:33 ` Ankit Nautiyal
-1 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel
For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24.
Check this condition for cases where bpc is forced by debugfs flag
dsc_force_bpc. If the check fails, then WARN and ignore the debugfs
flag.
For MST case the pipe_bpp is already computed (hardcoded to be 24),
and this check is not required.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 48 ++++++++++++++++---------
1 file changed, 31 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5cc62c51372d..9d2d05da594b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1695,6 +1695,12 @@ u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
return 0;
}
+static
+bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
+{
+ return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;
+}
+
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1706,7 +1712,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
- int pipe_bpp;
int ret;
pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
@@ -1718,28 +1723,37 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
return -EINVAL;
- if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
- pipe_bpp = intel_dp->force_dsc_bpc * 3;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
- intel_dp->force_dsc_bpc);
- } else if (compute_pipe_bpp) {
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
- } else {
- pipe_bpp = pipe_config->pipe_bpp;
- }
+ if (compute_pipe_bpp) {
+ int pipe_bpp;
+ int forced_bpp = intel_dp->force_dsc_bpc * 3;
- if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) {
- drm_dbg_kms(&dev_priv->drm,
- "Computed BPC less than min supported by source for DSC\n");
- return -EINVAL;
+ if (forced_bpp && is_dsc_pipe_bpp_sufficient(dev_priv, forced_bpp)) {
+ pipe_bpp = forced_bpp;
+ drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
+ intel_dp->force_dsc_bpc);
+ } else {
+ drm_WARN(&dev_priv->drm, forced_bpp,
+ "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
+ intel_dp->force_dsc_bpc);
+
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
+ conn_state->max_requested_bpc);
+
+ if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Computed BPC less than min supported by source for DSC\n");
+ return -EINVAL;
+ }
+ }
+
+ pipe_config->pipe_bpp = pipe_bpp;
}
/*
- * For now enable DSC for max bpp, max link rate, max lane count.
+ * For now enable DSC for max link rate, max lane count.
* Optimize this later for the minimum possible link rate/lane count
* with DSC enabled for the requested mode.
*/
- pipe_config->pipe_bpp = pipe_bpp;
pipe_config->port_clock = limits->max_rate;
pipe_config->lane_count = limits->max_lane_count;
@@ -1768,7 +1782,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
adjusted_mode->crtc_hdisplay,
pipe_config->bigjoiner_pipes,
pipe_config->output_format,
- pipe_bpp,
+ pipe_config->pipe_bpp,
timeslots);
if (!dsc_max_compressed_bpp) {
drm_dbg_kms(&dev_priv->drm,
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH 12/19] drm/i915/dp: Check min bpc DSC limits for dsc_force_bpc also
@ 2023-07-13 10:33 ` Ankit Nautiyal
0 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24.
Check this condition for cases where bpc is forced by debugfs flag
dsc_force_bpc. If the check fails, then WARN and ignore the debugfs
flag.
For MST case the pipe_bpp is already computed (hardcoded to be 24),
and this check is not required.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 48 ++++++++++++++++---------
1 file changed, 31 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5cc62c51372d..9d2d05da594b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1695,6 +1695,12 @@ u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
return 0;
}
+static
+bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
+{
+ return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;
+}
+
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1706,7 +1712,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
- int pipe_bpp;
int ret;
pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
@@ -1718,28 +1723,37 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
return -EINVAL;
- if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
- pipe_bpp = intel_dp->force_dsc_bpc * 3;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
- intel_dp->force_dsc_bpc);
- } else if (compute_pipe_bpp) {
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
- } else {
- pipe_bpp = pipe_config->pipe_bpp;
- }
+ if (compute_pipe_bpp) {
+ int pipe_bpp;
+ int forced_bpp = intel_dp->force_dsc_bpc * 3;
- if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) {
- drm_dbg_kms(&dev_priv->drm,
- "Computed BPC less than min supported by source for DSC\n");
- return -EINVAL;
+ if (forced_bpp && is_dsc_pipe_bpp_sufficient(dev_priv, forced_bpp)) {
+ pipe_bpp = forced_bpp;
+ drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
+ intel_dp->force_dsc_bpc);
+ } else {
+ drm_WARN(&dev_priv->drm, forced_bpp,
+ "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
+ intel_dp->force_dsc_bpc);
+
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
+ conn_state->max_requested_bpc);
+
+ if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Computed BPC less than min supported by source for DSC\n");
+ return -EINVAL;
+ }
+ }
+
+ pipe_config->pipe_bpp = pipe_bpp;
}
/*
- * For now enable DSC for max bpp, max link rate, max lane count.
+ * For now enable DSC for max link rate, max lane count.
* Optimize this later for the minimum possible link rate/lane count
* with DSC enabled for the requested mode.
*/
- pipe_config->pipe_bpp = pipe_bpp;
pipe_config->port_clock = limits->max_rate;
pipe_config->lane_count = limits->max_lane_count;
@@ -1768,7 +1782,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
adjusted_mode->crtc_hdisplay,
pipe_config->bigjoiner_pipes,
pipe_config->output_format,
- pipe_bpp,
+ pipe_config->pipe_bpp,
timeslots);
if (!dsc_max_compressed_bpp) {
drm_dbg_kms(&dev_priv->drm,
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [Intel-gfx] [PATCH 13/19] drm/i915/dp: Avoid left shift of DSC output bpp by 4
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-13 10:33 ` Ankit Nautiyal
-1 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel
To make way for fractional bpp support, avoid left shifting the
output_bpp by 4 in helper intel_dp_dsc_get_output_bpp.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++-------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9d2d05da594b..a7d58eb914c6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -812,11 +812,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
- /*
- * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
- * fractional part is 0
- */
- return bits_per_pixel << 4;
+ return bits_per_pixel;
}
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
@@ -1206,7 +1202,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
mode->hdisplay,
bigjoiner,
output_format,
- pipe_bpp, 64) >> 4;
+ pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1812,7 +1808,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->pipe_bpp);
pipe_config->dsc.compressed_bpp = min_t(u16,
- dsc_max_compressed_bpp >> 4,
+ dsc_max_compressed_bpp,
output_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index dff4717edbd0..4895d6242915 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -982,7 +982,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
mode->hdisplay,
bigjoiner,
INTEL_OUTPUT_FORMAT_RGB,
- pipe_bpp, 64) >> 4;
+ pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH 13/19] drm/i915/dp: Avoid left shift of DSC output bpp by 4
@ 2023-07-13 10:33 ` Ankit Nautiyal
0 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
To make way for fractional bpp support, avoid left shifting the
output_bpp by 4 in helper intel_dp_dsc_get_output_bpp.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++-------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9d2d05da594b..a7d58eb914c6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -812,11 +812,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
- /*
- * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
- * fractional part is 0
- */
- return bits_per_pixel << 4;
+ return bits_per_pixel;
}
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
@@ -1206,7 +1202,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
mode->hdisplay,
bigjoiner,
output_format,
- pipe_bpp, 64) >> 4;
+ pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1812,7 +1808,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->pipe_bpp);
pipe_config->dsc.compressed_bpp = min_t(u16,
- dsc_max_compressed_bpp >> 4,
+ dsc_max_compressed_bpp,
output_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index dff4717edbd0..4895d6242915 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -982,7 +982,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
mode->hdisplay,
bigjoiner,
INTEL_OUTPUT_FORMAT_RGB,
- pipe_bpp, 64) >> 4;
+ pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [Intel-gfx] [PATCH 13/19] drm/i915/dp: Avoid left shift of DSC output bpp by 4
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-20 9:31 ` Lisovskiy, Stanislav
-1 siblings, 0 replies; 72+ messages in thread
From: Lisovskiy, Stanislav @ 2023-07-20 9:31 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, dri-devel
On Thu, Jul 13, 2023 at 04:03:40PM +0530, Ankit Nautiyal wrote:
> To make way for fractional bpp support, avoid left shifting the
> output_bpp by 4 in helper intel_dp_dsc_get_output_bpp.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 10 +++-------
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> 2 files changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9d2d05da594b..a7d58eb914c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -812,11 +812,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
>
> bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
>
> - /*
> - * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
> - * fractional part is 0
> - */
> - return bits_per_pixel << 4;
> + return bits_per_pixel;
> }
>
> u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> @@ -1206,7 +1202,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
> mode->hdisplay,
> bigjoiner,
> output_format,
> - pipe_bpp, 64) >> 4;
> + pipe_bpp, 64);
> dsc_slice_count =
> intel_dp_dsc_get_slice_count(intel_dp,
> target_clock,
> @@ -1812,7 +1808,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> pipe_config->pipe_bpp);
>
> pipe_config->dsc.compressed_bpp = min_t(u16,
> - dsc_max_compressed_bpp >> 4,
> + dsc_max_compressed_bpp,
> output_bpp);
> }
> pipe_config->dsc.slice_count = dsc_dp_slice_count;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index dff4717edbd0..4895d6242915 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -982,7 +982,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
> mode->hdisplay,
> bigjoiner,
> INTEL_OUTPUT_FORMAT_RGB,
> - pipe_bpp, 64) >> 4;
> + pipe_bpp, 64);
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> dsc_slice_count =
> intel_dp_dsc_get_slice_count(intel_dp,
> target_clock,
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH 13/19] drm/i915/dp: Avoid left shift of DSC output bpp by 4
@ 2023-07-20 9:31 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 72+ messages in thread
From: Lisovskiy, Stanislav @ 2023-07-20 9:31 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, anusha.srivatsa, dri-devel, navaremanasi
On Thu, Jul 13, 2023 at 04:03:40PM +0530, Ankit Nautiyal wrote:
> To make way for fractional bpp support, avoid left shifting the
> output_bpp by 4 in helper intel_dp_dsc_get_output_bpp.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 10 +++-------
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> 2 files changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9d2d05da594b..a7d58eb914c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -812,11 +812,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
>
> bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
>
> - /*
> - * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
> - * fractional part is 0
> - */
> - return bits_per_pixel << 4;
> + return bits_per_pixel;
> }
>
> u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> @@ -1206,7 +1202,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
> mode->hdisplay,
> bigjoiner,
> output_format,
> - pipe_bpp, 64) >> 4;
> + pipe_bpp, 64);
> dsc_slice_count =
> intel_dp_dsc_get_slice_count(intel_dp,
> target_clock,
> @@ -1812,7 +1808,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> pipe_config->pipe_bpp);
>
> pipe_config->dsc.compressed_bpp = min_t(u16,
> - dsc_max_compressed_bpp >> 4,
> + dsc_max_compressed_bpp,
> output_bpp);
> }
> pipe_config->dsc.slice_count = dsc_dp_slice_count;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index dff4717edbd0..4895d6242915 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -982,7 +982,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
> mode->hdisplay,
> bigjoiner,
> INTEL_OUTPUT_FORMAT_RGB,
> - pipe_bpp, 64) >> 4;
> + pipe_bpp, 64);
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> dsc_slice_count =
> intel_dp_dsc_get_slice_count(intel_dp,
> target_clock,
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 72+ messages in thread
* [Intel-gfx] [PATCH 14/19] drm/i915/dp: Rename helper to get DSC max pipe_bpp
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-13 10:33 ` Ankit Nautiyal
-1 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel
The helper intel_dp_dsc_compute_bpp gives the maximum
pipe bpp that is allowed with DSC.
Rename the this to reflect that it returns max pipe bpp supported
with DSC.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++----
drivers/gpu/drm/i915/display/intel_dp.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a7d58eb914c6..c437ec23698a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1181,7 +1181,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be picked
*/
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX);
/*
* Output bpp is stored in 6.4 format so right shift by 4 to get the
@@ -1541,7 +1541,7 @@ u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
return 0;
}
-int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
+int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i, num_bpc;
@@ -1732,8 +1732,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
"Cannot force DSC BPC:%d, due to DSC BPC limits\n",
intel_dp->force_dsc_bpc);
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
- conn_state->max_requested_bpc);
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
+ conn_state->max_requested_bpc);
if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 6fd423463f5c..788a577ebe16 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -106,7 +106,7 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
unsigned int type);
bool intel_digital_port_connected(struct intel_encoder *encoder);
-int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
+int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 4895d6242915..3eb085fbc7c8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -971,7 +971,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be picked
*/
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX);
if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
dsc_max_compressed_bpp =
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH 14/19] drm/i915/dp: Rename helper to get DSC max pipe_bpp
@ 2023-07-13 10:33 ` Ankit Nautiyal
0 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
The helper intel_dp_dsc_compute_bpp gives the maximum
pipe bpp that is allowed with DSC.
Rename the this to reflect that it returns max pipe bpp supported
with DSC.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++----
drivers/gpu/drm/i915/display/intel_dp.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a7d58eb914c6..c437ec23698a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1181,7 +1181,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be picked
*/
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX);
/*
* Output bpp is stored in 6.4 format so right shift by 4 to get the
@@ -1541,7 +1541,7 @@ u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
return 0;
}
-int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
+int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i, num_bpc;
@@ -1732,8 +1732,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
"Cannot force DSC BPC:%d, due to DSC BPC limits\n",
intel_dp->force_dsc_bpc);
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
- conn_state->max_requested_bpc);
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
+ conn_state->max_requested_bpc);
if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 6fd423463f5c..788a577ebe16 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -106,7 +106,7 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
unsigned int type);
bool intel_digital_port_connected(struct intel_encoder *encoder);
-int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
+int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 4895d6242915..3eb085fbc7c8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -971,7 +971,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be picked
*/
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX);
if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
dsc_max_compressed_bpp =
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [Intel-gfx] [PATCH 15/19] drm/i915/dp: Separate out functions for edp/DP for computing DSC bpp
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-13 10:33 ` Ankit Nautiyal
-1 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel
Refactor code to separate functions for eDP and DP for computing
pipe_bpp/compressed bpp when DSC is involved.
This will help to optimize the link configuration for DP later.
v2: Fix checkpatch warning.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 191 ++++++++++++++++--------
1 file changed, 126 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c437ec23698a..c925cae40c49 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1697,6 +1697,115 @@ bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;
}
+static
+int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int forced_bpp;
+
+ if (!intel_dp->force_dsc_bpc)
+ return 0;
+
+ forced_bpp = intel_dp->force_dsc_bpc * 3;
+
+ if (is_dsc_pipe_bpp_sufficient(i915, forced_bpp)) {
+ drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
+ return forced_bpp;
+ }
+
+ drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
+ intel_dp->force_dsc_bpc);
+
+ return 0;
+}
+
+static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state,
+ struct link_config_limits *limits,
+ int timeslots)
+{
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u16 output_bpp, dsc_max_compressed_bpp = 0;
+ int forced_bpp, pipe_bpp;
+
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+
+ if (forced_bpp) {
+ pipe_bpp = forced_bpp;
+ } else {
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, conn_state->max_requested_bpc);
+
+ if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ drm_dbg_kms(&i915->drm,
+ "Computed BPC less than min supported by source for DSC\n");
+ return -EINVAL;
+ }
+ }
+ /*
+ * For now enable DSC for max link rate, max lane count.
+ * Optimize this later for the minimum possible link rate/lane count
+ * with DSC enabled for the requested mode.
+ */
+ pipe_config->port_clock = limits->max_rate;
+ pipe_config->lane_count = limits->max_lane_count;
+ dsc_max_compressed_bpp = intel_dp_dsc_get_max_compressed_bpp(i915,
+ pipe_config->port_clock,
+ pipe_config->lane_count,
+ adjusted_mode->crtc_clock,
+ adjusted_mode->crtc_hdisplay,
+ pipe_config->bigjoiner_pipes,
+ pipe_config->output_format,
+ pipe_bpp,
+ timeslots);
+ if (!dsc_max_compressed_bpp) {
+ drm_dbg_kms(&i915->drm, "Compressed BPP not supported\n");
+ return -EINVAL;
+ }
+
+ output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp);
+
+ pipe_config->dsc.compressed_bpp = min_t(u16, dsc_max_compressed_bpp, output_bpp);
+
+ pipe_config->pipe_bpp = pipe_bpp;
+
+ return 0;
+}
+
+static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state,
+ struct link_config_limits *limits)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int pipe_bpp, forced_bpp;
+
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+
+ if (forced_bpp) {
+ pipe_bpp = forced_bpp;
+ } else {
+ /* For eDP use max bpp that can be supported with DSC. */
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
+ conn_state->max_requested_bpc);
+ if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ drm_dbg_kms(&i915->drm,
+ "Computed BPC less than min supported by source for DSC\n");
+ return -EINVAL;
+ }
+ }
+ pipe_config->port_clock = limits->max_rate;
+ pipe_config->lane_count = limits->max_lane_count;
+ pipe_config->dsc.compressed_bpp =
+ min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
+ pipe_bpp);
+
+ pipe_config->pipe_bpp = pipe_bpp;
+
+ return 0;
+}
+
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1719,44 +1828,28 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
return -EINVAL;
+ /*
+ * compute pipe bpp is set to false for DP MST DSC case
+ * and compressed_bpp is calculated same time once
+ * vpci timeslots are allocated, because overall bpp
+ * calculation procedure is bit different for MST case.
+ */
if (compute_pipe_bpp) {
- int pipe_bpp;
- int forced_bpp = intel_dp->force_dsc_bpc * 3;
-
- if (forced_bpp && is_dsc_pipe_bpp_sufficient(dev_priv, forced_bpp)) {
- pipe_bpp = forced_bpp;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
- intel_dp->force_dsc_bpc);
- } else {
- drm_WARN(&dev_priv->drm, forced_bpp,
- "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
- intel_dp->force_dsc_bpc);
-
- pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
- conn_state->max_requested_bpc);
-
- if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
- drm_dbg_kms(&dev_priv->drm,
- "Computed BPC less than min supported by source for DSC\n");
- return -EINVAL;
- }
+ if (intel_dp_is_edp(intel_dp))
+ ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
+ conn_state, limits);
+ else
+ ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
+ conn_state, limits, timeslots);
+ if (ret) {
+ drm_dbg_kms(&dev_priv->drm,
+ "No Valid pipe bpp for given mode ret = %d\n", ret);
+ return ret;
}
-
- pipe_config->pipe_bpp = pipe_bpp;
}
- /*
- * For now enable DSC for max link rate, max lane count.
- * Optimize this later for the minimum possible link rate/lane count
- * with DSC enabled for the requested mode.
- */
- pipe_config->port_clock = limits->max_rate;
- pipe_config->lane_count = limits->max_lane_count;
-
+ /* Calculate Slice count */
if (intel_dp_is_edp(intel_dp)) {
- pipe_config->dsc.compressed_bpp =
- min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
- pipe_config->pipe_bpp);
pipe_config->dsc.slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
@@ -1766,26 +1859,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return -EINVAL;
}
} else {
- u16 dsc_max_compressed_bpp = 0;
u8 dsc_dp_slice_count;
- if (compute_pipe_bpp) {
- dsc_max_compressed_bpp =
- intel_dp_dsc_get_max_compressed_bpp(dev_priv,
- pipe_config->port_clock,
- pipe_config->lane_count,
- adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay,
- pipe_config->bigjoiner_pipes,
- pipe_config->output_format,
- pipe_config->pipe_bpp,
- timeslots);
- if (!dsc_max_compressed_bpp) {
- drm_dbg_kms(&dev_priv->drm,
- "Compressed BPP not supported\n");
- return -EINVAL;
- }
- }
dsc_dp_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
adjusted_mode->crtc_clock,
@@ -1797,20 +1872,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return -EINVAL;
}
- /*
- * compute pipe bpp is set to false for DP MST DSC case
- * and compressed_bpp is calculated same time once
- * vpci timeslots are allocated, because overall bpp
- * calculation procedure is bit different for MST case.
- */
- if (compute_pipe_bpp) {
- u16 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
- pipe_config->pipe_bpp);
-
- pipe_config->dsc.compressed_bpp = min_t(u16,
- dsc_max_compressed_bpp,
- output_bpp);
- }
pipe_config->dsc.slice_count = dsc_dp_slice_count;
}
/*
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH 15/19] drm/i915/dp: Separate out functions for edp/DP for computing DSC bpp
@ 2023-07-13 10:33 ` Ankit Nautiyal
0 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
Refactor code to separate functions for eDP and DP for computing
pipe_bpp/compressed bpp when DSC is involved.
This will help to optimize the link configuration for DP later.
v2: Fix checkpatch warning.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 191 ++++++++++++++++--------
1 file changed, 126 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c437ec23698a..c925cae40c49 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1697,6 +1697,115 @@ bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;
}
+static
+int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int forced_bpp;
+
+ if (!intel_dp->force_dsc_bpc)
+ return 0;
+
+ forced_bpp = intel_dp->force_dsc_bpc * 3;
+
+ if (is_dsc_pipe_bpp_sufficient(i915, forced_bpp)) {
+ drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
+ return forced_bpp;
+ }
+
+ drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
+ intel_dp->force_dsc_bpc);
+
+ return 0;
+}
+
+static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state,
+ struct link_config_limits *limits,
+ int timeslots)
+{
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u16 output_bpp, dsc_max_compressed_bpp = 0;
+ int forced_bpp, pipe_bpp;
+
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+
+ if (forced_bpp) {
+ pipe_bpp = forced_bpp;
+ } else {
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, conn_state->max_requested_bpc);
+
+ if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ drm_dbg_kms(&i915->drm,
+ "Computed BPC less than min supported by source for DSC\n");
+ return -EINVAL;
+ }
+ }
+ /*
+ * For now enable DSC for max link rate, max lane count.
+ * Optimize this later for the minimum possible link rate/lane count
+ * with DSC enabled for the requested mode.
+ */
+ pipe_config->port_clock = limits->max_rate;
+ pipe_config->lane_count = limits->max_lane_count;
+ dsc_max_compressed_bpp = intel_dp_dsc_get_max_compressed_bpp(i915,
+ pipe_config->port_clock,
+ pipe_config->lane_count,
+ adjusted_mode->crtc_clock,
+ adjusted_mode->crtc_hdisplay,
+ pipe_config->bigjoiner_pipes,
+ pipe_config->output_format,
+ pipe_bpp,
+ timeslots);
+ if (!dsc_max_compressed_bpp) {
+ drm_dbg_kms(&i915->drm, "Compressed BPP not supported\n");
+ return -EINVAL;
+ }
+
+ output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp);
+
+ pipe_config->dsc.compressed_bpp = min_t(u16, dsc_max_compressed_bpp, output_bpp);
+
+ pipe_config->pipe_bpp = pipe_bpp;
+
+ return 0;
+}
+
+static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state,
+ struct link_config_limits *limits)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int pipe_bpp, forced_bpp;
+
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+
+ if (forced_bpp) {
+ pipe_bpp = forced_bpp;
+ } else {
+ /* For eDP use max bpp that can be supported with DSC. */
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
+ conn_state->max_requested_bpc);
+ if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ drm_dbg_kms(&i915->drm,
+ "Computed BPC less than min supported by source for DSC\n");
+ return -EINVAL;
+ }
+ }
+ pipe_config->port_clock = limits->max_rate;
+ pipe_config->lane_count = limits->max_lane_count;
+ pipe_config->dsc.compressed_bpp =
+ min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
+ pipe_bpp);
+
+ pipe_config->pipe_bpp = pipe_bpp;
+
+ return 0;
+}
+
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1719,44 +1828,28 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
return -EINVAL;
+ /*
+ * compute pipe bpp is set to false for DP MST DSC case
+ * and compressed_bpp is calculated same time once
+ * vpci timeslots are allocated, because overall bpp
+ * calculation procedure is bit different for MST case.
+ */
if (compute_pipe_bpp) {
- int pipe_bpp;
- int forced_bpp = intel_dp->force_dsc_bpc * 3;
-
- if (forced_bpp && is_dsc_pipe_bpp_sufficient(dev_priv, forced_bpp)) {
- pipe_bpp = forced_bpp;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
- intel_dp->force_dsc_bpc);
- } else {
- drm_WARN(&dev_priv->drm, forced_bpp,
- "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
- intel_dp->force_dsc_bpc);
-
- pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
- conn_state->max_requested_bpc);
-
- if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
- drm_dbg_kms(&dev_priv->drm,
- "Computed BPC less than min supported by source for DSC\n");
- return -EINVAL;
- }
+ if (intel_dp_is_edp(intel_dp))
+ ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
+ conn_state, limits);
+ else
+ ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
+ conn_state, limits, timeslots);
+ if (ret) {
+ drm_dbg_kms(&dev_priv->drm,
+ "No Valid pipe bpp for given mode ret = %d\n", ret);
+ return ret;
}
-
- pipe_config->pipe_bpp = pipe_bpp;
}
- /*
- * For now enable DSC for max link rate, max lane count.
- * Optimize this later for the minimum possible link rate/lane count
- * with DSC enabled for the requested mode.
- */
- pipe_config->port_clock = limits->max_rate;
- pipe_config->lane_count = limits->max_lane_count;
-
+ /* Calculate Slice count */
if (intel_dp_is_edp(intel_dp)) {
- pipe_config->dsc.compressed_bpp =
- min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
- pipe_config->pipe_bpp);
pipe_config->dsc.slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
@@ -1766,26 +1859,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return -EINVAL;
}
} else {
- u16 dsc_max_compressed_bpp = 0;
u8 dsc_dp_slice_count;
- if (compute_pipe_bpp) {
- dsc_max_compressed_bpp =
- intel_dp_dsc_get_max_compressed_bpp(dev_priv,
- pipe_config->port_clock,
- pipe_config->lane_count,
- adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay,
- pipe_config->bigjoiner_pipes,
- pipe_config->output_format,
- pipe_config->pipe_bpp,
- timeslots);
- if (!dsc_max_compressed_bpp) {
- drm_dbg_kms(&dev_priv->drm,
- "Compressed BPP not supported\n");
- return -EINVAL;
- }
- }
dsc_dp_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
adjusted_mode->crtc_clock,
@@ -1797,20 +1872,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return -EINVAL;
}
- /*
- * compute pipe bpp is set to false for DP MST DSC case
- * and compressed_bpp is calculated same time once
- * vpci timeslots are allocated, because overall bpp
- * calculation procedure is bit different for MST case.
- */
- if (compute_pipe_bpp) {
- u16 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
- pipe_config->pipe_bpp);
-
- pipe_config->dsc.compressed_bpp = min_t(u16,
- dsc_max_compressed_bpp,
- output_bpp);
- }
pipe_config->dsc.slice_count = dsc_dp_slice_count;
}
/*
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [Intel-gfx] [PATCH 16/19] drm/i915/dp: Add DSC BPC/BPP constraints while selecting pipe bpp with DSC
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-13 10:33 ` Ankit Nautiyal
-1 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel
Currently we check if the pipe_bpp selected is >= the
min DSC bpc/bpp requirement. We do not check if it is <= the max DSC
bpc/bpp requirement.
Add checks for max DSC BPC/BPP constraints while computing the
pipe_bpp when DSC is in use.
v2: Fix the commit message.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 34 +++++++++++++++++--------
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c925cae40c49..c39039e214ff 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1692,13 +1692,27 @@ u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
}
static
-bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
+bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
+ struct drm_connector_state *conn_state,
+ struct link_config_limits *limits,
+ int pipe_bpp)
{
- return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;
+ u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
+
+ dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);
+ dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
+
+ dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->max_bpp);
+ dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->min_bpp);
+
+ return pipe_bpp >= dsc_min_pipe_bpp &&
+ pipe_bpp <= dsc_max_pipe_bpp;
}
static
-int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp)
+int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
+ struct drm_connector_state *conn_state,
+ struct link_config_limits *limits)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int forced_bpp;
@@ -1708,7 +1722,7 @@ int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp)
forced_bpp = intel_dp->force_dsc_bpc * 3;
- if (is_dsc_pipe_bpp_sufficient(i915, forced_bpp)) {
+ if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) {
drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
return forced_bpp;
}
@@ -1730,16 +1744,16 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
u16 output_bpp, dsc_max_compressed_bpp = 0;
int forced_bpp, pipe_bpp;
- forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
if (forced_bpp) {
pipe_bpp = forced_bpp;
} else {
pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, conn_state->max_requested_bpc);
- if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
drm_dbg_kms(&i915->drm,
- "Computed BPC less than min supported by source for DSC\n");
+ "Computed BPC is not in DSC BPC limits\n");
return -EINVAL;
}
}
@@ -1781,7 +1795,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int pipe_bpp, forced_bpp;
- forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
if (forced_bpp) {
pipe_bpp = forced_bpp;
@@ -1789,9 +1803,9 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
/* For eDP use max bpp that can be supported with DSC. */
pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
conn_state->max_requested_bpc);
- if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
drm_dbg_kms(&i915->drm,
- "Computed BPC less than min supported by source for DSC\n");
+ "Computed BPC is not in DSC BPC limits\n");
return -EINVAL;
}
}
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH 16/19] drm/i915/dp: Add DSC BPC/BPP constraints while selecting pipe bpp with DSC
@ 2023-07-13 10:33 ` Ankit Nautiyal
0 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
Currently we check if the pipe_bpp selected is >= the
min DSC bpc/bpp requirement. We do not check if it is <= the max DSC
bpc/bpp requirement.
Add checks for max DSC BPC/BPP constraints while computing the
pipe_bpp when DSC is in use.
v2: Fix the commit message.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 34 +++++++++++++++++--------
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c925cae40c49..c39039e214ff 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1692,13 +1692,27 @@ u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
}
static
-bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
+bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
+ struct drm_connector_state *conn_state,
+ struct link_config_limits *limits,
+ int pipe_bpp)
{
- return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;
+ u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
+
+ dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);
+ dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
+
+ dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->max_bpp);
+ dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->min_bpp);
+
+ return pipe_bpp >= dsc_min_pipe_bpp &&
+ pipe_bpp <= dsc_max_pipe_bpp;
}
static
-int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp)
+int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
+ struct drm_connector_state *conn_state,
+ struct link_config_limits *limits)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int forced_bpp;
@@ -1708,7 +1722,7 @@ int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp)
forced_bpp = intel_dp->force_dsc_bpc * 3;
- if (is_dsc_pipe_bpp_sufficient(i915, forced_bpp)) {
+ if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) {
drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
return forced_bpp;
}
@@ -1730,16 +1744,16 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
u16 output_bpp, dsc_max_compressed_bpp = 0;
int forced_bpp, pipe_bpp;
- forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
if (forced_bpp) {
pipe_bpp = forced_bpp;
} else {
pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, conn_state->max_requested_bpc);
- if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
drm_dbg_kms(&i915->drm,
- "Computed BPC less than min supported by source for DSC\n");
+ "Computed BPC is not in DSC BPC limits\n");
return -EINVAL;
}
}
@@ -1781,7 +1795,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int pipe_bpp, forced_bpp;
- forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
if (forced_bpp) {
pipe_bpp = forced_bpp;
@@ -1789,9 +1803,9 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
/* For eDP use max bpp that can be supported with DSC. */
pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
conn_state->max_requested_bpc);
- if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
drm_dbg_kms(&i915->drm,
- "Computed BPC less than min supported by source for DSC\n");
+ "Computed BPC is not in DSC BPC limits\n");
return -EINVAL;
}
}
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [Intel-gfx] [PATCH 17/19] drm/i915/dp: Separate out function to get compressed bpp with joiner
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-13 10:33 ` Ankit Nautiyal
-1 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel
Pull the code to get joiner constraints on maximum compressed bpp into
separate function.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 49 ++++++++++++++-----------
1 file changed, 28 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c39039e214ff..54fc60eb94a0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -740,6 +740,30 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p
return bits_per_pixel;
}
+static
+u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner)
+{
+ u32 max_bpp_small_joiner_ram;
+
+ /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
+ max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay;
+
+ if (bigjoiner) {
+ int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
+ u32 max_bpp_bigjoiner =
+ i915->display.cdclk.max_cdclk_freq * 2 * bigjoiner_interface_bits /
+ intel_dp_mode_to_fec_clock(mode_clock);
+
+ max_bpp_small_joiner_ram *= 2;
+
+ return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner);
+ }
+
+ return max_bpp_small_joiner_ram;
+}
+
u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
@@ -748,7 +772,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
u32 pipe_bpp,
u32 timeslots)
{
- u32 bits_per_pixel, max_bpp_small_joiner_ram;
+ u32 bits_per_pixel, joiner_max_bpp;
/*
* Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
@@ -788,27 +812,10 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
(link_clock * lane_count * 8),
intel_dp_mode_to_fec_clock(mode_clock));
- /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
- max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
- mode_hdisplay;
-
- if (bigjoiner)
- max_bpp_small_joiner_ram *= 2;
-
- /*
- * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
- * check, output bpp from small joiner RAM check)
- */
- bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
+ joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,
+ mode_hdisplay, bigjoiner);
- if (bigjoiner) {
- int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
- u32 max_bpp_bigjoiner =
- i915->display.cdclk.max_cdclk_freq * 2 * bigjoiner_interface_bits /
- intel_dp_mode_to_fec_clock(mode_clock);
-
- bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
- }
+ bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH 17/19] drm/i915/dp: Separate out function to get compressed bpp with joiner
@ 2023-07-13 10:33 ` Ankit Nautiyal
0 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
Pull the code to get joiner constraints on maximum compressed bpp into
separate function.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 49 ++++++++++++++-----------
1 file changed, 28 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c39039e214ff..54fc60eb94a0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -740,6 +740,30 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p
return bits_per_pixel;
}
+static
+u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner)
+{
+ u32 max_bpp_small_joiner_ram;
+
+ /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
+ max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay;
+
+ if (bigjoiner) {
+ int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
+ u32 max_bpp_bigjoiner =
+ i915->display.cdclk.max_cdclk_freq * 2 * bigjoiner_interface_bits /
+ intel_dp_mode_to_fec_clock(mode_clock);
+
+ max_bpp_small_joiner_ram *= 2;
+
+ return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner);
+ }
+
+ return max_bpp_small_joiner_ram;
+}
+
u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
@@ -748,7 +772,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
u32 pipe_bpp,
u32 timeslots)
{
- u32 bits_per_pixel, max_bpp_small_joiner_ram;
+ u32 bits_per_pixel, joiner_max_bpp;
/*
* Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
@@ -788,27 +812,10 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
(link_clock * lane_count * 8),
intel_dp_mode_to_fec_clock(mode_clock));
- /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
- max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
- mode_hdisplay;
-
- if (bigjoiner)
- max_bpp_small_joiner_ram *= 2;
-
- /*
- * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
- * check, output bpp from small joiner RAM check)
- */
- bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
+ joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,
+ mode_hdisplay, bigjoiner);
- if (bigjoiner) {
- int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
- u32 max_bpp_bigjoiner =
- i915->display.cdclk.max_cdclk_freq * 2 * bigjoiner_interface_bits /
- intel_dp_mode_to_fec_clock(mode_clock);
-
- bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
- }
+ bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [Intel-gfx] [PATCH 18/19] drm/i915/dp: Get optimal link config to have best compressed bpp
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-13 10:33 ` Ankit Nautiyal
-1 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel
Currently, we take the max lane, rate and pipe bpp, to get the maximum
compressed bpp possible. We then set the output bpp to this value.
This patch provides support to have max bpp, min rate and min lanes,
that can support the min compressed bpp.
v2:
-Avoid ending up with compressed bpp, same as pipe bpp. (Stan)
-Fix the checks for limits->max/min_bpp while iterating over list of
valid DSC bpcs. (Stan)
v3:
-Refactor the code to have pipe bpp/compressed bpp computation and slice
count calculation separately for different cases.
v4:
-Separate the pipe_bpp calculation for eDP and DP.
v5:
-Get rid of magic numbers for max and min bpp,
and improve documentation. (Stan).
-Use functions for {src_sink}_{min_max}_compressed_bpp (Ville).
v6:
-Remove lines to set link config to max.
v7:
-Split the part to separate edp and dp functions for computing DSC BPP
into separate patch.
v8:
-Separate mechanism to get compressed bpp for ICL,TGL and XELPD+.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 294 +++++++++++++++++++++---
1 file changed, 261 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 54fc60eb94a0..25a6c162332f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1688,6 +1688,231 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
}
+static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
+ u32 lane_count, u32 mode_clock,
+ enum intel_output_format output_format,
+ int timeslots)
+{
+ u32 available_bw, required_bw;
+
+ available_bw = (link_clock * lane_count * timeslots) / 8;
+ required_bw = compressed_bpp * (intel_dp_mode_to_fec_clock(mode_clock));
+
+ return available_bw > required_bw;
+}
+
+static int dsc_compute_link_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ u16 compressed_bpp,
+ int timeslots)
+{
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+ int link_rate, lane_count;
+ int i;
+
+ for (i = 0; i < intel_dp->num_common_rates; i++) {
+ link_rate = intel_dp_common_rate(intel_dp, i);
+ if (link_rate < limits->min_rate || link_rate > limits->max_rate)
+ continue;
+
+ for (lane_count = limits->min_lane_count;
+ lane_count <= limits->max_lane_count;
+ lane_count <<= 1) {
+ if (!is_bw_sufficient_for_dsc_config(compressed_bpp, link_rate, lane_count,
+ adjusted_mode->clock,
+ pipe_config->output_format,
+ timeslots))
+ continue;
+
+ pipe_config->lane_count = lane_count;
+ pipe_config->port_clock = link_rate;
+
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static
+u16 intel_dp_dsc_max_sink_compressed_bppx16(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int bpc)
+{
+ u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd);
+
+ if (max_bppx16)
+ return max_bppx16;
+ /*
+ * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
+ * values as given in spec Table 2-157 DP v2.0
+ */
+ switch (pipe_config->output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ return (3 * bpc) << 4;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ return (3 * (bpc / 2)) << 4;
+ default:
+ MISSING_CASE(pipe_config->output_format);
+ break;
+ }
+
+ return 0;
+}
+
+static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
+{
+ /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
+ switch (pipe_config->output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ return 8;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ return 6;
+ default:
+ MISSING_CASE(pipe_config->output_format);
+ break;
+ }
+
+ return 0;
+}
+
+static int dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int bpc)
+{
+ return intel_dp_dsc_max_sink_compressed_bppx16(intel_dp,
+ pipe_config, bpc) >> 4;
+}
+
+static int dsc_src_min_compressed_bpp(void)
+{
+ /* Min Compressed bpp supported by source is 8 */
+ return 8;
+}
+
+static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ /*
+ * Max Compressed bpp for Gen 13+ is 27bpp.
+ * For earlier platform is 23bpp. (Bspec:49259).
+ */
+ if (DISPLAY_VER(i915) <= 12)
+ return 23;
+ else
+ return 27;
+}
+
+/*
+ * From a list of valid compressed bpps try different compressed bpp and find a
+ * suitable link configuration that can support it.
+ */
+static int
+icl_dsc_compute_link_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ int dsc_max_bpp,
+ int dsc_min_bpp,
+ int pipe_bpp,
+ int timeslots)
+{
+ int i, ret;
+
+ /* Compressed BPP should be less than the Input DSC bpp */
+ dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+
+ for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {
+ if (valid_dsc_bpp[i] < dsc_min_bpp ||
+ valid_dsc_bpp[i] > dsc_max_bpp)
+ break;
+
+ ret = dsc_compute_link_config(intel_dp,
+ pipe_config,
+ limits,
+ valid_dsc_bpp[i],
+ timeslots);
+ if (ret == 0) {
+ pipe_config->dsc.compressed_bpp = valid_dsc_bpp[i];
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+/*
+ * From XE_LPD onwards we supports compression bpps in steps of 1 up to
+ * uncompressed bpp-1. So we start from max compressed bpp and see if any
+ * link configuration is able to support that compressed bpp, if not we
+ * step down and check for lower compressed bpp.
+ */
+static int
+xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ int dsc_max_bpp,
+ int dsc_min_bpp,
+ int pipe_bpp,
+ int timeslots)
+{
+ u16 compressed_bpp;
+ int ret;
+
+ /* Compressed BPP should be less than the Input DSC bpp */
+ dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+
+ for (compressed_bpp = dsc_max_bpp;
+ compressed_bpp >= dsc_min_bpp;
+ compressed_bpp--) {
+ ret = dsc_compute_link_config(intel_dp,
+ pipe_config,
+ limits,
+ compressed_bpp,
+ timeslots);
+ if (ret == 0) {
+ pipe_config->dsc.compressed_bpp = compressed_bpp;
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
+static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ int pipe_bpp,
+ int timeslots)
+{
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
+ int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
+ int dsc_joiner_max_bpp;
+
+ dsc_src_min_bpp = dsc_src_min_compressed_bpp();
+ dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
+ dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
+
+ dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
+ dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3);
+ dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
+
+ dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
+ adjusted_mode->hdisplay,
+ pipe_config->bigjoiner_pipes);
+ dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
+
+ if (DISPLAY_VER(i915) >= 13)
+ return xelpd_dsc_compute_link_config(intel_dp, pipe_config, limits,
+ dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
+ return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,
+ dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
+}
+
static
u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
{
@@ -1746,52 +1971,55 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
struct link_config_limits *limits,
int timeslots)
{
- const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- u16 output_bpp, dsc_max_compressed_bpp = 0;
+ u8 max_req_bpc = conn_state->max_requested_bpc;
+ u8 dsc_max_bpc, dsc_max_bpp;
+ u8 dsc_min_bpc, dsc_min_bpp;
+ u8 dsc_bpc[3] = {0};
int forced_bpp, pipe_bpp;
+ int num_bpc, i, ret;
forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
if (forced_bpp) {
- pipe_bpp = forced_bpp;
- } else {
- pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, conn_state->max_requested_bpc);
-
- if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
- drm_dbg_kms(&i915->drm,
- "Computed BPC is not in DSC BPC limits\n");
- return -EINVAL;
+ ret = dsc_compute_compressed_bpp(intel_dp, pipe_config,
+ limits, forced_bpp, timeslots);
+ if (ret == 0) {
+ pipe_config->pipe_bpp = forced_bpp;
+ return 0;
}
}
- /*
- * For now enable DSC for max link rate, max lane count.
- * Optimize this later for the minimum possible link rate/lane count
- * with DSC enabled for the requested mode.
- */
- pipe_config->port_clock = limits->max_rate;
- pipe_config->lane_count = limits->max_lane_count;
- dsc_max_compressed_bpp = intel_dp_dsc_get_max_compressed_bpp(i915,
- pipe_config->port_clock,
- pipe_config->lane_count,
- adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay,
- pipe_config->bigjoiner_pipes,
- pipe_config->output_format,
- pipe_bpp,
- timeslots);
- if (!dsc_max_compressed_bpp) {
- drm_dbg_kms(&i915->drm, "Compressed BPP not supported\n");
+
+ dsc_max_bpc = intel_dp_dsc_min_src_input_bpc(i915);
+ if (!dsc_max_bpc)
return -EINVAL;
- }
- output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp);
+ dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
+ dsc_max_bpp = min(dsc_max_bpc * 3, limits->max_bpp);
- pipe_config->dsc.compressed_bpp = min_t(u16, dsc_max_compressed_bpp, output_bpp);
+ dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
+ dsc_min_bpp = max(dsc_min_bpc * 3, limits->min_bpp);
- pipe_config->pipe_bpp = pipe_bpp;
+ /*
+ * Get the maximum DSC bpc that will be supported by any valid
+ * link configuration and compressed bpp.
+ */
+ num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, dsc_bpc);
+ for (i = 0; i < num_bpc; i++) {
+ pipe_bpp = dsc_bpc[i] * 3;
+ if (pipe_bpp < dsc_min_bpp)
+ break;
+ if (pipe_bpp > dsc_max_bpp)
+ continue;
+ ret = dsc_compute_compressed_bpp(intel_dp, pipe_config,
+ limits, pipe_bpp, timeslots);
+ if (ret == 0) {
+ pipe_config->pipe_bpp = pipe_bpp;
+ return 0;
+ }
+ }
- return 0;
+ return -EINVAL;
}
static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH 18/19] drm/i915/dp: Get optimal link config to have best compressed bpp
@ 2023-07-13 10:33 ` Ankit Nautiyal
0 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
Currently, we take the max lane, rate and pipe bpp, to get the maximum
compressed bpp possible. We then set the output bpp to this value.
This patch provides support to have max bpp, min rate and min lanes,
that can support the min compressed bpp.
v2:
-Avoid ending up with compressed bpp, same as pipe bpp. (Stan)
-Fix the checks for limits->max/min_bpp while iterating over list of
valid DSC bpcs. (Stan)
v3:
-Refactor the code to have pipe bpp/compressed bpp computation and slice
count calculation separately for different cases.
v4:
-Separate the pipe_bpp calculation for eDP and DP.
v5:
-Get rid of magic numbers for max and min bpp,
and improve documentation. (Stan).
-Use functions for {src_sink}_{min_max}_compressed_bpp (Ville).
v6:
-Remove lines to set link config to max.
v7:
-Split the part to separate edp and dp functions for computing DSC BPP
into separate patch.
v8:
-Separate mechanism to get compressed bpp for ICL,TGL and XELPD+.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 294 +++++++++++++++++++++---
1 file changed, 261 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 54fc60eb94a0..25a6c162332f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1688,6 +1688,231 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
}
+static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
+ u32 lane_count, u32 mode_clock,
+ enum intel_output_format output_format,
+ int timeslots)
+{
+ u32 available_bw, required_bw;
+
+ available_bw = (link_clock * lane_count * timeslots) / 8;
+ required_bw = compressed_bpp * (intel_dp_mode_to_fec_clock(mode_clock));
+
+ return available_bw > required_bw;
+}
+
+static int dsc_compute_link_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ u16 compressed_bpp,
+ int timeslots)
+{
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+ int link_rate, lane_count;
+ int i;
+
+ for (i = 0; i < intel_dp->num_common_rates; i++) {
+ link_rate = intel_dp_common_rate(intel_dp, i);
+ if (link_rate < limits->min_rate || link_rate > limits->max_rate)
+ continue;
+
+ for (lane_count = limits->min_lane_count;
+ lane_count <= limits->max_lane_count;
+ lane_count <<= 1) {
+ if (!is_bw_sufficient_for_dsc_config(compressed_bpp, link_rate, lane_count,
+ adjusted_mode->clock,
+ pipe_config->output_format,
+ timeslots))
+ continue;
+
+ pipe_config->lane_count = lane_count;
+ pipe_config->port_clock = link_rate;
+
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static
+u16 intel_dp_dsc_max_sink_compressed_bppx16(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int bpc)
+{
+ u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd);
+
+ if (max_bppx16)
+ return max_bppx16;
+ /*
+ * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
+ * values as given in spec Table 2-157 DP v2.0
+ */
+ switch (pipe_config->output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ return (3 * bpc) << 4;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ return (3 * (bpc / 2)) << 4;
+ default:
+ MISSING_CASE(pipe_config->output_format);
+ break;
+ }
+
+ return 0;
+}
+
+static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
+{
+ /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
+ switch (pipe_config->output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ return 8;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ return 6;
+ default:
+ MISSING_CASE(pipe_config->output_format);
+ break;
+ }
+
+ return 0;
+}
+
+static int dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int bpc)
+{
+ return intel_dp_dsc_max_sink_compressed_bppx16(intel_dp,
+ pipe_config, bpc) >> 4;
+}
+
+static int dsc_src_min_compressed_bpp(void)
+{
+ /* Min Compressed bpp supported by source is 8 */
+ return 8;
+}
+
+static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ /*
+ * Max Compressed bpp for Gen 13+ is 27bpp.
+ * For earlier platform is 23bpp. (Bspec:49259).
+ */
+ if (DISPLAY_VER(i915) <= 12)
+ return 23;
+ else
+ return 27;
+}
+
+/*
+ * From a list of valid compressed bpps try different compressed bpp and find a
+ * suitable link configuration that can support it.
+ */
+static int
+icl_dsc_compute_link_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ int dsc_max_bpp,
+ int dsc_min_bpp,
+ int pipe_bpp,
+ int timeslots)
+{
+ int i, ret;
+
+ /* Compressed BPP should be less than the Input DSC bpp */
+ dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+
+ for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {
+ if (valid_dsc_bpp[i] < dsc_min_bpp ||
+ valid_dsc_bpp[i] > dsc_max_bpp)
+ break;
+
+ ret = dsc_compute_link_config(intel_dp,
+ pipe_config,
+ limits,
+ valid_dsc_bpp[i],
+ timeslots);
+ if (ret == 0) {
+ pipe_config->dsc.compressed_bpp = valid_dsc_bpp[i];
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+/*
+ * From XE_LPD onwards we supports compression bpps in steps of 1 up to
+ * uncompressed bpp-1. So we start from max compressed bpp and see if any
+ * link configuration is able to support that compressed bpp, if not we
+ * step down and check for lower compressed bpp.
+ */
+static int
+xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ int dsc_max_bpp,
+ int dsc_min_bpp,
+ int pipe_bpp,
+ int timeslots)
+{
+ u16 compressed_bpp;
+ int ret;
+
+ /* Compressed BPP should be less than the Input DSC bpp */
+ dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+
+ for (compressed_bpp = dsc_max_bpp;
+ compressed_bpp >= dsc_min_bpp;
+ compressed_bpp--) {
+ ret = dsc_compute_link_config(intel_dp,
+ pipe_config,
+ limits,
+ compressed_bpp,
+ timeslots);
+ if (ret == 0) {
+ pipe_config->dsc.compressed_bpp = compressed_bpp;
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
+static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ int pipe_bpp,
+ int timeslots)
+{
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
+ int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
+ int dsc_joiner_max_bpp;
+
+ dsc_src_min_bpp = dsc_src_min_compressed_bpp();
+ dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
+ dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
+
+ dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
+ dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3);
+ dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
+
+ dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
+ adjusted_mode->hdisplay,
+ pipe_config->bigjoiner_pipes);
+ dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
+
+ if (DISPLAY_VER(i915) >= 13)
+ return xelpd_dsc_compute_link_config(intel_dp, pipe_config, limits,
+ dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
+ return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,
+ dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
+}
+
static
u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
{
@@ -1746,52 +1971,55 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
struct link_config_limits *limits,
int timeslots)
{
- const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- u16 output_bpp, dsc_max_compressed_bpp = 0;
+ u8 max_req_bpc = conn_state->max_requested_bpc;
+ u8 dsc_max_bpc, dsc_max_bpp;
+ u8 dsc_min_bpc, dsc_min_bpp;
+ u8 dsc_bpc[3] = {0};
int forced_bpp, pipe_bpp;
+ int num_bpc, i, ret;
forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
if (forced_bpp) {
- pipe_bpp = forced_bpp;
- } else {
- pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, conn_state->max_requested_bpc);
-
- if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
- drm_dbg_kms(&i915->drm,
- "Computed BPC is not in DSC BPC limits\n");
- return -EINVAL;
+ ret = dsc_compute_compressed_bpp(intel_dp, pipe_config,
+ limits, forced_bpp, timeslots);
+ if (ret == 0) {
+ pipe_config->pipe_bpp = forced_bpp;
+ return 0;
}
}
- /*
- * For now enable DSC for max link rate, max lane count.
- * Optimize this later for the minimum possible link rate/lane count
- * with DSC enabled for the requested mode.
- */
- pipe_config->port_clock = limits->max_rate;
- pipe_config->lane_count = limits->max_lane_count;
- dsc_max_compressed_bpp = intel_dp_dsc_get_max_compressed_bpp(i915,
- pipe_config->port_clock,
- pipe_config->lane_count,
- adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay,
- pipe_config->bigjoiner_pipes,
- pipe_config->output_format,
- pipe_bpp,
- timeslots);
- if (!dsc_max_compressed_bpp) {
- drm_dbg_kms(&i915->drm, "Compressed BPP not supported\n");
+
+ dsc_max_bpc = intel_dp_dsc_min_src_input_bpc(i915);
+ if (!dsc_max_bpc)
return -EINVAL;
- }
- output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp);
+ dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
+ dsc_max_bpp = min(dsc_max_bpc * 3, limits->max_bpp);
- pipe_config->dsc.compressed_bpp = min_t(u16, dsc_max_compressed_bpp, output_bpp);
+ dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
+ dsc_min_bpp = max(dsc_min_bpc * 3, limits->min_bpp);
- pipe_config->pipe_bpp = pipe_bpp;
+ /*
+ * Get the maximum DSC bpc that will be supported by any valid
+ * link configuration and compressed bpp.
+ */
+ num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, dsc_bpc);
+ for (i = 0; i < num_bpc; i++) {
+ pipe_bpp = dsc_bpc[i] * 3;
+ if (pipe_bpp < dsc_min_bpp)
+ break;
+ if (pipe_bpp > dsc_max_bpp)
+ continue;
+ ret = dsc_compute_compressed_bpp(intel_dp, pipe_config,
+ limits, pipe_bpp, timeslots);
+ if (ret == 0) {
+ pipe_config->pipe_bpp = pipe_bpp;
+ return 0;
+ }
+ }
- return 0;
+ return -EINVAL;
}
static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [Intel-gfx] [PATCH 19/19] drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info
2023-07-13 10:33 ` Ankit Nautiyal
@ 2023-07-13 10:33 ` Ankit Nautiyal
-1 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Currently we seem to be using wrong DPCD register for reading
compressed bpps, reading min/max input bpc instead of compressed bpp.
Fix that, so that we now apply min/max compressed bpp limitations we
get from DP Spec Table 2-157 DP v2.0 and/or correspondent DPCD
register DP_DSC_MAX_BITS_PER_PIXEL_LOW/HIGH.
This might also allow us to get rid of an ugly compressed bpp
recalculation, which we had to add to make some MST hubs usable.
v2: - Fix operator precedence
v3: - Added debug info about compressed bpps
v4: - Don't try to intersect Sink input bpp and compressed bpps.
v5: - Decrease step while looking for suitable compressed bpp to
accommodate.
v6: - Use helper for getting min and max compressed_bpp (Ankit)
v7: - Fix checkpatch warning (Ankit)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +++---
drivers/gpu/drm/i915/display/intel_dp.h | 4 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 47 +++++++++------------
3 files changed, 32 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 25a6c162332f..ce8b28ca1cfa 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1762,7 +1762,7 @@ u16 intel_dp_dsc_max_sink_compressed_bppx16(struct intel_dp *intel_dp,
return 0;
}
-static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
+int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
{
/* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
switch (pipe_config->output_format) {
@@ -1779,9 +1779,9 @@ static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
return 0;
}
-static int dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
- struct intel_crtc_state *pipe_config,
- int bpc)
+int intel_dp_dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int bpc)
{
return intel_dp_dsc_max_sink_compressed_bppx16(intel_dp,
pipe_config, bpc) >> 4;
@@ -1894,11 +1894,13 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
int dsc_joiner_max_bpp;
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
- dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
+ dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
- dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3);
+ dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(intel_dp,
+ pipe_config,
+ pipe_bpp / 3);
dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 788a577ebe16..f29e48028f39 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -114,6 +114,10 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
enum intel_output_format output_format,
u32 pipe_bpp,
u32 timeslots);
+int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config);
+int intel_dp_dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int bpc);
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
int mode_clock, int mode_hdisplay,
bool bigjoiner);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 3eb085fbc7c8..06a456517383 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -101,6 +101,9 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
crtc_state->lane_count);
}
+ drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n",
+ min_bpp, max_bpp);
+
for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
@@ -194,8 +197,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
u8 dsc_bpc[3] = {0};
int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
u8 dsc_max_bpc;
- bool need_timeslot_recalc = false;
- u32 last_compressed_bpp;
+ int min_compressed_bpp, max_compressed_bpp;
/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
if (DISPLAY_VER(i915) >= 12)
@@ -231,34 +233,25 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
if (max_bpp > sink_max_bpp)
max_bpp = sink_max_bpp;
- slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_bpp,
- min_bpp, limits,
- conn_state, 2 * 3, true);
-
- if (slots < 0)
- return slots;
-
- last_compressed_bpp = crtc_state->dsc.compressed_bpp;
+ max_compressed_bpp = intel_dp_dsc_sink_max_compressed_bpp(intel_dp,
+ crtc_state,
+ max_bpp / 3);
+ min_compressed_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
+ drm_dbg_kms(&i915->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n",
+ min_compressed_bpp, max_compressed_bpp);
- crtc_state->dsc.compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915,
- last_compressed_bpp,
- crtc_state->pipe_bpp);
+ /* Align compressed bpps according to our own constraints */
+ max_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, max_compressed_bpp,
+ crtc_state->pipe_bpp);
+ min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, min_compressed_bpp,
+ crtc_state->pipe_bpp);
- if (crtc_state->dsc.compressed_bpp != last_compressed_bpp)
- need_timeslot_recalc = true;
+ slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_compressed_bpp,
+ min_compressed_bpp, limits,
+ conn_state, 1, true);
- /*
- * Apparently some MST hubs dislike if vcpi slots are not matching precisely
- * the actual compressed bpp we use.
- */
- if (need_timeslot_recalc) {
- slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
- crtc_state->dsc.compressed_bpp,
- crtc_state->dsc.compressed_bpp,
- limits, conn_state, 2 * 3, true);
- if (slots < 0)
- return slots;
- }
+ if (slots < 0)
+ return slots;
intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
crtc_state->lane_count,
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH 19/19] drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info
@ 2023-07-13 10:33 ` Ankit Nautiyal
0 siblings, 0 replies; 72+ messages in thread
From: Ankit Nautiyal @ 2023-07-13 10:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Currently we seem to be using wrong DPCD register for reading
compressed bpps, reading min/max input bpc instead of compressed bpp.
Fix that, so that we now apply min/max compressed bpp limitations we
get from DP Spec Table 2-157 DP v2.0 and/or correspondent DPCD
register DP_DSC_MAX_BITS_PER_PIXEL_LOW/HIGH.
This might also allow us to get rid of an ugly compressed bpp
recalculation, which we had to add to make some MST hubs usable.
v2: - Fix operator precedence
v3: - Added debug info about compressed bpps
v4: - Don't try to intersect Sink input bpp and compressed bpps.
v5: - Decrease step while looking for suitable compressed bpp to
accommodate.
v6: - Use helper for getting min and max compressed_bpp (Ankit)
v7: - Fix checkpatch warning (Ankit)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +++---
drivers/gpu/drm/i915/display/intel_dp.h | 4 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 47 +++++++++------------
3 files changed, 32 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 25a6c162332f..ce8b28ca1cfa 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1762,7 +1762,7 @@ u16 intel_dp_dsc_max_sink_compressed_bppx16(struct intel_dp *intel_dp,
return 0;
}
-static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
+int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
{
/* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
switch (pipe_config->output_format) {
@@ -1779,9 +1779,9 @@ static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
return 0;
}
-static int dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
- struct intel_crtc_state *pipe_config,
- int bpc)
+int intel_dp_dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int bpc)
{
return intel_dp_dsc_max_sink_compressed_bppx16(intel_dp,
pipe_config, bpc) >> 4;
@@ -1894,11 +1894,13 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
int dsc_joiner_max_bpp;
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
- dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
+ dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
- dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3);
+ dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(intel_dp,
+ pipe_config,
+ pipe_bpp / 3);
dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 788a577ebe16..f29e48028f39 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -114,6 +114,10 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
enum intel_output_format output_format,
u32 pipe_bpp,
u32 timeslots);
+int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config);
+int intel_dp_dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int bpc);
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
int mode_clock, int mode_hdisplay,
bool bigjoiner);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 3eb085fbc7c8..06a456517383 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -101,6 +101,9 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
crtc_state->lane_count);
}
+ drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n",
+ min_bpp, max_bpp);
+
for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
@@ -194,8 +197,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
u8 dsc_bpc[3] = {0};
int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
u8 dsc_max_bpc;
- bool need_timeslot_recalc = false;
- u32 last_compressed_bpp;
+ int min_compressed_bpp, max_compressed_bpp;
/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
if (DISPLAY_VER(i915) >= 12)
@@ -231,34 +233,25 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
if (max_bpp > sink_max_bpp)
max_bpp = sink_max_bpp;
- slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_bpp,
- min_bpp, limits,
- conn_state, 2 * 3, true);
-
- if (slots < 0)
- return slots;
-
- last_compressed_bpp = crtc_state->dsc.compressed_bpp;
+ max_compressed_bpp = intel_dp_dsc_sink_max_compressed_bpp(intel_dp,
+ crtc_state,
+ max_bpp / 3);
+ min_compressed_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
+ drm_dbg_kms(&i915->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n",
+ min_compressed_bpp, max_compressed_bpp);
- crtc_state->dsc.compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915,
- last_compressed_bpp,
- crtc_state->pipe_bpp);
+ /* Align compressed bpps according to our own constraints */
+ max_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, max_compressed_bpp,
+ crtc_state->pipe_bpp);
+ min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, min_compressed_bpp,
+ crtc_state->pipe_bpp);
- if (crtc_state->dsc.compressed_bpp != last_compressed_bpp)
- need_timeslot_recalc = true;
+ slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_compressed_bpp,
+ min_compressed_bpp, limits,
+ conn_state, 1, true);
- /*
- * Apparently some MST hubs dislike if vcpi slots are not matching precisely
- * the actual compressed bpp we use.
- */
- if (need_timeslot_recalc) {
- slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
- crtc_state->dsc.compressed_bpp,
- crtc_state->dsc.compressed_bpp,
- limits, conn_state, 2 * 3, true);
- if (slots < 0)
- return slots;
- }
+ if (slots < 0)
+ return slots;
intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
crtc_state->lane_count,
--
2.40.1
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for DSC misc fixes (rev4)
2023-07-13 10:33 ` Ankit Nautiyal
` (19 preceding siblings ...)
(?)
@ 2023-07-13 11:56 ` Patchwork
-1 siblings, 0 replies; 72+ messages in thread
From: Patchwork @ 2023-07-13 11:56 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
== Series Details ==
Series: DSC misc fixes (rev4)
URL : https://patchwork.freedesktop.org/series/117662/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 72+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for DSC misc fixes (rev4)
2023-07-13 10:33 ` Ankit Nautiyal
` (20 preceding siblings ...)
(?)
@ 2023-07-13 12:07 ` Patchwork
-1 siblings, 0 replies; 72+ messages in thread
From: Patchwork @ 2023-07-13 12:07 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 48745 bytes --]
== Series Details ==
Series: DSC misc fixes (rev4)
URL : https://patchwork.freedesktop.org/series/117662/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13380 -> Patchwork_117662v4
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/index.html
Participating hosts (18 -> 40)
------------------------------
Additional (22): fi-rkl-11600 fi-apl-guc bat-rpls-1 fi-blb-e6850 bat-adlm-1 bat-dg2-9 fi-ilk-650 bat-atsm-1 fi-ivb-3770 bat-jsl-3 fi-skl-guc fi-glk-j4005 bat-jsl-1 bat-mtlp-8 bat-mtlp-6 bat-adlp-11 fi-tgl-1115g4 fi-cfl-guc fi-kbl-guc fi-kbl-x1275 fi-cfl-8109u fi-kbl-8809g
Known issues
------------
Here are the changes found in Patchwork_117662v4 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@unbind-rebind:
- fi-kbl-8809g: NOTRUN -> [DMESG-WARN][1] ([i915#8298])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-kbl-8809g/igt@core_hotunplug@unbind-rebind.html
* igt@debugfs_test@basic-hwmon:
- bat-mtlp-8: NOTRUN -> [SKIP][2] ([i915#7456])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-8/igt@debugfs_test@basic-hwmon.html
- fi-rkl-11600: NOTRUN -> [SKIP][3] ([i915#7456])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-rkl-11600/igt@debugfs_test@basic-hwmon.html
- bat-jsl-3: NOTRUN -> [SKIP][4] ([i915#7456])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-jsl-3/igt@debugfs_test@basic-hwmon.html
- bat-adlp-11: NOTRUN -> [SKIP][5] ([i915#7456])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlp-11/igt@debugfs_test@basic-hwmon.html
- bat-adlm-1: NOTRUN -> [SKIP][6] ([i915#7456])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlm-1/igt@debugfs_test@basic-hwmon.html
- bat-jsl-1: NOTRUN -> [SKIP][7] ([i915#7456])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-jsl-1/igt@debugfs_test@basic-hwmon.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][8] ([i915#7456])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-tgl-1115g4/igt@debugfs_test@basic-hwmon.html
- bat-rpls-1: NOTRUN -> [SKIP][9] ([i915#7456])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-rpls-1/igt@debugfs_test@basic-hwmon.html
- bat-mtlp-6: NOTRUN -> [SKIP][10] ([i915#7456])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@debugfs_test@basic-hwmon.html
* igt@fbdev@eof:
- bat-adlm-1: NOTRUN -> [SKIP][11] ([i915#2582]) +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlm-1/igt@fbdev@eof.html
* igt@fbdev@info:
- bat-dg2-9: NOTRUN -> [SKIP][12] ([i915#1849] / [i915#2582])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@fbdev@info.html
- fi-kbl-x1275: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1849])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-kbl-x1275/igt@fbdev@info.html
- fi-kbl-guc: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1849])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-kbl-guc/igt@fbdev@info.html
- bat-rpls-1: NOTRUN -> [SKIP][15] ([i915#1849] / [i915#2582])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-rpls-1/igt@fbdev@info.html
- fi-kbl-8809g: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#1849])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-kbl-8809g/igt@fbdev@info.html
- bat-adlm-1: NOTRUN -> [SKIP][17] ([i915#1849] / [i915#2582])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlm-1/igt@fbdev@info.html
- bat-mtlp-6: NOTRUN -> [SKIP][18] ([i915#1849] / [i915#2582])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@fbdev@info.html
* igt@fbdev@nullptr:
- bat-dg2-9: NOTRUN -> [SKIP][19] ([i915#2582]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@fbdev@nullptr.html
* igt@fbdev@write:
- bat-rpls-1: NOTRUN -> [SKIP][20] ([i915#2582]) +3 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-rpls-1/igt@fbdev@write.html
- bat-mtlp-6: NOTRUN -> [SKIP][21] ([i915#2582]) +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@fbdev@write.html
* igt@gem_exec_suspend@basic-s0@smem:
- bat-atsm-1: NOTRUN -> [DMESG-WARN][22] ([i915#8841]) +3 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-atsm-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_exec_suspend@basic-s3@lmem0:
- bat-atsm-1: NOTRUN -> [DMESG-WARN][23] ([i915#8504] / [i915#8841])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-atsm-1/igt@gem_exec_suspend@basic-s3@lmem0.html
* igt@gem_huc_copy@huc-copy:
- fi-cfl-8109u: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#2190])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-cfl-8109u/igt@gem_huc_copy@huc-copy.html
- fi-kbl-8809g: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#2190])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][26] ([i915#2190])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html
- bat-jsl-1: NOTRUN -> [SKIP][27] ([i915#2190])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-jsl-1/igt@gem_huc_copy@huc-copy.html
- fi-rkl-11600: NOTRUN -> [SKIP][28] ([i915#2190])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html
- bat-jsl-3: NOTRUN -> [SKIP][29] ([i915#2190])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-jsl-3/igt@gem_huc_copy@huc-copy.html
- fi-glk-j4005: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#2190])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-glk-j4005/igt@gem_huc_copy@huc-copy.html
- fi-kbl-x1275: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#2190])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-kbl-x1275/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#4613]) +3 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-apl-guc/igt@gem_lmem_swapping@basic.html
- bat-jsl-3: NOTRUN -> [SKIP][33] ([i915#4613]) +3 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-jsl-3/igt@gem_lmem_swapping@basic.html
- fi-glk-j4005: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#4613]) +3 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-glk-j4005/igt@gem_lmem_swapping@basic.html
- fi-skl-guc: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#4613]) +3 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-skl-guc/igt@gem_lmem_swapping@basic.html
- fi-kbl-8809g: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#4613]) +3 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-kbl-8809g/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-adlm-1: NOTRUN -> [SKIP][37] ([i915#4613]) +3 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlm-1/igt@gem_lmem_swapping@parallel-random-engines.html
- fi-rkl-11600: NOTRUN -> [SKIP][38] ([i915#4613]) +3 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-rkl-11600/igt@gem_lmem_swapping@parallel-random-engines.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][39] ([i915#4613]) +3 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-tgl-1115g4/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@random-engines:
- bat-rpls-1: NOTRUN -> [SKIP][40] ([i915#4613]) +3 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-rpls-1/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- fi-cfl-guc: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#4613]) +3 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-cfl-guc/igt@gem_lmem_swapping@verify-random.html
- bat-mtlp-6: NOTRUN -> [SKIP][42] ([i915#4613]) +3 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@gem_lmem_swapping@verify-random.html
- fi-kbl-x1275: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#4613]) +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-kbl-x1275/igt@gem_lmem_swapping@verify-random.html
- fi-cfl-8109u: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#4613]) +3 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-cfl-8109u/igt@gem_lmem_swapping@verify-random.html
- bat-mtlp-8: NOTRUN -> [SKIP][45] ([i915#4613]) +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-8/igt@gem_lmem_swapping@verify-random.html
- fi-kbl-guc: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#4613]) +3 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-kbl-guc/igt@gem_lmem_swapping@verify-random.html
- bat-jsl-1: NOTRUN -> [SKIP][47] ([i915#4613]) +3 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-jsl-1/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@basic:
- bat-atsm-1: NOTRUN -> [SKIP][48] ([i915#4083])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-atsm-1/igt@gem_mmap@basic.html
- bat-dg2-9: NOTRUN -> [SKIP][49] ([i915#4083])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@gem_mmap@basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][50] ([i915#4083])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-8/igt@gem_mmap@basic.html
- bat-mtlp-6: NOTRUN -> [SKIP][51] ([i915#4083])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@gem_mmap@basic.html
* igt@gem_mmap_gtt@basic:
- bat-dg2-9: NOTRUN -> [SKIP][52] ([i915#4077]) +2 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@gem_mmap_gtt@basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][53] ([i915#4077]) +3 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-8/igt@gem_mmap_gtt@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-dg2-9: NOTRUN -> [SKIP][54] ([i915#4079]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@gem_render_tiled_blits@basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][55] ([i915#4079]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-8/igt@gem_render_tiled_blits@basic.html
* igt@gem_tiled_blits@basic:
- bat-mtlp-6: NOTRUN -> [SKIP][56] ([i915#4077]) +2 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@gem_tiled_blits@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-atsm-1: NOTRUN -> [SKIP][57] ([i915#4077]) +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-atsm-1/igt@gem_tiled_fence_blits@basic.html
* igt@gem_tiled_pread_basic:
- fi-rkl-11600: NOTRUN -> [SKIP][58] ([i915#3282])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-rkl-11600/igt@gem_tiled_pread_basic.html
- bat-atsm-1: NOTRUN -> [SKIP][59] ([i915#4079]) +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-atsm-1/igt@gem_tiled_pread_basic.html
- bat-adlm-1: NOTRUN -> [SKIP][60] ([i915#3282])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlm-1/igt@gem_tiled_pread_basic.html
- bat-mtlp-6: NOTRUN -> [SKIP][61] ([i915#4079]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@gem_tiled_pread_basic.html
- bat-adlp-11: NOTRUN -> [SKIP][62] ([i915#3282])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlp-11/igt@gem_tiled_pread_basic.html
- bat-rpls-1: NOTRUN -> [SKIP][63] ([i915#3282])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-rpls-1/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-adlm-1: NOTRUN -> [SKIP][64] ([i915#7561])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlm-1/igt@i915_pm_backlight@basic-brightness.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][65] ([i915#3546] / [i915#7561])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html
- bat-rpls-1: NOTRUN -> [SKIP][66] ([i915#7561])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-rpls-1/igt@i915_pm_backlight@basic-brightness.html
- bat-mtlp-6: NOTRUN -> [SKIP][67] ([i915#3546])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@i915_pm_backlight@basic-brightness.html
- fi-rkl-11600: NOTRUN -> [SKIP][68] ([i915#7561])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html
- bat-dg2-9: NOTRUN -> [SKIP][69] ([i915#5354] / [i915#7561])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-kbl-guc: NOTRUN -> [SKIP][70] ([fdo#109271]) +34 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
- fi-cfl-8700k: [PASS][71] -> [FAIL][72] ([i915#7940])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/fi-cfl-8700k/igt@i915_pm_rpm@basic-pci-d3-state.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-cfl-8700k/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- fi-cfl-guc: NOTRUN -> [FAIL][73] ([i915#7940]) +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-cfl-guc/igt@i915_pm_rpm@basic-rte.html
- fi-cfl-8109u: NOTRUN -> [FAIL][74] ([i915#7940]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-cfl-8109u/igt@i915_pm_rpm@basic-rte.html
- fi-kbl-8809g: NOTRUN -> [FAIL][75] ([i915#8843])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-kbl-8809g/igt@i915_pm_rpm@basic-rte.html
- fi-kbl-guc: NOTRUN -> [FAIL][76] ([i915#8843])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
- fi-skl-guc: NOTRUN -> [FAIL][77] ([i915#7940]) +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-skl-guc/igt@i915_pm_rpm@basic-rte.html
* igt@i915_pm_rpm@module-reload:
- fi-blb-e6850: NOTRUN -> [SKIP][78] ([fdo#109271]) +38 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-blb-e6850/igt@i915_pm_rpm@module-reload.html
* igt@i915_pm_rps@basic-api:
- bat-atsm-1: NOTRUN -> [SKIP][79] ([i915#6621])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-atsm-1/igt@i915_pm_rps@basic-api.html
- bat-dg2-9: NOTRUN -> [SKIP][80] ([i915#6621])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@i915_pm_rps@basic-api.html
- bat-mtlp-8: NOTRUN -> [SKIP][81] ([i915#6621])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-8/igt@i915_pm_rps@basic-api.html
- bat-adlm-1: NOTRUN -> [SKIP][82] ([i915#6621])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlm-1/igt@i915_pm_rps@basic-api.html
- bat-rpls-1: NOTRUN -> [SKIP][83] ([i915#6621])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-rpls-1/igt@i915_pm_rps@basic-api.html
- bat-mtlp-6: NOTRUN -> [SKIP][84] ([i915#6621])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@gt_mocs:
- bat-mtlp-8: NOTRUN -> [DMESG-FAIL][85] ([i915#7059])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
- bat-mtlp-6: NOTRUN -> [DMESG-FAIL][86] ([i915#7059])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@hangcheck:
- bat-dg2-11: [PASS][87] -> [ABORT][88] ([i915#7913])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/bat-dg2-11/igt@i915_selftest@live@hangcheck.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-11/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- bat-mtlp-8: NOTRUN -> [DMESG-FAIL][89] ([i915#8497])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-8/igt@i915_selftest@live@requests.html
- bat-mtlp-6: NOTRUN -> [DMESG-FAIL][90] ([i915#7269])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: NOTRUN -> [ABORT][91] ([i915#4983] / [i915#7461] / [i915#7981] / [i915#8347] / [i915#8384])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-rpls-1/igt@i915_selftest@live@reset.html
* igt@i915_selftest@live@slpc:
- bat-mtlp-8: NOTRUN -> [DMESG-WARN][92] ([i915#6367])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-8/igt@i915_selftest@live@slpc.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-ivb-3770: NOTRUN -> [DMESG-WARN][93] ([i915#8841]) +6 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-ivb-3770/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][94] ([i915#7443] / [i915#8102])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-tgl-1115g4/igt@i915_suspend@basic-s3-without-i915.html
- bat-atsm-1: NOTRUN -> [SKIP][95] ([i915#6645])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-atsm-1/igt@i915_suspend@basic-s3-without-i915.html
- bat-mtlp-6: NOTRUN -> [SKIP][96] ([i915#6645])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@i915_suspend@basic-s3-without-i915.html
- bat-mtlp-8: NOTRUN -> [SKIP][97] ([i915#6645])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-8/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-mtlp-6: NOTRUN -> [SKIP][98] ([i915#4212]) +8 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9: NOTRUN -> [SKIP][99] ([i915#5190])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
- bat-mtlp-8: NOTRUN -> [SKIP][100] ([i915#5190])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
- bat-mtlp-6: NOTRUN -> [SKIP][101] ([i915#5190])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9: NOTRUN -> [SKIP][102] ([i915#4215] / [i915#5190])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@kms_addfb_basic@basic-y-tiled-legacy.html
- bat-mtlp-8: NOTRUN -> [SKIP][103] ([i915#4212]) +8 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9: NOTRUN -> [SKIP][104] ([i915#4212]) +7 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_addfb_basic@size-max:
- bat-atsm-1: NOTRUN -> [SKIP][105] ([i915#6077]) +36 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-atsm-1/igt@kms_addfb_basic@size-max.html
* igt@kms_addfb_basic@too-high:
- fi-kbl-8809g: NOTRUN -> [FAIL][106] ([i915#8296]) +2 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-kbl-8809g/igt@kms_addfb_basic@too-high.html
* igt@kms_chamelium_edid@dp-edid-read:
- fi-ilk-650: NOTRUN -> [SKIP][107] ([fdo#109271]) +29 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-ilk-650/igt@kms_chamelium_edid@dp-edid-read.html
- bat-jsl-1: NOTRUN -> [SKIP][108] ([i915#7828]) +8 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-jsl-1/igt@kms_chamelium_edid@dp-edid-read.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][109] ([i915#7828]) +7 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-tgl-1115g4/igt@kms_chamelium_edid@dp-edid-read.html
* igt@kms_chamelium_edid@hdmi-edid-read:
- fi-cfl-guc: NOTRUN -> [SKIP][110] ([fdo#109271]) +18 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-cfl-guc/igt@kms_chamelium_edid@hdmi-edid-read.html
- bat-mtlp-6: NOTRUN -> [SKIP][111] ([i915#7828]) +8 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@kms_chamelium_edid@hdmi-edid-read.html
* igt@kms_chamelium_frames@dp-crc-fast:
- bat-adlm-1: NOTRUN -> [SKIP][112] ([i915#7828]) +8 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlm-1/igt@kms_chamelium_frames@dp-crc-fast.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- bat-adlp-11: NOTRUN -> [SKIP][113] ([i915#7828]) +7 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlp-11/igt@kms_chamelium_frames@hdmi-crc-fast.html
- fi-cfl-8109u: NOTRUN -> [SKIP][114] ([fdo#109271]) +18 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-cfl-8109u/igt@kms_chamelium_frames@hdmi-crc-fast.html
- bat-mtlp-8: NOTRUN -> [SKIP][115] ([i915#7828]) +8 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-8/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_hpd@dp-hpd-fast:
- fi-rkl-11600: NOTRUN -> [SKIP][116] ([i915#7828]) +8 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-rkl-11600/igt@kms_chamelium_hpd@dp-hpd-fast.html
* igt@kms_chamelium_hpd@hdmi-hpd-fast:
- bat-rpls-1: NOTRUN -> [SKIP][117] ([i915#7828]) +7 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-rpls-1/igt@kms_chamelium_hpd@hdmi-hpd-fast.html
* igt@kms_chamelium_hpd@vga-hpd-fast:
- fi-apl-guc: NOTRUN -> [SKIP][118] ([fdo#109271]) +22 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-apl-guc/igt@kms_chamelium_hpd@vga-hpd-fast.html
- bat-jsl-3: NOTRUN -> [SKIP][119] ([i915#7828]) +8 similar issues
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-jsl-3/igt@kms_chamelium_hpd@vga-hpd-fast.html
- bat-dg2-9: NOTRUN -> [SKIP][120] ([i915#7828]) +8 similar issues
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@kms_chamelium_hpd@vga-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-glk-j4005: NOTRUN -> [SKIP][121] ([fdo#109271]) +18 similar issues
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-glk-j4005/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][122] ([i915#4103]) +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-rkl-11600: NOTRUN -> [SKIP][123] ([i915#4103]) +1 similar issue
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-jsl-3: NOTRUN -> [SKIP][124] ([i915#4103]) +1 similar issue
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-jsl-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-adlp-11: NOTRUN -> [SKIP][125] ([i915#4103]) +1 similar issue
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlp-11/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-mtlp-8: NOTRUN -> [SKIP][126] ([i915#4213]) +1 similar issue
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-jsl-1: NOTRUN -> [SKIP][127] ([i915#4103]) +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-jsl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- bat-atsm-1: NOTRUN -> [SKIP][128] ([i915#6078]) +19 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-atsm-1/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
- bat-dg2-9: NOTRUN -> [SKIP][129] ([i915#1845] / [i915#5354]) +13 similar issues
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- bat-rpls-1: NOTRUN -> [SKIP][130] ([i915#1845]) +14 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-rpls-1/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
- bat-mtlp-6: NOTRUN -> [SKIP][131] ([i915#1845]) +10 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
- bat-adlp-11: NOTRUN -> [ABORT][132] ([i915#4423])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlp-11/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- bat-adlm-1: NOTRUN -> [SKIP][133] ([i915#1845]) +15 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlm-1/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- fi-kbl-guc: NOTRUN -> [SKIP][134] ([fdo#109271] / [i915#1845]) +8 similar issues
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-kbl-guc/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
* igt@kms_flip@basic-flip-vs-dpms:
- bat-mtlp-6: NOTRUN -> [SKIP][135] ([i915#3637]) +3 similar issues
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@kms_flip@basic-flip-vs-dpms.html
- bat-dg2-9: NOTRUN -> [SKIP][136] ([i915#4098] / [i915#5354]) +3 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@kms_flip@basic-flip-vs-dpms.html
* igt@kms_flip@basic-flip-vs-modeset:
- bat-rpls-1: NOTRUN -> [SKIP][137] ([i915#3637]) +3 similar issues
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-rpls-1/igt@kms_flip@basic-flip-vs-modeset.html
* igt@kms_flip@basic-plain-flip:
- bat-atsm-1: NOTRUN -> [SKIP][138] ([i915#6166]) +3 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-atsm-1/igt@kms_flip@basic-plain-flip.html
- bat-adlm-1: NOTRUN -> [SKIP][139] ([i915#3637]) +3 similar issues
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlm-1/igt@kms_flip@basic-plain-flip.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-8809g: NOTRUN -> [DMESG-FAIL][140] ([i915#8299])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-kbl-8809g/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-8809g: NOTRUN -> [CRASH][141] ([i915#8299])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-kbl-8809g/igt@kms_force_connector_basic@force-edid.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-adlm-1: NOTRUN -> [SKIP][142] ([fdo#109285])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlm-1/igt@kms_force_connector_basic@force-load-detect.html
- fi-rkl-11600: NOTRUN -> [SKIP][143] ([fdo#109285] / [i915#4098])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][144] ([fdo#109285])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html
- bat-mtlp-6: NOTRUN -> [SKIP][145] ([fdo#109285])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@kms_force_connector_basic@force-load-detect.html
- bat-jsl-3: NOTRUN -> [SKIP][146] ([fdo#109285])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-jsl-3/igt@kms_force_connector_basic@force-load-detect.html
- bat-dg2-9: NOTRUN -> [SKIP][147] ([fdo#109285])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@kms_force_connector_basic@force-load-detect.html
- bat-mtlp-8: NOTRUN -> [SKIP][148] ([fdo#109285])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-8/igt@kms_force_connector_basic@force-load-detect.html
- bat-jsl-1: NOTRUN -> [SKIP][149] ([fdo#109285])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-jsl-1/igt@kms_force_connector_basic@force-load-detect.html
- bat-rpls-1: NOTRUN -> [SKIP][150] ([fdo#109285])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-rpls-1/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-atsm-1: NOTRUN -> [SKIP][151] ([i915#6093]) +3 similar issues
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-atsm-1/igt@kms_force_connector_basic@prune-stale-modes.html
- bat-dg2-9: NOTRUN -> [SKIP][152] ([i915#5274])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@kms_force_connector_basic@prune-stale-modes.html
- bat-mtlp-8: NOTRUN -> [SKIP][153] ([i915#5274])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html
- bat-mtlp-6: NOTRUN -> [SKIP][154] ([i915#5274])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@basic:
- bat-adlm-1: NOTRUN -> [SKIP][155] ([i915#1849])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlm-1/igt@kms_frontbuffer_tracking@basic.html
- bat-rpls-1: NOTRUN -> [SKIP][156] ([i915#1849])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-rpls-1/igt@kms_frontbuffer_tracking@basic.html
- bat-mtlp-6: NOTRUN -> [SKIP][157] ([i915#4342])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12:
- bat-dg2-9: NOTRUN -> [SKIP][158] ([i915#5354]) +2 similar issues
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-hdmi-a-2:
- fi-skl-guc: NOTRUN -> [SKIP][159] ([fdo#109271]) +20 similar issues
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-skl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-hdmi-a-2.html
* igt@kms_pipe_crc_basic@hang-read-crc:
- bat-atsm-1: NOTRUN -> [SKIP][160] ([i915#1836]) +6 similar issues
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-atsm-1/igt@kms_pipe_crc_basic@hang-read-crc.html
* igt@kms_pipe_crc_basic@read-crc:
- fi-kbl-x1275: NOTRUN -> [SKIP][161] ([fdo#109271]) +43 similar issues
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-mtlp-6: NOTRUN -> [SKIP][162] ([i915#1845] / [i915#4078]) +4 similar issues
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@kms_pipe_crc_basic@suspend-read-crc.html
* igt@kms_prop_blob@basic:
- bat-atsm-1: NOTRUN -> [SKIP][163] ([i915#7357])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-atsm-1/igt@kms_prop_blob@basic.html
* igt@kms_psr@cursor_plane_move:
- fi-kbl-8809g: NOTRUN -> [SKIP][164] ([fdo#109271]) +62 similar issues
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html
- fi-ivb-3770: NOTRUN -> [SKIP][165] ([fdo#109271]) +27 similar issues
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-ivb-3770/igt@kms_psr@cursor_plane_move.html
- bat-adlm-1: NOTRUN -> [SKIP][166] ([i915#1072]) +3 similar issues
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlm-1/igt@kms_psr@cursor_plane_move.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][167] ([fdo#110189]) +3 similar issues
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-tgl-1115g4/igt@kms_psr@cursor_plane_move.html
- bat-rpls-1: NOTRUN -> [SKIP][168] ([i915#1072]) +3 similar issues
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-rpls-1/igt@kms_psr@cursor_plane_move.html
- bat-mtlp-6: NOTRUN -> [SKIP][169] ([i915#1072]) +3 similar issues
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@kms_psr@cursor_plane_move.html
* igt@kms_psr@sprite_plane_onoff:
- fi-rkl-11600: NOTRUN -> [SKIP][170] ([i915#1072]) +3 similar issues
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-rkl-11600/igt@kms_psr@sprite_plane_onoff.html
- bat-atsm-1: NOTRUN -> [SKIP][171] ([i915#1072]) +3 similar issues
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-atsm-1/igt@kms_psr@sprite_plane_onoff.html
- bat-dg2-9: NOTRUN -> [SKIP][172] ([i915#1072]) +3 similar issues
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-rkl-11600: NOTRUN -> [SKIP][173] ([i915#3555] / [i915#4098])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html
- bat-atsm-1: NOTRUN -> [SKIP][174] ([i915#6094])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-atsm-1/igt@kms_setmode@basic-clone-single-crtc.html
- bat-jsl-3: NOTRUN -> [SKIP][175] ([i915#3555])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-jsl-3/igt@kms_setmode@basic-clone-single-crtc.html
- bat-dg2-9: NOTRUN -> [SKIP][176] ([i915#3555])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@kms_setmode@basic-clone-single-crtc.html
- bat-mtlp-8: NOTRUN -> [SKIP][177] ([i915#8809])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-8/igt@kms_setmode@basic-clone-single-crtc.html
- bat-adlm-1: NOTRUN -> [SKIP][178] ([i915#3555])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlm-1/igt@kms_setmode@basic-clone-single-crtc.html
- bat-jsl-1: NOTRUN -> [SKIP][179] ([i915#3555])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-jsl-1/igt@kms_setmode@basic-clone-single-crtc.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][180] ([i915#3555])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-tgl-1115g4/igt@kms_setmode@basic-clone-single-crtc.html
- bat-rpls-1: NOTRUN -> [SKIP][181] ([i915#3555])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-rpls-1/igt@kms_setmode@basic-clone-single-crtc.html
- bat-mtlp-6: NOTRUN -> [SKIP][182] ([i915#8809])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-atsm-1: NOTRUN -> [SKIP][183] ([fdo#109295] / [i915#6078])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-atsm-1/igt@prime_vgem@basic-fence-flip.html
- bat-dg2-9: NOTRUN -> [SKIP][184] ([i915#3708] / [i915#5354])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@prime_vgem@basic-fence-flip.html
- bat-adlm-1: NOTRUN -> [SKIP][185] ([i915#1845] / [i915#3708])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlm-1/igt@prime_vgem@basic-fence-flip.html
- bat-rpls-1: NOTRUN -> [SKIP][186] ([fdo#109295] / [i915#1845] / [i915#3708])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-rpls-1/igt@prime_vgem@basic-fence-flip.html
- bat-mtlp-6: NOTRUN -> [SKIP][187] ([i915#1845] / [i915#3708])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-atsm-1: NOTRUN -> [SKIP][188] ([fdo#109295] / [i915#4077]) +1 similar issue
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-atsm-1/igt@prime_vgem@basic-fence-mmap.html
- bat-mtlp-6: NOTRUN -> [SKIP][189] ([i915#3708] / [i915#4077]) +1 similar issue
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@prime_vgem@basic-fence-mmap.html
- bat-dg2-9: NOTRUN -> [SKIP][190] ([i915#3708] / [i915#4077]) +1 similar issue
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@prime_vgem@basic-fence-mmap.html
- bat-mtlp-8: NOTRUN -> [SKIP][191] ([i915#3708] / [i915#4077]) +1 similar issue
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-8/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- bat-mtlp-8: NOTRUN -> [SKIP][192] ([i915#3708]) +2 similar issues
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-8/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-read:
- fi-rkl-11600: NOTRUN -> [SKIP][193] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/fi-rkl-11600/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-write:
- bat-atsm-1: NOTRUN -> [SKIP][194] ([fdo#109295]) +2 similar issues
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-atsm-1/igt@prime_vgem@basic-write.html
- bat-dg2-9: NOTRUN -> [SKIP][195] ([i915#3291] / [i915#3708]) +2 similar issues
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-dg2-9/igt@prime_vgem@basic-write.html
- bat-adlm-1: NOTRUN -> [SKIP][196] ([i915#3708]) +2 similar issues
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-adlm-1/igt@prime_vgem@basic-write.html
- bat-rpls-1: NOTRUN -> [SKIP][197] ([fdo#109295] / [i915#3708]) +2 similar issues
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-rpls-1/igt@prime_vgem@basic-write.html
- bat-mtlp-6: NOTRUN -> [SKIP][198] ([i915#3708]) +2 similar issues
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/bat-mtlp-6/igt@prime_vgem@basic-write.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4342]: https://gitlab.freedesktop.org/drm/intel/issues/4342
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6077]: https://gitlab.freedesktop.org/drm/intel/issues/6077
[i915#6078]: https://gitlab.freedesktop.org/drm/intel/issues/6078
[i915#6093]: https://gitlab.freedesktop.org/drm/intel/issues/6093
[i915#6094]: https://gitlab.freedesktop.org/drm/intel/issues/6094
[i915#6166]: https://gitlab.freedesktop.org/drm/intel/issues/6166
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7269]: https://gitlab.freedesktop.org/drm/intel/issues/7269
[i915#7357]: https://gitlab.freedesktop.org/drm/intel/issues/7357
[i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
[i915#8102]: https://gitlab.freedesktop.org/drm/intel/issues/8102
[i915#8296]: https://gitlab.freedesktop.org/drm/intel/issues/8296
[i915#8298]: https://gitlab.freedesktop.org/drm/intel/issues/8298
[i915#8299]: https://gitlab.freedesktop.org/drm/intel/issues/8299
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
[i915#8384]: https://gitlab.freedesktop.org/drm/intel/issues/8384
[i915#8497]: https://gitlab.freedesktop.org/drm/intel/issues/8497
[i915#8504]: https://gitlab.freedesktop.org/drm/intel/issues/8504
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#8843]: https://gitlab.freedesktop.org/drm/intel/issues/8843
Build changes
-------------
* Linux: CI_DRM_13380 -> Patchwork_117662v4
CI-20190529: 20190529
CI_DRM_13380: c8d8bc62e682f5a569b3ded2b80848c47eb5c425 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7383: e9d66ac434bd580af20b475ddbee01f5c042ed61 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_117662v4: c8d8bc62e682f5a569b3ded2b80848c47eb5c425 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
dbcdc3815f3b drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info
a65b9fd6273f drm/i915/dp: Get optimal link config to have best compressed bpp
f7af07deb5b1 drm/i915/dp: Separate out function to get compressed bpp with joiner
afff5533b454 drm/i915/dp: Add DSC BPC/BPP constraints while selecting pipe bpp with DSC
6d7430c50f3e drm/i915/dp: Separate out functions for edp/DP for computing DSC bpp
cef065f3b888 drm/i915/dp: Rename helper to get DSC max pipe_bpp
24b570a05bef drm/i915/dp: Avoid left shift of DSC output bpp by 4
5528ecab3795 drm/i915/dp: Check min bpc DSC limits for dsc_force_bpc also
b8c6f962719f drm/i915/dp: Add functions to get min/max src input bpc with DSC
640a2a672220 drm/i915/dp: Avoid forcing DSC BPC for MST case
5cade65b8e8a drm/display/dp: Fix the DP DSC Receiver cap size
7335e7263299 drm/i915/dp: Remove extra logs for printing DSC info
0ad2e3ca9e00 drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck
83d84a190bdc drm/i915/display: Account for DSC not split case while computing cdclk
767db4670c3a drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp
ca217cb2c676 drm/i915/dp: Use consistent name for link bpp and compressed bpp
8d1506dcf850 drm/i915/dp_mst: Use output_format to get the final link bpp
307f53bc2f52 drm/i915/dp: Move compressed bpp check with 420 format inside the helper
dc57d0c94f86 drm/i915/dp: Consider output_format while computing dsc bpp
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/index.html
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^ permalink raw reply [flat|nested] 72+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for DSC misc fixes (rev4)
2023-07-13 10:33 ` Ankit Nautiyal
` (21 preceding siblings ...)
(?)
@ 2023-07-13 15:14 ` Patchwork
-1 siblings, 0 replies; 72+ messages in thread
From: Patchwork @ 2023-07-13 15:14 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 56992 bytes --]
== Series Details ==
Series: DSC misc fixes (rev4)
URL : https://patchwork.freedesktop.org/series/117662/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13380_full -> Patchwork_117662v4_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_117662v4_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_117662v4_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
Additional (1): pig-kbl-iris
Missing (1): shard-rkl0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_117662v4_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a3:
- shard-dg2: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-6/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a3.html
Known issues
------------
Here are the changes found in Patchwork_117662v4_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@object-reloc-purge-cache:
- shard-dg2: NOTRUN -> [SKIP][3] ([i915#8411])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@api_intel_bb@object-reloc-purge-cache.html
* igt@device_reset@cold-reset-bound:
- shard-rkl: NOTRUN -> [SKIP][4] ([i915#7701])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@device_reset@cold-reset-bound.html
* igt@drm_fdinfo@all-busy-check-all:
- shard-dg2: NOTRUN -> [SKIP][5] ([i915#8414])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@drm_fdinfo@all-busy-check-all.html
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [PASS][6] -> [FAIL][7] ([i915#7742]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-rkl-6/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-6/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@drm_fdinfo@virtual-busy-all:
- shard-mtlp: NOTRUN -> [SKIP][8] ([i915#8414])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@drm_fdinfo@virtual-busy-all.html
* igt@feature_discovery@display-4x:
- shard-mtlp: NOTRUN -> [SKIP][9] ([i915#1839])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@feature_discovery@display-4x.html
* igt@gem_ccs@ctrl-surf-copy:
- shard-mtlp: NOTRUN -> [SKIP][10] ([i915#5325])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@gem_ccs@ctrl-surf-copy.html
* igt@gem_create@create-ext-set-pat:
- shard-snb: NOTRUN -> [FAIL][11] ([i915#8621])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-snb4/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl: [PASS][12] -> [FAIL][13] ([i915#6268])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-rkl-2/igt@gem_ctx_exec@basic-nohangcheck.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-7/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_persistence@engines-queued:
- shard-snb: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1099]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-snb4/igt@gem_ctx_persistence@engines-queued.html
* igt@gem_ctx_persistence@heartbeat-close:
- shard-mtlp: NOTRUN -> [SKIP][15] ([i915#8555])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@gem_ctx_persistence@heartbeat-close.html
* igt@gem_eio@in-flight-suspend:
- shard-dg2: [PASS][16] -> [FAIL][17] ([fdo#103375] / [i915#6121])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-10/igt@gem_eio@in-flight-suspend.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-5/igt@gem_eio@in-flight-suspend.html
* igt@gem_eio@kms:
- shard-dg2: [PASS][18] -> [FAIL][19] ([i915#5784])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-11/igt@gem_eio@kms.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-12/igt@gem_eio@kms.html
* igt@gem_exec_balancer@bonded-true-hang:
- shard-dg2: NOTRUN -> [SKIP][20] ([i915#4812])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@gem_exec_balancer@bonded-true-hang.html
* igt@gem_exec_endless@dispatch@vecs0:
- shard-tglu: [PASS][21] -> [TIMEOUT][22] ([i915#3778])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-tglu-7/igt@gem_exec_endless@dispatch@vecs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-tglu-10/igt@gem_exec_endless@dispatch@vecs0.html
* igt@gem_exec_fair@basic-none:
- shard-dg2: NOTRUN -> [SKIP][23] ([i915#3539] / [i915#4852])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@gem_exec_fair@basic-none.html
* igt@gem_exec_fair@basic-none-rrul:
- shard-mtlp: NOTRUN -> [SKIP][24] ([i915#4473] / [i915#4771])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@gem_exec_fair@basic-none-rrul.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][25] -> [FAIL][26] ([i915#2842])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-apl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-rkl: NOTRUN -> [FAIL][27] ([i915#2842])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-tglu: [PASS][28] -> [FAIL][29] ([i915#2842])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-tglu-5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-tglu-9/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_reloc@basic-wc-gtt-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][30] ([i915#3281]) +4 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-8/igt@gem_exec_reloc@basic-wc-gtt-noreloc.html
* igt@gem_exec_suspend@basic-s4-devices@smem:
- shard-rkl: NOTRUN -> [ABORT][31] ([i915#7975] / [i915#8213])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@gem_exec_suspend@basic-s4-devices@smem.html
* igt@gem_fence_thrash@bo-write-verify-threaded-none:
- shard-mtlp: NOTRUN -> [SKIP][32] ([i915#4860])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-4/igt@gem_fence_thrash@bo-write-verify-threaded-none.html
* igt@gem_fenced_exec_thrash@too-many-fences:
- shard-dg2: NOTRUN -> [SKIP][33] ([i915#4860])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@gem_fenced_exec_thrash@too-many-fences.html
* igt@gem_lmem_swapping@parallel-random:
- shard-rkl: NOTRUN -> [SKIP][34] ([i915#4613])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_mmap_gtt@bad-object:
- shard-mtlp: NOTRUN -> [SKIP][35] ([i915#4077])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@gem_mmap_gtt@bad-object.html
* igt@gem_mmap_gtt@basic:
- shard-dg2: NOTRUN -> [SKIP][36] ([i915#4077]) +3 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-5/igt@gem_mmap_gtt@basic.html
* igt@gem_mmap_wc@write-cpu-read-wc-unflushed:
- shard-dg2: NOTRUN -> [SKIP][37] ([i915#4083]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@gem_mmap_wc@write-cpu-read-wc-unflushed.html
* igt@gem_partial_pwrite_pread@reads-snoop:
- shard-rkl: NOTRUN -> [SKIP][38] ([i915#3282])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@gem_partial_pwrite_pread@reads-snoop.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-dg2: NOTRUN -> [SKIP][39] ([i915#3282])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-rkl: NOTRUN -> [SKIP][40] ([i915#4270])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
* igt@gem_pxp@reject-modify-context-protection-off-1:
- shard-dg2: NOTRUN -> [SKIP][41] ([i915#4270])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@gem_pxp@reject-modify-context-protection-off-1.html
* igt@gem_pxp@verify-pxp-stale-ctx-execution:
- shard-mtlp: NOTRUN -> [SKIP][42] ([i915#4270]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@gem_pxp@verify-pxp-stale-ctx-execution.html
* igt@gem_readwrite@write-bad-handle:
- shard-mtlp: NOTRUN -> [SKIP][43] ([i915#3282]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@gem_readwrite@write-bad-handle.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled:
- shard-mtlp: NOTRUN -> [SKIP][44] ([i915#8428]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-4/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@gem_softpin@evict-snoop-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][45] ([i915#4885])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@gem_softpin@evict-snoop-interruptible.html
* igt@gem_tiled_pread_basic:
- shard-dg2: NOTRUN -> [SKIP][46] ([i915#4079])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@gem_tiled_pread_basic.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-mtlp: NOTRUN -> [SKIP][47] ([i915#3297]) +2 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-8/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gen7_exec_parse@basic-allowed:
- shard-mtlp: NOTRUN -> [SKIP][48] ([fdo#109289]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@gen7_exec_parse@basic-allowed.html
* igt@gen7_exec_parse@basic-offset:
- shard-rkl: NOTRUN -> [SKIP][49] ([fdo#109289])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@gen7_exec_parse@basic-offset.html
* igt@gen9_exec_parse@basic-rejected:
- shard-mtlp: NOTRUN -> [SKIP][50] ([i915#2856]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-4/igt@gen9_exec_parse@basic-rejected.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-rkl: NOTRUN -> [SKIP][51] ([i915#2527])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@gen9_exec_parse@batch-invalid-length.html
* igt@gen9_exec_parse@bb-secure:
- shard-dg2: NOTRUN -> [SKIP][52] ([i915#2856])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@gen9_exec_parse@bb-secure.html
* igt@i915_pipe_stress@stress-xrgb8888-ytiled:
- shard-dg2: NOTRUN -> [SKIP][53] ([i915#7091])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html
* igt@i915_pm_dc@dc9-dpms:
- shard-tglu: [PASS][54] -> [SKIP][55] ([i915#4281])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-tglu-4/igt@i915_pm_dc@dc9-dpms.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-tglu-7/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- shard-dg2: [PASS][56] -> [SKIP][57] ([i915#1937])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-10/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-5/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rpm@cursor-dpms:
- shard-tglu: [PASS][58] -> [FAIL][59] ([i915#7940]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-tglu-7/igt@i915_pm_rpm@cursor-dpms.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-tglu-5/igt@i915_pm_rpm@cursor-dpms.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-mtlp: NOTRUN -> [SKIP][60] ([fdo#109293])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-dg2: NOTRUN -> [SKIP][61] ([i915#1397])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_query@query-topology-coherent-slice-mask:
- shard-dg2: NOTRUN -> [SKIP][62] ([i915#6188])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@i915_query@query-topology-coherent-slice-mask.html
* igt@i915_selftest@live@gt_mocs:
- shard-mtlp: [PASS][63] -> [DMESG-FAIL][64] ([i915#7059])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-6/igt@i915_selftest@live@gt_mocs.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-3/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@slpc:
- shard-mtlp: [PASS][65] -> [DMESG-WARN][66] ([i915#6367])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-6/igt@i915_selftest@live@slpc.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-3/igt@i915_selftest@live@slpc.html
* igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
- shard-mtlp: NOTRUN -> [SKIP][67] ([i915#4212])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-4/igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-snb: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#1769])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-snb2/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-rkl: NOTRUN -> [SKIP][69] ([i915#5286])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@linear-32bpp-rotate-90:
- shard-mtlp: NOTRUN -> [SKIP][70] ([fdo#111614]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-8/igt@kms_big_fb@linear-32bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-glk: [PASS][71] -> [FAIL][72] ([i915#3743])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-glk4/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-glk3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-mtlp: [PASS][73] -> [FAIL][74] ([i915#3743])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-dg2: NOTRUN -> [SKIP][75] ([i915#5190]) +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-rkl: NOTRUN -> [SKIP][76] ([fdo#110723]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- shard-mtlp: NOTRUN -> [SKIP][77] ([fdo#111615]) +3 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-yf_tiled_ccs:
- shard-rkl: NOTRUN -> [SKIP][78] ([i915#3734] / [i915#5354] / [i915#6095]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@kms_ccs@pipe-a-missing-ccs-buffer-yf_tiled_ccs.html
* igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_dg2_rc_ccs_cc:
- shard-mtlp: NOTRUN -> [SKIP][79] ([i915#6095]) +10 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-4/igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs:
- shard-rkl: NOTRUN -> [SKIP][80] ([i915#5354] / [i915#6095]) +3 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-rkl: NOTRUN -> [SKIP][81] ([i915#3886] / [i915#5354] / [i915#6095])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-dg2: NOTRUN -> [SKIP][82] ([i915#3689] / [i915#3886] / [i915#5354]) +2 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-basic-4_tiled_mtl_rc_ccs:
- shard-rkl: NOTRUN -> [SKIP][83] ([i915#5354]) +6 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@kms_ccs@pipe-c-crc-primary-basic-4_tiled_mtl_rc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs:
- shard-dg2: NOTRUN -> [SKIP][84] ([i915#3689] / [i915#5354]) +2 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-mtlp: NOTRUN -> [SKIP][85] ([i915#3886] / [i915#6095]) +3 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs:
- shard-dg2: NOTRUN -> [SKIP][86] ([i915#5354]) +8 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs.html
* igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][87] ([i915#7213]) +3 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-2/igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-2.html
* igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][88] ([i915#4087]) +3 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-6/igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3.html
* igt@kms_chamelium_audio@hdmi-audio-edid:
- shard-mtlp: NOTRUN -> [SKIP][89] ([i915#7828]) +2 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-4/igt@kms_chamelium_audio@hdmi-audio-edid.html
* igt@kms_chamelium_color@ctm-negative:
- shard-mtlp: NOTRUN -> [SKIP][90] ([fdo#111827])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@kms_chamelium_color@ctm-negative.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- shard-rkl: NOTRUN -> [SKIP][91] ([i915#7828]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_hpd@dp-hpd:
- shard-dg2: NOTRUN -> [SKIP][92] ([i915#7828]) +2 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@kms_chamelium_hpd@dp-hpd.html
* igt@kms_color@deep-color:
- shard-rkl: NOTRUN -> [SKIP][93] ([i915#3555])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-1/igt@kms_color@deep-color.html
* igt@kms_content_protection@atomic-dpms:
- shard-mtlp: NOTRUN -> [SKIP][94] ([i915#6944])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@kms_content_protection@atomic-dpms.html
* igt@kms_cursor_crc@cursor-offscreen-512x512:
- shard-mtlp: NOTRUN -> [SKIP][95] ([i915#3359])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-8/igt@kms_cursor_crc@cursor-offscreen-512x512.html
* igt@kms_cursor_crc@cursor-sliding-32x10:
- shard-dg2: NOTRUN -> [SKIP][96] ([i915#3555]) +1 similar issue
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@kms_cursor_crc@cursor-sliding-32x10.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-dg2: NOTRUN -> [SKIP][97] ([i915#4103] / [i915#4213])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-mtlp: [PASS][98] -> [FAIL][99] ([i915#8248])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-7/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-4/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
- shard-dg2: NOTRUN -> [SKIP][100] ([fdo#109274] / [i915#5354])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-mtlp: NOTRUN -> [SKIP][101] ([i915#3546]) +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-mtlp: NOTRUN -> [FAIL][102] ([i915#2346])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_dsc@dsc-with-formats:
- shard-rkl: NOTRUN -> [SKIP][103] ([i915#3555] / [i915#3840])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@kms_dsc@dsc-with-formats.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-mtlp: NOTRUN -> [SKIP][104] ([i915#3840])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-8/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_flip@2x-blocking-absolute-wf_vblank:
- shard-rkl: NOTRUN -> [SKIP][105] ([fdo#111825])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@kms_flip@2x-blocking-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-mtlp: NOTRUN -> [SKIP][106] ([i915#3637]) +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-dg2: NOTRUN -> [SKIP][107] ([fdo#109274] / [fdo#111767])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][108] -> [FAIL][109] ([i915#79])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-edp1:
- shard-mtlp: [PASS][110] -> [DMESG-WARN][111] ([i915#1982])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-8/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-edp1.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-8/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-vga1:
- shard-snb: NOTRUN -> [DMESG-WARN][112] ([i915#8841]) +1 similar issue
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-snb2/igt@kms_flip@flip-vs-suspend-interruptible@b-vga1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][113] ([i915#2672])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][114] ([i915#2672]) +2 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
- shard-rkl: NOTRUN -> [SKIP][115] ([fdo#111825] / [i915#1825]) +3 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render:
- shard-dg2: NOTRUN -> [SKIP][116] ([i915#3458]) +3 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-mtlp: NOTRUN -> [SKIP][117] ([i915#1825]) +13 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu:
- shard-rkl: NOTRUN -> [SKIP][118] ([i915#3023]) +4 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][119] ([i915#8708]) +2 similar issues
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][120] ([i915#8708]) +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch:
- shard-rkl: NOTRUN -> [SKIP][121] ([i915#3555] / [i915#8228])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-1/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@static-swap:
- shard-dg2: NOTRUN -> [SKIP][122] ([i915#3555] / [i915#8228])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-6/igt@kms_hdr@static-swap.html
* igt@kms_hdr@static-toggle-suspend:
- shard-mtlp: NOTRUN -> [SKIP][123] ([i915#8228])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
- shard-dg2: NOTRUN -> [SKIP][124] ([fdo#109289]) +2 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][125] ([i915#5176]) +11 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-10/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1.html
- shard-rkl: NOTRUN -> [SKIP][126] ([i915#5176]) +7 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][127] ([i915#5176]) +3 similar issues
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-4/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-edp-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][128] ([i915#5235]) +11 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3.html
* igt@kms_prime@basic-crc-hybrid:
- shard-rkl: NOTRUN -> [SKIP][129] ([i915#6524])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-dg2: NOTRUN -> [SKIP][130] ([i915#658])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-dg2: NOTRUN -> [SKIP][131] ([i915#1072])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@kms_psr@psr2_sprite_plane_onoff.html
* igt@kms_rotation_crc@exhaust-fences:
- shard-dg2: NOTRUN -> [SKIP][132] ([i915#4235])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@kms_rotation_crc@exhaust-fences.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
- shard-mtlp: NOTRUN -> [SKIP][133] ([i915#5289])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-rkl: NOTRUN -> [SKIP][134] ([fdo#111615] / [i915#5289])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_setmode@basic-clone-single-crtc:
- shard-rkl: NOTRUN -> [SKIP][135] ([i915#3555] / [i915#4098])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@kms_tv_load_detect@load-detect:
- shard-dg2: NOTRUN -> [SKIP][136] ([fdo#109309])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@kms_tv_load_detect@load-detect.html
* igt@kms_vblank@pipe-c-query-busy-hang:
- shard-snb: NOTRUN -> [SKIP][137] ([fdo#109271]) +264 similar issues
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-snb4/igt@kms_vblank@pipe-c-query-busy-hang.html
* igt@kms_vblank@pipe-c-query-forked:
- shard-rkl: NOTRUN -> [SKIP][138] ([i915#4070] / [i915#6768]) +1 similar issue
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@kms_vblank@pipe-c-query-forked.html
* igt@kms_vblank@pipe-d-query-idle:
- shard-rkl: NOTRUN -> [SKIP][139] ([i915#4070] / [i915#533] / [i915#6768])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@kms_vblank@pipe-d-query-idle.html
* igt@kms_vrr@flipline:
- shard-mtlp: NOTRUN -> [SKIP][140] ([i915#8808]) +1 similar issue
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@kms_vrr@flipline.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- shard-dg2: NOTRUN -> [SKIP][141] ([i915#2436])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@perf_pmu@busy-idle-check-all@vcs0:
- shard-mtlp: [PASS][142] -> [FAIL][143] ([i915#4521])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-7/igt@perf_pmu@busy-idle-check-all@vcs0.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-2/igt@perf_pmu@busy-idle-check-all@vcs0.html
* igt@sysfs_heartbeat_interval@nopreempt@vcs1:
- shard-mtlp: [PASS][144] -> [FAIL][145] ([i915#6015])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-6/igt@sysfs_heartbeat_interval@nopreempt@vcs1.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-4/igt@sysfs_heartbeat_interval@nopreempt@vcs1.html
* igt@v3d/v3d_submit_cl@multiple-job-submission:
- shard-dg2: NOTRUN -> [SKIP][146] ([i915#2575]) +1 similar issue
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@v3d/v3d_submit_cl@multiple-job-submission.html
* igt@v3d/v3d_submit_cl@multisync-out-syncs:
- shard-rkl: NOTRUN -> [SKIP][147] ([fdo#109315]) +2 similar issues
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@v3d/v3d_submit_cl@multisync-out-syncs.html
* igt@v3d/v3d_submit_cl@simple-flush-cache:
- shard-mtlp: NOTRUN -> [SKIP][148] ([i915#2575]) +1 similar issue
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@v3d/v3d_submit_cl@simple-flush-cache.html
* igt@vc4/vc4_create_bo@create-bo-0:
- shard-dg2: NOTRUN -> [SKIP][149] ([i915#7711]) +1 similar issue
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@vc4/vc4_create_bo@create-bo-0.html
* igt@vc4/vc4_mmap@mmap-bo:
- shard-rkl: NOTRUN -> [SKIP][150] ([i915#7711])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-2/igt@vc4/vc4_mmap@mmap-bo.html
* igt@vc4/vc4_purgeable_bo@mark-unpurgeable-check-retained:
- shard-mtlp: NOTRUN -> [SKIP][151] ([i915#7711])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-check-retained.html
#### Possible fixes ####
* igt@gem_barrier_race@remote-request@rcs0:
- shard-dg2: [ABORT][152] ([i915#7461] / [i915#8211] / [i915#8234]) -> [PASS][153]
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-10/igt@gem_barrier_race@remote-request@rcs0.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-5/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_eio@hibernate:
- shard-dg2: [ABORT][154] ([i915#7975] / [i915#8213]) -> [PASS][155]
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-8/igt@gem_eio@hibernate.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-11/igt@gem_eio@hibernate.html
* igt@gem_eio@unwedge-stress:
- {shard-dg1}: [FAIL][156] ([i915#5784]) -> [PASS][157]
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg1-14/igt@gem_eio@unwedge-stress.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg1-19/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][158] ([i915#2846]) -> [PASS][159]
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-glk9/igt@gem_exec_fair@basic-deadline.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-glk2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][160] ([i915#2842]) -> [PASS][161]
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-rkl: [FAIL][162] ([i915#2842]) -> [PASS][163]
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-rkl-3/igt@gem_exec_fair@basic-pace@bcs0.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-4/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg2: [DMESG-WARN][164] ([i915#7061]) -> [PASS][165]
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-7/igt@i915_module_load@reload-with-fault-injection.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-10/igt@i915_module_load@reload-with-fault-injection.html
- shard-mtlp: [ABORT][166] ([i915#8489] / [i915#8668]) -> [PASS][167]
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-2/igt@i915_module_load@reload-with-fault-injection.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-5/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_dc@dc6-dpms:
- shard-tglu: [FAIL][168] ([i915#3989] / [i915#454]) -> [PASS][169]
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-tglu-3/igt@i915_pm_dc@dc6-dpms.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-tglu-2/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- shard-rkl: [SKIP][170] ([i915#1937]) -> [PASS][171]
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-rkl-3/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
- {shard-dg1}: [SKIP][172] ([i915#1937]) -> [PASS][173]
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg1-15/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg1-19/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rpm@cursor:
- shard-tglu: [FAIL][174] ([i915#7940]) -> [PASS][175]
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-tglu-4/igt@i915_pm_rpm@cursor.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-tglu-7/igt@i915_pm_rpm@cursor.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- shard-dg2: [SKIP][176] ([i915#1397]) -> [PASS][177]
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-5/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-12/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
* igt@i915_pm_rpm@gem-execbuf-stress@smem0:
- {shard-dg1}: [FAIL][178] ([i915#7940]) -> [PASS][179]
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg1-12/igt@i915_pm_rpm@gem-execbuf-stress@smem0.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg1-13/igt@i915_pm_rpm@gem-execbuf-stress@smem0.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-rkl: [SKIP][180] ([i915#1397]) -> [PASS][181] +1 similar issue
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-4/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-180:
- shard-mtlp: [FAIL][182] ([i915#5138]) -> [PASS][183]
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-5/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-4/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [FAIL][184] ([i915#72]) -> [PASS][185]
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [FAIL][186] ([i915#2346]) -> [PASS][187] +1 similar issue
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
- shard-glk: [FAIL][188] ([i915#2346]) -> [PASS][189]
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][190] ([i915#79]) -> [PASS][191] +1 similar issue
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [FAIL][192] ([i915#7484]) -> [PASS][193]
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-2/igt@perf@non-zero-reason@0-rcs0.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-1/igt@perf@non-zero-reason@0-rcs0.html
* igt@perf_pmu@most-busy-check-all@rcs0:
- shard-rkl: [FAIL][194] ([i915#4349]) -> [PASS][195]
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-rkl-3/igt@perf_pmu@most-busy-check-all@rcs0.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-4/igt@perf_pmu@most-busy-check-all@rcs0.html
#### Warnings ####
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [DMESG-WARN][196] ([i915#4936] / [i915#5493]) -> [TIMEOUT][197] ([i915#5493])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-1/igt@gem_lmem_swapping@smem-oom@lmem0.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-7/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@kms_content_protection@type1:
- shard-dg2: [SKIP][198] ([i915#7118] / [i915#7162]) -> [SKIP][199] ([i915#7118])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-11/igt@kms_content_protection@type1.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-dg2-1/igt@kms_content_protection@type1.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-rkl: [SKIP][200] ([fdo#109285]) -> [SKIP][201] ([fdo#109285] / [i915#4098])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-rkl-7/igt@kms_force_connector_basic@force-load-detect.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-4/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][202] ([i915#4816]) -> [SKIP][203] ([i915#4070] / [i915#4816])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-rkl-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-rkl-6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@sysfs_preempt_timeout@timeout@vecs0:
- shard-mtlp: [ABORT][204] ([i915#8521]) -> [TIMEOUT][205] ([i915#7947])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-5/igt@sysfs_preempt_timeout@timeout@vecs0.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/shard-mtlp-4/igt@sysfs_preempt_timeout@timeout@vecs0.html
### Piglit changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- pig-kbl-iris: NOTRUN -> [FAIL][206] ([i915#5603])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/pig-kbl-iris/igt@i915_pm_rpm@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
[i915#4521]: https://gitlab.freedesktop.org/drm/intel/issues/4521
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5603]: https://gitlab.freedesktop.org/drm/intel/issues/5603
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6015]: https://gitlab.freedesktop.org/drm/intel/issues/6015
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
[i915#6188]: https://gitlab.freedesktop.org/drm/intel/issues/6188
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7061]: https://gitlab.freedesktop.org/drm/intel/issues/7061
[i915#7091]: https://gitlab.freedesktop.org/drm/intel/issues/7091
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484
[i915#7691]: https://gitlab.freedesktop.org/drm/intel/issues/7691
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
[i915#7947]: https://gitlab.freedesktop.org/drm/intel/issues/7947
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
[i915#8248]: https://gitlab.freedesktop.org/drm/intel/issues/8248
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8489]: https://gitlab.freedesktop.org/drm/intel/issues/8489
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
[i915#8521]: https://gitlab.freedesktop.org/drm/intel/issues/8521
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8621]: https://gitlab.freedesktop.org/drm/intel/issues/8621
[i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
[i915#8808]: https://gitlab.freedesktop.org/drm/intel/issues/8808
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
Build changes
-------------
* Linux: CI_DRM_13380 -> Patchwork_117662v4
* Piglit: None -> piglit_4509
CI-20190529: 20190529
CI_DRM_13380: c8d8bc62e682f5a569b3ded2b80848c47eb5c425 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7383: e9d66ac434bd580af20b475ddbee01f5c042ed61 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_117662v4: c8d8bc62e682f5a569b3ded2b80848c47eb5c425 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v4/index.html
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