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From: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: daire.mcnamara@microchip.com, conor@kernel.org,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	linux-riscv@lists.infradead.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v2 7/8] PCI: microchip: Rename and refactor mc_pcie_enable_msi()
Date: Thu, 27 Jul 2023 17:27:57 +0200	[thread overview]
Message-ID: <ZMKM/f3q1o7N/bBv@lpieralisi> (raw)
In-Reply-To: <20230719174135.GA507746@bhelgaas>

On Wed, Jul 19, 2023 at 12:41:35PM -0500, Bjorn Helgaas wrote:
> On Fri, Jun 30, 2023 at 04:48:58PM +0100, daire.mcnamara@microchip.com wrote:
> > From: Daire McNamara <daire.mcnamara@microchip.com>
> > 
> > After improving driver to get MSI-related information from
> > configuration registers (set at power on from the Libero FPGA
> > design), its now clear that mc_pcie_enable_msi() is not a good
> 
> it's (contraction of "it is")
> 
> > name for this function.  The function is better named as
> > mc_pcie_fixup_ecam() as its purpose is to correct the queue
> > size of the MSI CAP CTRL.
> 
> > -static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *base)
> > +static void mc_pcie_fixup_ecam(struct mc_pcie *port, void __iomem *ecam)
> 
> Since the purpose of this seems to be to fix stuff in the MSI cap,
> removing "msi" from the name seems weird.  The fact that it uses ECAM
> to access the registers is incidental.
> 
> > -	msg_ctrl &= ~PCI_MSI_FLAGS_QSIZE;
> > -	msg_ctrl |= queue_size << 4;
> > -	writew_relaxed(msg_ctrl, base + cap_offset + PCI_MSI_FLAGS);
> > +	reg &= ~PCI_MSI_FLAGS_QSIZE;
> > +	reg |= queue_size << 4;
> 
> Could maybe use FIELD_PREP() instead of the shift?  I guess this would
> go in the "Gather MSI information" patch.

Daire,

can you follow up on these review comments please ?

Thanks,
Lorenzo

> 
> Bjorn

WARNING: multiple messages have this Message-ID (diff)
From: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: daire.mcnamara@microchip.com, conor@kernel.org,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	linux-riscv@lists.infradead.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v2 7/8] PCI: microchip: Rename and refactor mc_pcie_enable_msi()
Date: Thu, 27 Jul 2023 17:27:57 +0200	[thread overview]
Message-ID: <ZMKM/f3q1o7N/bBv@lpieralisi> (raw)
In-Reply-To: <20230719174135.GA507746@bhelgaas>

On Wed, Jul 19, 2023 at 12:41:35PM -0500, Bjorn Helgaas wrote:
> On Fri, Jun 30, 2023 at 04:48:58PM +0100, daire.mcnamara@microchip.com wrote:
> > From: Daire McNamara <daire.mcnamara@microchip.com>
> > 
> > After improving driver to get MSI-related information from
> > configuration registers (set at power on from the Libero FPGA
> > design), its now clear that mc_pcie_enable_msi() is not a good
> 
> it's (contraction of "it is")
> 
> > name for this function.  The function is better named as
> > mc_pcie_fixup_ecam() as its purpose is to correct the queue
> > size of the MSI CAP CTRL.
> 
> > -static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *base)
> > +static void mc_pcie_fixup_ecam(struct mc_pcie *port, void __iomem *ecam)
> 
> Since the purpose of this seems to be to fix stuff in the MSI cap,
> removing "msi" from the name seems weird.  The fact that it uses ECAM
> to access the registers is incidental.
> 
> > -	msg_ctrl &= ~PCI_MSI_FLAGS_QSIZE;
> > -	msg_ctrl |= queue_size << 4;
> > -	writew_relaxed(msg_ctrl, base + cap_offset + PCI_MSI_FLAGS);
> > +	reg &= ~PCI_MSI_FLAGS_QSIZE;
> > +	reg |= queue_size << 4;
> 
> Could maybe use FIELD_PREP() instead of the shift?  I guess this would
> go in the "Gather MSI information" patch.

Daire,

can you follow up on these review comments please ?

Thanks,
Lorenzo

> 
> Bjorn

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  reply	other threads:[~2023-07-27 15:28 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-30 15:48 [PATCH v2 0/8] PCI: microchip: Fixes and clean-ups daire.mcnamara
2023-06-30 15:48 ` daire.mcnamara
2023-06-30 15:48 ` [PATCH v2 1/8] PCI: microchip: Correct the DED and SEC interrupt bit offsets daire.mcnamara
2023-06-30 15:48   ` daire.mcnamara
2023-06-30 15:48 ` [PATCH v2 2/8] PCI: microchip: Enable building driver as a module daire.mcnamara
2023-06-30 15:48   ` daire.mcnamara
2023-06-30 15:48 ` [PATCH v2 3/8] PCI: microchip: Align register, offset, and mask names with hw docs daire.mcnamara
2023-06-30 15:48   ` daire.mcnamara
2023-06-30 15:48 ` [PATCH v2 4/8] PCI: microchip: Enable event handlers to access bridge and ctrl ptrs daire.mcnamara
2023-06-30 15:48   ` daire.mcnamara
2023-06-30 15:48 ` [PATCH v2 5/8] PCI: microchip: Clean up initialisation of interrupts daire.mcnamara
2023-06-30 15:48   ` daire.mcnamara
2023-06-30 15:48 ` [PATCH v2 6/8] PCI: microchip: Gather MSI information from hardware config registers daire.mcnamara
2023-06-30 15:48   ` daire.mcnamara
2023-06-30 15:48 ` [PATCH v2 7/8] PCI: microchip: Rename and refactor mc_pcie_enable_msi() daire.mcnamara
2023-06-30 15:48   ` daire.mcnamara
2023-07-01 23:13   ` Conor Dooley
2023-07-01 23:13     ` Conor Dooley
2023-07-19 17:41   ` Bjorn Helgaas
2023-07-19 17:41     ` Bjorn Helgaas
2023-07-27 15:27     ` Lorenzo Pieralisi [this message]
2023-07-27 15:27       ` Lorenzo Pieralisi
2023-06-30 15:48 ` [PATCH v2 8/8] PCI: microchip: Re-partition code between probe() and init() daire.mcnamara
2023-06-30 15:48   ` daire.mcnamara
2023-07-19 17:00 ` [PATCH v2 0/8] PCI: microchip: Fixes and clean-ups Conor Dooley
2023-07-19 17:00   ` Conor Dooley
2023-07-20  8:07   ` Lorenzo Pieralisi
2023-07-20  8:07     ` Lorenzo Pieralisi

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