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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Vinod Govindapillai <vinod.govindapillai@intel.com>
Cc: intel-gfx@lists.freedesktop.org, ville.syrjala@intel.com,
	intel-xe@lists.freedesktop.org
Subject: Re: [Intel-gfx] [Intel-xe] [PATCH 2/4] drm/i915/lnl: update FBC debugfs to include plane information
Date: Tue, 29 Aug 2023 10:46:11 +0300	[thread overview]
Message-ID: <ZO2iQytXpy04CG1R@intel.com> (raw)
In-Reply-To: <20230828062035.6906-3-vinod.govindapillai@intel.com>

On Mon, Aug 28, 2023 at 09:20:33AM +0300, Vinod Govindapillai wrote:
> In future platforms, FBC can be supported on planes other than
> the primary plane. So update the debugfs entry for FBC status
> to have the plane ID included.
> 
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index d36499d7e0be..45e205a0f740 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1837,7 +1837,9 @@ static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
>  	mutex_lock(&fbc->lock);
>  
>  	if (fbc->active) {
> -		seq_puts(m, "FBC enabled\n");
> +		seq_printf(m, "FBC enabled: [PLANE:%d:%s]\n",
> +			   fbc->state.plane->base.base.id,
> +			   fbc->state.plane->base.name);

That informtion is already part of the plane loop below.

>  		seq_printf(m, "Compressing: %s\n",
>  			   str_yes_no(intel_fbc_is_compressing(fbc)));
>  	} else {
> @@ -1910,10 +1912,16 @@ static void intel_fbc_debugfs_add(struct intel_fbc *fbc,
>  
>  void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc)
>  {
> -	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +	struct intel_plane *plane;
> +
> +	for_each_intel_plane(&i915->drm, plane) {
> +		if (!plane->fbc || plane->pipe != crtc->pipe)
> +			continue;
>  
> -	if (plane->fbc)
>  		intel_fbc_debugfs_add(plane->fbc, crtc->base.debugfs_entry);
> +		break;
> +	}

Do we have a case where the first plane wouldn't support FBC? If not
this wouldn't really be needed. But I guess no harm in iterating here
too.

>  }
>  
>  /* FIXME: remove this once igt is on board with per-crtc stuff */
> -- 
> 2.34.1

-- 
Ville Syrjälä
Intel

WARNING: multiple messages have this Message-ID (diff)
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Vinod Govindapillai <vinod.govindapillai@intel.com>
Cc: intel-gfx@lists.freedesktop.org, ville.syrjala@intel.com,
	intel-xe@lists.freedesktop.org
Subject: Re: [Intel-xe] [PATCH 2/4] drm/i915/lnl: update FBC debugfs to include plane information
Date: Tue, 29 Aug 2023 10:46:11 +0300	[thread overview]
Message-ID: <ZO2iQytXpy04CG1R@intel.com> (raw)
In-Reply-To: <20230828062035.6906-3-vinod.govindapillai@intel.com>

On Mon, Aug 28, 2023 at 09:20:33AM +0300, Vinod Govindapillai wrote:
> In future platforms, FBC can be supported on planes other than
> the primary plane. So update the debugfs entry for FBC status
> to have the plane ID included.
> 
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index d36499d7e0be..45e205a0f740 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1837,7 +1837,9 @@ static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
>  	mutex_lock(&fbc->lock);
>  
>  	if (fbc->active) {
> -		seq_puts(m, "FBC enabled\n");
> +		seq_printf(m, "FBC enabled: [PLANE:%d:%s]\n",
> +			   fbc->state.plane->base.base.id,
> +			   fbc->state.plane->base.name);

That informtion is already part of the plane loop below.

>  		seq_printf(m, "Compressing: %s\n",
>  			   str_yes_no(intel_fbc_is_compressing(fbc)));
>  	} else {
> @@ -1910,10 +1912,16 @@ static void intel_fbc_debugfs_add(struct intel_fbc *fbc,
>  
>  void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc)
>  {
> -	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +	struct intel_plane *plane;
> +
> +	for_each_intel_plane(&i915->drm, plane) {
> +		if (!plane->fbc || plane->pipe != crtc->pipe)
> +			continue;
>  
> -	if (plane->fbc)
>  		intel_fbc_debugfs_add(plane->fbc, crtc->base.debugfs_entry);
> +		break;
> +	}

Do we have a case where the first plane wouldn't support FBC? If not
this wouldn't really be needed. But I guess no harm in iterating here
too.

>  }
>  
>  /* FIXME: remove this once igt is on board with per-crtc stuff */
> -- 
> 2.34.1

-- 
Ville Syrjälä
Intel

  parent reply	other threads:[~2023-08-29  7:46 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-28  6:20 [Intel-gfx] [PATCH 0/4] fbc on any plane Vinod Govindapillai
2023-08-28  6:20 ` [Intel-xe] " Vinod Govindapillai
2023-08-28  6:20 ` [Intel-gfx] [PATCH 1/4] drm/i915/lnl: FBC can be enabled with PSR2 Vinod Govindapillai
2023-08-28  6:20   ` [Intel-xe] " Vinod Govindapillai
2023-08-28 23:58   ` [Intel-gfx] " Matt Roper
2023-08-28 23:58     ` Matt Roper
2023-08-29 12:16     ` [Intel-gfx] " Govindapillai, Vinod
2023-08-29 12:16       ` Govindapillai, Vinod
2023-08-28  6:20 ` [Intel-gfx] [PATCH 2/4] drm/i915/lnl: update FBC debugfs to include plane information Vinod Govindapillai
2023-08-28  6:20   ` [Intel-xe] " Vinod Govindapillai
2023-08-29  0:01   ` [Intel-gfx] " Matt Roper
2023-08-29  0:01     ` Matt Roper
2023-08-29  7:46   ` Ville Syrjälä [this message]
2023-08-29  7:46     ` Ville Syrjälä
2023-08-28  6:20 ` [Intel-gfx] [PATCH 3/4] drm/i915/lnl: support FBC on any plane Vinod Govindapillai
2023-08-28  6:20   ` [Intel-xe] " Vinod Govindapillai
2023-08-28  9:00   ` [Intel-gfx] " Jani Nikula
2023-08-28  9:00     ` Jani Nikula
2023-08-28 10:10     ` [Intel-gfx] " Govindapillai, Vinod
2023-08-28 10:10       ` Govindapillai, Vinod
2023-08-29  0:16   ` [Intel-gfx] " Matt Roper
2023-08-29  0:16     ` Matt Roper
2023-08-29 13:50     ` [Intel-gfx] " Govindapillai, Vinod
2023-08-29 13:50       ` Govindapillai, Vinod
2023-08-29 16:04       ` [Intel-gfx] " Matt Roper
2023-08-29 16:04         ` Matt Roper
2023-08-30  6:06         ` [Intel-gfx] " Ville Syrjälä
2023-08-30  6:06           ` [Intel-xe] [Intel-gfx] " Ville Syrjälä
2023-08-29  7:50   ` [Intel-gfx] [Intel-xe] " Ville Syrjälä
2023-08-29  7:50     ` Ville Syrjälä
2023-08-29 13:34     ` [Intel-gfx] " Govindapillai, Vinod
2023-08-29 13:34       ` Govindapillai, Vinod
2023-08-30  5:34       ` [Intel-gfx] " Ville Syrjälä
2023-08-30  5:34         ` Ville Syrjälä
2023-08-28  6:20 ` [Intel-gfx] [PATCH 4/4] drm/i915/lnl: FBC is supported with per pixel alpha Vinod Govindapillai
2023-08-28  6:20   ` [Intel-xe] " Vinod Govindapillai
2023-08-28  7:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for fbc on any plane Patchwork
2023-08-28  7:24 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-08-28  7:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-08-28  9:04 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-09-01  3:28 ` [Intel-xe] ✓ CI.Patch_applied: success for fbc on any plane (rev2) Patchwork
2023-09-01  3:28 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-09-01  3:29 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-09-01  3:36 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-09-01  3:36 ` [Intel-xe] ✗ CI.Hooks: failure " Patchwork
2023-09-01  3:37 ` [Intel-xe] ✗ CI.checksparse: warning " Patchwork
2023-09-01  4:09 ` [Intel-xe] ✓ CI.BAT: success " Patchwork

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