Re: [PATCH 4/4] riscv: dts: sophgo: add reset phandle to all uart nodes

From: Jisheng Zhang <jszhang@kernel.org>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>, Chao Wei <chao.wei@sophgo.com>,
	Chen Wang <unicorn_wang@outlook.com>
Subject: Re: [PATCH 4/4] riscv: dts: sophgo: add reset phandle to all uart nodes
Date: Mon, 13 Nov 2023 21:09:01 +0800	[thread overview]
Message-ID: <ZVIf7cw1ak+nxnuW@xhacker> (raw)
In-Reply-To: <95c20c6c-66cd-4f87-920b-5da766317e19@sifive.com>

On Sun, Nov 12, 2023 at 09:04:55PM -0500, Samuel Holland wrote:
> Hi Jisheng,
> 
> On 2023-11-12 6:55 PM, Jisheng Zhang wrote:
> > Although, the resets are deasserted by default. Add them for
> > completeness.
> > 
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > ---
> >  arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 6 ++++++
> >  1 file changed, 6 insertions(+)
> > 
> > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > index 4032419486be..e04df04a91c0 100644
> > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > @@ -4,6 +4,7 @@
> >   */
> >  
> >  #include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/reset/sophgo,cv1800b-reset.h>
> >  
> >  / {
> >  	compatible = "sophgo,cv1800b";
> > @@ -65,6 +66,7 @@ uart0: serial@4140000 {
> >  			reg = <0x04140000 0x100>;
> >  			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&osc>;
> > +			resets = <&rst RST_UART0>;
> 
> Since it's not obvious: this breaks devicetree forward compatibility. An
> existing kernel will fail the devm_reset_control_get_optional_exclusive() in
> 8250_dw.c because it has no driver for the reset controller.
> 
> This may not be a concern yet, since the devicetree is still "in development".
> But it is something to keep in mind for the future. To avoid this sort of
> problem, it's best to fully model the clocks/resets/other dependencies as early
> as possible, and not rely on the firmware setting anything up.

Thank you. This may be discussed before, "DT backward compatibility is a
must while forward compatibility is optional"? maybe I'm wrong.

And Indeed, it's better if we can have forward compatibility, will take
care this in future.

> 
> Regards,
> Samuel
> 
> >  			reg-shift = <2>;
> >  			reg-io-width = <4>;
> >  			status = "disabled";
> > @@ -75,6 +77,7 @@ uart1: serial@4150000 {
> >  			reg = <0x04150000 0x100>;
> >  			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&osc>;
> > +			resets = <&rst RST_UART1>;
> >  			reg-shift = <2>;
> >  			reg-io-width = <4>;
> >  			status = "disabled";
> > @@ -85,6 +88,7 @@ uart2: serial@4160000 {
> >  			reg = <0x04160000 0x100>;
> >  			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&osc>;
> > +			resets = <&rst RST_UART2>;
> >  			reg-shift = <2>;
> >  			reg-io-width = <4>;
> >  			status = "disabled";
> > @@ -95,6 +99,7 @@ uart3: serial@4170000 {
> >  			reg = <0x04170000 0x100>;
> >  			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&osc>;
> > +			resets = <&rst RST_UART3>;
> >  			reg-shift = <2>;
> >  			reg-io-width = <4>;
> >  			status = "disabled";
> > @@ -105,6 +110,7 @@ uart4: serial@41c0000 {
> >  			reg = <0x041c0000 0x100>;
> >  			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&osc>;
> > +			resets = <&rst RST_UART4>;
> >  			reg-shift = <2>;
> >  			reg-io-width = <4>;
> >  			status = "disabled";
> 

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