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From: Sean Christopherson <seanjc@google.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Peter Zijlstra <peterz@infradead.org>,
	Borislav Petkov <bp@alien8.de>, Ingo Molnar <mingo@kernel.org>,
	 "Ahmed S. Darwish" <darwi@linutronix.de>,
	Ard Biesheuvel <ardb+git@google.com>,
	linux-kernel@vger.kernel.org,  x86@kernel.org,
	Ard Biesheuvel <ardb@kernel.org>,
	 Linus Torvalds <torvalds@linux-foundation.org>,
	Brian Gerst <brgerst@gmail.com>,
	 "Kirill A. Shutemov" <kirill@shutemov.name>
Subject: Re: [PATCH v4 1/6] x86/cpu: Use a new feature flag for 5 level paging
Date: Thu, 22 May 2025 15:15:57 -0700	[thread overview]
Message-ID: <aC-iHUcRmgYoE59E@google.com> (raw)
In-Reply-To: <87h61cquww.ffs@tglx>

On Thu, May 22, 2025, Thomas Gleixner wrote:
> On Thu, May 22 2025 at 08:08, Sean Christopherson wrote:
> > On Thu, May 22, 2025, Peter Zijlstra wrote:
> >> On Wed, May 21, 2025 at 05:23:37PM +0200, Thomas Gleixner wrote:
> >> 
> >> >    4) Drivers having access to CPUID is just wrong. We've had issues
> >> >       with that in the past because drivers evaluated CPUID themself and
> >> >       missed that the core code had stuff disabled.
> >> 
> >> I had this patch that read the module instructions and failed loading if
> >> they used 'fancy' instructions. Do you want me to revive that?
> 
> Once we have the new infrastructure in place....
> 
> > Unless you want to grant exceptions, that's not going to fly for KVM.  KVM makes
> > heavy use of CPUID, the consumption/output of which is firmly entrenched in KVM's
> > ABI.
> 
> If there is a full in memory copy of all CPUID leafs, then what needs KVM beyond
> reading it from there?

Ah, I missed that context.  If it's a truly full (e.g. includes the XSTATE sizes
sub-leafs and all that jazz) and unmodified copy, then it'll work.

If it's a modified/filtered copy, it might work?  I'd have to think/dig more.
I'm pretty sure the only CPUID-based feature that KVM supports based solely on
hardware capabilities is LA57, and it sounds like that will have special handling
anyways.

My bigger concern is cases where the kernel _adds_ features.  KVM's default
handling of features is to advertise support if and only both the host kernel
and hardware support a feature.  I.e. KVM does a bitwise-AND of CPUID and
boot_cpu_data.x86_capability.  KVM does opt-in for a handful of features, but
they are the exception, not the rule.  I don't see an obvious way to maintain
that behavior without KVM doing CPUID itself.

  reply	other threads:[~2025-05-22 22:15 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-17  9:16 [PATCH v4 0/6] x86: Robustify pgtable_l5_enabled() Ard Biesheuvel
2025-05-17  9:16 ` [PATCH v4 1/6] x86/cpu: Use a new feature flag for 5 level paging Ard Biesheuvel
2025-05-17 14:28   ` Ard Biesheuvel
2025-05-19  8:35     ` Ingo Molnar
2025-05-19  9:40   ` Borislav Petkov
2025-05-19  9:46     ` Ard Biesheuvel
2025-05-19 12:15       ` Borislav Petkov
2025-05-19 12:24         ` Borislav Petkov
2025-05-19 12:25         ` Ard Biesheuvel
2025-05-19 13:08     ` Ingo Molnar
2025-05-19 13:19       ` Borislav Petkov
2025-05-21 15:23         ` Thomas Gleixner
2025-05-21 18:11           ` Borislav Petkov
2025-05-21 18:56             ` Thomas Gleixner
2025-05-21 19:29               ` Borislav Petkov
2025-05-21 19:41                 ` Thomas Gleixner
2025-05-21 19:48                   ` Borislav Petkov
2025-05-21 20:07                     ` Thomas Gleixner
2025-05-22  7:55           ` Peter Zijlstra
2025-05-22 15:08             ` Sean Christopherson
2025-05-22 19:58               ` Thomas Gleixner
2025-05-22 22:15                 ` Sean Christopherson [this message]
2025-05-19 12:55   ` [tip: x86/core] x86/cpu: Use a new feature flag for 5-level paging tip-bot2 for Ard Biesheuvel
2025-05-19 13:12     ` Ingo Molnar
2025-05-17  9:16 ` [PATCH v4 2/6] x86/cpu: Move CPU capability override arrays from BSS to __ro_after_init Ard Biesheuvel
2025-05-19 12:01   ` Brian Gerst
2025-05-17  9:16 ` [PATCH v4 3/6] x86/cpu: Allow caps to be set arbitrarily early Ard Biesheuvel
2025-05-17  9:16 ` [PATCH v4 4/6] x86/boot: Set 5-level paging CPU cap before entering C code Ard Biesheuvel
2025-05-17  9:16 ` [PATCH v4 5/6] x86/boot: Drop the early variant of pgtable_l5_enabled() Ard Biesheuvel
2025-05-17  9:16 ` [PATCH v4 6/6] x86/boot: Drop 5-level paging related variables and early updates Ard Biesheuvel

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