Re: [PATCH v4 1/6] x86/cpu: Use a new feature flag for 5 level paging

[Ingo Molnar <mingo@kernel.org>]

* Borislav Petkov <bp@alien8.de> wrote:

> On Sat, May 17, 2025 at 11:16:41AM +0200, Ard Biesheuvel wrote:
> > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> > index f67a93fc9391..5c19bee0af11 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -395,7 +395,7 @@
> >  #define X86_FEATURE_AVX512_BITALG	(16*32+12) /* "avx512_bitalg" Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */
> >  #define X86_FEATURE_TME			(16*32+13) /* "tme" Intel Total Memory Encryption */
> >  #define X86_FEATURE_AVX512_VPOPCNTDQ	(16*32+14) /* "avx512_vpopcntdq" POPCNT for vectors of DW/QW */
> > -#define X86_FEATURE_LA57		(16*32+16) /* "la57" 5-level page tables */
> > +#define X86_FEATURE_LA57		(16*32+16) /* 57-bit linear addressing */
> >  #define X86_FEATURE_RDPID		(16*32+22) /* "rdpid" RDPID instruction */
> >  #define X86_FEATURE_BUS_LOCK_DETECT	(16*32+24) /* "bus_lock_detect" Bus Lock detect */
> >  #define X86_FEATURE_CLDEMOTE		(16*32+25) /* "cldemote" CLDEMOTE instruction */
> > @@ -483,6 +483,7 @@
> >  #define X86_FEATURE_PREFER_YMM		(21*32+ 8) /* Avoid ZMM registers due to downclocking */
> >  #define X86_FEATURE_APX			(21*32+ 9) /* Advanced Performance Extensions */
> >  #define X86_FEATURE_INDIRECT_THUNK_ITS	(21*32+10) /* Use thunk for indirect branches in lower half of cacheline */
> > +#define X86_FEATURE_5LEVEL_PAGING	(21*32+11) /* "la57" Whether 5 levels of page tables are in use */
> 
> I don't think we need this second flag - you can simply clear the existing
> one.

That's what the old code did, and it was an error to do that, we almost 
never do that for CPU hardware capability flags:

 - Do we clear the PAE flag just because the kernel isn't PAE?  We don't.
 - Do we clear the CX8 flag just because it's a UP kernel?      We don't.
 - Do we clear the VMX/SVM flag just because KVM isn't running? We don't.
 - etc. etc.

The handling of the LA57 flag is the odd one out, and it was a mistake 
for the 5-level paging kernel to clear the LA57 flag.

The second best thing we can do is to have a sane, constant LA57 flag 
for the hardware capability, and introduce a synthethic flag that is 
set conditionally (X86_FEATURE_5LEVEL_PAGING) - which is how it should 
have been done originally, and to maintain compatibility, expose the 
synthethic flag in /proc/cpuinfo as 'la57' to maintain the ABI.

And let's remember this the next time someone submits a kernel series 
with CPU flag clearing... ;-)

Thanks,

	Ingo