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From: Ingo Molnar <mingo@kernel.org>
To: Ard Biesheuvel <ardb@kernel.org>
Cc: Ard Biesheuvel <ardb+git@google.com>,
	linux-kernel@vger.kernel.org, x86@kernel.org,
	Linus Torvalds <torvalds@linux-foundation.org>,
	Brian Gerst <brgerst@gmail.com>,
	"Kirill A. Shutemov" <kirill@shutemov.name>
Subject: Re: [PATCH v4 1/6] x86/cpu: Use a new feature flag for 5 level paging
Date: Mon, 19 May 2025 10:35:53 +0200	[thread overview]
Message-ID: <aCrtaQhArS7gSb04@gmail.com> (raw)
In-Reply-To: <CAMj1kXE=-408evLMwPkH5SqK-=QPpONGSXCi4_YeZAgLt06Aqg@mail.gmail.com>


* Ard Biesheuvel <ardb@kernel.org> wrote:

> >, and add a
> > new string la57_capable to indicate that the CPU feature is implemented
> > by the hardware.
> >
> 
> ^^^ forgot to drop this

I've rewritten this paragraph to:

    The 'la57' flag's behavior in /proc/cpuinfo remains unchanged.

Thanks,

	Ingo

  reply	other threads:[~2025-05-19  8:35 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-17  9:16 [PATCH v4 0/6] x86: Robustify pgtable_l5_enabled() Ard Biesheuvel
2025-05-17  9:16 ` [PATCH v4 1/6] x86/cpu: Use a new feature flag for 5 level paging Ard Biesheuvel
2025-05-17 14:28   ` Ard Biesheuvel
2025-05-19  8:35     ` Ingo Molnar [this message]
2025-05-19  9:40   ` Borislav Petkov
2025-05-19  9:46     ` Ard Biesheuvel
2025-05-19 12:15       ` Borislav Petkov
2025-05-19 12:24         ` Borislav Petkov
2025-05-19 12:25         ` Ard Biesheuvel
2025-05-19 13:08     ` Ingo Molnar
2025-05-19 13:19       ` Borislav Petkov
2025-05-21 15:23         ` Thomas Gleixner
2025-05-21 18:11           ` Borislav Petkov
2025-05-21 18:56             ` Thomas Gleixner
2025-05-21 19:29               ` Borislav Petkov
2025-05-21 19:41                 ` Thomas Gleixner
2025-05-21 19:48                   ` Borislav Petkov
2025-05-21 20:07                     ` Thomas Gleixner
2025-05-22  7:55           ` Peter Zijlstra
2025-05-22 15:08             ` Sean Christopherson
2025-05-22 19:58               ` Thomas Gleixner
2025-05-22 22:15                 ` Sean Christopherson
2025-05-19 12:55   ` [tip: x86/core] x86/cpu: Use a new feature flag for 5-level paging tip-bot2 for Ard Biesheuvel
2025-05-19 13:12     ` Ingo Molnar
2025-05-17  9:16 ` [PATCH v4 2/6] x86/cpu: Move CPU capability override arrays from BSS to __ro_after_init Ard Biesheuvel
2025-05-19 12:01   ` Brian Gerst
2025-05-17  9:16 ` [PATCH v4 3/6] x86/cpu: Allow caps to be set arbitrarily early Ard Biesheuvel
2025-05-17  9:16 ` [PATCH v4 4/6] x86/boot: Set 5-level paging CPU cap before entering C code Ard Biesheuvel
2025-05-17  9:16 ` [PATCH v4 5/6] x86/boot: Drop the early variant of pgtable_l5_enabled() Ard Biesheuvel
2025-05-17  9:16 ` [PATCH v4 6/6] x86/boot: Drop 5-level paging related variables and early updates Ard Biesheuvel

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