* [PATCH 01/10] riscv: lib: Split out support for T-Head cache management operations
2025-04-26 16:56 [PATCH 00/10] Initial SPL support for T-Head TH1520 SoC Yao Zi
@ 2025-04-26 16:56 ` Yao Zi
2025-05-12 9:56 ` Leo Liang
2025-04-26 16:56 ` [PATCH 02/10] riscv: dts: th1520: Add clock-frequency for UART0 Yao Zi
` (9 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Yao Zi @ 2025-04-26 16:56 UTC (permalink / raw)
To: Rick Chen, Leo, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang
Cc: u-boot, Han Gao, Han Gao, Yao Zi
Designed before a standard set of cache management operations defined in
RISC-V, earlier T-Head cores like C906 and C910 provide CMO through the
customized extension XTheadCMO, which has been used in the CV1800B port
of U-Boot.
This patch splits XTheadCMO-related code into a generic module, allowing
SoCs shipping T-Head cores to share the code.
Link: https://github.com/XUANTIE-RV/thead-extension-spec
Signed-off-by: Yao Zi <ziyao@disroot.org>
---
arch/riscv/Kconfig | 8 ++++++++
arch/riscv/cpu/cv1800b/Kconfig | 1 +
arch/riscv/cpu/cv1800b/Makefile | 1 -
arch/riscv/lib/Makefile | 1 +
arch/riscv/{cpu/cv1800b/cache.c => lib/thead_cmo.c} | 0
5 files changed, 10 insertions(+), 1 deletion(-)
rename arch/riscv/{cpu/cv1800b/cache.c => lib/thead_cmo.c} (100%)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index b24623590f2..dc36d9b8566 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -77,6 +77,14 @@ config SYS_DCACHE_OFF
help
Do not enable data cache in U-Boot.
+config SYS_CACHE_THEAD_CMO
+ bool "THEAD non-standard cache operations"
+ depends on !SYS_DCACHE_OFF
+ default n
+ help
+ Support for non-standard cache management operations on SoCs based on
+ T-Head C906/C910 cores.
+
config SPL_SYS_DCACHE_OFF
bool "Do not enable dcache in SPL"
depends on SPL
diff --git a/arch/riscv/cpu/cv1800b/Kconfig b/arch/riscv/cpu/cv1800b/Kconfig
index 7225b1210c5..57f724ae043 100644
--- a/arch/riscv/cpu/cv1800b/Kconfig
+++ b/arch/riscv/cpu/cv1800b/Kconfig
@@ -6,6 +6,7 @@ config SOPHGO_CV1800B
bool
select ARCH_EARLY_INIT_R
select SYS_CACHE_SHIFT_6
+ select SYS_CACHE_THEAD_CMO
imply CPU
imply CPU_RISCV
imply RISCV_TIMER
diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile
index 95beb34b51a..da12e0f64e1 100644
--- a/arch/riscv/cpu/cv1800b/Makefile
+++ b/arch/riscv/cpu/cv1800b/Makefile
@@ -4,4 +4,3 @@
obj-y += dram.o
obj-y += cpu.o
-obj-y += cache.o
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 189b35c24d3..db8d235c699 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
obj-$(CONFIG_CMD_GO) += boot.o
obj-y += cache.o
obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
+obj-$(CONFIG_SYS_CACHE_THEAD_CMO) += thead_cmo.o
ifeq ($(CONFIG_$(PHASE_)RISCV_MMODE),y)
obj-$(CONFIG_$(PHASE_)RISCV_ACLINT) += aclint_ipi.o
obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o
diff --git a/arch/riscv/cpu/cv1800b/cache.c b/arch/riscv/lib/thead_cmo.c
similarity index 100%
rename from arch/riscv/cpu/cv1800b/cache.c
rename to arch/riscv/lib/thead_cmo.c
--
2.49.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 01/10] riscv: lib: Split out support for T-Head cache management operations
2025-04-26 16:56 ` [PATCH 01/10] riscv: lib: Split out support for T-Head cache management operations Yao Zi
@ 2025-05-12 9:56 ` Leo Liang
0 siblings, 0 replies; 27+ messages in thread
From: Leo Liang @ 2025-05-12 9:56 UTC (permalink / raw)
To: Yao Zi
Cc: Rick Chen, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang, u-boot, Han Gao,
Han Gao
On Sat, Apr 26, 2025 at 04:56:55PM +0000, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> Designed before a standard set of cache management operations defined in
> RISC-V, earlier T-Head cores like C906 and C910 provide CMO through the
> customized extension XTheadCMO, which has been used in the CV1800B port
> of U-Boot.
>
> This patch splits XTheadCMO-related code into a generic module, allowing
> SoCs shipping T-Head cores to share the code.
>
> Link: https://github.com/XUANTIE-RV/thead-extension-spec
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
> arch/riscv/Kconfig | 8 ++++++++
> arch/riscv/cpu/cv1800b/Kconfig | 1 +
> arch/riscv/cpu/cv1800b/Makefile | 1 -
> arch/riscv/lib/Makefile | 1 +
> arch/riscv/{cpu/cv1800b/cache.c => lib/thead_cmo.c} | 0
> 5 files changed, 10 insertions(+), 1 deletion(-)
> rename arch/riscv/{cpu/cv1800b/cache.c => lib/thead_cmo.c} (100%)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 02/10] riscv: dts: th1520: Add clock-frequency for UART0
2025-04-26 16:56 [PATCH 00/10] Initial SPL support for T-Head TH1520 SoC Yao Zi
2025-04-26 16:56 ` [PATCH 01/10] riscv: lib: Split out support for T-Head cache management operations Yao Zi
@ 2025-04-26 16:56 ` Yao Zi
2025-05-12 9:57 ` Leo Liang
2025-04-26 16:56 ` [PATCH 03/10] riscv: cpu: Add TH1520 CPU support Yao Zi
` (8 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Yao Zi @ 2025-04-26 16:56 UTC (permalink / raw)
To: Rick Chen, Leo, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang
Cc: u-boot, Han Gao, Han Gao, Yao Zi
The BROM of TH1520 always initializes its clock and configure the
baudrate to 115200. Add a clock-frequency property to provide such
information without introducing CCF to SPL.
Signed-off-by: Yao Zi <ziyao@disroot.org>
---
arch/riscv/dts/th1520.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi
index cbe3481fadd..e4c8cee66bc 100644
--- a/arch/riscv/dts/th1520.dtsi
+++ b/arch/riscv/dts/th1520.dtsi
@@ -175,6 +175,7 @@
reg = <0xff 0xe7014000 0x0 0x100>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_sclk>;
+ clock-frequency = <100000000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
--
2.49.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 02/10] riscv: dts: th1520: Add clock-frequency for UART0
2025-04-26 16:56 ` [PATCH 02/10] riscv: dts: th1520: Add clock-frequency for UART0 Yao Zi
@ 2025-05-12 9:57 ` Leo Liang
2025-05-12 11:53 ` e
0 siblings, 1 reply; 27+ messages in thread
From: Leo Liang @ 2025-05-12 9:57 UTC (permalink / raw)
To: Yao Zi
Cc: Rick Chen, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang, u-boot, Han Gao,
Han Gao
On Sat, Apr 26, 2025 at 04:56:56PM +0000, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> The BROM of TH1520 always initializes its clock and configure the
> baudrate to 115200. Add a clock-frequency property to provide such
> information without introducing CCF to SPL.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
> arch/riscv/dts/th1520.dtsi | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 02/10] riscv: dts: th1520: Add clock-frequency for UART0
2025-05-12 9:57 ` Leo Liang
@ 2025-05-12 11:53 ` e
2025-05-13 4:06 ` Yao Zi
0 siblings, 1 reply; 27+ messages in thread
From: e @ 2025-05-12 11:53 UTC (permalink / raw)
To: Leo Liang
Cc: Yao Zi, Rick Chen, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang, u-boot, Han Gao,
Han Gao
On 2025-05-12 05:57, Leo Liang wrote:
> On Sat, Apr 26, 2025 at 04:56:56PM +0000, Yao Zi wrote:
>> [EXTERNAL MAIL]
>>
>> The BROM of TH1520 always initializes its clock and configure the
>> baudrate to 115200. Add a clock-frequency property to provide such
>> information without introducing CCF to SPL.
>>
>> Signed-off-by: Yao Zi <ziyao@disroot.org>
>> ---
>> arch/riscv/dts/th1520.dtsi | 1 +
>> 1 file changed, 1 insertion(+)
>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
NAK from me. Quoting Emil "The uart0 node already has a reference to the
uart0_core clock, so it shouldn't
need this property." If SPL does not support the clock framework to do
this parent node lookup properly from device-tree then we should not be
adjusting the device-tree in this way; use instead the codepath in
serial driver that checks a compile-time define.
See for example:
https://lore.kernel.org/u-boot/20250503115301.972550-1-e@freeshell.de/
- E
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 02/10] riscv: dts: th1520: Add clock-frequency for UART0
2025-05-12 11:53 ` e
@ 2025-05-13 4:06 ` Yao Zi
0 siblings, 0 replies; 27+ messages in thread
From: Yao Zi @ 2025-05-13 4:06 UTC (permalink / raw)
To: e, Leo Liang
Cc: Rick Chen, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang, u-boot, Han Gao,
Han Gao
On Mon, May 12, 2025 at 07:53:01AM -0400, e wrote:
> On 2025-05-12 05:57, Leo Liang wrote:
> > On Sat, Apr 26, 2025 at 04:56:56PM +0000, Yao Zi wrote:
> > > [EXTERNAL MAIL]
> > >
> > > The BROM of TH1520 always initializes its clock and configure the
> > > baudrate to 115200. Add a clock-frequency property to provide such
> > > information without introducing CCF to SPL.
> > >
> > > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > > ---
> > > arch/riscv/dts/th1520.dtsi | 1 +
> > > 1 file changed, 1 insertion(+)
> >
> > Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
>
> NAK from me. Quoting Emil "The uart0 node already has a reference to the
> uart0_core clock, so it shouldn't
> need this property." If SPL does not support the clock framework to do this
> parent node lookup properly from device-tree then we should not be adjusting
> the device-tree in this way; use instead the codepath in serial driver that
> checks a compile-time define.
I was not aware of the codepath, thanks for the hint! It should be the
correct way to go and I'll try to take in v2.
> See for example:
> https://lore.kernel.org/u-boot/20250503115301.972550-1-e@freeshell.de/
>
> - E
Best regards,
Yao Zi
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 03/10] riscv: cpu: Add TH1520 CPU support
2025-04-26 16:56 [PATCH 00/10] Initial SPL support for T-Head TH1520 SoC Yao Zi
2025-04-26 16:56 ` [PATCH 01/10] riscv: lib: Split out support for T-Head cache management operations Yao Zi
2025-04-26 16:56 ` [PATCH 02/10] riscv: dts: th1520: Add clock-frequency for UART0 Yao Zi
@ 2025-04-26 16:56 ` Yao Zi
2025-05-12 9:59 ` Leo Liang
2025-04-26 16:56 ` [PATCH 04/10] ram: thead: Add initial DDR controller support for TH1520 Yao Zi
` (7 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Yao Zi @ 2025-04-26 16:56 UTC (permalink / raw)
To: Rick Chen, Leo, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang
Cc: u-boot, Han Gao, Han Gao, Yao Zi
Introduce the SoC-specific code and corresponding Kconfig entries for
TH1520 SoC. Following features are implemented for TH1520,
- Cache enable/disable through customized CSR
- Invalidation of customized PMP entries
- DRAM driver probing for SPL
Signed-off-by: Yao Zi <ziyao@disroot.org>
---
arch/riscv/Kconfig | 1 +
arch/riscv/cpu/th1520/Kconfig | 21 ++++++++++++++++
arch/riscv/cpu/th1520/Makefile | 8 ++++++
arch/riscv/cpu/th1520/cache.c | 32 ++++++++++++++++++++++++
arch/riscv/cpu/th1520/cpu.c | 21 ++++++++++++++++
arch/riscv/cpu/th1520/dram.c | 21 ++++++++++++++++
arch/riscv/cpu/th1520/spl.c | 31 +++++++++++++++++++++++
arch/riscv/include/asm/arch-th1520/cpu.h | 9 +++++++
arch/riscv/include/asm/arch-th1520/spl.h | 10 ++++++++
9 files changed, 154 insertions(+)
create mode 100644 arch/riscv/cpu/th1520/Kconfig
create mode 100644 arch/riscv/cpu/th1520/Makefile
create mode 100644 arch/riscv/cpu/th1520/cache.c
create mode 100644 arch/riscv/cpu/th1520/cpu.c
create mode 100644 arch/riscv/cpu/th1520/dram.c
create mode 100644 arch/riscv/cpu/th1520/spl.c
create mode 100644 arch/riscv/include/asm/arch-th1520/cpu.h
create mode 100644 arch/riscv/include/asm/arch-th1520/spl.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index dc36d9b8566..8c6feae5735 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -126,6 +126,7 @@ source "arch/riscv/cpu/generic/Kconfig"
source "arch/riscv/cpu/jh7110/Kconfig"
source "arch/riscv/cpu/k1/Kconfig"
source "arch/riscv/cpu/k230/Kconfig"
+source "arch/riscv/cpu/th1520/Kconfig"
# architecture-specific options below
diff --git a/arch/riscv/cpu/th1520/Kconfig b/arch/riscv/cpu/th1520/Kconfig
new file mode 100644
index 00000000000..a916d364e6c
--- /dev/null
+++ b/arch/riscv/cpu/th1520/Kconfig
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+# Copyright (C) 2025, Yao Zi <ziyao@disroot.org>
+
+config THEAD_TH1520
+ bool
+ select ARCH_EARLY_INIT_R
+ select SYS_CACHE_SHIFT_6
+ select SUPPORT_SPL
+ select BINMAN if SPL
+ select SYS_CACHE_THEAD_CMO
+ imply CPU
+ imply CPU_RISCV
+ imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+ imply RISCV_ACLINT if RISCV_MMODE
+ imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE
+ imply CMD_CPU
+ imply SPL_CPU
+ imply SPL_OPENSBI
+ imply SPL_LOAD_FIT
diff --git a/arch/riscv/cpu/th1520/Makefile b/arch/riscv/cpu/th1520/Makefile
new file mode 100644
index 00000000000..5d806c06e2e
--- /dev/null
+++ b/arch/riscv/cpu/th1520/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2025, Yao Zi <ziyao@disroot.org>
+
+obj-y += cache.o
+obj-y += cpu.o
+obj-y += dram.o
+obj-y += spl.o
diff --git a/arch/riscv/cpu/th1520/cache.c b/arch/riscv/cpu/th1520/cache.c
new file mode 100644
index 00000000000..08aa1f789fd
--- /dev/null
+++ b/arch/riscv/cpu/th1520/cache.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025 Yao Zi <ziyao@disroot.org>
+ */
+
+#include <asm/io.h>
+#include <cpu_func.h>
+#include <linux/bitops.h>
+
+#define CSR_MHCR 0x7c1
+#define CSR_MHCR_IE BIT(0)
+#define CSR_MHCR_DE BIT(1)
+
+void icache_enable(void)
+{
+ csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_IE);
+}
+
+void dcache_enable(void)
+{
+ csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_DE);
+}
+
+int icache_status(void)
+{
+ return (csr_read(CSR_MHCR) & CSR_MHCR_IE) != 0;
+}
+
+int dcache_status(void)
+{
+ return (csr_read(CSR_MHCR) & CSR_MHCR_DE) != 0;
+}
diff --git a/arch/riscv/cpu/th1520/cpu.c b/arch/riscv/cpu/th1520/cpu.c
new file mode 100644
index 00000000000..b83f1272c67
--- /dev/null
+++ b/arch/riscv/cpu/th1520/cpu.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025 Yao Zi <ziyao@disroot.org>
+ *
+ * TH1520 SoC has a set of undocumented customized PMP registers that are
+ * configured through MMIO operation. It must be disabled before entering
+ * the DRAM region, or an exception will be raised.
+ */
+
+#include <asm/io.h>
+#include <cpu_func.h>
+
+#define TH1520_PMP_BASE (void *)0xffdc020000
+
+void th1520_invalidate_pmp(void)
+{
+ /* Invalidate the PMP configuration as in vendor U-Boot code */
+ writel(0x0, TH1520_PMP_BASE + 0x0);
+
+ invalidate_icache_all();
+}
diff --git a/arch/riscv/cpu/th1520/dram.c b/arch/riscv/cpu/th1520/dram.c
new file mode 100644
index 00000000000..91007c0a3d3
--- /dev/null
+++ b/arch/riscv/cpu/th1520/dram.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <fdtdec.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
diff --git a/arch/riscv/cpu/th1520/spl.c b/arch/riscv/cpu/th1520/spl.c
new file mode 100644
index 00000000000..aec398528d1
--- /dev/null
+++ b/arch/riscv/cpu/th1520/spl.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
+ */
+#include <dm.h>
+#include <linux/sizes.h>
+#include <log.h>
+#include <init.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_dram_init(void)
+{
+ int ret;
+ struct udevice *dev;
+
+ ret = fdtdec_setup_mem_size_base();
+ if (ret) {
+ printf("failed to setup memory size and base: %d\n", ret);
+ return ret;
+ }
+
+ /* DDR init */
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ printf("DRAM init failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/arch/riscv/include/asm/arch-th1520/cpu.h b/arch/riscv/include/asm/arch-th1520/cpu.h
new file mode 100644
index 00000000000..837f0b8d06b
--- /dev/null
+++ b/arch/riscv/include/asm/arch-th1520/cpu.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2025 Yao Zi <ziyao@disroot.org>
+ */
+
+#ifndef _ASM_TH1520_CPU_H_
+#define _ASM_TH1520_CPU_H_
+void th1520_invalidate_pmp(void);
+#endif /* _ASM_TH1520_CPU_H_ */
diff --git a/arch/riscv/include/asm/arch-th1520/spl.h b/arch/riscv/include/asm/arch-th1520/spl.h
new file mode 100644
index 00000000000..59aed8cad62
--- /dev/null
+++ b/arch/riscv/include/asm/arch-th1520/spl.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
+ */
+#ifndef _ASM_ARCH_TH1520_SPL_H_
+#define _ASM_ARCH_TH1520_SPL_H_
+
+void spl_dram_init(void);
+
+#endif // _ASM_ARCH_TH1520_SPL_H_
--
2.49.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 03/10] riscv: cpu: Add TH1520 CPU support
2025-04-26 16:56 ` [PATCH 03/10] riscv: cpu: Add TH1520 CPU support Yao Zi
@ 2025-05-12 9:59 ` Leo Liang
0 siblings, 0 replies; 27+ messages in thread
From: Leo Liang @ 2025-05-12 9:59 UTC (permalink / raw)
To: Yao Zi
Cc: Rick Chen, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang, u-boot, Han Gao,
Han Gao
On Sat, Apr 26, 2025 at 04:56:57PM +0000, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> Introduce the SoC-specific code and corresponding Kconfig entries for
> TH1520 SoC. Following features are implemented for TH1520,
>
> - Cache enable/disable through customized CSR
> - Invalidation of customized PMP entries
> - DRAM driver probing for SPL
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
> arch/riscv/Kconfig | 1 +
> arch/riscv/cpu/th1520/Kconfig | 21 ++++++++++++++++
> arch/riscv/cpu/th1520/Makefile | 8 ++++++
> arch/riscv/cpu/th1520/cache.c | 32 ++++++++++++++++++++++++
> arch/riscv/cpu/th1520/cpu.c | 21 ++++++++++++++++
> arch/riscv/cpu/th1520/dram.c | 21 ++++++++++++++++
> arch/riscv/cpu/th1520/spl.c | 31 +++++++++++++++++++++++
> arch/riscv/include/asm/arch-th1520/cpu.h | 9 +++++++
> arch/riscv/include/asm/arch-th1520/spl.h | 10 ++++++++
> 9 files changed, 154 insertions(+)
> create mode 100644 arch/riscv/cpu/th1520/Kconfig
> create mode 100644 arch/riscv/cpu/th1520/Makefile
> create mode 100644 arch/riscv/cpu/th1520/cache.c
> create mode 100644 arch/riscv/cpu/th1520/cpu.c
> create mode 100644 arch/riscv/cpu/th1520/dram.c
> create mode 100644 arch/riscv/cpu/th1520/spl.c
> create mode 100644 arch/riscv/include/asm/arch-th1520/cpu.h
> create mode 100644 arch/riscv/include/asm/arch-th1520/spl.h
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 04/10] ram: thead: Add initial DDR controller support for TH1520
2025-04-26 16:56 [PATCH 00/10] Initial SPL support for T-Head TH1520 SoC Yao Zi
` (2 preceding siblings ...)
2025-04-26 16:56 ` [PATCH 03/10] riscv: cpu: Add TH1520 CPU support Yao Zi
@ 2025-04-26 16:56 ` Yao Zi
2025-04-26 17:09 ` Yao Zi
` (2 more replies)
2025-04-26 17:00 ` Yao Zi
` (6 subsequent siblings)
10 siblings, 3 replies; 27+ messages in thread
From: Yao Zi @ 2025-04-26 16:56 UTC (permalink / raw)
To: Rick Chen, Leo, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang
Cc: u-boot, Han Gao, Han Gao, Yao Zi
This patch cleans the vendor code of DDR initialization up, converts the
driver to fit in DM framework and use a firmware[1] packaged by binman to
ship PHY configuration.
Currently the driver is only capable of initializing the controller to
work with dual-rank 3733MHz LPDDR4, which is shipped by 16GiB variants
of LicheePi 4A boards and I could test with. Support for other
configurations could be easily added later.
Link: https://github.com/ziyao233/th1520-firmware # [1]
Signed-off-by: Yao Zi <ziyao@disroot.org>
---
drivers/ram/Kconfig | 1 +
drivers/ram/Makefile | 4 +
drivers/ram/thead/Kconfig | 5 +
drivers/ram/thead/Makefile | 1 +
drivers/ram/thead/th1520_ddr.c | 781 +++++++++++++++++++++++++++++++++
5 files changed, 792 insertions(+)
create mode 100644 drivers/ram/thead/Kconfig
create mode 100644 drivers/ram/thead/Makefile
create mode 100644 drivers/ram/thead/th1520_ddr.c
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 2a40b0c9f81..39d03e8d3d3 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -135,3 +135,4 @@ source "drivers/ram/sifive/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
source "drivers/ram/starfive/Kconfig"
source "drivers/ram/sunxi/Kconfig"
+source "drivers/ram/thead/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index f92e86eaa3f..82afd5fcbcc 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -30,3 +30,7 @@ obj-$(CONFIG_ARCH_OCTEON) += octeon/
obj-$(CONFIG_ARCH_RENESAS) += renesas/
obj-$(CONFIG_CADENCE_DDR_CTRL) += cadence/
+
+ifdef CONFIG_XPL_BUILD
+obj-$(CONFIG_SPL_THEAD_TH1520_DDR) += thead/
+endif
diff --git a/drivers/ram/thead/Kconfig b/drivers/ram/thead/Kconfig
new file mode 100644
index 00000000000..7b05abb6986
--- /dev/null
+++ b/drivers/ram/thead/Kconfig
@@ -0,0 +1,5 @@
+config SPL_THEAD_TH1520_DDR
+ bool "T-Head TH1520 DDR driver in SPL"
+ depends on SPL_RAM && THEAD_TH1520
+ help
+ This enables DDR support for T-Head TH1520 platforms.
diff --git a/drivers/ram/thead/Makefile b/drivers/ram/thead/Makefile
new file mode 100644
index 00000000000..ad4d053cfc2
--- /dev/null
+++ b/drivers/ram/thead/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_SPL_THEAD_TH1520_DDR) += th1520_ddr.o
diff --git a/drivers/ram/thead/th1520_ddr.c b/drivers/ram/thead/th1520_ddr.c
new file mode 100644
index 00000000000..ff9860b9c3d
--- /dev/null
+++ b/drivers/ram/thead/th1520_ddr.c
@@ -0,0 +1,781 @@
+#include <binman.h>
+#include <binman_sym.h>
+#include <dm.h>
+#include <init.h>
+#include <linux/bitfield.h>
+#include <linux/iopoll.h>
+#include <ram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#pragma pack(push, 1)
+
+struct th1520_ddr_fw {
+ u64 magic;
+ u8 type, ranknum, bitwidth, freq;
+ u8 reserved[8];
+
+ u32 cfgnum;
+ union th1520_ddr_cfg {
+ u32 opaddr;
+
+ struct th1520_ddr_phy {
+ u32 opaddr;
+ u16 data;
+ } phy;
+
+ struct th1520_ddr_range {
+ u32 opaddr;
+ u32 num;
+ u16 data[];
+ } range;
+ } cfgs[];
+};
+
+#pragma pack(pop)
+
+/* Firmware constants */
+#define TH1520_DDR_MAGIC 0x4452444445415448
+
+#define TH1520_DDR_TYPE_LPDDR4 0
+#define TH1520_DDR_TYPE_LPDDR4X 1
+
+#define TH1520_DDR_FREQ_2133 0
+#define TH1520_DDR_FREQ_3200 1
+#define TH1520_DDR_FREQ_3733 2
+#define TH1520_DDR_FREQ_4266 3
+
+#define TH1520_DDR_CFG_OP GENMASK(31, 24)
+#define TH1520_DDR_CFG_ADDR GENMASK(23, 0)
+
+#define TH1520_DDR_CFG_PHY0 0
+#define TH1520_DDR_CFG_PHY1 1
+#define TH1520_DDR_CFG_PHY 2
+#define TH1520_DDR_CFG_RANGE 3
+#define TH1520_DDR_CFG_WAITFW0 4
+#define TH1520_DDR_CFG_WAITFW1 5
+
+/* Driver constants */
+#define TH1520_SYS_PLL_TIMEOUT_US 30
+#define TH1520_CTRL_INIT_TIMEOUT_US 1000000
+#define TH1520_PHY_MSG_TIMEOUT_US 1000000
+
+/* System configuration registers */
+#define TH1520_SYS_DDR_CFG0 0x00
+#define TH1520_SYS_DDR_CFG0_APB_RSTN BIT(4)
+#define TH1520_SYS_DDR_CFG0_CTRL_RSTN BIT(5)
+#define TH1520_SYS_DDR_CFG0_PHY_PWROK_RSTN BIT(6)
+#define TH1520_SYS_DDR_CFG0_PHY_CORE_RSTN BIT(7)
+#define TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(n) BIT(n + 4 + 4)
+#define TH1520_SYS_DDR_CFG1 0x04
+#define TH1520_SYS_PLL_CFG0 0x08
+#define TH1520_SYS_PLL_CFG0_POSTDIV2 GENMASK(26, 24)
+#define TH1520_SYS_PLL_CFG0_POSTDIV1 GENMASK(22, 20)
+#define TH1520_SYS_PLL_CFG0_FBDIV GENMASK(19, 8)
+#define TH1520_SYS_PLL_CFG0_REFDIV GENMASK(5, 0)
+#define TH1520_SYS_PLL_CFG1 0x0c
+#define TH1520_SYS_PLL_CFG1_RST BIT(30)
+#define TH1520_SYS_PLL_CFG1_FOUTPOSTDIVPD BIT(27)
+#define TH1520_SYS_PLL_CFG1_FOUT4PHASEPD BIT(25)
+#define Th1520_SYS_PLL_CFG1_DACPD BIT(24)
+#define TH1520_SYS_PLL_CFG2 0x10
+#define TH1520_SYS_PLL_CFG3 0x14
+#define TH1520_SYS_PLL_STS 0x18
+#define TH1520_SYS_PLL_STS_EN BIT(16)
+#define TH1520_SYS_PLL_STS_LOCKED BIT(0)
+
+/* DDR Controller Registers */
+#define TH1520_CTRL_MSTR 0x0000
+#define TH1520_CTRL_STAT 0x0004
+#define TH1520_CTRL_MRCTRL0 0x0010
+#define TH1520_CTRL_MRCTRL1 0x0014
+#define TH1520_CTRL_MRSTAT 0x0018
+#define TH1520_CTRL_DERATEEN 0x0020
+#define TH1520_CTRL_DERATEINT 0x0024
+#define TH1520_CTRL_DERATECTL 0x002c
+#define TH1520_CTRL_PWRCTL 0x0030
+#define TH1520_CTRL_PWRTMG 0x0034
+#define TH1520_CTRL_HWLPCTL 0x0038
+#define TH1520_CTRL_RFSHCTL0 0x0050
+#define TH1520_CTRL_RFSHCTL1 0x0054
+#define TH1520_CTRL_RFSHCTL3 0x0060
+#define TH1520_CTRL_RFSHTMG 0x0064
+#define TH1520_CTRL_RFSHTMG1 0x0068
+#define TH1520_CTRL_CRCPARCTL0 0x00c0
+#define TH1520_CTRL_CRCPARSTAT 0x00cc
+#define TH1520_CTRL_INIT0 0x00d0
+#define TH1520_CTRL_INIT1 0x00d4
+#define TH1520_CTRL_INIT2 0x00d8
+#define TH1520_CTRL_INIT3 0x00dc
+#define TH1520_CTRL_INIT4 0x00e0
+#define TH1520_CTRL_INIT5 0x00e4
+#define TH1520_CTRL_INIT6 0x00e8
+#define TH1520_CTRL_INIT7 0x00ec
+#define TH1520_CTRL_DIMMCTL 0x00f0
+#define TH1520_CTRL_RANKCTL 0x00f4
+#define TH1520_CTRL_RANKCTL1 0x00f8
+#define TH1520_CTRL_DRAMTMG0 0x0100
+#define TH1520_CTRL_DRAMTMG1 0x0104
+#define TH1520_CTRL_DRAMTMG2 0x0108
+#define TH1520_CTRL_DRAMTMG3 0x010c
+#define TH1520_CTRL_DRAMTMG4 0x0110
+#define TH1520_CTRL_DRAMTMG5 0x0114
+#define TH1520_CTRL_DRAMTMG6 0x0118
+#define TH1520_CTRL_DRAMTMG7 0x011c
+#define TH1520_CTRL_DRAMTMG8 0x0120
+#define TH1520_CTRL_DRAMTMG12 0x0130
+#define TH1520_CTRL_DRAMTMG13 0x0134
+#define TH1520_CTRL_DRAMTMG14 0x0138
+#define TH1520_CTRL_DRAMTMG17 0x0144
+#define TH1520_CTRL_ZQCTL0 0x0180
+#define TH1520_CTRL_ZQCTL1 0x0184
+#define TH1520_CTRL_ZQCTL2 0x0188
+#define TH1520_CTRL_ZQSTAT 0x018c
+#define TH1520_CTRL_DFITMG0 0x0190
+#define TH1520_CTRL_DFITMG1 0x0194
+#define TH1520_CTRL_DFILPCFG0 0x0198
+#define TH1520_CTRL_DFIUPD0 0x01a0
+#define TH1520_CTRL_DFIUPD1 0x01a4
+#define TH1520_CTRL_DFIUPD2 0x01a8
+#define TH1520_CTRL_DFIMISC 0x01b0
+#define TH1520_CTRL_DFITMG2 0x01b4
+#define TH1520_CTRL_DFISTAT 0x01bc
+#define TH1520_CTRL_DBICTL 0x01c0
+#define TH1520_CTRL_DFIPHYMSTR 0x01c4
+#define TH1520_CTRL_ADDRMAP0 0x0200
+#define TH1520_CTRL_ADDRMAP1 0x0204
+#define TH1520_CTRL_ADDRMAP2 0x0208
+#define TH1520_CTRL_ADDRMAP3 0x020c
+#define TH1520_CTRL_ADDRMAP4 0x0210
+#define TH1520_CTRL_ADDRMAP5 0x0214
+#define TH1520_CTRL_ADDRMAP6 0x0218
+#define TH1520_CTRL_ADDRMAP7 0x021c
+#define TH1520_CTRL_ADDRMAP8 0x0220
+#define TH1520_CTRL_ADDRMAP9 0x0224
+#define TH1520_CTRL_ADDRMAP10 0x0228
+#define TH1520_CTRL_ADDRMAP11 0x022c
+#define TH1520_CTRL_ODTCFG 0x0240
+#define TH1520_CTRL_ODTMAP 0x0244
+#define TH1520_CTRL_SCHED 0x0250
+#define TH1520_CTRL_SCHED1 0x0254
+#define TH1520_CTRL_PERFHPR1 0x025c
+#define TH1520_CTRL_PERFLPR1 0x0264
+#define TH1520_CTRL_PERFWR1 0x026c
+#define TH1520_CTRL_SCHED3 0x0270
+#define TH1520_CTRL_SCHED4 0x0274
+#define TH1520_CTRL_DBG0 0x0300
+#define TH1520_CTRL_DBG1 0x0304
+#define TH1520_CTRL_DBGCAM 0x0308
+#define TH1520_CTRL_DBGCMD 0x030c
+#define TH1520_CTRL_DBGSTAT 0x0310
+#define TH1520_CTRL_SWCTL 0x0320
+#define TH1520_CTRL_SWSTAT 0x0324
+#define TH1520_CTRL_SWCTLSTATIC 0x0328
+#define TH1520_CTRL_POISONCFG 0x036c
+#define TH1520_CTRL_POISONSTAT 0x0370
+#define TH1520_CTRL_DERATESTAT 0x03f0
+#define TH1520_CTRL_PSTAT 0x03fc
+#define TH1520_CTRL_PCCFG 0x0400
+#define TH1520_CTRL_PCFGR_0 0x0404
+#define TH1520_CTRL_PCFGW_0 0x0408
+#define TH1520_CTRL_PCTRL_0 0x0490
+#define TH1520_CTRL_PCFGQOS0_0 0x0494
+#define TH1520_CTRL_PCFGQOS1_0 0x0498
+#define TH1520_CTRL_PCFGWQOS0_0 0x049c
+#define TH1520_CTRL_PCFGWQOS1_0 0x04a0
+#define TH1520_CTRL_PCFGR_1 0x04b4
+#define TH1520_CTRL_PCFGW_1 0x04b8
+#define TH1520_CTRL_PCTRL_1 0x0540
+#define TH1520_CTRL_PCFGQOS0_1 0x0544
+#define TH1520_CTRL_PCFGQOS1_1 0x0548
+#define TH1520_CTRL_PCFGWQOS0_1 0x054c
+#define TH1520_CTRL_PCFGWQOS1_1 0x0550
+#define TH1520_CTRL_PCFGR_2 0x0564
+#define TH1520_CTRL_PCFGW_2 0x0568
+#define TH1520_CTRL_PCTRL_2 0x05f0
+#define TH1520_CTRL_PCFGQOS0_2 0x05f4
+#define TH1520_CTRL_PCFGQOS1_2 0x05f8
+#define TH1520_CTRL_PCFGWQOS0_2 0x05fc
+#define TH1520_CTRL_PCFGWQOS1_2 0x0600
+#define TH1520_CTRL_PCFGR_3 0x0614
+#define TH1520_CTRL_PCFGW_3 0x0618
+#define TH1520_CTRL_PCTRL_3 0x06a0
+#define TH1520_CTRL_PCFGQOS0_3 0x06a4
+#define TH1520_CTRL_PCFGQOS1_3 0x06a8
+#define TH1520_CTRL_PCFGWQOS0_3 0x06ac
+#define TH1520_CTRL_PCFGWQOS1_3 0x06b0
+#define TH1520_CTRL_PCFGR_4 0x06c4
+#define TH1520_CTRL_PCFGW_4 0x06c8
+#define TH1520_CTRL_PCTRL_4 0x0750
+#define TH1520_CTRL_PCFGQOS0_4 0x0754
+#define TH1520_CTRL_PCFGQOS1_4 0x0758
+#define TH1520_CTRL_PCFGWQOS0_4 0x075c
+#define TH1520_CTRL_PCFGWQOS1_4 0x0760
+#define TH1520_CTRL_UMCTL2_VER_NUMBER 0x0ff0
+#define TH1520_CTRL_UMCTL2_VER_TYPE 0x0ff4
+#define TH1520_CTRL_DCH1_STAT 0x1b04
+#define TH1520_CTRL_DCH1_MRCTRL0 0x1b10
+#define TH1520_CTRL_DCH1_MRCTRL1 0x1b14
+#define TH1520_CTRL_DCH1_MRSTAT 0x1b18
+#define TH1520_CTRL_DCH1_DERATECTL 0x1b2c
+#define TH1520_CTRL_DCH1_PWRCTL 0x1b30
+#define TH1520_CTRL_DCH1_HWLPCTL 0x1b38
+#define TH1520_CTRL_DCH1_CRCPARCTL0 0x1bc0
+#define TH1520_CTRL_DCH1_ZQCTL2 0x1c88
+#define TH1520_CTRL_DCH1_DFISTAT 0x1cbc
+#define TH1520_CTRL_DCH1_ODTMAP 0x1d44
+#define TH1520_CTRL_DCH1_DBG1 0x1e04
+#define TH1520_CTRL_DCH1_DBGCMD 0x1e0c
+#define TH1520_CTRL_DCH1_DBGCAM 0x1e08
+
+/* PHY configuration registers */
+#define TH1520_DDR_PHY_REG(regid) ((regid) * 2)
+
+/* UctShadowRegs */
+#define TH1520_PHY_MSG_STATUS TH1520_DDR_PHY_REG(0xd0004)
+#define TH1520_PHY_MSG_STATUS_EMPTY BIT(0)
+/* DctWriteProt */
+#define TH1520_PHY_MSG_ACK TH1520_DDR_PHY_REG(0xd0031)
+#define TH1520_PHY_MSG_ACK_EN BIT(0)
+/* UctWriteOnlyShadow */
+#define TH1520_PHY_MSG_ID TH1520_DDR_PHY_REG(0xd0032)
+#define TH1520_PHY_MSG_ID_COMPLETION 0x7
+#define TH1520_PHY_MSG_ID_ERROR 0xff
+/* UctDatWriteOnlyShadow */
+#define TH1520_PHY_MSG_DATA TH1520_DDR_PHY_REG(0xd0034)
+
+struct th1520_ddr_priv {
+ void __iomem *phy0;
+ void __iomem *phy1;
+ void __iomem *ctrl;
+ void __iomem *sys;
+};
+
+binman_sym_declare(ulong, ddr_fw, image_pos);
+
+static int th1520_ddr_pll_config(void __iomem *sysreg, unsigned int frequency)
+{
+ u32 tmp;
+ int ret;
+
+ tmp = TH1520_SYS_PLL_CFG1_RST |
+ TH1520_SYS_PLL_CFG1_FOUTPOSTDIVPD |
+ TH1520_SYS_PLL_CFG1_FOUT4PHASEPD |
+ Th1520_SYS_PLL_CFG1_DACPD;
+ writel(tmp, sysreg + TH1520_SYS_PLL_CFG1);
+
+ switch (frequency) {
+ case TH1520_DDR_FREQ_3733:
+ writel(FIELD_PREP(TH1520_SYS_PLL_CFG0_REFDIV, 1) |
+ FIELD_PREP(TH1520_SYS_PLL_CFG0_FBDIV, 77) |
+ FIELD_PREP(TH1520_SYS_PLL_CFG0_POSTDIV1, 2) |
+ FIELD_PREP(TH1520_SYS_PLL_CFG0_POSTDIV2, 1),
+ sysreg + TH1520_SYS_PLL_CFG0);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ udelay(2);
+ tmp &= ~TH1520_SYS_PLL_CFG1_RST;
+ writel(tmp, sysreg + TH1520_SYS_PLL_CFG1);
+
+ ret = readl_poll_timeout(sysreg + TH1520_SYS_PLL_STS, tmp,
+ tmp & TH1520_SYS_PLL_STS_LOCKED,
+ TH1520_SYS_PLL_TIMEOUT_US);
+
+ writel(TH1520_SYS_PLL_STS_EN, sysreg + TH1520_SYS_PLL_STS);
+
+ return ret;
+}
+
+static int th1520_ddr_ctrl_init(void __iomem *ctrlreg, struct th1520_ddr_fw *fw)
+{
+ int ret;
+ u32 tmp;
+
+ writel(0x00000001, ctrlreg + TH1520_CTRL_DBG1);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_PWRCTL);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_STAT, tmp,
+ tmp == 0x00000000,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ if (fw->ranknum == 2)
+ writel(0x03080020, ctrlreg + TH1520_CTRL_MSTR);
+ else
+ return -EINVAL;
+
+ writel(0x00003030, ctrlreg + TH1520_CTRL_MRCTRL0);
+ writel(0x0002d90f, ctrlreg + TH1520_CTRL_MRCTRL1);
+
+ switch (fw->freq) {
+ case TH1520_DDR_FREQ_3733:
+ writel(0x000013f3, ctrlreg + TH1520_CTRL_DERATEEN);
+ writel(0x40000000, ctrlreg + TH1520_CTRL_DERATEINT);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_DERATECTL);
+ writel(0x00000020, ctrlreg + TH1520_CTRL_PWRCTL);
+ writel(0x0040ae04, ctrlreg + TH1520_CTRL_PWRTMG);
+ writel(0x00430000, ctrlreg + TH1520_CTRL_HWLPCTL);
+ writel(0x00210004, ctrlreg + TH1520_CTRL_RFSHCTL0);
+ writel(0x000d0021, ctrlreg + TH1520_CTRL_RFSHCTL1);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_RFSHCTL3);
+ writel(0x81c00084, ctrlreg + TH1520_CTRL_RFSHTMG);
+ writel(0x00540000, ctrlreg + TH1520_CTRL_RFSHTMG1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_CRCPARCTL0);
+ writel(0xc0020002, ctrlreg + TH1520_CTRL_INIT0);
+ writel(0x00010002, ctrlreg + TH1520_CTRL_INIT1);
+ writel(0x00001f00, ctrlreg + TH1520_CTRL_INIT2);
+ writel(0x00640036, ctrlreg + TH1520_CTRL_INIT3);
+ writel(0x00f20008, ctrlreg + TH1520_CTRL_INIT4);
+ writel(0x0004000b, ctrlreg + TH1520_CTRL_INIT5);
+ writel(0x00440012, ctrlreg + TH1520_CTRL_INIT6);
+ writel(0x0004001a, ctrlreg + TH1520_CTRL_INIT7);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DIMMCTL);
+ writel(0x0000ab9f, ctrlreg + TH1520_CTRL_RANKCTL);
+ writel(0x00000017, ctrlreg + TH1520_CTRL_RANKCTL1);
+ writel(0x1f263f28, ctrlreg + TH1520_CTRL_DRAMTMG0);
+ writel(0x00080839, ctrlreg + TH1520_CTRL_DRAMTMG1);
+ writel(0x08121d17, ctrlreg + TH1520_CTRL_DRAMTMG2);
+ writel(0x00d0e000, ctrlreg + TH1520_CTRL_DRAMTMG3);
+ writel(0x11040a12, ctrlreg + TH1520_CTRL_DRAMTMG4);
+ writel(0x02050e0e, ctrlreg + TH1520_CTRL_DRAMTMG5);
+ writel(0x01010008, ctrlreg + TH1520_CTRL_DRAMTMG6);
+ writel(0x00000502, ctrlreg + TH1520_CTRL_DRAMTMG7);
+ writel(0x00000101, ctrlreg + TH1520_CTRL_DRAMTMG8);
+ writel(0x00020000, ctrlreg + TH1520_CTRL_DRAMTMG12);
+ writel(0x0d100002, ctrlreg + TH1520_CTRL_DRAMTMG13);
+ writel(0x0000010c, ctrlreg + TH1520_CTRL_DRAMTMG14);
+ writel(0x03a50021, ctrlreg + TH1520_CTRL_ZQCTL0);
+ writel(0x02f00800, ctrlreg + TH1520_CTRL_ZQCTL1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_ZQCTL2);
+ writel(0x059f820c, ctrlreg + TH1520_CTRL_DFITMG0);
+ writel(0x000c0303, ctrlreg + TH1520_CTRL_DFITMG1);
+ writel(0x0351a101, ctrlreg + TH1520_CTRL_DFILPCFG0);
+ writel(0x00000011, ctrlreg + TH1520_CTRL_DFIMISC);
+ writel(0x00001f0c, ctrlreg + TH1520_CTRL_DFITMG2);
+ writel(0x00000007, ctrlreg + TH1520_CTRL_DBICTL);
+ writel(0x14000001, ctrlreg + TH1520_CTRL_DFIPHYMSTR);
+ writel(0x06090b40, ctrlreg + TH1520_CTRL_ODTCFG);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ writel(0x00400018, ctrlreg + TH1520_CTRL_DFIUPD0);
+ writel(0x00280032, ctrlreg + TH1520_CTRL_DFIUPD1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DFIUPD2);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_ODTMAP);
+ writel(0x1f829b1c, ctrlreg + TH1520_CTRL_SCHED);
+ writel(0x4400b00f, ctrlreg + TH1520_CTRL_SCHED1);
+ writel(0x0f000001, ctrlreg + TH1520_CTRL_PERFHPR1);
+ writel(0x0f00007f, ctrlreg + TH1520_CTRL_PERFLPR1);
+ writel(0x0f00007f, ctrlreg + TH1520_CTRL_PERFWR1);
+ writel(0x00000208, ctrlreg + TH1520_CTRL_SCHED3);
+ writel(0x08400810, ctrlreg + TH1520_CTRL_SCHED4);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DBG0);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DBG1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DBGCMD);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_SWCTL);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_SWCTLSTATIC);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_POISONCFG);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_PCTRL_0);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_PCTRL_1);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_PCTRL_2);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_PCTRL_3);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_PCTRL_4);
+ writel(0x00003030, ctrlreg + TH1520_CTRL_DCH1_MRCTRL0);
+ writel(0x0002d90f, ctrlreg + TH1520_CTRL_DCH1_MRCTRL1);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_DCH1_DERATECTL);
+ writel(0x00000020, ctrlreg + TH1520_CTRL_DCH1_PWRCTL);
+ writel(0x00430002, ctrlreg + TH1520_CTRL_DCH1_HWLPCTL);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_CRCPARCTL0);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_ZQCTL2);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_ODTMAP);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_DBG1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_DBGCMD);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_RFSHCTL3, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000010, ctrlreg + TH1520_CTRL_PCCFG);
+ writel(0x0000500f, ctrlreg + TH1520_CTRL_PCFGR_0);
+ writel(0x0000500f, ctrlreg + TH1520_CTRL_PCFGW_0);
+ writel(0x00005020, ctrlreg + TH1520_CTRL_PCFGR_1);
+ writel(0x0000501f, ctrlreg + TH1520_CTRL_PCFGW_1);
+ writel(0x0000501f, ctrlreg + TH1520_CTRL_PCFGR_2);
+ writel(0x0000503f, ctrlreg + TH1520_CTRL_PCFGW_2);
+ writel(0x000051ff, ctrlreg + TH1520_CTRL_PCFGR_3);
+ writel(0x000051ff, ctrlreg + TH1520_CTRL_PCFGW_3);
+ writel(0x0000503f, ctrlreg + TH1520_CTRL_PCFGR_4);
+ writel(0x0000503f, ctrlreg + TH1520_CTRL_PCFGW_4);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_PWRCTL, tmp,
+ tmp == 0x00000020,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000020, ctrlreg + TH1520_CTRL_PWRCTL);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DCH1_PWRCTL, tmp,
+ tmp == 0x00000020,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000020, ctrlreg + TH1520_CTRL_DCH1_PWRCTL);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DBG1);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_PWRCTL, tmp,
+ tmp == 0x00000020,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000020, ctrlreg + TH1520_CTRL_PWRCTL);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_PWRCTL, tmp,
+ tmp == 0x00000020,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000020, ctrlreg + TH1520_CTRL_PWRCTL);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_DBG1);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DCH1_PWRCTL, tmp,
+ tmp == 0x00000020,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000020, ctrlreg + TH1520_CTRL_DCH1_PWRCTL);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DCH1_PWRCTL, tmp,
+ tmp == 0x00000020,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000020, ctrlreg + TH1520_CTRL_DCH1_PWRCTL);
+ writel(0x14000001, ctrlreg + TH1520_CTRL_DFIPHYMSTR);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_SWCTL);
+ writel(0x00000010, ctrlreg + TH1520_CTRL_DFIMISC);
+ writel(0x00000010, ctrlreg + TH1520_CTRL_DFIMISC);
+ writel(0x00000002, ctrlreg + TH1520_CTRL_DBG1);
+ writel(0x00000002, ctrlreg + TH1520_CTRL_DCH1_DBG1);
+
+ switch (fw->bitwidth) {
+ case 64:
+ writel(0x00040018, ctrlreg + TH1520_CTRL_ADDRMAP0);
+ writel(0x00090909, ctrlreg + TH1520_CTRL_ADDRMAP1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_ADDRMAP2);
+ writel(0x01010101, ctrlreg + TH1520_CTRL_ADDRMAP3);
+ writel(0x00001f1f, ctrlreg + TH1520_CTRL_ADDRMAP4);
+ writel(0x080f0808, ctrlreg + TH1520_CTRL_ADDRMAP5);
+ writel(0x08080808, ctrlreg + TH1520_CTRL_ADDRMAP6);
+ writel(0x00000f0f, ctrlreg + TH1520_CTRL_ADDRMAP7);
+ writel(0x08080808, ctrlreg + TH1520_CTRL_ADDRMAP9);
+ writel(0x08080808, ctrlreg + TH1520_CTRL_ADDRMAP10);
+ writel(0x00000008, ctrlreg + TH1520_CTRL_ADDRMAP11);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int th1520_ddr_read_msg(void __iomem *phyreg, u16 *id, u16 *data)
+{
+ u32 tmp;
+ int ret;
+
+ ret = readw_poll_timeout(phyreg + TH1520_PHY_MSG_STATUS, tmp,
+ !(tmp & TH1520_PHY_MSG_STATUS_EMPTY),
+ TH1520_PHY_MSG_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ *id = readw(phyreg + TH1520_PHY_MSG_ID);
+ *data = readw(phyreg + TH1520_PHY_MSG_DATA);
+
+ writew(0, phyreg + TH1520_PHY_MSG_ACK);
+
+ ret = readw_poll_timeout(phyreg + TH1520_PHY_MSG_STATUS, tmp,
+ tmp & TH1520_PHY_MSG_STATUS_EMPTY,
+ TH1520_PHY_MSG_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writew(TH1520_PHY_MSG_ACK_EN, phyreg + TH1520_PHY_MSG_ACK);
+
+ return 0;
+}
+
+static int th1520_phy_wait_pmu_completion(void __iomem *phyreg)
+{
+ u16 id, data;
+ int ret;
+
+ do {
+ ret = th1520_ddr_read_msg(phyreg, &id, &data);
+
+ if (ret)
+ return ret;
+ } while (id != TH1520_PHY_MSG_ID_COMPLETION &&
+ id != TH1520_PHY_MSG_ID_ERROR &&
+ !ret);
+
+ return id == TH1520_PHY_MSG_ID_COMPLETION ? ret : -EIO;
+}
+
+static int lpddr4_load_firmware(struct th1520_ddr_priv *priv,
+ struct th1520_ddr_fw *fw)
+{
+ union th1520_ddr_cfg *cfg;
+ size_t i, j;
+ int ret;
+
+ for (cfg = fw->cfgs, i = 0; i < fw->cfgnum; i++) {
+ u32 addr = FIELD_GET(TH1520_DDR_CFG_ADDR, cfg->opaddr) * 2;
+ u32 op = FIELD_GET(TH1520_DDR_CFG_OP, cfg->opaddr);
+
+ switch (op) {
+ case TH1520_DDR_CFG_PHY0:
+ writew(cfg->phy.data, priv->phy0 + addr);
+ break;
+ case TH1520_DDR_CFG_PHY1:
+ writew(cfg->phy.data, priv->phy1 + addr);
+ break;
+ case TH1520_DDR_CFG_PHY:
+ writew(cfg->phy.data, priv->phy0 + addr);
+ writew(cfg->phy.data, priv->phy1 + addr);
+ break;
+ case TH1520_DDR_CFG_RANGE:
+ for (j = 0; j < cfg->range.num; j++) {
+ writew(cfg->range.data[j],
+ priv->phy0 + addr + j * 2);
+ writew(cfg->range.data[j],
+ priv->phy1 + addr + j * 2);
+ }
+ break;
+ case TH1520_DDR_CFG_WAITFW0:
+ ret = th1520_phy_wait_pmu_completion(priv->phy0);
+
+ if (ret) {
+ pr_err("phy 0 training failed: %d\n", ret);
+ return ret;
+ }
+
+ break;
+ case TH1520_DDR_CFG_WAITFW1:
+ ret = th1520_phy_wait_pmu_completion(priv->phy1);
+
+ if (ret) {
+ pr_err("phy 1 training failed: %d\n", ret);
+ return ret;
+ }
+
+ break;
+ default:
+ pr_err("Unknown DRAM configuration %d\n", op);
+
+ return -EOPNOTSUPP;
+ }
+
+ if (op == TH1520_DDR_CFG_RANGE)
+ cfg = (void *)cfg + sizeof(cfg->range) +
+ cfg->range.num * sizeof(u16);
+ else
+ cfg = (union th1520_ddr_cfg *)(&cfg->phy + 1);
+ }
+
+ return 0;
+}
+
+static int th1520_ddr_ctrl_enable(void __iomem *ctrlreg,
+ struct th1520_ddr_fw *fw)
+{
+ u32 tmp;
+ int ret;
+
+ writel(0x00000030, ctrlreg + TH1520_CTRL_DFIMISC);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DFISTAT, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DCH1_DFISTAT, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000010, ctrlreg + TH1520_CTRL_DFIMISC);
+ writel(0x00000011, ctrlreg + TH1520_CTRL_DFIMISC);
+ writel(0x0000000a, ctrlreg + TH1520_CTRL_PWRCTL);
+ writel(0x0000000a, ctrlreg + TH1520_CTRL_DCH1_PWRCTL);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_SWCTL);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_SWSTAT, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_STAT, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DCH1_STAT, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x14000001, ctrlreg + TH1520_CTRL_DFIPHYMSTR);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_SWCTL);
+ writel(0x00020002, ctrlreg + TH1520_CTRL_INIT0);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_SWCTL);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_SWSTAT, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+
+ if (ret)
+ return ret;
+
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DBG1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_DBG1);
+
+ return 0;
+}
+
+static void th1520_ddr_enable_self_refresh(void __iomem *ctrlreg,
+ void __iomem *sysreg)
+{
+ writel(0x00000000, ctrlreg + TH1520_CTRL_RFSHCTL3);
+
+ writel(0x000a0000, sysreg + TH1520_SYS_DDR_CFG1);
+
+ writel(0x00000000, ctrlreg + TH1520_CTRL_SWCTL);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_SWCTLSTATIC);
+ writel(0x0040ae04, ctrlreg + TH1520_CTRL_PWRTMG);
+ writel(0x00430003, ctrlreg + TH1520_CTRL_HWLPCTL);
+ writel(0x00430003, ctrlreg + TH1520_CTRL_DCH1_HWLPCTL);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_SWCTL);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_SWCTLSTATIC);
+ writel(0x0000000b, ctrlreg + TH1520_CTRL_PWRCTL);
+ writel(0x0000000b, ctrlreg + TH1520_CTRL_DCH1_PWRCTL);
+}
+
+static int th1520_ddr_init(struct th1520_ddr_priv *priv)
+{
+ struct th1520_ddr_fw *fw = (void *)binman_sym(ulong, ddr_fw, image_pos);
+ u32 reset;
+ int ret;
+
+ ret = th1520_ddr_pll_config(priv->sys, fw->freq);
+ if (ret) {
+ pr_err("failed to configure PLL: %d\n", ret);
+ return ret;
+ }
+
+ reset = TH1520_SYS_DDR_CFG0_PHY_PWROK_RSTN;
+ writel(reset, priv->sys + TH1520_SYS_DDR_CFG0);
+ reset |= TH1520_SYS_DDR_CFG0_PHY_CORE_RSTN;
+ writel(reset, priv->sys + TH1520_SYS_DDR_CFG0);
+ reset |= TH1520_SYS_DDR_CFG0_APB_RSTN;
+ writel(reset, priv->sys + TH1520_SYS_DDR_CFG0);
+
+ ret = th1520_ddr_ctrl_init(priv->ctrl, fw);
+ if (ret) {
+ pr_err("failed to initialize DDR controller: %d\n", ret);
+ return ret;
+ }
+
+ reset |= TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(0) |
+ TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(1) |
+ TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(2) |
+ TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(3) |
+ TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(4) |
+ TH1520_SYS_DDR_CFG0_CTRL_RSTN;
+ writel(reset, priv->sys + TH1520_SYS_DDR_CFG0);
+
+ lpddr4_load_firmware(priv, fw);
+
+ ret = th1520_ddr_ctrl_enable(priv->ctrl, fw);
+ if (ret) {
+ pr_err("failed to enable DDR controller: %d\n", ret);
+ return ret;
+ }
+
+ th1520_ddr_enable_self_refresh(priv->ctrl, priv->sys);
+
+ return 0;
+}
+
+static int th1520_ddr_probe(struct udevice *dev)
+{
+ struct th1520_ddr_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+
+ addr = dev_read_addr_name(dev, "phy-0");
+ priv->phy0 = (void __iomem *)addr;
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ addr = dev_read_addr_name(dev, "phy-1");
+ priv->phy1 = (void __iomem *)addr;
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ addr = dev_read_addr_name(dev, "ctrl");
+ priv->ctrl = (void __iomem *)addr;
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ addr = dev_read_addr_name(dev, "sys");
+ priv->sys = (void __iomem *)addr;
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ return th1520_ddr_init(priv);
+}
+
+static int th1520_ddr_get_info(struct udevice *dev, struct ram_info *info)
+{
+ info->base = gd->ram_base;
+ info->size = gd->ram_size;
+
+ return 0;
+}
+
+static struct ram_ops th1520_ddr_ops = {
+ .get_info = th1520_ddr_get_info,
+};
+
+static const struct udevice_id th1520_ddr_ids[] = {
+ { .compatible = "thead,th1520-ddrc" },
+ { }
+};
+
+U_BOOT_DRIVER(th1520_ddr) = {
+ .name = "th1520_ddr",
+ .id = UCLASS_RAM,
+ .ops = &th1520_ddr_ops,
+ .of_match = th1520_ddr_ids,
+ .probe = th1520_ddr_probe,
+ .priv_auto = sizeof(struct th1520_ddr_priv),
+};
--
2.49.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 04/10] ram: thead: Add initial DDR controller support for TH1520
2025-04-26 16:56 ` [PATCH 04/10] ram: thead: Add initial DDR controller support for TH1520 Yao Zi
@ 2025-04-26 17:09 ` Yao Zi
2025-05-12 17:55 ` Leo Liang
2025-05-12 17:47 ` Leo Liang
2025-05-24 19:16 ` Drew Fustini
2 siblings, 1 reply; 27+ messages in thread
From: Yao Zi @ 2025-04-26 17:09 UTC (permalink / raw)
To: Rick Chen, Leo, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang
Cc: u-boot, Han Gao, Han Gao
On Sat, Apr 26, 2025 at 04:56:58PM +0000, Yao Zi wrote:
> This patch cleans the vendor code of DDR initialization up, converts the
> driver to fit in DM framework and use a firmware[1] packaged by binman to
> ship PHY configuration.
>
> Currently the driver is only capable of initializing the controller to
> work with dual-rank 3733MHz LPDDR4, which is shipped by 16GiB variants
> of LicheePi 4A boards and I could test with. Support for other
> configurations could be easily added later.
I wrongly repeated this patch twice when sending the series, sorry for
the noise.
> Link: https://github.com/ziyao233/th1520-firmware # [1]
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
> drivers/ram/Kconfig | 1 +
> drivers/ram/Makefile | 4 +
> drivers/ram/thead/Kconfig | 5 +
> drivers/ram/thead/Makefile | 1 +
> drivers/ram/thead/th1520_ddr.c | 781 +++++++++++++++++++++++++++++++++
> 5 files changed, 792 insertions(+)
> create mode 100644 drivers/ram/thead/Kconfig
> create mode 100644 drivers/ram/thead/Makefile
> create mode 100644 drivers/ram/thead/th1520_ddr.c
...
> diff --git a/drivers/ram/thead/th1520_ddr.c b/drivers/ram/thead/th1520_ddr.c
> new file mode 100644
> index 00000000000..ff9860b9c3d
> --- /dev/null
> +++ b/drivers/ram/thead/th1520_ddr.c
> @@ -0,0 +1,781 @@
> +#include <binman.h>
> +#include <binman_sym.h>
> +#include <dm.h>
> +#include <init.h>
> +#include <linux/bitfield.h>
> +#include <linux/iopoll.h>
> +#include <ram.h>
And here is missing an SPDX license header and a copyright notice. I'll
add them in v2.
Thanks,
Yao Zi
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 04/10] ram: thead: Add initial DDR controller support for TH1520
2025-04-26 17:09 ` Yao Zi
@ 2025-05-12 17:55 ` Leo Liang
0 siblings, 0 replies; 27+ messages in thread
From: Leo Liang @ 2025-05-12 17:55 UTC (permalink / raw)
To: Yao Zi
Cc: Rick Chen, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang, u-boot, Han Gao,
Han Gao
On Sat, Apr 26, 2025 at 05:09:16PM +0000, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> On Sat, Apr 26, 2025 at 04:56:58PM +0000, Yao Zi wrote:
> > This patch cleans the vendor code of DDR initialization up, converts the
> > driver to fit in DM framework and use a firmware[1] packaged by binman to
> > ship PHY configuration.
> >
> > Currently the driver is only capable of initializing the controller to
> > work with dual-rank 3733MHz LPDDR4, which is shipped by 16GiB variants
> > of LicheePi 4A boards and I could test with. Support for other
> > configurations could be easily added later.
>
> I wrongly repeated this patch twice when sending the series, sorry for
> the noise.
>
> > Link: https://github.com/ziyao233/th1520-firmware # [1]
> > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > ---
> > drivers/ram/Kconfig | 1 +
> > drivers/ram/Makefile | 4 +
> > drivers/ram/thead/Kconfig | 5 +
> > drivers/ram/thead/Makefile | 1 +
> > drivers/ram/thead/th1520_ddr.c | 781 +++++++++++++++++++++++++++++++++
> > 5 files changed, 792 insertions(+)
> > create mode 100644 drivers/ram/thead/Kconfig
> > create mode 100644 drivers/ram/thead/Makefile
> > create mode 100644 drivers/ram/thead/th1520_ddr.c
>
> And here is missing an SPDX license header and a copyright notice. I'll
> add them in v2.
Hi Yao,
You could add my reviewed-by tag when sending v2 patch.
Best regards,
Leo
>
> Thanks,
> Yao Zi
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 04/10] ram: thead: Add initial DDR controller support for TH1520
2025-04-26 16:56 ` [PATCH 04/10] ram: thead: Add initial DDR controller support for TH1520 Yao Zi
2025-04-26 17:09 ` Yao Zi
@ 2025-05-12 17:47 ` Leo Liang
2025-05-24 19:16 ` Drew Fustini
2 siblings, 0 replies; 27+ messages in thread
From: Leo Liang @ 2025-05-12 17:47 UTC (permalink / raw)
To: Yao Zi
Cc: Rick Chen, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang, u-boot, Han Gao,
Han Gao
On Sat, Apr 26, 2025 at 04:56:58PM +0000, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> This patch cleans the vendor code of DDR initialization up, converts the
> driver to fit in DM framework and use a firmware[1] packaged by binman to
> ship PHY configuration.
>
> Currently the driver is only capable of initializing the controller to
> work with dual-rank 3733MHz LPDDR4, which is shipped by 16GiB variants
> of LicheePi 4A boards and I could test with. Support for other
> configurations could be easily added later.
>
> Link: https://github.com/ziyao233/th1520-firmware # [1]
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
> drivers/ram/Kconfig | 1 +
> drivers/ram/Makefile | 4 +
> drivers/ram/thead/Kconfig | 5 +
> drivers/ram/thead/Makefile | 1 +
> drivers/ram/thead/th1520_ddr.c | 781 +++++++++++++++++++++++++++++++++
> 5 files changed, 792 insertions(+)
> create mode 100644 drivers/ram/thead/Kconfig
> create mode 100644 drivers/ram/thead/Makefile
> create mode 100644 drivers/ram/thead/th1520_ddr.c
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 04/10] ram: thead: Add initial DDR controller support for TH1520
2025-04-26 16:56 ` [PATCH 04/10] ram: thead: Add initial DDR controller support for TH1520 Yao Zi
2025-04-26 17:09 ` Yao Zi
2025-05-12 17:47 ` Leo Liang
@ 2025-05-24 19:16 ` Drew Fustini
2 siblings, 0 replies; 27+ messages in thread
From: Drew Fustini @ 2025-05-24 19:16 UTC (permalink / raw)
To: Yao Zi
Cc: Rick Chen, Leo, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang, u-boot, Han Gao,
Han Gao
On Sat, Apr 26, 2025 at 04:56:58PM +0000, Yao Zi wrote:
> This patch cleans the vendor code of DDR initialization up, converts the
> driver to fit in DM framework and use a firmware[1] packaged by binman to
> ship PHY configuration.
>
> Currently the driver is only capable of initializing the controller to
> work with dual-rank 3733MHz LPDDR4, which is shipped by 16GiB variants
> of LicheePi 4A boards and I could test with. Support for other
> configurations could be easily added later.
Thank you for this patch series. I only have the 8GB LPi4a. Do you have
any suggestions for how I can get that working?
Here is existing output at boot:
-----------------------------------------------
U-Boot SPL 2020.01-g55b713fa (Jan 12 2024 - 02:17:34 +0000)
FM[1] lpddr4x dualrank freq=3733 64bit dbi_off=n sdram init
ddr initialized, jump to uboot
it worksimage has no header
U-Boot 2020.01-g55b713fa (Jan 12 2024 - 02:17:34 +0000)
CPU: rv64imafdcvsu
Model: T-HEAD c910 light
DRAM: 8 GiB
-----------------------------------------------
Thanks,
Drew
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 04/10] ram: thead: Add initial DDR controller support for TH1520
2025-04-26 16:56 [PATCH 00/10] Initial SPL support for T-Head TH1520 SoC Yao Zi
` (3 preceding siblings ...)
2025-04-26 16:56 ` [PATCH 04/10] ram: thead: Add initial DDR controller support for TH1520 Yao Zi
@ 2025-04-26 17:00 ` Yao Zi
2025-04-26 17:00 ` [PATCH 05/10] riscv: dts: th1520: Preserve necessary devices for SPL Yao Zi
` (5 subsequent siblings)
10 siblings, 0 replies; 27+ messages in thread
From: Yao Zi @ 2025-04-26 17:00 UTC (permalink / raw)
To: Rick Chen, Leo, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang
Cc: u-boot, Han Gao, Han Gao, Yao Zi
This patch cleans the vendor code of DDR initialization up, converts the
driver to fit in DM framework and use a firmware[1] packaged by binman to
ship PHY configuration.
Currently the driver is only capable of initializing the controller to
work with dual-rank 3733MHz LPDDR4, which is shipped by 16GiB variants
of LicheePi 4A boards and I could test with. Support for other
configurations could be easily added later.
Link: https://github.com/ziyao233/th1520-firmware # [1]
Signed-off-by: Yao Zi <ziyao@disroot.org>
---
drivers/ram/Kconfig | 1 +
drivers/ram/Makefile | 4 +
drivers/ram/thead/Kconfig | 5 +
drivers/ram/thead/Makefile | 1 +
drivers/ram/thead/th1520_ddr.c | 781 +++++++++++++++++++++++++++++++++
5 files changed, 792 insertions(+)
create mode 100644 drivers/ram/thead/Kconfig
create mode 100644 drivers/ram/thead/Makefile
create mode 100644 drivers/ram/thead/th1520_ddr.c
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 2a40b0c9f81..39d03e8d3d3 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -135,3 +135,4 @@ source "drivers/ram/sifive/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
source "drivers/ram/starfive/Kconfig"
source "drivers/ram/sunxi/Kconfig"
+source "drivers/ram/thead/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index f92e86eaa3f..82afd5fcbcc 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -30,3 +30,7 @@ obj-$(CONFIG_ARCH_OCTEON) += octeon/
obj-$(CONFIG_ARCH_RENESAS) += renesas/
obj-$(CONFIG_CADENCE_DDR_CTRL) += cadence/
+
+ifdef CONFIG_XPL_BUILD
+obj-$(CONFIG_SPL_THEAD_TH1520_DDR) += thead/
+endif
diff --git a/drivers/ram/thead/Kconfig b/drivers/ram/thead/Kconfig
new file mode 100644
index 00000000000..7b05abb6986
--- /dev/null
+++ b/drivers/ram/thead/Kconfig
@@ -0,0 +1,5 @@
+config SPL_THEAD_TH1520_DDR
+ bool "T-Head TH1520 DDR driver in SPL"
+ depends on SPL_RAM && THEAD_TH1520
+ help
+ This enables DDR support for T-Head TH1520 platforms.
diff --git a/drivers/ram/thead/Makefile b/drivers/ram/thead/Makefile
new file mode 100644
index 00000000000..ad4d053cfc2
--- /dev/null
+++ b/drivers/ram/thead/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_SPL_THEAD_TH1520_DDR) += th1520_ddr.o
diff --git a/drivers/ram/thead/th1520_ddr.c b/drivers/ram/thead/th1520_ddr.c
new file mode 100644
index 00000000000..ff9860b9c3d
--- /dev/null
+++ b/drivers/ram/thead/th1520_ddr.c
@@ -0,0 +1,781 @@
+#include <binman.h>
+#include <binman_sym.h>
+#include <dm.h>
+#include <init.h>
+#include <linux/bitfield.h>
+#include <linux/iopoll.h>
+#include <ram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#pragma pack(push, 1)
+
+struct th1520_ddr_fw {
+ u64 magic;
+ u8 type, ranknum, bitwidth, freq;
+ u8 reserved[8];
+
+ u32 cfgnum;
+ union th1520_ddr_cfg {
+ u32 opaddr;
+
+ struct th1520_ddr_phy {
+ u32 opaddr;
+ u16 data;
+ } phy;
+
+ struct th1520_ddr_range {
+ u32 opaddr;
+ u32 num;
+ u16 data[];
+ } range;
+ } cfgs[];
+};
+
+#pragma pack(pop)
+
+/* Firmware constants */
+#define TH1520_DDR_MAGIC 0x4452444445415448
+
+#define TH1520_DDR_TYPE_LPDDR4 0
+#define TH1520_DDR_TYPE_LPDDR4X 1
+
+#define TH1520_DDR_FREQ_2133 0
+#define TH1520_DDR_FREQ_3200 1
+#define TH1520_DDR_FREQ_3733 2
+#define TH1520_DDR_FREQ_4266 3
+
+#define TH1520_DDR_CFG_OP GENMASK(31, 24)
+#define TH1520_DDR_CFG_ADDR GENMASK(23, 0)
+
+#define TH1520_DDR_CFG_PHY0 0
+#define TH1520_DDR_CFG_PHY1 1
+#define TH1520_DDR_CFG_PHY 2
+#define TH1520_DDR_CFG_RANGE 3
+#define TH1520_DDR_CFG_WAITFW0 4
+#define TH1520_DDR_CFG_WAITFW1 5
+
+/* Driver constants */
+#define TH1520_SYS_PLL_TIMEOUT_US 30
+#define TH1520_CTRL_INIT_TIMEOUT_US 1000000
+#define TH1520_PHY_MSG_TIMEOUT_US 1000000
+
+/* System configuration registers */
+#define TH1520_SYS_DDR_CFG0 0x00
+#define TH1520_SYS_DDR_CFG0_APB_RSTN BIT(4)
+#define TH1520_SYS_DDR_CFG0_CTRL_RSTN BIT(5)
+#define TH1520_SYS_DDR_CFG0_PHY_PWROK_RSTN BIT(6)
+#define TH1520_SYS_DDR_CFG0_PHY_CORE_RSTN BIT(7)
+#define TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(n) BIT(n + 4 + 4)
+#define TH1520_SYS_DDR_CFG1 0x04
+#define TH1520_SYS_PLL_CFG0 0x08
+#define TH1520_SYS_PLL_CFG0_POSTDIV2 GENMASK(26, 24)
+#define TH1520_SYS_PLL_CFG0_POSTDIV1 GENMASK(22, 20)
+#define TH1520_SYS_PLL_CFG0_FBDIV GENMASK(19, 8)
+#define TH1520_SYS_PLL_CFG0_REFDIV GENMASK(5, 0)
+#define TH1520_SYS_PLL_CFG1 0x0c
+#define TH1520_SYS_PLL_CFG1_RST BIT(30)
+#define TH1520_SYS_PLL_CFG1_FOUTPOSTDIVPD BIT(27)
+#define TH1520_SYS_PLL_CFG1_FOUT4PHASEPD BIT(25)
+#define Th1520_SYS_PLL_CFG1_DACPD BIT(24)
+#define TH1520_SYS_PLL_CFG2 0x10
+#define TH1520_SYS_PLL_CFG3 0x14
+#define TH1520_SYS_PLL_STS 0x18
+#define TH1520_SYS_PLL_STS_EN BIT(16)
+#define TH1520_SYS_PLL_STS_LOCKED BIT(0)
+
+/* DDR Controller Registers */
+#define TH1520_CTRL_MSTR 0x0000
+#define TH1520_CTRL_STAT 0x0004
+#define TH1520_CTRL_MRCTRL0 0x0010
+#define TH1520_CTRL_MRCTRL1 0x0014
+#define TH1520_CTRL_MRSTAT 0x0018
+#define TH1520_CTRL_DERATEEN 0x0020
+#define TH1520_CTRL_DERATEINT 0x0024
+#define TH1520_CTRL_DERATECTL 0x002c
+#define TH1520_CTRL_PWRCTL 0x0030
+#define TH1520_CTRL_PWRTMG 0x0034
+#define TH1520_CTRL_HWLPCTL 0x0038
+#define TH1520_CTRL_RFSHCTL0 0x0050
+#define TH1520_CTRL_RFSHCTL1 0x0054
+#define TH1520_CTRL_RFSHCTL3 0x0060
+#define TH1520_CTRL_RFSHTMG 0x0064
+#define TH1520_CTRL_RFSHTMG1 0x0068
+#define TH1520_CTRL_CRCPARCTL0 0x00c0
+#define TH1520_CTRL_CRCPARSTAT 0x00cc
+#define TH1520_CTRL_INIT0 0x00d0
+#define TH1520_CTRL_INIT1 0x00d4
+#define TH1520_CTRL_INIT2 0x00d8
+#define TH1520_CTRL_INIT3 0x00dc
+#define TH1520_CTRL_INIT4 0x00e0
+#define TH1520_CTRL_INIT5 0x00e4
+#define TH1520_CTRL_INIT6 0x00e8
+#define TH1520_CTRL_INIT7 0x00ec
+#define TH1520_CTRL_DIMMCTL 0x00f0
+#define TH1520_CTRL_RANKCTL 0x00f4
+#define TH1520_CTRL_RANKCTL1 0x00f8
+#define TH1520_CTRL_DRAMTMG0 0x0100
+#define TH1520_CTRL_DRAMTMG1 0x0104
+#define TH1520_CTRL_DRAMTMG2 0x0108
+#define TH1520_CTRL_DRAMTMG3 0x010c
+#define TH1520_CTRL_DRAMTMG4 0x0110
+#define TH1520_CTRL_DRAMTMG5 0x0114
+#define TH1520_CTRL_DRAMTMG6 0x0118
+#define TH1520_CTRL_DRAMTMG7 0x011c
+#define TH1520_CTRL_DRAMTMG8 0x0120
+#define TH1520_CTRL_DRAMTMG12 0x0130
+#define TH1520_CTRL_DRAMTMG13 0x0134
+#define TH1520_CTRL_DRAMTMG14 0x0138
+#define TH1520_CTRL_DRAMTMG17 0x0144
+#define TH1520_CTRL_ZQCTL0 0x0180
+#define TH1520_CTRL_ZQCTL1 0x0184
+#define TH1520_CTRL_ZQCTL2 0x0188
+#define TH1520_CTRL_ZQSTAT 0x018c
+#define TH1520_CTRL_DFITMG0 0x0190
+#define TH1520_CTRL_DFITMG1 0x0194
+#define TH1520_CTRL_DFILPCFG0 0x0198
+#define TH1520_CTRL_DFIUPD0 0x01a0
+#define TH1520_CTRL_DFIUPD1 0x01a4
+#define TH1520_CTRL_DFIUPD2 0x01a8
+#define TH1520_CTRL_DFIMISC 0x01b0
+#define TH1520_CTRL_DFITMG2 0x01b4
+#define TH1520_CTRL_DFISTAT 0x01bc
+#define TH1520_CTRL_DBICTL 0x01c0
+#define TH1520_CTRL_DFIPHYMSTR 0x01c4
+#define TH1520_CTRL_ADDRMAP0 0x0200
+#define TH1520_CTRL_ADDRMAP1 0x0204
+#define TH1520_CTRL_ADDRMAP2 0x0208
+#define TH1520_CTRL_ADDRMAP3 0x020c
+#define TH1520_CTRL_ADDRMAP4 0x0210
+#define TH1520_CTRL_ADDRMAP5 0x0214
+#define TH1520_CTRL_ADDRMAP6 0x0218
+#define TH1520_CTRL_ADDRMAP7 0x021c
+#define TH1520_CTRL_ADDRMAP8 0x0220
+#define TH1520_CTRL_ADDRMAP9 0x0224
+#define TH1520_CTRL_ADDRMAP10 0x0228
+#define TH1520_CTRL_ADDRMAP11 0x022c
+#define TH1520_CTRL_ODTCFG 0x0240
+#define TH1520_CTRL_ODTMAP 0x0244
+#define TH1520_CTRL_SCHED 0x0250
+#define TH1520_CTRL_SCHED1 0x0254
+#define TH1520_CTRL_PERFHPR1 0x025c
+#define TH1520_CTRL_PERFLPR1 0x0264
+#define TH1520_CTRL_PERFWR1 0x026c
+#define TH1520_CTRL_SCHED3 0x0270
+#define TH1520_CTRL_SCHED4 0x0274
+#define TH1520_CTRL_DBG0 0x0300
+#define TH1520_CTRL_DBG1 0x0304
+#define TH1520_CTRL_DBGCAM 0x0308
+#define TH1520_CTRL_DBGCMD 0x030c
+#define TH1520_CTRL_DBGSTAT 0x0310
+#define TH1520_CTRL_SWCTL 0x0320
+#define TH1520_CTRL_SWSTAT 0x0324
+#define TH1520_CTRL_SWCTLSTATIC 0x0328
+#define TH1520_CTRL_POISONCFG 0x036c
+#define TH1520_CTRL_POISONSTAT 0x0370
+#define TH1520_CTRL_DERATESTAT 0x03f0
+#define TH1520_CTRL_PSTAT 0x03fc
+#define TH1520_CTRL_PCCFG 0x0400
+#define TH1520_CTRL_PCFGR_0 0x0404
+#define TH1520_CTRL_PCFGW_0 0x0408
+#define TH1520_CTRL_PCTRL_0 0x0490
+#define TH1520_CTRL_PCFGQOS0_0 0x0494
+#define TH1520_CTRL_PCFGQOS1_0 0x0498
+#define TH1520_CTRL_PCFGWQOS0_0 0x049c
+#define TH1520_CTRL_PCFGWQOS1_0 0x04a0
+#define TH1520_CTRL_PCFGR_1 0x04b4
+#define TH1520_CTRL_PCFGW_1 0x04b8
+#define TH1520_CTRL_PCTRL_1 0x0540
+#define TH1520_CTRL_PCFGQOS0_1 0x0544
+#define TH1520_CTRL_PCFGQOS1_1 0x0548
+#define TH1520_CTRL_PCFGWQOS0_1 0x054c
+#define TH1520_CTRL_PCFGWQOS1_1 0x0550
+#define TH1520_CTRL_PCFGR_2 0x0564
+#define TH1520_CTRL_PCFGW_2 0x0568
+#define TH1520_CTRL_PCTRL_2 0x05f0
+#define TH1520_CTRL_PCFGQOS0_2 0x05f4
+#define TH1520_CTRL_PCFGQOS1_2 0x05f8
+#define TH1520_CTRL_PCFGWQOS0_2 0x05fc
+#define TH1520_CTRL_PCFGWQOS1_2 0x0600
+#define TH1520_CTRL_PCFGR_3 0x0614
+#define TH1520_CTRL_PCFGW_3 0x0618
+#define TH1520_CTRL_PCTRL_3 0x06a0
+#define TH1520_CTRL_PCFGQOS0_3 0x06a4
+#define TH1520_CTRL_PCFGQOS1_3 0x06a8
+#define TH1520_CTRL_PCFGWQOS0_3 0x06ac
+#define TH1520_CTRL_PCFGWQOS1_3 0x06b0
+#define TH1520_CTRL_PCFGR_4 0x06c4
+#define TH1520_CTRL_PCFGW_4 0x06c8
+#define TH1520_CTRL_PCTRL_4 0x0750
+#define TH1520_CTRL_PCFGQOS0_4 0x0754
+#define TH1520_CTRL_PCFGQOS1_4 0x0758
+#define TH1520_CTRL_PCFGWQOS0_4 0x075c
+#define TH1520_CTRL_PCFGWQOS1_4 0x0760
+#define TH1520_CTRL_UMCTL2_VER_NUMBER 0x0ff0
+#define TH1520_CTRL_UMCTL2_VER_TYPE 0x0ff4
+#define TH1520_CTRL_DCH1_STAT 0x1b04
+#define TH1520_CTRL_DCH1_MRCTRL0 0x1b10
+#define TH1520_CTRL_DCH1_MRCTRL1 0x1b14
+#define TH1520_CTRL_DCH1_MRSTAT 0x1b18
+#define TH1520_CTRL_DCH1_DERATECTL 0x1b2c
+#define TH1520_CTRL_DCH1_PWRCTL 0x1b30
+#define TH1520_CTRL_DCH1_HWLPCTL 0x1b38
+#define TH1520_CTRL_DCH1_CRCPARCTL0 0x1bc0
+#define TH1520_CTRL_DCH1_ZQCTL2 0x1c88
+#define TH1520_CTRL_DCH1_DFISTAT 0x1cbc
+#define TH1520_CTRL_DCH1_ODTMAP 0x1d44
+#define TH1520_CTRL_DCH1_DBG1 0x1e04
+#define TH1520_CTRL_DCH1_DBGCMD 0x1e0c
+#define TH1520_CTRL_DCH1_DBGCAM 0x1e08
+
+/* PHY configuration registers */
+#define TH1520_DDR_PHY_REG(regid) ((regid) * 2)
+
+/* UctShadowRegs */
+#define TH1520_PHY_MSG_STATUS TH1520_DDR_PHY_REG(0xd0004)
+#define TH1520_PHY_MSG_STATUS_EMPTY BIT(0)
+/* DctWriteProt */
+#define TH1520_PHY_MSG_ACK TH1520_DDR_PHY_REG(0xd0031)
+#define TH1520_PHY_MSG_ACK_EN BIT(0)
+/* UctWriteOnlyShadow */
+#define TH1520_PHY_MSG_ID TH1520_DDR_PHY_REG(0xd0032)
+#define TH1520_PHY_MSG_ID_COMPLETION 0x7
+#define TH1520_PHY_MSG_ID_ERROR 0xff
+/* UctDatWriteOnlyShadow */
+#define TH1520_PHY_MSG_DATA TH1520_DDR_PHY_REG(0xd0034)
+
+struct th1520_ddr_priv {
+ void __iomem *phy0;
+ void __iomem *phy1;
+ void __iomem *ctrl;
+ void __iomem *sys;
+};
+
+binman_sym_declare(ulong, ddr_fw, image_pos);
+
+static int th1520_ddr_pll_config(void __iomem *sysreg, unsigned int frequency)
+{
+ u32 tmp;
+ int ret;
+
+ tmp = TH1520_SYS_PLL_CFG1_RST |
+ TH1520_SYS_PLL_CFG1_FOUTPOSTDIVPD |
+ TH1520_SYS_PLL_CFG1_FOUT4PHASEPD |
+ Th1520_SYS_PLL_CFG1_DACPD;
+ writel(tmp, sysreg + TH1520_SYS_PLL_CFG1);
+
+ switch (frequency) {
+ case TH1520_DDR_FREQ_3733:
+ writel(FIELD_PREP(TH1520_SYS_PLL_CFG0_REFDIV, 1) |
+ FIELD_PREP(TH1520_SYS_PLL_CFG0_FBDIV, 77) |
+ FIELD_PREP(TH1520_SYS_PLL_CFG0_POSTDIV1, 2) |
+ FIELD_PREP(TH1520_SYS_PLL_CFG0_POSTDIV2, 1),
+ sysreg + TH1520_SYS_PLL_CFG0);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ udelay(2);
+ tmp &= ~TH1520_SYS_PLL_CFG1_RST;
+ writel(tmp, sysreg + TH1520_SYS_PLL_CFG1);
+
+ ret = readl_poll_timeout(sysreg + TH1520_SYS_PLL_STS, tmp,
+ tmp & TH1520_SYS_PLL_STS_LOCKED,
+ TH1520_SYS_PLL_TIMEOUT_US);
+
+ writel(TH1520_SYS_PLL_STS_EN, sysreg + TH1520_SYS_PLL_STS);
+
+ return ret;
+}
+
+static int th1520_ddr_ctrl_init(void __iomem *ctrlreg, struct th1520_ddr_fw *fw)
+{
+ int ret;
+ u32 tmp;
+
+ writel(0x00000001, ctrlreg + TH1520_CTRL_DBG1);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_PWRCTL);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_STAT, tmp,
+ tmp == 0x00000000,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ if (fw->ranknum == 2)
+ writel(0x03080020, ctrlreg + TH1520_CTRL_MSTR);
+ else
+ return -EINVAL;
+
+ writel(0x00003030, ctrlreg + TH1520_CTRL_MRCTRL0);
+ writel(0x0002d90f, ctrlreg + TH1520_CTRL_MRCTRL1);
+
+ switch (fw->freq) {
+ case TH1520_DDR_FREQ_3733:
+ writel(0x000013f3, ctrlreg + TH1520_CTRL_DERATEEN);
+ writel(0x40000000, ctrlreg + TH1520_CTRL_DERATEINT);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_DERATECTL);
+ writel(0x00000020, ctrlreg + TH1520_CTRL_PWRCTL);
+ writel(0x0040ae04, ctrlreg + TH1520_CTRL_PWRTMG);
+ writel(0x00430000, ctrlreg + TH1520_CTRL_HWLPCTL);
+ writel(0x00210004, ctrlreg + TH1520_CTRL_RFSHCTL0);
+ writel(0x000d0021, ctrlreg + TH1520_CTRL_RFSHCTL1);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_RFSHCTL3);
+ writel(0x81c00084, ctrlreg + TH1520_CTRL_RFSHTMG);
+ writel(0x00540000, ctrlreg + TH1520_CTRL_RFSHTMG1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_CRCPARCTL0);
+ writel(0xc0020002, ctrlreg + TH1520_CTRL_INIT0);
+ writel(0x00010002, ctrlreg + TH1520_CTRL_INIT1);
+ writel(0x00001f00, ctrlreg + TH1520_CTRL_INIT2);
+ writel(0x00640036, ctrlreg + TH1520_CTRL_INIT3);
+ writel(0x00f20008, ctrlreg + TH1520_CTRL_INIT4);
+ writel(0x0004000b, ctrlreg + TH1520_CTRL_INIT5);
+ writel(0x00440012, ctrlreg + TH1520_CTRL_INIT6);
+ writel(0x0004001a, ctrlreg + TH1520_CTRL_INIT7);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DIMMCTL);
+ writel(0x0000ab9f, ctrlreg + TH1520_CTRL_RANKCTL);
+ writel(0x00000017, ctrlreg + TH1520_CTRL_RANKCTL1);
+ writel(0x1f263f28, ctrlreg + TH1520_CTRL_DRAMTMG0);
+ writel(0x00080839, ctrlreg + TH1520_CTRL_DRAMTMG1);
+ writel(0x08121d17, ctrlreg + TH1520_CTRL_DRAMTMG2);
+ writel(0x00d0e000, ctrlreg + TH1520_CTRL_DRAMTMG3);
+ writel(0x11040a12, ctrlreg + TH1520_CTRL_DRAMTMG4);
+ writel(0x02050e0e, ctrlreg + TH1520_CTRL_DRAMTMG5);
+ writel(0x01010008, ctrlreg + TH1520_CTRL_DRAMTMG6);
+ writel(0x00000502, ctrlreg + TH1520_CTRL_DRAMTMG7);
+ writel(0x00000101, ctrlreg + TH1520_CTRL_DRAMTMG8);
+ writel(0x00020000, ctrlreg + TH1520_CTRL_DRAMTMG12);
+ writel(0x0d100002, ctrlreg + TH1520_CTRL_DRAMTMG13);
+ writel(0x0000010c, ctrlreg + TH1520_CTRL_DRAMTMG14);
+ writel(0x03a50021, ctrlreg + TH1520_CTRL_ZQCTL0);
+ writel(0x02f00800, ctrlreg + TH1520_CTRL_ZQCTL1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_ZQCTL2);
+ writel(0x059f820c, ctrlreg + TH1520_CTRL_DFITMG0);
+ writel(0x000c0303, ctrlreg + TH1520_CTRL_DFITMG1);
+ writel(0x0351a101, ctrlreg + TH1520_CTRL_DFILPCFG0);
+ writel(0x00000011, ctrlreg + TH1520_CTRL_DFIMISC);
+ writel(0x00001f0c, ctrlreg + TH1520_CTRL_DFITMG2);
+ writel(0x00000007, ctrlreg + TH1520_CTRL_DBICTL);
+ writel(0x14000001, ctrlreg + TH1520_CTRL_DFIPHYMSTR);
+ writel(0x06090b40, ctrlreg + TH1520_CTRL_ODTCFG);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ writel(0x00400018, ctrlreg + TH1520_CTRL_DFIUPD0);
+ writel(0x00280032, ctrlreg + TH1520_CTRL_DFIUPD1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DFIUPD2);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_ODTMAP);
+ writel(0x1f829b1c, ctrlreg + TH1520_CTRL_SCHED);
+ writel(0x4400b00f, ctrlreg + TH1520_CTRL_SCHED1);
+ writel(0x0f000001, ctrlreg + TH1520_CTRL_PERFHPR1);
+ writel(0x0f00007f, ctrlreg + TH1520_CTRL_PERFLPR1);
+ writel(0x0f00007f, ctrlreg + TH1520_CTRL_PERFWR1);
+ writel(0x00000208, ctrlreg + TH1520_CTRL_SCHED3);
+ writel(0x08400810, ctrlreg + TH1520_CTRL_SCHED4);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DBG0);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DBG1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DBGCMD);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_SWCTL);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_SWCTLSTATIC);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_POISONCFG);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_PCTRL_0);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_PCTRL_1);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_PCTRL_2);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_PCTRL_3);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_PCTRL_4);
+ writel(0x00003030, ctrlreg + TH1520_CTRL_DCH1_MRCTRL0);
+ writel(0x0002d90f, ctrlreg + TH1520_CTRL_DCH1_MRCTRL1);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_DCH1_DERATECTL);
+ writel(0x00000020, ctrlreg + TH1520_CTRL_DCH1_PWRCTL);
+ writel(0x00430002, ctrlreg + TH1520_CTRL_DCH1_HWLPCTL);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_CRCPARCTL0);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_ZQCTL2);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_ODTMAP);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_DBG1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_DBGCMD);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_RFSHCTL3, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000010, ctrlreg + TH1520_CTRL_PCCFG);
+ writel(0x0000500f, ctrlreg + TH1520_CTRL_PCFGR_0);
+ writel(0x0000500f, ctrlreg + TH1520_CTRL_PCFGW_0);
+ writel(0x00005020, ctrlreg + TH1520_CTRL_PCFGR_1);
+ writel(0x0000501f, ctrlreg + TH1520_CTRL_PCFGW_1);
+ writel(0x0000501f, ctrlreg + TH1520_CTRL_PCFGR_2);
+ writel(0x0000503f, ctrlreg + TH1520_CTRL_PCFGW_2);
+ writel(0x000051ff, ctrlreg + TH1520_CTRL_PCFGR_3);
+ writel(0x000051ff, ctrlreg + TH1520_CTRL_PCFGW_3);
+ writel(0x0000503f, ctrlreg + TH1520_CTRL_PCFGR_4);
+ writel(0x0000503f, ctrlreg + TH1520_CTRL_PCFGW_4);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_PWRCTL, tmp,
+ tmp == 0x00000020,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000020, ctrlreg + TH1520_CTRL_PWRCTL);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DCH1_PWRCTL, tmp,
+ tmp == 0x00000020,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000020, ctrlreg + TH1520_CTRL_DCH1_PWRCTL);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DBG1);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_PWRCTL, tmp,
+ tmp == 0x00000020,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000020, ctrlreg + TH1520_CTRL_PWRCTL);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_PWRCTL, tmp,
+ tmp == 0x00000020,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000020, ctrlreg + TH1520_CTRL_PWRCTL);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_DBG1);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DCH1_PWRCTL, tmp,
+ tmp == 0x00000020,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000020, ctrlreg + TH1520_CTRL_DCH1_PWRCTL);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DCH1_PWRCTL, tmp,
+ tmp == 0x00000020,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000020, ctrlreg + TH1520_CTRL_DCH1_PWRCTL);
+ writel(0x14000001, ctrlreg + TH1520_CTRL_DFIPHYMSTR);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_SWCTL);
+ writel(0x00000010, ctrlreg + TH1520_CTRL_DFIMISC);
+ writel(0x00000010, ctrlreg + TH1520_CTRL_DFIMISC);
+ writel(0x00000002, ctrlreg + TH1520_CTRL_DBG1);
+ writel(0x00000002, ctrlreg + TH1520_CTRL_DCH1_DBG1);
+
+ switch (fw->bitwidth) {
+ case 64:
+ writel(0x00040018, ctrlreg + TH1520_CTRL_ADDRMAP0);
+ writel(0x00090909, ctrlreg + TH1520_CTRL_ADDRMAP1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_ADDRMAP2);
+ writel(0x01010101, ctrlreg + TH1520_CTRL_ADDRMAP3);
+ writel(0x00001f1f, ctrlreg + TH1520_CTRL_ADDRMAP4);
+ writel(0x080f0808, ctrlreg + TH1520_CTRL_ADDRMAP5);
+ writel(0x08080808, ctrlreg + TH1520_CTRL_ADDRMAP6);
+ writel(0x00000f0f, ctrlreg + TH1520_CTRL_ADDRMAP7);
+ writel(0x08080808, ctrlreg + TH1520_CTRL_ADDRMAP9);
+ writel(0x08080808, ctrlreg + TH1520_CTRL_ADDRMAP10);
+ writel(0x00000008, ctrlreg + TH1520_CTRL_ADDRMAP11);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int th1520_ddr_read_msg(void __iomem *phyreg, u16 *id, u16 *data)
+{
+ u32 tmp;
+ int ret;
+
+ ret = readw_poll_timeout(phyreg + TH1520_PHY_MSG_STATUS, tmp,
+ !(tmp & TH1520_PHY_MSG_STATUS_EMPTY),
+ TH1520_PHY_MSG_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ *id = readw(phyreg + TH1520_PHY_MSG_ID);
+ *data = readw(phyreg + TH1520_PHY_MSG_DATA);
+
+ writew(0, phyreg + TH1520_PHY_MSG_ACK);
+
+ ret = readw_poll_timeout(phyreg + TH1520_PHY_MSG_STATUS, tmp,
+ tmp & TH1520_PHY_MSG_STATUS_EMPTY,
+ TH1520_PHY_MSG_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writew(TH1520_PHY_MSG_ACK_EN, phyreg + TH1520_PHY_MSG_ACK);
+
+ return 0;
+}
+
+static int th1520_phy_wait_pmu_completion(void __iomem *phyreg)
+{
+ u16 id, data;
+ int ret;
+
+ do {
+ ret = th1520_ddr_read_msg(phyreg, &id, &data);
+
+ if (ret)
+ return ret;
+ } while (id != TH1520_PHY_MSG_ID_COMPLETION &&
+ id != TH1520_PHY_MSG_ID_ERROR &&
+ !ret);
+
+ return id == TH1520_PHY_MSG_ID_COMPLETION ? ret : -EIO;
+}
+
+static int lpddr4_load_firmware(struct th1520_ddr_priv *priv,
+ struct th1520_ddr_fw *fw)
+{
+ union th1520_ddr_cfg *cfg;
+ size_t i, j;
+ int ret;
+
+ for (cfg = fw->cfgs, i = 0; i < fw->cfgnum; i++) {
+ u32 addr = FIELD_GET(TH1520_DDR_CFG_ADDR, cfg->opaddr) * 2;
+ u32 op = FIELD_GET(TH1520_DDR_CFG_OP, cfg->opaddr);
+
+ switch (op) {
+ case TH1520_DDR_CFG_PHY0:
+ writew(cfg->phy.data, priv->phy0 + addr);
+ break;
+ case TH1520_DDR_CFG_PHY1:
+ writew(cfg->phy.data, priv->phy1 + addr);
+ break;
+ case TH1520_DDR_CFG_PHY:
+ writew(cfg->phy.data, priv->phy0 + addr);
+ writew(cfg->phy.data, priv->phy1 + addr);
+ break;
+ case TH1520_DDR_CFG_RANGE:
+ for (j = 0; j < cfg->range.num; j++) {
+ writew(cfg->range.data[j],
+ priv->phy0 + addr + j * 2);
+ writew(cfg->range.data[j],
+ priv->phy1 + addr + j * 2);
+ }
+ break;
+ case TH1520_DDR_CFG_WAITFW0:
+ ret = th1520_phy_wait_pmu_completion(priv->phy0);
+
+ if (ret) {
+ pr_err("phy 0 training failed: %d\n", ret);
+ return ret;
+ }
+
+ break;
+ case TH1520_DDR_CFG_WAITFW1:
+ ret = th1520_phy_wait_pmu_completion(priv->phy1);
+
+ if (ret) {
+ pr_err("phy 1 training failed: %d\n", ret);
+ return ret;
+ }
+
+ break;
+ default:
+ pr_err("Unknown DRAM configuration %d\n", op);
+
+ return -EOPNOTSUPP;
+ }
+
+ if (op == TH1520_DDR_CFG_RANGE)
+ cfg = (void *)cfg + sizeof(cfg->range) +
+ cfg->range.num * sizeof(u16);
+ else
+ cfg = (union th1520_ddr_cfg *)(&cfg->phy + 1);
+ }
+
+ return 0;
+}
+
+static int th1520_ddr_ctrl_enable(void __iomem *ctrlreg,
+ struct th1520_ddr_fw *fw)
+{
+ u32 tmp;
+ int ret;
+
+ writel(0x00000030, ctrlreg + TH1520_CTRL_DFIMISC);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DFISTAT, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DCH1_DFISTAT, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000010, ctrlreg + TH1520_CTRL_DFIMISC);
+ writel(0x00000011, ctrlreg + TH1520_CTRL_DFIMISC);
+ writel(0x0000000a, ctrlreg + TH1520_CTRL_PWRCTL);
+ writel(0x0000000a, ctrlreg + TH1520_CTRL_DCH1_PWRCTL);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_SWCTL);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_SWSTAT, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_STAT, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DCH1_STAT, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x14000001, ctrlreg + TH1520_CTRL_DFIPHYMSTR);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_SWCTL);
+ writel(0x00020002, ctrlreg + TH1520_CTRL_INIT0);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_SWCTL);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_SWSTAT, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+
+ if (ret)
+ return ret;
+
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DBG1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_DBG1);
+
+ return 0;
+}
+
+static void th1520_ddr_enable_self_refresh(void __iomem *ctrlreg,
+ void __iomem *sysreg)
+{
+ writel(0x00000000, ctrlreg + TH1520_CTRL_RFSHCTL3);
+
+ writel(0x000a0000, sysreg + TH1520_SYS_DDR_CFG1);
+
+ writel(0x00000000, ctrlreg + TH1520_CTRL_SWCTL);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_SWCTLSTATIC);
+ writel(0x0040ae04, ctrlreg + TH1520_CTRL_PWRTMG);
+ writel(0x00430003, ctrlreg + TH1520_CTRL_HWLPCTL);
+ writel(0x00430003, ctrlreg + TH1520_CTRL_DCH1_HWLPCTL);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_SWCTL);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_SWCTLSTATIC);
+ writel(0x0000000b, ctrlreg + TH1520_CTRL_PWRCTL);
+ writel(0x0000000b, ctrlreg + TH1520_CTRL_DCH1_PWRCTL);
+}
+
+static int th1520_ddr_init(struct th1520_ddr_priv *priv)
+{
+ struct th1520_ddr_fw *fw = (void *)binman_sym(ulong, ddr_fw, image_pos);
+ u32 reset;
+ int ret;
+
+ ret = th1520_ddr_pll_config(priv->sys, fw->freq);
+ if (ret) {
+ pr_err("failed to configure PLL: %d\n", ret);
+ return ret;
+ }
+
+ reset = TH1520_SYS_DDR_CFG0_PHY_PWROK_RSTN;
+ writel(reset, priv->sys + TH1520_SYS_DDR_CFG0);
+ reset |= TH1520_SYS_DDR_CFG0_PHY_CORE_RSTN;
+ writel(reset, priv->sys + TH1520_SYS_DDR_CFG0);
+ reset |= TH1520_SYS_DDR_CFG0_APB_RSTN;
+ writel(reset, priv->sys + TH1520_SYS_DDR_CFG0);
+
+ ret = th1520_ddr_ctrl_init(priv->ctrl, fw);
+ if (ret) {
+ pr_err("failed to initialize DDR controller: %d\n", ret);
+ return ret;
+ }
+
+ reset |= TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(0) |
+ TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(1) |
+ TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(2) |
+ TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(3) |
+ TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(4) |
+ TH1520_SYS_DDR_CFG0_CTRL_RSTN;
+ writel(reset, priv->sys + TH1520_SYS_DDR_CFG0);
+
+ lpddr4_load_firmware(priv, fw);
+
+ ret = th1520_ddr_ctrl_enable(priv->ctrl, fw);
+ if (ret) {
+ pr_err("failed to enable DDR controller: %d\n", ret);
+ return ret;
+ }
+
+ th1520_ddr_enable_self_refresh(priv->ctrl, priv->sys);
+
+ return 0;
+}
+
+static int th1520_ddr_probe(struct udevice *dev)
+{
+ struct th1520_ddr_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+
+ addr = dev_read_addr_name(dev, "phy-0");
+ priv->phy0 = (void __iomem *)addr;
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ addr = dev_read_addr_name(dev, "phy-1");
+ priv->phy1 = (void __iomem *)addr;
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ addr = dev_read_addr_name(dev, "ctrl");
+ priv->ctrl = (void __iomem *)addr;
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ addr = dev_read_addr_name(dev, "sys");
+ priv->sys = (void __iomem *)addr;
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ return th1520_ddr_init(priv);
+}
+
+static int th1520_ddr_get_info(struct udevice *dev, struct ram_info *info)
+{
+ info->base = gd->ram_base;
+ info->size = gd->ram_size;
+
+ return 0;
+}
+
+static struct ram_ops th1520_ddr_ops = {
+ .get_info = th1520_ddr_get_info,
+};
+
+static const struct udevice_id th1520_ddr_ids[] = {
+ { .compatible = "thead,th1520-ddrc" },
+ { }
+};
+
+U_BOOT_DRIVER(th1520_ddr) = {
+ .name = "th1520_ddr",
+ .id = UCLASS_RAM,
+ .ops = &th1520_ddr_ops,
+ .of_match = th1520_ddr_ids,
+ .probe = th1520_ddr_probe,
+ .priv_auto = sizeof(struct th1520_ddr_priv),
+};
--
2.49.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 05/10] riscv: dts: th1520: Preserve necessary devices for SPL
2025-04-26 16:56 [PATCH 00/10] Initial SPL support for T-Head TH1520 SoC Yao Zi
` (4 preceding siblings ...)
2025-04-26 17:00 ` Yao Zi
@ 2025-04-26 17:00 ` Yao Zi
2025-05-12 18:02 ` Leo Liang
2025-04-26 17:00 ` [PATCH 06/10] riscv: dts: lichee-module-4a: Preserve memory node " Yao Zi
` (4 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Yao Zi @ 2025-04-26 17:00 UTC (permalink / raw)
To: Rick Chen, Leo, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang
Cc: u-boot, Han Gao, Han Gao, Yao Zi
SPL for TH1520 requires CPU and boot UART nodes to function. Preserve
them in SPL devicetree blob with bootph-pre-ram property.
Signed-off-by: Yao Zi <ziyao@disroot.org>
---
arch/riscv/dts/th1520.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi
index e4c8cee66bc..ef84d8cc265 100644
--- a/arch/riscv/dts/th1520.dtsi
+++ b/arch/riscv/dts/th1520.dtsi
@@ -14,6 +14,7 @@
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
+ bootph-pre-ram;
timebase-frequency = <3000000>;
c910_0: cpu@0 {
@@ -21,6 +22,7 @@
device_type = "cpu";
riscv,isa = "rv64imafdc";
reg = <0>;
+ bootph-pre-ram;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -42,6 +44,7 @@
device_type = "cpu";
riscv,isa = "rv64imafdc";
reg = <1>;
+ bootph-pre-ram;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -63,6 +66,7 @@
device_type = "cpu";
riscv,isa = "rv64imafdc";
reg = <2>;
+ bootph-pre-ram;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -84,6 +88,7 @@
device_type = "cpu";
riscv,isa = "rv64imafdc";
reg = <3>;
+ bootph-pre-ram;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
@@ -173,6 +178,7 @@
uart0: serial@ffe7014000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7014000 0x0 0x100>;
+ bootph-pre-ram;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_sclk>;
clock-frequency = <100000000>;
--
2.49.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 05/10] riscv: dts: th1520: Preserve necessary devices for SPL
2025-04-26 17:00 ` [PATCH 05/10] riscv: dts: th1520: Preserve necessary devices for SPL Yao Zi
@ 2025-05-12 18:02 ` Leo Liang
0 siblings, 0 replies; 27+ messages in thread
From: Leo Liang @ 2025-05-12 18:02 UTC (permalink / raw)
To: Yao Zi
Cc: Rick Chen, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang, u-boot, Han Gao,
Han Gao
On Sat, Apr 26, 2025 at 05:00:54PM +0000, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> SPL for TH1520 requires CPU and boot UART nodes to function. Preserve
> them in SPL devicetree blob with bootph-pre-ram property.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
> arch/riscv/dts/th1520.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 06/10] riscv: dts: lichee-module-4a: Preserve memory node for SPL
2025-04-26 16:56 [PATCH 00/10] Initial SPL support for T-Head TH1520 SoC Yao Zi
` (5 preceding siblings ...)
2025-04-26 17:00 ` [PATCH 05/10] riscv: dts: th1520: Preserve necessary devices for SPL Yao Zi
@ 2025-04-26 17:00 ` Yao Zi
2025-05-12 18:03 ` Leo Liang
2025-04-26 17:00 ` [PATCH 07/10] riscv: dts: th1520: Add DRAM controller Yao Zi
` (3 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Yao Zi @ 2025-04-26 17:00 UTC (permalink / raw)
To: Rick Chen, Leo, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang
Cc: u-boot, Han Gao, Han Gao, Yao Zi
Memory node is necessary for TH1520 SPL to configure size and base
address of DRAM. Let's preserve it in SPL devicetree blob.
Signed-off-by: Yao Zi <ziyao@disroot.org>
---
arch/riscv/dts/th1520-lichee-module-4a.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi
index 86a81bdcf77..20dbc4c7d24 100644
--- a/arch/riscv/dts/th1520-lichee-module-4a.dtsi
+++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi
@@ -14,6 +14,7 @@
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x2 0x00000000>;
+ bootph-pre-ram;
};
};
--
2.49.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 06/10] riscv: dts: lichee-module-4a: Preserve memory node for SPL
2025-04-26 17:00 ` [PATCH 06/10] riscv: dts: lichee-module-4a: Preserve memory node " Yao Zi
@ 2025-05-12 18:03 ` Leo Liang
0 siblings, 0 replies; 27+ messages in thread
From: Leo Liang @ 2025-05-12 18:03 UTC (permalink / raw)
To: Yao Zi
Cc: Rick Chen, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang, u-boot, Han Gao,
Han Gao
On Sat, Apr 26, 2025 at 05:00:55PM +0000, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> Memory node is necessary for TH1520 SPL to configure size and base
> address of DRAM. Let's preserve it in SPL devicetree blob.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
> arch/riscv/dts/th1520-lichee-module-4a.dtsi | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 07/10] riscv: dts: th1520: Add DRAM controller
2025-04-26 16:56 [PATCH 00/10] Initial SPL support for T-Head TH1520 SoC Yao Zi
` (6 preceding siblings ...)
2025-04-26 17:00 ` [PATCH 06/10] riscv: dts: lichee-module-4a: Preserve memory node " Yao Zi
@ 2025-04-26 17:00 ` Yao Zi
2025-05-12 18:04 ` Leo Liang
2025-04-26 17:00 ` [PATCH 08/10] riscv: dts: th1520: Add binman configuration Yao Zi
` (2 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Yao Zi @ 2025-04-26 17:00 UTC (permalink / raw)
To: Rick Chen, Leo, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang
Cc: u-boot, Han Gao, Han Gao, Yao Zi
Describe DRAM controller integrated in TH1520 SoC and preserve it in SPL
devicetree blob.
Signed-off-by: Yao Zi <ziyao@disroot.org>
---
arch/riscv/dts/th1520.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi
index ef84d8cc265..b908eb37e41 100644
--- a/arch/riscv/dts/th1520.dtsi
+++ b/arch/riscv/dts/th1520.dtsi
@@ -372,6 +372,16 @@
status = "disabled";
};
+ ddrc: ddrc@fffd000000 {
+ compatible = "thead,th1520-ddrc";
+ reg = <0xff 0xfd000000 0x0 0x1000000>,
+ <0xff 0xfe000000 0x0 0x1000000>,
+ <0xff 0xff000000 0x0 0x4000>,
+ <0xff 0xff005000 0x0 0x1000>;
+ reg-names = "phy-0", "phy-1", "ctrl", "sys";
+ bootph-pre-ram;
+ };
+
timer4: timer@ffffc33000 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xffc33000 0x0 0x14>;
--
2.49.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 07/10] riscv: dts: th1520: Add DRAM controller
2025-04-26 17:00 ` [PATCH 07/10] riscv: dts: th1520: Add DRAM controller Yao Zi
@ 2025-05-12 18:04 ` Leo Liang
0 siblings, 0 replies; 27+ messages in thread
From: Leo Liang @ 2025-05-12 18:04 UTC (permalink / raw)
To: Yao Zi
Cc: Rick Chen, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang, u-boot, Han Gao,
Han Gao
On Sat, Apr 26, 2025 at 05:00:56PM +0000, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> Describe DRAM controller integrated in TH1520 SoC and preserve it in SPL
> devicetree blob.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
> arch/riscv/dts/th1520.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 08/10] riscv: dts: th1520: Add binman configuration
2025-04-26 16:56 [PATCH 00/10] Initial SPL support for T-Head TH1520 SoC Yao Zi
` (7 preceding siblings ...)
2025-04-26 17:00 ` [PATCH 07/10] riscv: dts: th1520: Add DRAM controller Yao Zi
@ 2025-04-26 17:00 ` Yao Zi
2025-05-12 18:04 ` Leo Liang
2025-04-26 17:03 ` [PATCH 09/10] board: thead: licheepi4a: Enable SPL support Yao Zi
2025-04-26 17:03 ` [PATCH 10/10] doc: thead: lpi4a: Update documentation Yao Zi
10 siblings, 1 reply; 27+ messages in thread
From: Yao Zi @ 2025-04-26 17:00 UTC (permalink / raw)
To: Rick Chen, Leo, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang
Cc: u-boot, Han Gao, Han Gao, Yao Zi
Add binman configuration for TH1520 SoC, whose BROM loads the image
combined into SRAM and directly jumps to it. The configuration creates
u-boot-with-spl.bin where the SPL code locates at the start and the DDR
firmware is shipped.
Signed-off-by: Yao Zi <ziyao@disroot.org>
---
arch/riscv/dts/thead-th1520-binman.dtsi | 55 +++++++++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 arch/riscv/dts/thead-th1520-binman.dtsi
diff --git a/arch/riscv/dts/thead-th1520-binman.dtsi b/arch/riscv/dts/thead-th1520-binman.dtsi
new file mode 100644
index 00000000000..f060639e1c6
--- /dev/null
+++ b/arch/riscv/dts/thead-th1520-binman.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 Yao Zi <ziyao@disroot.org>
+ */
+
+#include <config.h>
+
+/ {
+ binman: binman {
+ };
+};
+
+&binman {
+ filename = "u-boot-with-spl.bin";
+
+ u-boot-spl {
+ };
+
+ ddr-fw {
+ filename = "th1520-ddr-firmware.bin";
+ type = "blob-ext";
+ };
+
+ fit {
+ offset = <CONFIG_SPL_PAD_TO>;
+
+ description = "Configuration to load M-mode U-Boot";
+
+ #address-cells = <2>;
+ fit,fdt-list = "of-list";
+
+ images {
+ uboot {
+ description = "U-Boot";
+ type = "standalone";
+ os = "U-boot";
+ arch = "riscv";
+ compression = "none";
+ load = /bits/ 64 <CONFIG_TEXT_BASE>;
+
+ uboot_blob: u-boot {
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-th1520-lichee-pi-4a";
+
+ conf-th1520-lichee-pi-4a {
+ description = "th1520-lichee-pi-4a";
+ loadables = "uboot";
+ };
+ };
+ };
+};
--
2.49.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 08/10] riscv: dts: th1520: Add binman configuration
2025-04-26 17:00 ` [PATCH 08/10] riscv: dts: th1520: Add binman configuration Yao Zi
@ 2025-05-12 18:04 ` Leo Liang
0 siblings, 0 replies; 27+ messages in thread
From: Leo Liang @ 2025-05-12 18:04 UTC (permalink / raw)
To: Yao Zi
Cc: Rick Chen, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang, u-boot, Han Gao,
Han Gao
On Sat, Apr 26, 2025 at 05:00:57PM +0000, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> Add binman configuration for TH1520 SoC, whose BROM loads the image
> combined into SRAM and directly jumps to it. The configuration creates
> u-boot-with-spl.bin where the SPL code locates at the start and the DDR
> firmware is shipped.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
> arch/riscv/dts/thead-th1520-binman.dtsi | 55 +++++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
> create mode 100644 arch/riscv/dts/thead-th1520-binman.dtsi
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 09/10] board: thead: licheepi4a: Enable SPL support
2025-04-26 16:56 [PATCH 00/10] Initial SPL support for T-Head TH1520 SoC Yao Zi
` (8 preceding siblings ...)
2025-04-26 17:00 ` [PATCH 08/10] riscv: dts: th1520: Add binman configuration Yao Zi
@ 2025-04-26 17:03 ` Yao Zi
2025-05-12 18:05 ` Leo Liang
2025-04-26 17:03 ` [PATCH 10/10] doc: thead: lpi4a: Update documentation Yao Zi
10 siblings, 1 reply; 27+ messages in thread
From: Yao Zi @ 2025-04-26 17:03 UTC (permalink / raw)
To: Rick Chen, Leo, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang
Cc: u-boot, Han Gao, Han Gao, Yao Zi
Adjust Kconfig and defconfig and add SPL initialization code for
Lichee Pi 4A. Then enable SPL support which we've added for TH1520 SoC
earlier. The board devicetree is changed to use TH1520 binman
configuration to generate bootable images.
Signed-off-by: Yao Zi <ziyao@disroot.org>
---
arch/riscv/dts/th1520-lichee-pi-4a.dts | 1 +
board/thead/th1520_lpi4a/Kconfig | 5 +--
board/thead/th1520_lpi4a/Makefile | 1 +
board/thead/th1520_lpi4a/spl.c | 48 ++++++++++++++++++++++++++
configs/th1520_lpi4a_defconfig | 18 ++++++++++
5 files changed, 71 insertions(+), 2 deletions(-)
create mode 100644 board/thead/th1520_lpi4a/spl.c
diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/th1520-lichee-pi-4a.dts
index a1248b2ee3a..49af88b7adf 100644
--- a/arch/riscv/dts/th1520-lichee-pi-4a.dts
+++ b/arch/riscv/dts/th1520-lichee-pi-4a.dts
@@ -4,6 +4,7 @@
*/
#include "th1520-lichee-module-4a.dtsi"
+#include "thead-th1520-binman.dtsi"
/ {
model = "Sipeed Lichee Pi 4A";
diff --git a/board/thead/th1520_lpi4a/Kconfig b/board/thead/th1520_lpi4a/Kconfig
index 622246127c1..f139d5ff2bb 100644
--- a/board/thead/th1520_lpi4a/Kconfig
+++ b/board/thead/th1520_lpi4a/Kconfig
@@ -11,7 +11,7 @@ config SYS_VENDOR
default "thead"
config SYS_CPU
- default "generic"
+ default "th1520"
config SYS_CONFIG_NAME
default "th1520_lpi4a"
@@ -22,7 +22,7 @@ config TEXT_BASE
default 0x01c00000 if RISCV_SMODE
config SPL_TEXT_BASE
- default 0x08000000
+ default 0xffe0000000
config SPL_OPENSBI_LOAD_ADDR
default 0x80000000
@@ -30,6 +30,7 @@ config SPL_OPENSBI_LOAD_ADDR
config BOARD_SPECIFIC_OPTIONS
def_bool y
select ARCH_EARLY_INIT_R
+ select THEAD_TH1520
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if RISCV_SMODE
diff --git a/board/thead/th1520_lpi4a/Makefile b/board/thead/th1520_lpi4a/Makefile
index 9671b3bbb0b..a7ddfc48d40 100644
--- a/board/thead/th1520_lpi4a/Makefile
+++ b/board/thead/th1520_lpi4a/Makefile
@@ -3,3 +3,4 @@
# Copyright (c) 2023, Yixun Lan <dlan@gentoo.org>
obj-y += board.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
diff --git a/board/thead/th1520_lpi4a/spl.c b/board/thead/th1520_lpi4a/spl.c
new file mode 100644
index 00000000000..25dfa387c36
--- /dev/null
+++ b/board/thead/th1520_lpi4a/spl.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025, Yao Zi <ziyao@disroot.org>
+ */
+
+#include <asm/io.h>
+#include <asm/spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/spl.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <hang.h>
+#include <spl.h>
+
+u32 spl_boot_device(void)
+{
+ /*
+ * We don't bother to load proper U-Boot from an external device as
+ * it fits in the integrated SRAM nicely.
+ */
+ return BOOT_DEVICE_RAM;
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret = spl_early_init();
+ struct udevice *dev;
+
+ if (ret)
+ panic("spl_early_init() failed %d\n", ret);
+
+ preloader_console_init();
+
+ /*
+ * Manually bind CPU ahead of time to make sure in-core timers are
+ * available in SPL.
+ */
+ ret = uclass_get_device(UCLASS_CPU, 0, &dev);
+ if (ret)
+ panic("failed to bind CPU: %d\n", ret);
+
+ spl_dram_init();
+
+ icache_enable();
+ dcache_enable();
+
+ th1520_invalidate_pmp();
+}
diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig
index d13c97463a8..b19dc009fde 100644
--- a/configs/th1520_lpi4a_defconfig
+++ b/configs/th1520_lpi4a_defconfig
@@ -90,3 +90,21 @@ CONFIG_ZLIB_UNCOMPRESS=y
CONFIG_BZIP2=y
CONFIG_ZSTD=y
CONFIG_LIB_RATIONAL=y
+CONFIG_SPL=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_LOAD_FIT_ADDRESS=0xffe0040000
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_STACK=0xffe0170000
+CONFIG_SPL_BSS_START_ADDR=0xffe0160000
+CONFIG_SPL_BSS_MAX_SIZE=0x10000
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_SPL_THEAD_TH1520_DDR=y
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_MMC_y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x10000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x400000
--
2.49.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 09/10] board: thead: licheepi4a: Enable SPL support
2025-04-26 17:03 ` [PATCH 09/10] board: thead: licheepi4a: Enable SPL support Yao Zi
@ 2025-05-12 18:05 ` Leo Liang
0 siblings, 0 replies; 27+ messages in thread
From: Leo Liang @ 2025-05-12 18:05 UTC (permalink / raw)
To: Yao Zi
Cc: Rick Chen, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang, u-boot, Han Gao,
Han Gao
On Sat, Apr 26, 2025 at 05:03:20PM +0000, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> Adjust Kconfig and defconfig and add SPL initialization code for
> Lichee Pi 4A. Then enable SPL support which we've added for TH1520 SoC
> earlier. The board devicetree is changed to use TH1520 binman
> configuration to generate bootable images.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
> arch/riscv/dts/th1520-lichee-pi-4a.dts | 1 +
> board/thead/th1520_lpi4a/Kconfig | 5 +--
> board/thead/th1520_lpi4a/Makefile | 1 +
> board/thead/th1520_lpi4a/spl.c | 48 ++++++++++++++++++++++++++
> configs/th1520_lpi4a_defconfig | 18 ++++++++++
> 5 files changed, 71 insertions(+), 2 deletions(-)
> create mode 100644 board/thead/th1520_lpi4a/spl.c
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 10/10] doc: thead: lpi4a: Update documentation
2025-04-26 16:56 [PATCH 00/10] Initial SPL support for T-Head TH1520 SoC Yao Zi
` (9 preceding siblings ...)
2025-04-26 17:03 ` [PATCH 09/10] board: thead: licheepi4a: Enable SPL support Yao Zi
@ 2025-04-26 17:03 ` Yao Zi
2025-05-12 18:06 ` Leo Liang
10 siblings, 1 reply; 27+ messages in thread
From: Yao Zi @ 2025-04-26 17:03 UTC (permalink / raw)
To: Rick Chen, Leo, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang
Cc: u-boot, Han Gao, Han Gao, Yao Zi
Support for eMMC, SD card, GPIO and SPL have been available in LPi4A
port. Update the documentation of support status and build
instructions.
Signed-off-by: Yao Zi <ziyao@disroot.org>
---
doc/board/thead/lpi4a.rst | 58 +++++++++++++++++++++++++++++++++++++--
1 file changed, 55 insertions(+), 3 deletions(-)
diff --git a/doc/board/thead/lpi4a.rst b/doc/board/thead/lpi4a.rst
index e395c6ae12c..7e4c4ea81ee 100644
--- a/doc/board/thead/lpi4a.rst
+++ b/doc/board/thead/lpi4a.rst
@@ -32,6 +32,8 @@ Mainline support
The support for following drivers are already enabled:
1. ns16550 UART Driver.
+2. eMMC and SD card
+
Building
~~~~~~~~
@@ -43,15 +45,32 @@ Building
export CROSS_COMPILE=<riscv64 toolchain prefix>
-The U-Boot is capable of running in M-Mode, so we can directly build it.
+3. Build DDR firmware
+
+DDR driver requires a firmware to function, to build it:
+
+.. code-block:: bash
+
+ git clone --depth 1 https://github.com/ziyao233/th1520-firmware
+ cd th1520-firmware
+ lua5.4 ddr-generate.lua src/<CONFIGURATION_NAME>.lua th1520-ddr-firmware.bin
+
+4. Build U-Boot images
+
+The U-Boot is capable of running in M-Mode, so we can directly build it without
+OpenSBI. The DDR firmware should be copied to U-Boot source directory before
+building.
.. code-block:: console
cd <U-Boot-dir>
+ cp <path-to-ddr-firmware> th1520-ddr-firmware.bin
make th1520_lpi4a_defconfig
make
-This will generate u-boot-dtb.bin
+This will generate u-boot-dtb.bin and u-boot-with-spl.bin. The former contains
+only proper U-Boot and is for chainloading; the later contains also SPL and
+DDR firmware and is ready for booting by BROM directly.
Booting
~~~~~~~
@@ -61,7 +80,7 @@ and chain load the mainline u-boot image either via tftp or emmc storage,
then bootup from it.
Sample boot log from Lichee PI 4A board via tftp
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
.. code-block:: none
@@ -127,3 +146,36 @@ Sample boot log from Lichee PI 4A board via tftp
Err: serial@ffe7014000
Model: Sipeed Lichee Pi 4A
LPI4A=>
+
+SPL support is still in an early stage and not all of the functionalities are
+available when booting from mainline SPL. When using mainline SPL,
+u-boot-with-spl.bin should be loaded to SRAM through fastboot.
+
+Sample boot log from Lichee PI 4A board via fastboot and mainline SPL
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. code-block:: none
+
+ brom_ver 8
+ [APP][E] protocol_connect failed, exit.
+ Starting download of 636588 bytes
+
+ downloading of 636588 bytes finished
+
+ U-Boot SPL 2025.04-rc2-00049-geaa9fc99d4cd-dirty (Apr 26 2025 - 13:31:41 +0000)
+ Trying to boot from RAM
+
+
+ U-Boot 2025.04-rc2-00049-geaa9fc99d4cd-dirty (Apr 26 2025 - 13:31:41 +0000)
+
+ CPU: thead,c910
+ Model: Sipeed Lichee Pi 4A
+ DRAM: 8 GiB
+ Core: 30 devices, 9 uclasses, devicetree: separate
+ MMC: mmc@ffe7080000: 0, mmc@ffe7090000: 1
+ Loading Environment from <NULL>... OK
+ In: serial@ffe7014000
+ Out: serial@ffe7014000
+ Err: serial@ffe7014000
+ Model: Sipeed Lichee Pi 4A
+ LPI4A=>
--
2.49.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 10/10] doc: thead: lpi4a: Update documentation
2025-04-26 17:03 ` [PATCH 10/10] doc: thead: lpi4a: Update documentation Yao Zi
@ 2025-05-12 18:06 ` Leo Liang
0 siblings, 0 replies; 27+ messages in thread
From: Leo Liang @ 2025-05-12 18:06 UTC (permalink / raw)
To: Yao Zi
Cc: Rick Chen, Tom Rini, Wei Fu, Yixun Lan, Maksim Kiselev,
Jaehoon Chung, Simon Glass, Heinrich Schuchardt, Ilias Apalodimas,
Neha Malcom Francis, Jayesh Choudhary, Wadim Egorov,
Vaishnav Achath, Andrew Davis, Chia-Wei Wang, u-boot, Han Gao,
Han Gao
On Sat, Apr 26, 2025 at 05:03:21PM +0000, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> Support for eMMC, SD card, GPIO and SPL have been available in LPi4A
> port. Update the documentation of support status and build
> instructions.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
> doc/board/thead/lpi4a.rst | 58 +++++++++++++++++++++++++++++++++++++--
> 1 file changed, 55 insertions(+), 3 deletions(-)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 27+ messages in thread