* [PATCH 01/11] Add handoff files
2025-09-17 15:22 [PATCH 00/11] ARM: boards: add support for Enclustra Mercury SA2 David Picard
@ 2025-09-17 15:22 ` David Picard
2025-09-17 15:22 ` [PATCH 02/11] Add Enclustra Mercury+ SA2 module David Picard
` (9 subsequent siblings)
10 siblings, 0 replies; 30+ messages in thread
From: David Picard @ 2025-09-17 15:22 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX; +Cc: David Picard
Copy handoff files from Mercury_SA2_ST1_Reference_Design
released by Enclustra.
Signed-off-by: David Picard <david.picard@clermont.in2p3.fr>
---
.../boards/enclustra-sa2/iocsr_config_cyclone5.c | 678 +++++++++++++++++++++
arch/arm/boards/enclustra-sa2/pinmux_config.c | 241 ++++++++
arch/arm/boards/enclustra-sa2/pll_config.h | 107 ++++
arch/arm/boards/enclustra-sa2/sdram_config.h | 112 ++++
arch/arm/boards/enclustra-sa2/sequencer_auto.h | 225 +++++++
.../boards/enclustra-sa2/sequencer_auto_ac_init.c | 67 ++
.../enclustra-sa2/sequencer_auto_inst_init.c | 158 +++++
arch/arm/boards/enclustra-sa2/sequencer_defines.h | 165 +++++
8 files changed, 1753 insertions(+)
diff --git a/arch/arm/boards/enclustra-sa2/iocsr_config_cyclone5.c b/arch/arm/boards/enclustra-sa2/iocsr_config_cyclone5.c
new file mode 100644
index 0000000000000000000000000000000000000000..30af190f340a065ffb385790d3bab328b1ff1ebf
--- /dev/null
+++ b/arch/arm/boards/enclustra-sa2/iocsr_config_cyclone5.c
@@ -0,0 +1,678 @@
+/* GENERATED FILE - DO NOT EDIT */
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Altera Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <mach/socfpga/cyclone5-scan-manager.h>
+
+static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)]
+ = {
+ 0x00000000,
+ 0x00000000,
+ 0x0FF00000,
+ 0xC0000000,
+ 0x0000003F,
+ 0x00008000,
+ 0x00060180,
+ 0x18060000,
+ 0x18000000,
+ 0x00018060,
+ 0x00000000,
+ 0x00004000,
+ 0x000300C0,
+ 0x0C030000,
+ 0x0C000000,
+ 0x00000030,
+ 0x0000C030,
+ 0x00002000,
+ 0x00018060,
+ 0x06018000,
+ 0x06000000,
+ 0x00000018,
+ 0x00006018,
+ 0x00001000,
+};
+
+static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)]
+ = {
+ 0x000C0300,
+ 0x300C0000,
+ 0x300000C0,
+ 0x000000C0,
+ 0x000300C0,
+ 0x00008000,
+ 0x00060180,
+ 0x18060000,
+ 0x18000000,
+ 0x00000060,
+ 0x00018060,
+ 0x00004000,
+ 0x000300C0,
+ 0x0C030000,
+ 0x0C000000,
+ 0x00000030,
+ 0x0000C030,
+ 0x00002000,
+ 0x06018060,
+ 0x06018000,
+ 0x01FE0000,
+ 0xF8000000,
+ 0x00000007,
+ 0x00001000,
+ 0x0000C030,
+ 0x0300C000,
+ 0x03000000,
+ 0x0000300C,
+ 0x0000300C,
+ 0x00000800,
+ 0x00000000,
+ 0x00000000,
+ 0x01800000,
+ 0x00000006,
+ 0x00001806,
+ 0x00000400,
+ 0x00000000,
+ 0x00C03000,
+ 0x00000003,
+ 0x00000000,
+ 0x00000000,
+ 0x00000200,
+ 0x00601806,
+ 0x00000000,
+ 0x80600000,
+ 0x80000601,
+ 0x00000601,
+ 0x00000100,
+ 0x00300C03,
+ 0xC0300C00,
+ 0xC0300000,
+ 0xC0000300,
+ 0x000C0300,
+ 0x00000080,
+};
+
+static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)]
+ = {
+ 0x000C0300,
+ 0x00000000,
+ 0x0FF00000,
+ 0x00000000,
+ 0x0C0300C0,
+ 0x00008000,
+ 0x00060180,
+ 0x18060000,
+ 0x18000000,
+ 0x00000060,
+ 0x00018060,
+ 0x00004000,
+ 0x200300C0,
+ 0x0C030000,
+ 0x0C000000,
+ 0x00000030,
+ 0x0000C030,
+ 0x00002000,
+ 0x00018060,
+ 0x06018000,
+ 0x06000000,
+ 0x00010018,
+ 0x00006018,
+ 0x00001000,
+ 0x0000C030,
+ 0x0300C000,
+ 0x03000000,
+ 0x0000000C,
+ 0x0000300C,
+ 0x00000800,
+};
+
+static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)]
+ = {
+ 0x0C420D80,
+ 0x0C3000FF,
+ 0x0A804001,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x20430000,
+ 0x0C003001,
+ 0x00C00481,
+ 0x00000000,
+ 0x4810C021,
+ 0x82000C00,
+ 0x05400000,
+ 0x03C80000,
+ 0x04010000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x90218000,
+ 0x86001800,
+ 0x00600240,
+ 0x80090218,
+ 0x00000001,
+ 0x40000000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x4810C000,
+ 0x43000C00,
+ 0x00300120,
+ 0xC004810C,
+ 0x12043000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000010,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0x40680208,
+ 0x8E034010,
+ 0x1C701A03,
+ 0x802080D0,
+ 0x34010406,
+ 0x01A00410,
+ 0x300D0000,
+ 0x1040680C,
+ 0x00410340,
+ 0xD002081A,
+ 0x06802080,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x18000000,
+ 0x01800902,
+ 0x00240860,
+ 0x007F8006,
+ 0x00000000,
+ 0x0A800001,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x20430000,
+ 0x0C003001,
+ 0x00C00481,
+ 0x00000FF0,
+ 0x4810C000,
+ 0x80000C00,
+ 0x05400000,
+ 0x02480000,
+ 0x04000000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x90218000,
+ 0x86001800,
+ 0x00600240,
+ 0x80090218,
+ 0x24086001,
+ 0x40000600,
+ 0x02A00040,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x4810C000,
+ 0x43000C00,
+ 0x00300120,
+ 0xC004810C,
+ 0x12043000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000010,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0x40680C30,
+ 0x41034010,
+ 0x02081A00,
+ 0x802080D0,
+ 0x34051406,
+ 0x01A00040,
+ 0x080D0002,
+ 0x10406802,
+ 0x00410340,
+ 0xD002081A,
+ 0x06802080,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x18000000,
+ 0x01800902,
+ 0x00240860,
+ 0x007F8006,
+ 0x00000000,
+ 0x99300001,
+ 0x34343400,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x2043090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00000000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x18864000,
+ 0x49247A06,
+ 0xB3CF23D9,
+ 0xF751451E,
+ 0x0342E388,
+ 0x821A0000,
+ 0x0000D000,
+ 0x01040680,
+ 0xD149247A,
+ 0x1EB3CF23,
+ 0x88F75E79,
+ 0x000342E3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x00003FC2,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000000,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00015000,
+ 0x0000F200,
+ 0x00000000,
+ 0x00000482,
+ 0x86120800,
+ 0x00600240,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x18864000,
+ 0x49247A06,
+ 0xB3CF23D9,
+ 0xF75E791E,
+ 0x0342E388,
+ 0x821A028A,
+ 0x0000D000,
+ 0x00000680,
+ 0xD149247A,
+ 0x1EB2CB23,
+ 0x88F55E79,
+ 0x000342E3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x00000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x2043090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00000000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x04864000,
+ 0x69A47A01,
+ 0xF228A3D5,
+ 0xF751451E,
+ 0x03529248,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD969A47A,
+ 0x1EB3CF23,
+ 0x48F75145,
+ 0x00035292,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x00000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000000,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00400000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F1690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x18864000,
+ 0x49247A06,
+ 0xB2CB23D1,
+ 0xF75E791E,
+ 0x035CE388,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD949247A,
+ 0x1EB3CF23,
+ 0x88F75E79,
+ 0x000342E3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x00000002,
+ 0x00820000,
+ 0x00489800,
+ 0x801A1A1A,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x00000004,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x40002000,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x20001000,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x00000001,
+ 0x00000000,
+ 0x00000000,
+ 0x00FF0000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000800,
+ 0xC0000001,
+ 0x00041419,
+ 0x40000000,
+ 0x04000816,
+ 0x000D0000,
+ 0x00006800,
+ 0x00000340,
+ 0xD000001A,
+ 0x06800000,
+ 0x00340000,
+ 0x0001A000,
+ 0x00000D00,
+ 0x40000068,
+ 0x1A000003,
+ 0x00D00000,
+ 0x00068000,
+ 0x00003400,
+ 0x000001A0,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x80000008,
+ 0x0000007F,
+ 0x00000000,
+ 0x00000000,
+ 0xE0000000,
+ 0x0000001F,
+ 0x00004000,
+};
diff --git a/arch/arm/boards/enclustra-sa2/pinmux_config.c b/arch/arm/boards/enclustra-sa2/pinmux_config.c
new file mode 100644
index 0000000000000000000000000000000000000000..8bcb0b5196bc0fa0d5fb748c5e8104db7a206dfc
--- /dev/null
+++ b/arch/arm/boards/enclustra-sa2/pinmux_config.c
@@ -0,0 +1,241 @@
+/* GENERATED FILE - DO NOT EDIT */
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Altera Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <common.h>
+
+/* pin MUX configuration data */
+static unsigned long sys_mgr_init_table[] = {
+ 0, /* EMACIO0 */
+ 2, /* EMACIO1 */
+ 2, /* EMACIO2 */
+ 2, /* EMACIO3 */
+ 2, /* EMACIO4 */
+ 2, /* EMACIO5 */
+ 2, /* EMACIO6 */
+ 2, /* EMACIO7 */
+ 2, /* EMACIO8 */
+ 0, /* EMACIO9 */
+ 2, /* EMACIO10 */
+ 2, /* EMACIO11 */
+ 2, /* EMACIO12 */
+ 2, /* EMACIO13 */
+ 0, /* EMACIO14 */
+ 0, /* EMACIO15 */
+ 0, /* EMACIO16 */
+ 0, /* EMACIO17 */
+ 0, /* EMACIO18 */
+ 0, /* EMACIO19 */
+ 3, /* FLASHIO0 */
+ 0, /* FLASHIO1 */
+ 3, /* FLASHIO2 */
+ 3, /* FLASHIO3 */
+ 0, /* FLASHIO4 */
+ 0, /* FLASHIO5 */
+ 0, /* FLASHIO6 */
+ 0, /* FLASHIO7 */
+ 0, /* FLASHIO8 */
+ 3, /* FLASHIO9 */
+ 3, /* FLASHIO10 */
+ 3, /* FLASHIO11 */
+ 0, /* GENERALIO0 */
+ 0, /* GENERALIO1 */
+ 0, /* GENERALIO2 */
+ 0, /* GENERALIO3 */
+ 0, /* GENERALIO4 */
+ 0, /* GENERALIO5 */
+ 0, /* GENERALIO6 */
+ 1, /* GENERALIO7 */
+ 1, /* GENERALIO8 */
+ 0, /* GENERALIO9 */
+ 0, /* GENERALIO10 */
+ 0, /* GENERALIO11 */
+ 0, /* GENERALIO12 */
+ 0, /* GENERALIO13 */
+ 0, /* GENERALIO14 */
+ 0, /* GENERALIO15 */
+ 0, /* GENERALIO16 */
+ 2, /* GENERALIO17 */
+ 2, /* GENERALIO18 */
+ 0, /* GENERALIO19 */
+ 0, /* GENERALIO20 */
+ 0, /* GENERALIO21 */
+ 0, /* GENERALIO22 */
+ 0, /* GENERALIO23 */
+ 0, /* GENERALIO24 */
+ 0, /* GENERALIO25 */
+ 0, /* GENERALIO26 */
+ 0, /* GENERALIO27 */
+ 0, /* GENERALIO28 */
+ 0, /* GENERALIO29 */
+ 0, /* GENERALIO30 */
+ 0, /* GENERALIO31 */
+ 2, /* MIXED1IO0 */
+ 2, /* MIXED1IO1 */
+ 2, /* MIXED1IO2 */
+ 2, /* MIXED1IO3 */
+ 2, /* MIXED1IO4 */
+ 2, /* MIXED1IO5 */
+ 2, /* MIXED1IO6 */
+ 2, /* MIXED1IO7 */
+ 2, /* MIXED1IO8 */
+ 2, /* MIXED1IO9 */
+ 2, /* MIXED1IO10 */
+ 2, /* MIXED1IO11 */
+ 2, /* MIXED1IO12 */
+ 2, /* MIXED1IO13 */
+ 0, /* MIXED1IO14 */
+ 3, /* MIXED1IO15 */
+ 3, /* MIXED1IO16 */
+ 3, /* MIXED1IO17 */
+ 3, /* MIXED1IO18 */
+ 3, /* MIXED1IO19 */
+ 3, /* MIXED1IO20 */
+ 0, /* MIXED1IO21 */
+ 0, /* MIXED2IO0 */
+ 0, /* MIXED2IO1 */
+ 0, /* MIXED2IO2 */
+ 0, /* MIXED2IO3 */
+ 0, /* MIXED2IO4 */
+ 0, /* MIXED2IO5 */
+ 0, /* MIXED2IO6 */
+ 0, /* MIXED2IO7 */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 0, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 0, /* SPIS1USEFPGA */
+ 0, /* RGMII0USEFPGA */
+ 0, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 1, /* I2C1USEFPGA */
+ 0, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
diff --git a/arch/arm/boards/enclustra-sa2/pll_config.h b/arch/arm/boards/enclustra-sa2/pll_config.h
new file mode 100644
index 0000000000000000000000000000000000000000..df04f312cdd1213f846edb0945fde31f67886b43
--- /dev/null
+++ b/arch/arm/boards/enclustra-sa2/pll_config.h
@@ -0,0 +1,107 @@
+/* GENERATED FILE - DO NOT EDIT */
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Altera Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PRELOADER_PLL_CONFIG_H_
+#define _PRELOADER_PLL_CONFIG_H_
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 (1)
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0)
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (31)
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3)
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511)
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0)
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1)
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1)
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (0)
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (19)
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0)
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (511)
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3)
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511)
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4)
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4)
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (39)
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0)
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (4)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (4)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (4)
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249)
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2)
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2)
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1)
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0)
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (15)
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (15)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0)
+
+#define CONFIG_HPS_CLK_OSC1_HZ (50000000)
+#define CONFIG_HPS_CLK_OSC2_HZ (25000000)
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0)
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0)
+#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
+#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
+#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000)
+#define CONFIG_HPS_CLK_EMAC0_HZ (1953125)
+#define CONFIG_HPS_CLK_EMAC1_HZ (250000000)
+#define CONFIG_HPS_CLK_USBCLK_HZ (200000000)
+#define CONFIG_HPS_CLK_NAND_HZ (50000000)
+#define CONFIG_HPS_CLK_SDMMC_HZ (200000000)
+#define CONFIG_HPS_CLK_QSPI_HZ (400000000)
+#define CONFIG_HPS_CLK_SPIM_HZ (12500000)
+#define CONFIG_HPS_CLK_CAN0_HZ (12500000)
+#define CONFIG_HPS_CLK_CAN1_HZ (12500000)
+#define CONFIG_HPS_CLK_GPIODB_HZ (32000)
+#define CONFIG_HPS_CLK_L4_MP_HZ (100000000)
+#define CONFIG_HPS_CLK_L4_SP_HZ (100000000)
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK (1)
+#define CONFIG_HPS_ALTERAGRP_MAINCLK (3)
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK (3)
+
+#endif /* _PRELOADER_PLL_CONFIG_H_ */
diff --git a/arch/arm/boards/enclustra-sa2/sdram_config.h b/arch/arm/boards/enclustra-sa2/sdram_config.h
new file mode 100644
index 0000000000000000000000000000000000000000..9b117d845a051cdd12281f029027c8062bddb868
--- /dev/null
+++ b/arch/arm/boards/enclustra-sa2/sdram_config.h
@@ -0,0 +1,112 @@
+/* GENERATED FILE - DO NOT EDIT */
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Altera Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SDRAM_CONFIG_H
+#define __SDRAM_CONFIG_H
+
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE (2)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL (8)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER (0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN (0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN (0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN (1)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT (10)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN (0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS (0)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL (5)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL (0)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL (6)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD (4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW (12)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC (104)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI (3120)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD (6)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP (6)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR (6)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR (4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP (4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS (15)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC (21)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD (4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD (4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT (512)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT (3)
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES (0)
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES (8)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS (10)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS (16)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS (3)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS (1)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH (32)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH (8)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN (0)
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK (3)
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL (2)
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA (0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH (2)
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN (0)
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE (0)
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC (0)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY (0x0)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 (0x21084210)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 (0x10441)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 (0x78)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 (0x0)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 (0x0)
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 (0x200)
+
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH (0x44555)
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP (0x2C011000)
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP (0xB00088)
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP (0x760210)
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP (0x980543)
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR (0x5A56A)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 (0x20820820)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 (0x8208208)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 (0)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 (0x41041041)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 (0x410410)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \
+(0x01010101)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \
+(0x01010101)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \
+(0x0101)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ (0)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE (1)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED (0x1)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED (0x1)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED (0x1)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST (0x111)
+
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR (2)
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC (2)
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2)
+
+#endif /*#ifndef__SDRAM_CONFIG_H */
diff --git a/arch/arm/boards/enclustra-sa2/sequencer_auto.h b/arch/arm/boards/enclustra-sa2/sequencer_auto.h
new file mode 100644
index 0000000000000000000000000000000000000000..a740d3ce70d3541b0a382db101635d27c3ebbb82
--- /dev/null
+++ b/arch/arm/boards/enclustra-sa2/sequencer_auto.h
@@ -0,0 +1,225 @@
+/*
+Copyright (C) 2023 Intel Corporation. All rights reserved.
+
+SPDX-License-Identifier: BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of Intel Corporation nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#define __RW_MGR_ac_mrs1 0x04
+#define __RW_MGR_ac_mrs3 0x06
+#define __RW_MGR_ac_write_bank_0_col_0_nodata_wl_1 0x1C
+#define __RW_MGR_ac_act_1 0x11
+#define __RW_MGR_ac_write_postdata 0x1A
+#define __RW_MGR_ac_act_0 0x10
+#define __RW_MGR_ac_des 0x0D
+#define __RW_MGR_ac_init_reset_1_cke_0 0x01
+#define __RW_MGR_ac_write_data 0x19
+#define __RW_MGR_ac_init_reset_0_cke_0 0x00
+#define __RW_MGR_ac_read_bank_0_1_norden 0x22
+#define __RW_MGR_ac_pre_all 0x12
+#define __RW_MGR_ac_mrs0_user 0x02
+#define __RW_MGR_ac_mrs0_dll_reset 0x03
+#define __RW_MGR_ac_read_bank_0_0 0x1D
+#define __RW_MGR_ac_write_bank_0_col_1 0x16
+#define __RW_MGR_ac_read_bank_0_1 0x1F
+#define __RW_MGR_ac_write_bank_1_col_0 0x15
+#define __RW_MGR_ac_write_bank_1_col_1 0x17
+#define __RW_MGR_ac_write_bank_0_col_0 0x14
+#define __RW_MGR_ac_read_bank_1_0 0x1E
+#define __RW_MGR_ac_mrs1_mirr 0x0A
+#define __RW_MGR_ac_read_bank_1_1 0x20
+#define __RW_MGR_ac_des_odt_1 0x0E
+#define __RW_MGR_ac_mrs0_dll_reset_mirr 0x09
+#define __RW_MGR_ac_zqcl 0x07
+#define __RW_MGR_ac_write_predata 0x18
+#define __RW_MGR_ac_mrs0_user_mirr 0x08
+#define __RW_MGR_ac_ref 0x13
+#define __RW_MGR_ac_nop 0x0F
+#define __RW_MGR_ac_rdimm 0x23
+#define __RW_MGR_ac_mrs2_mirr 0x0B
+#define __RW_MGR_ac_write_bank_0_col_0_nodata 0x1B
+#define __RW_MGR_ac_read_en 0x21
+#define __RW_MGR_ac_mrs3_mirr 0x0C
+#define __RW_MGR_ac_mrs2 0x05
+#define __RW_MGR_CONTENT_ac_mrs1 0x10090044
+#define __RW_MGR_CONTENT_ac_mrs3 0x100B0000
+#define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata_wl_1 0x18980000
+#define __RW_MGR_CONTENT_ac_act_1 0x106B0000
+#define __RW_MGR_CONTENT_ac_write_postdata 0x38780000
+#define __RW_MGR_CONTENT_ac_act_0 0x10680000
+#define __RW_MGR_CONTENT_ac_des 0x30780000
+#define __RW_MGR_CONTENT_ac_init_reset_1_cke_0 0x20780000
+#define __RW_MGR_CONTENT_ac_write_data 0x3CF80000
+#define __RW_MGR_CONTENT_ac_init_reset_0_cke_0 0x20700000
+#define __RW_MGR_CONTENT_ac_read_bank_0_1_norden 0x10580008
+#define __RW_MGR_CONTENT_ac_pre_all 0x10280400
+#define __RW_MGR_CONTENT_ac_mrs0_user 0x10080421
+#define __RW_MGR_CONTENT_ac_mrs0_dll_reset 0x10080520
+#define __RW_MGR_CONTENT_ac_read_bank_0_0 0x13580000
+#define __RW_MGR_CONTENT_ac_write_bank_0_col_1 0x1C980008
+#define __RW_MGR_CONTENT_ac_read_bank_0_1 0x13580008
+#define __RW_MGR_CONTENT_ac_write_bank_1_col_0 0x1C9B0000
+#define __RW_MGR_CONTENT_ac_write_bank_1_col_1 0x1C9B0008
+#define __RW_MGR_CONTENT_ac_write_bank_0_col_0 0x1C980000
+#define __RW_MGR_CONTENT_ac_read_bank_1_0 0x135B0000
+#define __RW_MGR_CONTENT_ac_mrs1_mirr 0x100A0024
+#define __RW_MGR_CONTENT_ac_read_bank_1_1 0x135B0008
+#define __RW_MGR_CONTENT_ac_des_odt_1 0x38780000
+#define __RW_MGR_CONTENT_ac_mrs0_dll_reset_mirr 0x100804C0
+#define __RW_MGR_CONTENT_ac_zqcl 0x10380400
+#define __RW_MGR_CONTENT_ac_write_predata 0x38F80000
+#define __RW_MGR_CONTENT_ac_mrs0_user_mirr 0x10080441
+#define __RW_MGR_CONTENT_ac_ref 0x10480000
+#define __RW_MGR_CONTENT_ac_nop 0x30780000
+#define __RW_MGR_CONTENT_ac_rdimm 0x10780000
+#define __RW_MGR_CONTENT_ac_mrs2_mirr 0x10090200
+#define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata 0x18180000
+#define __RW_MGR_CONTENT_ac_read_en 0x33780000
+#define __RW_MGR_CONTENT_ac_mrs3_mirr 0x100B0000
+#define __RW_MGR_CONTENT_ac_mrs2 0x100A0200
+
+/*
+Copyright (C) 2023 Intel Corporation. All rights reserved.
+
+SPDX-License-Identifier: BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of Intel Corporation nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#define __RW_MGR_READ_B2B_WAIT2 0x6B
+#define __RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
+#define __RW_MGR_REFRESH_ALL 0x14
+#define __RW_MGR_ZQCL 0x06
+#define __RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
+#define __RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
+#define __RW_MGR_ACTIVATE_0_AND_1 0x0D
+#define __RW_MGR_MRS2_MIRR 0x0A
+#define __RW_MGR_INIT_RESET_0_CKE_0 0x6F
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
+#define __RW_MGR_ACTIVATE_1 0x0F
+#define __RW_MGR_MRS2 0x04
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
+#define __RW_MGR_MRS1 0x03
+#define __RW_MGR_IDLE_LOOP1 0x7B
+#define __RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
+#define __RW_MGR_MRS3 0x05
+#define __RW_MGR_IDLE_LOOP2 0x7A
+#define __RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
+#define __RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
+#define __RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
+#define __RW_MGR_RDIMM_CMD 0x79
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
+#define __RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
+#define __RW_MGR_GUARANTEED_READ_CONT 0x54
+#define __RW_MGR_REFRESH_DELAY 0x15
+#define __RW_MGR_MRS3_MIRR 0x0B
+#define __RW_MGR_IDLE 0x00
+#define __RW_MGR_READ_B2B 0x59
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
+#define __RW_MGR_GUARANTEED_WRITE 0x18
+#define __RW_MGR_PRECHARGE_ALL 0x12
+#define __RW_MGR_SGLE_READ 0x7D
+#define __RW_MGR_MRS0_USER_MIRR 0x0C
+#define __RW_MGR_RETURN 0x01
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
+#define __RW_MGR_MRS0_USER 0x07
+#define __RW_MGR_GUARANTEED_READ 0x4C
+#define __RW_MGR_MRS0_DLL_RESET_MIRR 0x08
+#define __RW_MGR_INIT_RESET_1_CKE_0 0x74
+#define __RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
+#define __RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
+#define __RW_MGR_MRS0_DLL_RESET 0x02
+#define __RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
+#define __RW_MGR_LFSR_WR_RD_BANK_0 0x22
+#define __RW_MGR_CLEAR_DQS_ENABLE 0x49
+#define __RW_MGR_MRS1_MIRR 0x09
+#define __RW_MGR_READ_B2B_WAIT1 0x61
+#define __RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680
+#define __RW_MGR_CONTENT_REFRESH_ALL 0x000980
+#define __RW_MGR_CONTENT_ZQCL 0x008380
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00
+#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800
+#define __RW_MGR_CONTENT_MRS2_MIRR 0x008580
+#define __RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680
+#define __RW_MGR_CONTENT_ACTIVATE_1 0x000880
+#define __RW_MGR_CONTENT_MRS2 0x008280
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00
+#define __RW_MGR_CONTENT_MRS1 0x008200
+#define __RW_MGR_CONTENT_IDLE_LOOP1 0x00A680
+#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8
+#define __RW_MGR_CONTENT_MRS3 0x008300
+#define __RW_MGR_CONTENT_IDLE_LOOP2 0x008680
+#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0
+#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88
+#define __RW_MGR_CONTENT_RDIMM_CMD 0x009180
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700
+#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0
+#define __RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168
+#define __RW_MGR_CONTENT_REFRESH_DELAY 0x00A680
+#define __RW_MGR_CONTENT_MRS3_MIRR 0x008600
+#define __RW_MGR_CONTENT_IDLE 0x080000
+#define __RW_MGR_CONTENT_READ_B2B 0x040E88
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00
+#define __RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68
+#define __RW_MGR_CONTENT_PRECHARGE_ALL 0x000900
+#define __RW_MGR_CONTENT_SGLE_READ 0x040F08
+#define __RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400
+#define __RW_MGR_CONTENT_RETURN 0x080680
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80
+#define __RW_MGR_CONTENT_MRS0_USER 0x008100
+#define __RW_MGR_CONTENT_GUARANTEED_READ 0x001168
+#define __RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480
+#define __RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080
+#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00
+#define __RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180
+#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80
+#define __RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158
+#define __RW_MGR_CONTENT_MRS1_MIRR 0x008500
+#define __RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680
diff --git a/arch/arm/boards/enclustra-sa2/sequencer_auto_ac_init.c b/arch/arm/boards/enclustra-sa2/sequencer_auto_ac_init.c
new file mode 100644
index 0000000000000000000000000000000000000000..5bea3ae501044510541fcae3d871d3a9465e1f04
--- /dev/null
+++ b/arch/arm/boards/enclustra-sa2/sequencer_auto_ac_init.c
@@ -0,0 +1,67 @@
+/*
+Copyright (C) 2023 Intel Corporation. All rights reserved.
+
+SPDX-License-Identifier: BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of Intel Corporation nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+static const uint32_t ac_rom_init_size = 36;
+static const uint32_t ac_rom_init[36] = {
+ 0x20700000,
+ 0x20780000,
+ 0x10080421,
+ 0x10080520,
+ 0x10090044,
+ 0x100a0200,
+ 0x100b0000,
+ 0x10380400,
+ 0x10080441,
+ 0x100804c0,
+ 0x100a0024,
+ 0x10090200,
+ 0x100b0000,
+ 0x30780000,
+ 0x38780000,
+ 0x30780000,
+ 0x10680000,
+ 0x106b0000,
+ 0x10280400,
+ 0x10480000,
+ 0x1c980000,
+ 0x1c9b0000,
+ 0x1c980008,
+ 0x1c9b0008,
+ 0x38f80000,
+ 0x3cf80000,
+ 0x38780000,
+ 0x18180000,
+ 0x18980000,
+ 0x13580000,
+ 0x135b0000,
+ 0x13580008,
+ 0x135b0008,
+ 0x33780000,
+ 0x10580008,
+ 0x10780000
+};
diff --git a/arch/arm/boards/enclustra-sa2/sequencer_auto_inst_init.c b/arch/arm/boards/enclustra-sa2/sequencer_auto_inst_init.c
new file mode 100644
index 0000000000000000000000000000000000000000..c3c79973ad412ea720fae64acbe0732dcca28f30
--- /dev/null
+++ b/arch/arm/boards/enclustra-sa2/sequencer_auto_inst_init.c
@@ -0,0 +1,158 @@
+/*
+Copyright (C) 2023 Intel Corporation. All rights reserved.
+
+SPDX-License-Identifier: BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of Intel Corporation nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+static const uint32_t inst_rom_init_size = 127;
+static const uint32_t inst_rom_init[127] = {
+ 0x80000,
+ 0x80680,
+ 0x8180,
+ 0x8200,
+ 0x8280,
+ 0x8300,
+ 0x8380,
+ 0x8100,
+ 0x8480,
+ 0x8500,
+ 0x8580,
+ 0x8600,
+ 0x8400,
+ 0x800,
+ 0x8680,
+ 0x880,
+ 0xa680,
+ 0x80680,
+ 0x900,
+ 0x80680,
+ 0x980,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xb68,
+ 0xcce8,
+ 0xae8,
+ 0x8ce8,
+ 0xb88,
+ 0xec88,
+ 0xa08,
+ 0xac88,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x60e80,
+ 0x61080,
+ 0x61080,
+ 0x61080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x70e80,
+ 0x71080,
+ 0x71080,
+ 0x71080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0x1158,
+ 0x6d8,
+ 0x80680,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0x87e8,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0xa7e8,
+ 0x80680,
+ 0x40e88,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x40f68,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0xa680,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x41008,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x1100,
+ 0xc680,
+ 0x8680,
+ 0xe680,
+ 0x80680,
+ 0x0,
+ 0x8000,
+ 0xa000,
+ 0xc000,
+ 0x80000,
+ 0x80,
+ 0x8080,
+ 0xa080,
+ 0xc080,
+ 0x80080,
+ 0x9180,
+ 0x8680,
+ 0xa680,
+ 0x80680,
+ 0x40f08,
+ 0x80680
+};
diff --git a/arch/arm/boards/enclustra-sa2/sequencer_defines.h b/arch/arm/boards/enclustra-sa2/sequencer_defines.h
new file mode 100644
index 0000000000000000000000000000000000000000..c6c5dda6fa34c4eee4063258984765b1a38594b0
--- /dev/null
+++ b/arch/arm/boards/enclustra-sa2/sequencer_defines.h
@@ -0,0 +1,165 @@
+/*
+Copyright (C) 2016 Intel Corporation
+All rights reserved.
+
+SPDX-License-Identifier: BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of Altera Corporation nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+#ifndef _SEQUENCER_DEFINES_H_
+#define _SEQUENCER_DEFINES_H_
+
+#define AC_ROM_MR1_MIRR 0000000100100
+#define AC_ROM_MR1_OCD_ENABLE
+#define AC_ROM_MR2_MIRR 0001000000000
+#define AC_ROM_MR3_MIRR 0000000000000
+#define AC_ROM_MR0_CALIB
+#define AC_ROM_MR0_DLL_RESET_MIRR 0010011000000
+#define AC_ROM_MR0_DLL_RESET 0010100100000
+#define AC_ROM_MR0_MIRR 0010001000001
+#define AC_ROM_MR0 0010000100001
+#define AC_ROM_MR1 0000001000100
+#define AC_ROM_MR2 0001000000000
+#define AC_ROM_MR3 0000000000000
+#define AC_ROM_USER_ADD_0 0_0000_0000_0000
+#define AC_ROM_USER_ADD_1 0_0000_0000_1000
+#define AFI_CLK_FREQ 401
+#define AFI_RATE_RATIO 1
+#define AP_MODE 0
+#define ARRIAVGZ 0
+#define ARRIAV 0
+#define AVL_CLK_FREQ 67
+#define BFM_MODE 0
+#define BURST2 0
+#define CALIBRATE_BIT_SLIPS 0
+#define CALIB_LFIFO_OFFSET 7
+#define CALIB_VFIFO_OFFSET 5
+#define CYCLONEV 1
+#define DDR2 0
+#define DDR3 1
+#define DDRX 1
+#define DM_PINS_ENABLED 1
+#define ENABLE_ASSERT 0
+#define ENABLE_BRINGUP_DEBUGGING 0
+#define ENABLE_DELAY_CHAIN_WRITE 0
+#define ENABLE_DQS_IN_CENTERING 1
+#define ENABLE_DQS_OUT_CENTERING 0
+#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0
+#define ENABLE_INST_ROM_WRITE 1
+#define ENABLE_MARGIN_REPORT_GEN 0
+#define ENABLE_NON_DESTRUCTIVE_CALIB 0
+#define ENABLE_NON_DES_CAL_TEST 0
+#define ENABLE_NON_DES_CAL 0
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define ENABLE_TCL_DEBUG 0
+#define FAKE_CAL_FAIL 0
+#define FIX_READ_LATENCY 8
+#define FULL_RATE 1
+#define GUARANTEED_READ_BRINGUP_TEST 0
+#define HALF_RATE 0
+#define HARD_PHY 1
+#define HARD_VFIFO 1
+#define HCX_COMPAT_MODE 0
+#define HHP_HPS_SIMULATION 0
+#define HHP_HPS_VERIFICATION 0
+#define HHP_HPS 1
+#define HPS_HW 1
+#define HR_DDIO_OUT_HAS_THREE_REGS 0
+#define IO_DELAY_PER_DCHAIN_TAP 25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
+#define IO_DELAY_PER_OPA_TAP 312
+#define IO_DLL_CHAIN_LENGTH 8
+#define IO_DM_OUT_RESERVE 0
+#define IO_DQDQS_OUT_PHASE_MAX 0
+#define IO_DQS_EN_DELAY_MAX 31
+#define IO_DQS_EN_DELAY_OFFSET 0
+#define IO_DQS_EN_PHASE_MAX 7
+#define IO_DQS_IN_DELAY_MAX 31
+#define IO_DQS_IN_RESERVE 4
+#define IO_DQS_OUT_RESERVE 4
+#define IO_DQ_OUT_RESERVE 0
+#define IO_IO_IN_DELAY_MAX 31
+#define IO_IO_OUT1_DELAY_MAX 31
+#define IO_IO_OUT2_DELAY_MAX 0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define LPDDR1 0
+#define LPDDR2 0
+#define LRDIMM 0
+#define MARGIN_VARIATION_TEST 0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define MEM_ADDR_WIDTH 13
+#define MRS_MIRROR_PING_PONG_ATSO 0
+#define MULTIPLE_AFI_WLAT 0
+#define NON_DES_CAL 0
+#define NUM_SHADOW_REGS 1
+#define QDRII 0
+#define QUARTER_RATE 0
+#define RDIMM 0
+#define READ_AFTER_WRITE_CALIBRATION 1
+#define READ_VALID_FIFO_SIZE 16
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504dd
+#define RLDRAM3 0
+#define RLDRAMII 0
+#define RLDRAMX 0
+#define RUNTIME_CAL_REPORT 0
+#define RW_MGR_MEM_ADDRESS_MIRRORING 0
+#define RW_MGR_MEM_ADDRESS_WIDTH 16
+#define RW_MGR_MEM_BANK_WIDTH 3
+#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1
+#define RW_MGR_MEM_CLK_EN_WIDTH 1
+#define RW_MGR_MEM_CONTROL_WIDTH 1
+#define RW_MGR_MEM_DATA_MASK_WIDTH 4
+#define RW_MGR_MEM_DATA_WIDTH 32
+#define RW_MGR_MEM_DQ_PER_READ_DQS 8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
+#define RW_MGR_MEM_ODT_WIDTH 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_MR0_BL 1
+#define RW_MGR_MR0_CAS_LATENCY 2
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
+#define RW_MGR_WRITE_TO_DEBUG_READ 1.0
+#define SET_FIX_READ_LATENCY_ENABLE 0
+#define SKEW_CALIBRATION 0
+#define SKIP_PTAP_0_DQS_EN_CAL 1
+#define STATIC_FULL_CALIBRATION 1
+#define STATIC_SIM_FILESET 0
+#define STATIC_SKIP_MEM_INIT 0
+#define STRATIXV 0
+#define TINIT_CNTR1_VAL 32
+#define TINIT_CNTR2_VAL 32
+#define TINIT_CNTR0_VAL 99
+#define TRACKING_ERROR_TEST 0
+#define TRACKING_WATCH_TEST 0
+#define TRESET_CNTR1_VAL 99
+#define TRESET_CNTR2_VAL 10
+#define TRESET_CNTR0_VAL 99
+#define USE_DQS_TRACKING 1
+#define USE_SHADOW_REGS 0
+#define USE_USER_RDIMM_VALUE 0
+
+#endif /* _SEQUENCER_DEFINES_H_ */
--
2.43.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 02/11] Add Enclustra Mercury+ SA2 module
2025-09-17 15:22 [PATCH 00/11] ARM: boards: add support for Enclustra Mercury SA2 David Picard
2025-09-17 15:22 ` [PATCH 01/11] Add handoff files David Picard
@ 2025-09-17 15:22 ` David Picard
2025-09-18 6:21 ` Sascha Hauer
2025-09-17 15:22 ` [PATCH 03/11] Add Enclustra devicetree files David Picard
` (8 subsequent siblings)
10 siblings, 1 reply; 30+ messages in thread
From: David Picard @ 2025-09-17 15:22 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX; +Cc: David Picard
Signed-off-by: David Picard <david.picard@clermont.in2p3.fr>
---
arch/arm/boards/Makefile | 1 +
arch/arm/boards/enclustra-sa2/Makefile | 2 ++
arch/arm/boards/enclustra-sa2/board.c | 32 +++++++++++++++++++++++++++
arch/arm/boards/enclustra-sa2/lowlevel.c | 13 +++++++++++
arch/arm/configs/socfpga-xload_defconfig | 1 +
arch/arm/configs/socfpga_defconfig | 3 +--
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_cyclone5_mercury_sa2.dts | 31 ++++++++++++++++++++++++++
arch/arm/mach-socfpga/Kconfig | 4 ++++
images/Makefile.socfpga | 8 +++++++
10 files changed, 94 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index ac1fa74d4c03de7a462746cb93a061017cd2b64d..3c3801aaae8425689f2f070321d4ec2fd38ad90a 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -118,6 +118,7 @@ obj-$(CONFIG_MACH_SEEED_ODYSSEY) += seeed-odyssey/
obj-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += altera-socdk/
obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/
obj-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1) += enclustra-aa1/
+obj-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_SA2) += enclustra-sa2/
obj-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += reflex-achilles/
obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += terasic-de0-nano-soc/
obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += terasic-de10-nano/
diff --git a/arch/arm/boards/enclustra-sa2/Makefile b/arch/arm/boards/enclustra-sa2/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..8c927fe291a6b3eb20a32a2db96c73f231ab4697
--- /dev/null
+++ b/arch/arm/boards/enclustra-sa2/Makefile
@@ -0,0 +1,2 @@
+obj-y += lowlevel.o board.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/enclustra-sa2/board.c b/arch/arm/boards/enclustra-sa2/board.c
new file mode 100644
index 0000000000000000000000000000000000000000..834d0ab91871d0329af20f89a13af65e194b21c3
--- /dev/null
+++ b/arch/arm/boards/enclustra-sa2/board.c
@@ -0,0 +1,32 @@
+#include <common.h>
+#include <types.h>
+#include <driver.h>
+#include <init.h>
+#include <asm/armlinux.h>
+#include <linux/mdio.h>
+#include <linux/micrel_phy.h>
+#include <linux/phy.h>
+#include <linux/sizes.h>
+#include <fcntl.h>
+#include <fs.h>
+#include <mach/socfpga/cyclone5-regs.h>
+
+/*
+ * Ethernet PHY: Microchip/Micrel KSZ9031RNX
+ */
+static int phy_fixup(struct phy_device *dev)
+{
+ return 0;
+}
+
+static int socfpga_init(void)
+{
+ if (!of_machine_is_compatible("altr,socfpga-cyclone5"))
+ return 0;
+
+ if (IS_ENABLED(CONFIG_PHYLIB))
+ phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, phy_fixup);
+
+ return 0;
+}
+console_initcall(socfpga_init);
diff --git a/arch/arm/boards/enclustra-sa2/lowlevel.c b/arch/arm/boards/enclustra-sa2/lowlevel.c
new file mode 100644
index 0000000000000000000000000000000000000000..a5065a4d89a82e7c048879488c9f441d32556f00
--- /dev/null
+++ b/arch/arm/boards/enclustra-sa2/lowlevel.c
@@ -0,0 +1,13 @@
+#include "sdram_config.h"
+#include "pinmux_config.c"
+#include "pll_config.h"
+#include "sequencer_defines.h"
+#include "sequencer_auto.h"
+#include "sequencer_auto_inst_init.c"
+#include "sequencer_auto_ac_init.c"
+#include "iocsr_config_cyclone5.c"
+
+#include <mach/socfpga/lowlevel.h>
+
+SOCFPGA_C5_ENTRY(start_socfpga_sa2, socfpga_cyclone5_mercury_sa2, SZ_1G);
+SOCFPGA_C5_XLOAD_ENTRY(start_socfpga_sa2_xload, SZ_1G);
diff --git a/arch/arm/configs/socfpga-xload_defconfig b/arch/arm/configs/socfpga-xload_defconfig
index 37e9ecec71876d6e6596faf0d4faf1ab9fa1c466..039196d4954ee32401c269a58d92e6c5cba602ed 100644
--- a/arch/arm/configs/socfpga-xload_defconfig
+++ b/arch/arm/configs/socfpga-xload_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARCH_SOCFPGA=y
CONFIG_ARCH_SOCFPGA_XLOAD=y
CONFIG_MACH_SOCFPGA_ALTERA_SOCDK=y
CONFIG_MACH_SOCFPGA_EBV_SOCRATES=y
+CONFIG_MACH_SOCFPGA_ENCLUSTRA_SA2=y
CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC=y
CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO=y
CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT=y
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index 0050dd2e4f4e4ae485e3cb0ca1f37ead0b947189..20d323017891531ad7a9f47b5dcf1334fd3534d8 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -1,8 +1,7 @@
CONFIG_ARCH_SOCFPGA=y
CONFIG_MACH_SOCFPGA_ALTERA_SOCDK=y
CONFIG_MACH_SOCFPGA_EBV_SOCRATES=y
-CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1=y
-CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES=y
+CONFIG_MACH_SOCFPGA_ENCLUSTRA_SA2=y
CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC=y
CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO=y
CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6612a514523103fdaaae026527f3441ebc57d228..5f624ea6f95fb15970bd6fe4b36515ff360544a3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -141,6 +141,7 @@ lwl-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o
lwl-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += socfpga_cyclone5_socdk.dtb.o
lwl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o
lwl-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1) += socfpga_arria10_mercury_aa1.dtb.o
+lwl-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_SA2) += socfpga_cyclone5_mercury_sa2.dtb.o
lwl-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += socfpga_arria10_achilles.dtb.o
lwl-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += socfpga_cyclone5_de0_nano_soc.dtb.o
lwl-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += socfpga_cyclone5_de10_nano.dtb.o
diff --git a/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dts b/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dts
new file mode 100644
index 0000000000000000000000000000000000000000..9e2f2c1af19e68c0c662f62bc154856f75df2510
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dts
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2025 David Picard <david.picard@clermont.in2p3.fr>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <arm/intel/socfpga/socfpga_cyclone5_mercury_sa2.dts>
+#include "socfpga.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart0;
+
+ environment {
+ compatible = "barebox,environment";
+ device-path = &mmc, "partname:1";
+ file-path = "barebox.env";
+ };
+ };
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 4ec376056db8c07ad1d73041b079cde2cfeb9a17..a4f859ebf3d7956697d180e15f50b3495cd4c472 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -34,6 +34,10 @@ config MACH_SOCFPGA_ENCLUSTRA_AA1
select ARCH_SOCFPGA_ARRIA10
bool "Enclustra AA1"
+config MACH_SOCFPGA_ENCLUSTRA_SA2
+ select ARCH_SOCFPGA_CYCLONE5
+ bool "Enclustra SA2"
+
config MACH_SOCFPGA_REFLEX_ACHILLES
select ARCH_SOCFPGA_ARRIA10
bool "Reflex Achilles"
diff --git a/images/Makefile.socfpga b/images/Makefile.socfpga
index 7f95bed03297e616532ffb38cb36742b155146f5..e4c96801bee69910f7ce5e77ccdd3ac2766e1926 100644
--- a/images/Makefile.socfpga
+++ b/images/Makefile.socfpga
@@ -51,6 +51,14 @@ pblb-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1) += start_socfpga_aa1_bringup
FILE_barebox-socfpga-aa1-bringup.img = start_socfpga_aa1_bringup.pblb
socfpga-barebox-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1) += barebox-socfpga-aa1-bringup.img
+pblb-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_SA2) += start_socfpga_sa2_xload
+FILE_barebox-socfpga-sa2-xload.img = start_socfpga_sa2_xload.pblb.socfpgaimg
+socfpga-xload-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_SA2) += barebox-socfpga-sa2-xload.img
+
+pblb-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_SA2) += start_socfpga_sa2
+FILE_barebox-socfpga-sa2.img = start_socfpga_sa2.pblb
+socfpga-barebox-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_SA2) += barebox-socfpga-sa2.img
+
pblb-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += start_socfpga_achilles_xload
FILE_barebox-socfpga-achilles-xload.img = start_socfpga_achilles_xload.pblb.socfpgaimg
socfpga-barebox-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += barebox-socfpga-achilles-xload.img
--
2.43.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 02/11] Add Enclustra Mercury+ SA2 module
2025-09-17 15:22 ` [PATCH 02/11] Add Enclustra Mercury+ SA2 module David Picard
@ 2025-09-18 6:21 ` Sascha Hauer
0 siblings, 0 replies; 30+ messages in thread
From: Sascha Hauer @ 2025-09-18 6:21 UTC (permalink / raw)
To: David Picard; +Cc: BAREBOX
On Wed, Sep 17, 2025 at 05:22:05PM +0200, David Picard wrote:
> Signed-off-by: David Picard <david.picard@clermont.in2p3.fr>
> ---
> arch/arm/boards/Makefile | 1 +
> arch/arm/boards/enclustra-sa2/Makefile | 2 ++
> arch/arm/boards/enclustra-sa2/board.c | 32 +++++++++++++++++++++++++++
> arch/arm/boards/enclustra-sa2/lowlevel.c | 13 +++++++++++
> arch/arm/configs/socfpga-xload_defconfig | 1 +
> arch/arm/configs/socfpga_defconfig | 3 +--
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/socfpga_cyclone5_mercury_sa2.dts | 31 ++++++++++++++++++++++++++
> arch/arm/mach-socfpga/Kconfig | 4 ++++
> images/Makefile.socfpga | 8 +++++++
> 10 files changed, 94 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
> index ac1fa74d4c03de7a462746cb93a061017cd2b64d..3c3801aaae8425689f2f070321d4ec2fd38ad90a 100644
> --- a/arch/arm/boards/Makefile
> +++ b/arch/arm/boards/Makefile
> @@ -118,6 +118,7 @@ obj-$(CONFIG_MACH_SEEED_ODYSSEY) += seeed-odyssey/
> obj-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += altera-socdk/
> obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/
> obj-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1) += enclustra-aa1/
> +obj-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_SA2) += enclustra-sa2/
> obj-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += reflex-achilles/
> obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += terasic-de0-nano-soc/
> obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += terasic-de10-nano/
> diff --git a/arch/arm/boards/enclustra-sa2/Makefile b/arch/arm/boards/enclustra-sa2/Makefile
> new file mode 100644
> index 0000000000000000000000000000000000000000..8c927fe291a6b3eb20a32a2db96c73f231ab4697
> --- /dev/null
> +++ b/arch/arm/boards/enclustra-sa2/Makefile
> @@ -0,0 +1,2 @@
> +obj-y += lowlevel.o board.o
> +pbl-y += lowlevel.o
> diff --git a/arch/arm/boards/enclustra-sa2/board.c b/arch/arm/boards/enclustra-sa2/board.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..834d0ab91871d0329af20f89a13af65e194b21c3
> --- /dev/null
> +++ b/arch/arm/boards/enclustra-sa2/board.c
> @@ -0,0 +1,32 @@
> +#include <common.h>
> +#include <types.h>
> +#include <driver.h>
> +#include <init.h>
> +#include <asm/armlinux.h>
> +#include <linux/mdio.h>
> +#include <linux/micrel_phy.h>
> +#include <linux/phy.h>
> +#include <linux/sizes.h>
> +#include <fcntl.h>
> +#include <fs.h>
> +#include <mach/socfpga/cyclone5-regs.h>
> +
> +/*
> + * Ethernet PHY: Microchip/Micrel KSZ9031RNX
> + */
> +static int phy_fixup(struct phy_device *dev)
> +{
> + return 0;
> +}
> +
> +static int socfpga_init(void)
> +{
> + if (!of_machine_is_compatible("altr,socfpga-cyclone5"))
> + return 0;
This is too broad and fixed later in this series. Please start with the
correct compatible here instead of fixing it later.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 03/11] Add Enclustra devicetree files
2025-09-17 15:22 [PATCH 00/11] ARM: boards: add support for Enclustra Mercury SA2 David Picard
2025-09-17 15:22 ` [PATCH 01/11] Add handoff files David Picard
2025-09-17 15:22 ` [PATCH 02/11] Add Enclustra Mercury+ SA2 module David Picard
@ 2025-09-17 15:22 ` David Picard
2025-09-17 15:22 ` [PATCH 04/11] ARM: dts: socfpga: use upstream SA2 device tree David Picard
` (7 subsequent siblings)
10 siblings, 0 replies; 30+ messages in thread
From: David Picard @ 2025-09-17 15:22 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX; +Cc: David Picard
Copied from Enclustra's BSP
Signed-off-by: David Picard <david.picard@clermont.in2p3.fr>
---
dts/src/arm/intel/socfpga/skeleton.dtsi | 13 +
.../intel/socfpga/socfpga_cyclone5_enclustra.dtsi | 69 ++
.../intel/socfpga/socfpga_cyclone5_mercury_sa2.dts | 128 +++
dts/src/arm/intel/socfpga/socfpga_enclustra.dtsi | 971 +++++++++++++++++++++
4 files changed, 1181 insertions(+)
diff --git a/dts/src/arm/intel/socfpga/skeleton.dtsi b/dts/src/arm/intel/socfpga/skeleton.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..b41d241de2cde0ccf022134519e9f9d3ae4261a4
--- /dev/null
+++ b/dts/src/arm/intel/socfpga/skeleton.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Skeleton device tree; the bare minimum needed to boot; just include and
+ * add a compatible value. The bootloader will typically populate the memory
+ * node.
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chosen { };
+ aliases { };
+ memory { device_type = "memory"; reg = <0 0>; };
+};
diff --git a/dts/src/arm/intel/socfpga/socfpga_cyclone5_enclustra.dtsi b/dts/src/arm/intel/socfpga/socfpga_cyclone5_enclustra.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..9ea1b76f1d55b28fd162231144bcb537a111c53f
--- /dev/null
+++ b/dts/src/arm/intel/socfpga/socfpga_cyclone5_enclustra.dtsi
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+/* First 4KB has trampoline code for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
+#include "socfpga_enclustra.dtsi"
+
+/ {
+ soc {
+ clkmgr@ffd04000 {
+ clocks {
+ osc1 {
+ clock-frequency = <50000000>;
+ };
+ };
+ };
+
+ mmc0: dwmmc0@ff704000 {
+ num-slots = <1>;
+ broken-cd;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ };
+
+ ethernet@ff702000 {
+ phy-mode = "rgmii";
+ phy-addr = <0xffffffff>; /* probe for phy addr */
+ status = "okay";
+ };
+
+ sysmgr@ffd08000 {
+ cpu1-start-addr = <0xffd080c4>;
+ };
+ };
+};
+
+&watchdog0 {
+ status = "okay";
+};
+
+&i2c0 {
+ /* Both RTCs disabled by default, choose one */
+ pcf85063: pcf85063@51 {
+ status = "disabled";
+ compatible = "nxp,pcf85063";
+ reg = <0x51>;
+ };
+ isl12022: isl12022@68 {
+ status = "disabled";
+ compatible = "isil,isl12022";
+ reg = <0x6f>;
+ };
+};
diff --git a/dts/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2.dts b/dts/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2.dts
new file mode 100644
index 0000000000000000000000000000000000000000..cc55bf8f575433046915d3f33aaf789861d13b1a
--- /dev/null
+++ b/dts/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2.dts
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "socfpga_cyclone5_enclustra.dtsi"
+
+/ {
+ model = "Enclustra Mercury SA2 SOM";
+ compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+
+ aliases {
+ /* this allow the ethaddr uboot environmnet variable contents
+ * to be added to the gmac1 device tree blob.
+ */
+ ethernet0 = &gmac1;
+ };
+
+ regulator_3_3v: vcc3p3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&gmac1 {
+ status = "okay";
+ phy-mode = "rgmii";
+
+ rxd0-skew-ps = <0>;
+ rxd1-skew-ps = <0>;
+ rxd2-skew-ps = <0>;
+ rxd3-skew-ps = <0>;
+ txen-skew-ps = <0>;
+ txc-skew-ps = <2600>;
+ rxdv-skew-ps = <0>;
+ rxc-skew-ps = <2000>;
+
+ phy-handle = <&phy3>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®ulator_3_3v>;
+ vqmmc-supply = <®ulator_3_3v>;
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+
+ flash0: n25q00@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ m25p,fast-read;
+ cdns,read-delay = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+
+ part0: partition@0 {
+ label = "Flash 0 Raw Data";
+ reg = < 0x00000000 0x01000000 >;
+ };
+
+ part1: partition@800000 {
+ label = "Flash 1 jffs2 Filesystem";
+ reg = < 0x01000000 0x03000000 >;
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&isl12022 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ spidev@0 {
+ compatible = "spidev";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
diff --git a/dts/src/arm/intel/socfpga/socfpga_enclustra.dtsi b/dts/src/arm/intel/socfpga/socfpga_enclustra.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..a5ccc1933a7ed851effc4844a2e22f55d58c6905
--- /dev/null
+++ b/dts/src/arm/intel/socfpga/socfpga_enclustra.dtsi
@@ -0,0 +1,971 @@
+/*
+ * Copyright (C) 2012 Altera <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/reset/altr,rst-mgr.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ timer0 = &timer0;
+ timer1 = &timer1;
+ timer2 = &timer2;
+ timer3 = &timer3;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "altr,socfpga-smp";
+
+ cpu@0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+ cpu@1 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ intc: intc@fffed000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xfffed000 0x1000>,
+ <0xfffec100 0x100>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ device_type = "soc";
+ interrupt-parent = <&intc>;
+ ranges;
+
+ amba {
+ compatible = "arm,amba-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pdma: pdma@ffe01000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0xffe01000 0x1000>;
+ interrupts = <0 104 4>,
+ <0 105 4>,
+ <0 106 4>,
+ <0 107 4>,
+ <0 108 4>,
+ <0 109 4>,
+ <0 110 4>,
+ <0 111 4>;
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ clocks = <&l4_main_clk>;
+ clock-names = "apb_pclk";
+ };
+ };
+
+ can0: can@ffc00000 {
+ compatible = "bosch,d_can";
+ reg = <0xffc00000 0x1000>;
+ interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
+ clocks = <&can0_clk>;
+ status = "disabled";
+ };
+
+ can1: can@ffc01000 {
+ compatible = "bosch,d_can";
+ reg = <0xffc01000 0x1000>;
+ interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
+ clocks = <&can1_clk>;
+ status = "disabled";
+ };
+
+ clkmgr@ffd04000 {
+ compatible = "altr,clk-mgr";
+ reg = <0xffd04000 0x1000>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ osc1: osc1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ osc2: osc2 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ f2s_periph_ref_clk: f2s_periph_ref_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ f2s_sdram_ref_clk: f2s_sdram_ref_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ main_pll: main_pll {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-pll-clock";
+ clocks = <&osc1>;
+ reg = <0x40>;
+
+ mpuclk: mpuclk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&main_pll>;
+ div-reg = <0xe0 0 9>;
+ reg = <0x48>;
+ };
+
+ mainclk: mainclk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&main_pll>;
+ div-reg = <0xe4 0 9>;
+ reg = <0x4C>;
+ };
+
+ dbg_base_clk: dbg_base_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&main_pll>, <&osc1>;
+ div-reg = <0xe8 0 9>;
+ reg = <0x50>;
+ };
+
+ main_qspi_clk: main_qspi_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x54>;
+ };
+
+ main_nand_sdmmc_clk: main_nand_sdmmc_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x58>;
+ };
+
+ cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x5C>;
+ };
+ };
+
+ periph_pll: periph_pll {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-pll-clock";
+ clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
+ reg = <0x80>;
+
+ emac0_clk: emac0_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0x88>;
+ };
+
+ emac1_clk: emac1_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0x8C>;
+ };
+
+ per_qspi_clk: per_qsi_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0x90>;
+ };
+
+ per_nand_mmc_clk: per_nand_mmc_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0x94>;
+ };
+
+ per_base_clk: per_base_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0x98>;
+ };
+
+ h2f_usr1_clk: h2f_usr1_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0x9C>;
+ };
+ };
+
+ sdram_pll: sdram_pll {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-pll-clock";
+ clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
+ reg = <0xC0>;
+
+ ddr_dqs_clk: ddr_dqs_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&sdram_pll>;
+ reg = <0xC8>;
+ };
+
+ ddr_2x_dqs_clk: ddr_2x_dqs_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&sdram_pll>;
+ reg = <0xCC>;
+ };
+
+ ddr_dq_clk: ddr_dq_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&sdram_pll>;
+ reg = <0xD0>;
+ };
+
+ h2f_usr2_clk: h2f_usr2_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&sdram_pll>;
+ reg = <0xD4>;
+ };
+ };
+
+ mpu_periph_clk: mpu_periph_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&mpuclk>;
+ fixed-divider = <4>;
+ };
+
+ mpu_l2_ram_clk: mpu_l2_ram_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&mpuclk>;
+ fixed-divider = <2>;
+ };
+
+ l4_main_clk: l4_main_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&mainclk>;
+ clk-gate = <0x60 0>;
+ };
+
+ l3_main_clk: l3_main_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&mainclk>;
+ fixed-divider = <1>;
+ };
+
+ l3_mp_clk: l3_mp_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&mainclk>;
+ div-reg = <0x64 0 2>;
+ clk-gate = <0x60 1>;
+ };
+
+ l3_sp_clk: l3_sp_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&l3_mp_clk>;
+ div-reg = <0x64 2 2>;
+ };
+
+ l4_mp_clk: l4_mp_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&mainclk>, <&per_base_clk>;
+ div-reg = <0x64 4 3>;
+ clk-gate = <0x60 2>;
+ };
+
+ l4_sp_clk: l4_sp_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&mainclk>, <&per_base_clk>;
+ div-reg = <0x64 7 3>;
+ clk-gate = <0x60 3>;
+ };
+
+ dbg_at_clk: dbg_at_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&dbg_base_clk>;
+ div-reg = <0x68 0 2>;
+ clk-gate = <0x60 4>;
+ };
+
+ dbg_clk: dbg_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&dbg_at_clk>;
+ div-reg = <0x68 2 2>;
+ clk-gate = <0x60 5>;
+ };
+
+ dbg_trace_clk: dbg_trace_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&dbg_base_clk>;
+ div-reg = <0x6C 0 3>;
+ clk-gate = <0x60 6>;
+ };
+
+ dbg_timer_clk: dbg_timer_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&dbg_base_clk>;
+ clk-gate = <0x60 7>;
+ };
+
+ cfg_clk: cfg_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&cfg_h2f_usr0_clk>;
+ clk-gate = <0x60 8>;
+ };
+
+ h2f_user0_clk: h2f_user0_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&cfg_h2f_usr0_clk>;
+ clk-gate = <0x60 9>;
+ };
+
+ emac_0_clk: emac_0_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&emac0_clk>;
+ clk-gate = <0xa0 0>;
+ };
+
+ emac_1_clk: emac_1_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&emac1_clk>;
+ clk-gate = <0xa0 1>;
+ };
+
+ usb_mp_clk: usb_mp_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&per_base_clk>;
+ clk-gate = <0xa0 2>;
+ div-reg = <0xa4 0 3>;
+ };
+
+ spi_m_clk: spi_m_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&per_base_clk>;
+ clk-gate = <0xa0 3>;
+ div-reg = <0xa4 3 3>;
+ };
+
+ can0_clk: can0_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&per_base_clk>;
+ clk-gate = <0xa0 4>;
+ div-reg = <0xa4 6 3>;
+ };
+
+ can1_clk: can1_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&per_base_clk>;
+ clk-gate = <0xa0 5>;
+ div-reg = <0xa4 9 3>;
+ };
+
+ gpio_db_clk: gpio_db_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&per_base_clk>;
+ clk-gate = <0xa0 6>;
+ div-reg = <0xa8 0 24>;
+ };
+
+ h2f_user1_clk: h2f_user1_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&h2f_usr1_clk>;
+ clk-gate = <0xa0 7>;
+ };
+
+ sdmmc_clk: sdmmc_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+ clk-gate = <0xa0 8>;
+ clk-phase = <0 135>;
+ };
+
+ sdmmc_clk_divided: sdmmc_clk_divided {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&sdmmc_clk>;
+ clk-gate = <0xa0 8>;
+ fixed-divider = <4>;
+ };
+
+ nand_x_clk: nand_x_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+ clk-gate = <0xa0 9>;
+ };
+
+ nand_clk: nand_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+ clk-gate = <0xa0 10>;
+ fixed-divider = <4>;
+ };
+
+ qspi_clk: qspi_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
+ clk-gate = <0xa0 11>;
+ fixed-divider = <2>;
+ };
+
+ ddr_dqs_clk_gate: ddr_dqs_clk_gate {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&ddr_dqs_clk>;
+ clk-gate = <0xd8 0>;
+ };
+
+ ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&ddr_2x_dqs_clk>;
+ clk-gate = <0xd8 1>;
+ };
+
+ ddr_dq_clk_gate: ddr_dq_clk_gate {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&ddr_dq_clk>;
+ clk-gate = <0xd8 2>;
+ };
+
+ h2f_user2_clk: h2f_user2_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&h2f_usr2_clk>;
+ clk-gate = <0xd8 3>;
+ };
+
+ };
+ };
+
+ gmac0: ethernet@ff700000 {
+ compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+ altr,sysmgr-syscon = <&sysmgr 0x60 0>;
+ reg = <0xff700000 0x2000>;
+ interrupts = <0 115 4>;
+ interrupt-names = "macirq";
+ mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+ clocks = <&emac0_clk>;
+ clock-names = "stmmaceth";
+ resets = <&rst EMAC0_RESET>;
+ reset-names = "stmmaceth";
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <128>;
+ tx-fifo-depth = <4096>;
+ rx-fifo-depth = <4096>;
+ status = "disabled";
+ };
+
+ gmac1: ethernet@ff702000 {
+ compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+ altr,sysmgr-syscon = <&sysmgr 0x60 2>;
+ reg = <0xff702000 0x2000>;
+ interrupts = <0 120 4>;
+ interrupt-names = "macirq";
+ mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+ clocks = <&emac1_clk>;
+ clock-names = "stmmaceth";
+ resets = <&rst EMAC1_RESET>;
+ reset-names = "stmmaceth";
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <128>;
+ tx-fifo-depth = <4096>;
+ rx-fifo-depth = <4096>;
+ status = "disabled";
+ };
+
+ hps_0_fpgamgr: fpgamgr@0xff706000 {
+ compatible = "altr,fpga-mgr-1.0", "altr,fpga-mgr";
+ transport = "mmio";
+ reg = <0xFF706000 0x1000
+ 0xFFB90000 0x1000>;
+ interrupts = <0 175 4>;
+ };
+
+ hps_fpgabridge0: fpgabridge@0 {
+ compatible = "altr,socfpga-hps2fpga-bridge";
+ label = "hps2fpga";
+ resets = <&rst HPS2FPGA_RESET>;
+ reset-names = "hps2fpga";
+ clocks = <&l4_main_clk>;
+ };
+
+ hps_fpgabridge1: fpgabridge@1 {
+ compatible = "altr,socfpga-lwhps2fpga-bridge";
+ label = "lwhps2fpga";
+ resets = <&rst LWHPS2FPGA_RESET>;
+ reset-names = "lwhps2fpga";
+ clocks = <&l4_main_clk>;
+ };
+
+ hps_fpgabridge2: fpgabridge@2 {
+ compatible = "altr,socfpga-fpga2hps-bridge";
+ label = "fpga2hps";
+ resets = <&rst FPGA2HPS_RESET>;
+ reset-names = "fpga2hps";
+ clocks = <&l4_main_clk>;
+ };
+
+ i2c0: i2c@ffc04000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc04000 0x1000>;
+ clocks = <&l4_sp_clk>;
+ interrupts = <0 158 0x4>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@ffc05000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc05000 0x1000>;
+ clocks = <&l4_sp_clk>;
+ interrupts = <0 159 0x4>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@ffc06000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc06000 0x1000>;
+ clocks = <&l4_sp_clk>;
+ interrupts = <0 160 0x4>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@ffc07000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc07000 0x1000>;
+ clocks = <&l4_sp_clk>;
+ interrupts = <0 161 0x4>;
+ status = "disabled";
+ };
+
+ gpio0: gpio@ff708000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff708000 0x1000>;
+ clocks = <&l4_mp_clk>;
+ status = "disabled";
+
+ porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <29>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 164 4>;
+ };
+ };
+
+ gpio1: gpio@ff709000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff709000 0x1000>;
+ clocks = <&l4_mp_clk>;
+ status = "disabled";
+
+ portb: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <29>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 165 4>;
+ };
+ };
+
+ gpio2: gpio@ff70a000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff70a000 0x1000>;
+ clocks = <&l4_mp_clk>;
+ status = "disabled";
+
+ portc: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <27>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 166 4>;
+ };
+ };
+
+ sdr: sdr@ffc25000 {
+ compatible = "syscon";
+ reg = <0xffc25000 0x1000>;
+ };
+
+ sdramedac {
+ compatible = "altr,sdram-edac";
+ altr,sdr-syscon = <&sdr>;
+ interrupts = <0 39 4>;
+ };
+
+ L2: l2-cache@fffef000 {
+ compatible = "arm,pl310-cache", "syscon";
+ reg = <0xfffef000 0x1000>;
+ interrupts = <0 38 0x04>;
+ cache-unified;
+ cache-level = <2>;
+ arm,tag-latency = <1 1 1>;
+ arm,data-latency = <2 1 1>;
+ prefetch-data = <1>;
+ prefetch-instr = <1>;
+ };
+
+ mmc: dwmmc0@ff704000 {
+ compatible = "altr,socfpga-dw-mshc";
+ reg = <0xff704000 0x1000>;
+ interrupts = <0 139 4>;
+ fifo-depth = <0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
+ clock-names = "biu", "ciu";
+ };
+
+ nand: nand@ff900000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "denali,denali-nand-dt";
+ reg = <0xff900000 0x100000>, <0xffb80000 0x10000>;
+ reg-names = "nand_data", "denali_reg";
+ interrupts = <0 144 4>;
+ dma-mask = <0xffffffff>;
+ clocks = <&nand_clk>;
+ have-hw-ecc-fixup;
+ status = "disabled";
+
+ partition@nand-boot {
+ /* 8MB for raw data. */
+ label = "NAND Flash Boot Area 8MB";
+ reg = <0x0 0x800000>;
+ };
+ partition@nand-rootfs {
+ /* 128MB jffs2 root filesystem. */
+ label = "NAND Flash jffs2 Root Filesystem 128MB";
+ reg = <0x800000 0x8000000>;
+ };
+ partition@nand-128 {
+ label = "NAND Flash 128 MB";
+ reg = <0x8800000 0x8000000>;
+ };
+ partition@nand-64 {
+ label = "NAND Flash 64 MB";
+ reg = <0x10800000 0x4000000>;
+ };
+ partition@nand-32 {
+ label = "NAND Flash 32 MB";
+ reg = <0x14800000 0x2000000>;
+ };
+ partition@nand-16 {
+ label = "NAND Flash 16 MB";
+ reg = <0x16800000 0x1000000>;
+ };
+ };
+
+ ocram: sram@ffff0000 {
+ compatible = "mmio-sram";
+ reg = <0xffff0000 0x10000>;
+ };
+
+ pmu {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <0 176 4>, <0 177 4>;
+ ranges;
+
+ cti0: cti0@ff118000 {
+ compatible = "arm,coresight-cti";
+ reg = <0xff118000 0x100>;
+ };
+
+ cti1: cti1@ff119000 {
+ compatible = "arm,coresight-cti";
+ reg = <0xff119000 0x100>;
+ };
+ };
+
+ sdrctl@0xffc25000 {
+ compatible = "altr,sdr-ctl", "syscon";
+ reg = <0xffc25000 0x1000>;
+ };
+
+ l2edac@xffd08140 {
+ compatible = "altr,l2-edac";
+ reg = <0xffd08140 0x4>;
+ interrupts = <0 36 1>, <0 37 1>;
+ };
+
+ ocramedac@ffd08144 {
+ compatible = "altr,ocram-edac";
+ reg = <0xffd08144 0x4>;
+ iram = <&ocram>;
+ interrupts = <0 178 1>, <0 179 1>;
+ };
+
+ l3regs@0xff800000 {
+ compatible = "altr,l3regs", "syscon";
+ reg = <0xff800000 0x1000>;
+ };
+
+ qspi: spi@ff705000 {
+ compatible = "cdns,qspi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xff705000 0x1000>,
+ <0xffa00000 0x1000>;
+ interrupts = <0 151 4>;
+ clocks = <&qspi_clk>;
+ is-decoded-cs = <1>;
+ fifo-depth = <128>;
+ status = "disabled";
+ m25p,fast-read;
+ };
+
+ spi0: spi@fff00000 {
+ compatible = "snps,dw-apb-ssi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfff00000 0x1000>;
+ interrupts = <0 154 4>;
+ num-cs = <4>;
+ tx-dma-channel = <&pdma 16>;
+ rx-dma-channel = <&pdma 17>;
+ clocks = <&per_base_clk>;
+ status = "disabled";
+ };
+
+ scu: snoop-control-unit@fffec000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0xfffec000 0x100>;
+ };
+
+ spi1: spi@fff01000 {
+ compatible = "snps,dw-apb-ssi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfff01000 0x1000>;
+ interrupts = <0 155 4>;
+ num-cs = <4>;
+ tx-dma-channel = <&pdma 20>;
+ rx-dma-channel = <&pdma 21>;
+ clocks = <&per_base_clk>;
+ status = "disabled";
+ };
+
+ /* Local timer */
+ timer@fffec600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0xfffec600 0x100>;
+ interrupts = <1 13 0xf04>;
+ clocks = <&mpu_periph_clk>;
+ };
+
+ timer0: timer0@ffc08000 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 167 4>;
+ reg = <0xffc08000 0x1000>;
+ clocks = <&l4_sp_clk>;
+ clock-names = "timer";
+ };
+
+ timer1: timer1@ffc09000 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 168 4>;
+ reg = <0xffc09000 0x1000>;
+ clocks = <&l4_sp_clk>;
+ clock-names = "timer";
+ };
+
+ timer2: timer2@ffd00000 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 169 4>;
+ reg = <0xffd00000 0x1000>;
+ clocks = <&osc1>;
+ clock-names = "timer";
+ };
+
+ timer3: timer3@ffd01000 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 170 4>;
+ reg = <0xffd01000 0x1000>;
+ clocks = <&osc1>;
+ clock-names = "timer";
+ };
+
+ uart0: serial0@ffc02000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xffc02000 0x1000>;
+ interrupts = <0 162 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ /*clocks = <&l4_sp_clk>;*/
+ clock-frequency = <100000000>;
+ dmas = <&pdma 28>,
+ <&pdma 29>;
+ dma-names = "tx", "rx";
+ };
+
+ uart1: serial1@ffc03000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xffc03000 0x1000>;
+ interrupts = <0 163 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&l4_sp_clk>;
+ dmas = <&pdma 30>,
+ <&pdma 31>;
+ dma-names = "tx", "rx";
+ };
+
+ rst: rstmgr@ffd05000 {
+ #reset-cells = <1>;
+ compatible = "altr,rst-mgr";
+ reg = <0xffd05000 0x1000>;
+ altr,modrst-offset = <0x10>;
+ };
+
+ usbphy0: usbphy@0 {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ status = "okay";
+ };
+
+ usb0: usb@ffb00000 {
+ compatible = "snps,dwc2";
+ reg = <0xffb00000 0xffff>;
+ interrupts = <0 125 4>;
+ clocks = <&usb_mp_clk>;
+ clock-names = "otg";
+ phys = <&usbphy0>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ usb1: usb@ffb40000 {
+ compatible = "snps,dwc2";
+ reg = <0xffb40000 0xffff>;
+ interrupts = <0 128 4>;
+ clocks = <&usb_mp_clk>;
+ clock-names = "otg";
+ phys = <&usbphy0>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ watchdog0: watchdog@ffd02000 {
+ compatible = "snps,dw-wdt";
+ reg = <0xffd02000 0x1000>;
+ interrupts = <0 171 4>;
+ clocks = <&osc1>;
+ status = "disabled";
+ };
+
+ watchdog1: watchdog@ffd03000 {
+ compatible = "snps,dw-wdt";
+ reg = <0xffd03000 0x1000>;
+ interrupts = <0 172 4>;
+ clocks = <&osc1>;
+ status = "disabled";
+ };
+
+ sysmgr: sysmgr@ffd08000 {
+ compatible = "altr,sys-mgr", "syscon";
+ reg = <0xffd08000 0x4000>;
+ };
+ };
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 04/11] ARM: dts: socfpga: use upstream SA2 device tree
2025-09-17 15:22 [PATCH 00/11] ARM: boards: add support for Enclustra Mercury SA2 David Picard
` (2 preceding siblings ...)
2025-09-17 15:22 ` [PATCH 03/11] Add Enclustra devicetree files David Picard
@ 2025-09-17 15:22 ` David Picard
2025-09-18 6:32 ` Sascha Hauer
2025-09-17 15:22 ` [PATCH 05/11] ARM: dts: socfpga: adapt " David Picard
` (6 subsequent siblings)
10 siblings, 1 reply; 30+ messages in thread
From: David Picard @ 2025-09-17 15:22 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX; +Cc: David Picard, Ahmad Fatoum
From: Ahmad Fatoum <ahmad@a3f.at>
The device trees from the Enclustra BSP are outdated and not compatible
with what barebox expects. Drop them and use the upstream SoC device
tree imported from Linux instead. For the board itself, we import the
device tree in the most recent posting[1] to the kernel mailing lists.
[1]: https://lore.kernel.org/all/20241116131025.114542-1-l.rubusch@gmail.com/
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
---
arch/arm/dts/socfpga_cyclone5_mercury_sa2.dts | 18 +-
arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi | 150 ++++
dts/src/arm/intel/socfpga/skeleton.dtsi | 13 -
.../intel/socfpga/socfpga_cyclone5_enclustra.dtsi | 69 --
.../intel/socfpga/socfpga_cyclone5_mercury_sa2.dts | 128 ---
dts/src/arm/intel/socfpga/socfpga_enclustra.dtsi | 971 ---------------------
6 files changed, 152 insertions(+), 1197 deletions(-)
diff --git a/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dts b/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dts
index 9e2f2c1af19e68c0c662f62bc154856f75df2510..2e69f33b030a144d08d55eacb01fd69b009f38e8 100644
--- a/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dts
+++ b/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dts
@@ -1,27 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2025 David Picard <david.picard@clermont.in2p3.fr>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include <arm/intel/socfpga/socfpga_cyclone5_mercury_sa2.dts>
+#include "socfpga_cyclone5_mercury_sa2.dtsi"
#include "socfpga.dtsi"
/ {
chosen {
- stdout-path = &uart0;
-
environment {
compatible = "barebox,environment";
device-path = &mmc, "partname:1";
diff --git a/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi b/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..73bd75fcf224fbf31fce27dda6566d4bfe37d624
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ *
+ * TODO: This whole file should be dropped, once the patches[1] are upstream
+ * and synced into barebox dts/src/arm.
+ * [1]: https://lore.kernel.org/all/20241116131025.114542-1-l.rubusch@gmail.com/
+ */
+
+#include <arm/intel/socfpga/socfpga_cyclone5.dtsi>
+
+/ {
+ model = "Enclustra Mercury+ SA2";
+ compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ ethernet0 = &gmac1;
+ };
+
+ /* Adjusted the i2c labels to use generic base-board dtsi files for
+ * Enclustra Arria10 and Cyclone5 SoMs.
+ *
+ * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in
+ * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi
+ * fragments. Thus define generic labels here to match the correct i2c
+ * bus in a generic base-board .dtsi file.
+ */
+ soc {
+ i2c_encl: i2c@ffc04000 {
+ };
+ i2c_encl_fpga: i2c@ffc05000 {
+ };
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x80000000>; /* 2GB */
+ };
+};
+
+&osc1 {
+ clock-frequency = <50000000>;
+};
+
+&i2c_encl {
+ i2c-sda-hold-time-ns = <300>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ isl12020: rtc@6f {
+ compatible = "isil,isl12022";
+ reg = <0x6f>;
+ };
+
+ atsha204a: crypto@64 {
+ compatible = "atmel,atsha204a";
+ reg = <0x64>;
+ };
+};
+
+&i2c_encl_fpga {
+ i2c-sda-hold-time-ns = <300>;
+ status = "disabled";
+};
+
+&uart0 {
+ clock-frequency = <100000000>;
+};
+
+&mmc0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+
+ flash0: flash@0 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25fl512s", "jedec,spi-nor";
+ reg = <0>;
+
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ spi-max-frequency = <10000000>;
+
+ cdns,read-delay = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+
+ partition@raw {
+ label = "Flash Raw";
+ reg = <0x0 0x4000000>;
+ };
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gmac1 {
+ status = "okay";
+ /delete-property/ mac-address;
+ phy-mode = "rgmii";
+ phy-handle = <&phy3>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+
+ /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/
+ rxc-skew-ps = <1680>;
+ rxd0-skew-ps = <420>;
+ rxd1-skew-ps = <420>;
+ rxd2-skew-ps = <420>;
+ rxd3-skew-ps = <420>;
+ rxdv-skew-ps = <420>;
+
+ /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/
+ txc-skew-ps = <1860>;
+ txd0-skew-ps = <0>;
+ txd1-skew-ps = <0>;
+ txd2-skew-ps = <0>;
+ txd3-skew-ps = <0>;
+ txen-skew-ps = <0>;
+ };
+ };
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
diff --git a/dts/src/arm/intel/socfpga/skeleton.dtsi b/dts/src/arm/intel/socfpga/skeleton.dtsi
deleted file mode 100644
index b41d241de2cde0ccf022134519e9f9d3ae4261a4..0000000000000000000000000000000000000000
--- a/dts/src/arm/intel/socfpga/skeleton.dtsi
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Skeleton device tree; the bare minimum needed to boot; just include and
- * add a compatible value. The bootloader will typically populate the memory
- * node.
- */
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- chosen { };
- aliases { };
- memory { device_type = "memory"; reg = <0 0>; };
-};
diff --git a/dts/src/arm/intel/socfpga/socfpga_cyclone5_enclustra.dtsi b/dts/src/arm/intel/socfpga/socfpga_cyclone5_enclustra.dtsi
deleted file mode 100644
index 9ea1b76f1d55b28fd162231144bcb537a111c53f..0000000000000000000000000000000000000000
--- a/dts/src/arm/intel/socfpga/socfpga_cyclone5_enclustra.dtsi
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/dts-v1/;
-/* First 4KB has trampoline code for secondary cores. */
-/memreserve/ 0x00000000 0x0001000;
-#include "socfpga_enclustra.dtsi"
-
-/ {
- soc {
- clkmgr@ffd04000 {
- clocks {
- osc1 {
- clock-frequency = <50000000>;
- };
- };
- };
-
- mmc0: dwmmc0@ff704000 {
- num-slots = <1>;
- broken-cd;
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- };
-
- ethernet@ff702000 {
- phy-mode = "rgmii";
- phy-addr = <0xffffffff>; /* probe for phy addr */
- status = "okay";
- };
-
- sysmgr@ffd08000 {
- cpu1-start-addr = <0xffd080c4>;
- };
- };
-};
-
-&watchdog0 {
- status = "okay";
-};
-
-&i2c0 {
- /* Both RTCs disabled by default, choose one */
- pcf85063: pcf85063@51 {
- status = "disabled";
- compatible = "nxp,pcf85063";
- reg = <0x51>;
- };
- isl12022: isl12022@68 {
- status = "disabled";
- compatible = "isil,isl12022";
- reg = <0x6f>;
- };
-};
diff --git a/dts/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2.dts b/dts/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2.dts
deleted file mode 100644
index cc55bf8f575433046915d3f33aaf789861d13b1a..0000000000000000000000000000000000000000
--- a/dts/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2.dts
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "socfpga_cyclone5_enclustra.dtsi"
-
-/ {
- model = "Enclustra Mercury SA2 SOM";
- compatible = "altr,socfpga-cyclone5", "altr,socfpga";
-
- chosen {
- bootargs = "console=ttyS0,115200";
- };
-
- memory {
- name = "memory";
- device_type = "memory";
- reg = <0x0 0x40000000>; /* 1GB */
- };
-
- aliases {
- /* this allow the ethaddr uboot environmnet variable contents
- * to be added to the gmac1 device tree blob.
- */
- ethernet0 = &gmac1;
- };
-
- regulator_3_3v: vcc3p3-regulator {
- compatible = "regulator-fixed";
- regulator-name = "VCC3P3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "rgmii";
-
- rxd0-skew-ps = <0>;
- rxd1-skew-ps = <0>;
- rxd2-skew-ps = <0>;
- rxd3-skew-ps = <0>;
- txen-skew-ps = <0>;
- txc-skew-ps = <2600>;
- rxdv-skew-ps = <0>;
- rxc-skew-ps = <2000>;
-
- phy-handle = <&phy3>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy3: ethernet-phy@3 {
- reg = <3>;
- };
- };
-};
-
-&mmc0 {
- vmmc-supply = <®ulator_3_3v>;
- vqmmc-supply = <®ulator_3_3v>;
-};
-
-&usb1 {
- status = "okay";
-};
-
-&qspi {
- status = "okay";
-
- flash0: n25q00@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "n25q00";
- reg = <0>;
- spi-max-frequency = <100000000>;
- cdns,page-size = <256>;
- cdns,block-size = <16>;
- m25p,fast-read;
- cdns,read-delay = <4>;
- cdns,tshsl-ns = <50>;
- cdns,tsd2d-ns = <50>;
- cdns,tchsh-ns = <4>;
- cdns,tslch-ns = <4>;
-
- part0: partition@0 {
- label = "Flash 0 Raw Data";
- reg = < 0x00000000 0x01000000 >;
- };
-
- part1: partition@800000 {
- label = "Flash 1 jffs2 Filesystem";
- reg = < 0x01000000 0x03000000 >;
- };
- };
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&isl12022 {
- status = "okay";
-};
-
-&spi0 {
- status = "okay";
- spidev@0 {
- compatible = "spidev";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
-};
diff --git a/dts/src/arm/intel/socfpga/socfpga_enclustra.dtsi b/dts/src/arm/intel/socfpga/socfpga_enclustra.dtsi
deleted file mode 100644
index a5ccc1933a7ed851effc4844a2e22f55d58c6905..0000000000000000000000000000000000000000
--- a/dts/src/arm/intel/socfpga/socfpga_enclustra.dtsi
+++ /dev/null
@@ -1,971 +0,0 @@
-/*
- * Copyright (C) 2012 Altera <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "skeleton.dtsi"
-#include <dt-bindings/reset/altr,rst-mgr.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- aliases {
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
- serial0 = &uart0;
- serial1 = &uart1;
- timer0 = &timer0;
- timer1 = &timer1;
- timer2 = &timer2;
- timer3 = &timer3;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- enable-method = "altr,socfpga-smp";
-
- cpu@0 {
- compatible = "arm,cortex-a9";
- device_type = "cpu";
- reg = <0>;
- next-level-cache = <&L2>;
- };
- cpu@1 {
- compatible = "arm,cortex-a9";
- device_type = "cpu";
- reg = <1>;
- next-level-cache = <&L2>;
- };
- };
-
- intc: intc@fffed000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0xfffed000 0x1000>,
- <0xfffec100 0x100>;
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- device_type = "soc";
- interrupt-parent = <&intc>;
- ranges;
-
- amba {
- compatible = "arm,amba-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- pdma: pdma@ffe01000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0xffe01000 0x1000>;
- interrupts = <0 104 4>,
- <0 105 4>,
- <0 106 4>,
- <0 107 4>,
- <0 108 4>,
- <0 109 4>,
- <0 110 4>,
- <0 111 4>;
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- clocks = <&l4_main_clk>;
- clock-names = "apb_pclk";
- };
- };
-
- can0: can@ffc00000 {
- compatible = "bosch,d_can";
- reg = <0xffc00000 0x1000>;
- interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
- clocks = <&can0_clk>;
- status = "disabled";
- };
-
- can1: can@ffc01000 {
- compatible = "bosch,d_can";
- reg = <0xffc01000 0x1000>;
- interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
- clocks = <&can1_clk>;
- status = "disabled";
- };
-
- clkmgr@ffd04000 {
- compatible = "altr,clk-mgr";
- reg = <0xffd04000 0x1000>;
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- osc1: osc1 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
-
- osc2: osc2 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
-
- f2s_periph_ref_clk: f2s_periph_ref_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
-
- f2s_sdram_ref_clk: f2s_sdram_ref_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
-
- main_pll: main_pll {
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <0>;
- compatible = "altr,socfpga-pll-clock";
- clocks = <&osc1>;
- reg = <0x40>;
-
- mpuclk: mpuclk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&main_pll>;
- div-reg = <0xe0 0 9>;
- reg = <0x48>;
- };
-
- mainclk: mainclk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&main_pll>;
- div-reg = <0xe4 0 9>;
- reg = <0x4C>;
- };
-
- dbg_base_clk: dbg_base_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&main_pll>, <&osc1>;
- div-reg = <0xe8 0 9>;
- reg = <0x50>;
- };
-
- main_qspi_clk: main_qspi_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&main_pll>;
- reg = <0x54>;
- };
-
- main_nand_sdmmc_clk: main_nand_sdmmc_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&main_pll>;
- reg = <0x58>;
- };
-
- cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&main_pll>;
- reg = <0x5C>;
- };
- };
-
- periph_pll: periph_pll {
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <0>;
- compatible = "altr,socfpga-pll-clock";
- clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
- reg = <0x80>;
-
- emac0_clk: emac0_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x88>;
- };
-
- emac1_clk: emac1_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x8C>;
- };
-
- per_qspi_clk: per_qsi_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x90>;
- };
-
- per_nand_mmc_clk: per_nand_mmc_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x94>;
- };
-
- per_base_clk: per_base_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x98>;
- };
-
- h2f_usr1_clk: h2f_usr1_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x9C>;
- };
- };
-
- sdram_pll: sdram_pll {
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <0>;
- compatible = "altr,socfpga-pll-clock";
- clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
- reg = <0xC0>;
-
- ddr_dqs_clk: ddr_dqs_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&sdram_pll>;
- reg = <0xC8>;
- };
-
- ddr_2x_dqs_clk: ddr_2x_dqs_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&sdram_pll>;
- reg = <0xCC>;
- };
-
- ddr_dq_clk: ddr_dq_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&sdram_pll>;
- reg = <0xD0>;
- };
-
- h2f_usr2_clk: h2f_usr2_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&sdram_pll>;
- reg = <0xD4>;
- };
- };
-
- mpu_periph_clk: mpu_periph_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&mpuclk>;
- fixed-divider = <4>;
- };
-
- mpu_l2_ram_clk: mpu_l2_ram_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&mpuclk>;
- fixed-divider = <2>;
- };
-
- l4_main_clk: l4_main_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&mainclk>;
- clk-gate = <0x60 0>;
- };
-
- l3_main_clk: l3_main_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&mainclk>;
- fixed-divider = <1>;
- };
-
- l3_mp_clk: l3_mp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&mainclk>;
- div-reg = <0x64 0 2>;
- clk-gate = <0x60 1>;
- };
-
- l3_sp_clk: l3_sp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&l3_mp_clk>;
- div-reg = <0x64 2 2>;
- };
-
- l4_mp_clk: l4_mp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&mainclk>, <&per_base_clk>;
- div-reg = <0x64 4 3>;
- clk-gate = <0x60 2>;
- };
-
- l4_sp_clk: l4_sp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&mainclk>, <&per_base_clk>;
- div-reg = <0x64 7 3>;
- clk-gate = <0x60 3>;
- };
-
- dbg_at_clk: dbg_at_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&dbg_base_clk>;
- div-reg = <0x68 0 2>;
- clk-gate = <0x60 4>;
- };
-
- dbg_clk: dbg_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&dbg_at_clk>;
- div-reg = <0x68 2 2>;
- clk-gate = <0x60 5>;
- };
-
- dbg_trace_clk: dbg_trace_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&dbg_base_clk>;
- div-reg = <0x6C 0 3>;
- clk-gate = <0x60 6>;
- };
-
- dbg_timer_clk: dbg_timer_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&dbg_base_clk>;
- clk-gate = <0x60 7>;
- };
-
- cfg_clk: cfg_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&cfg_h2f_usr0_clk>;
- clk-gate = <0x60 8>;
- };
-
- h2f_user0_clk: h2f_user0_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&cfg_h2f_usr0_clk>;
- clk-gate = <0x60 9>;
- };
-
- emac_0_clk: emac_0_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&emac0_clk>;
- clk-gate = <0xa0 0>;
- };
-
- emac_1_clk: emac_1_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&emac1_clk>;
- clk-gate = <0xa0 1>;
- };
-
- usb_mp_clk: usb_mp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&per_base_clk>;
- clk-gate = <0xa0 2>;
- div-reg = <0xa4 0 3>;
- };
-
- spi_m_clk: spi_m_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&per_base_clk>;
- clk-gate = <0xa0 3>;
- div-reg = <0xa4 3 3>;
- };
-
- can0_clk: can0_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&per_base_clk>;
- clk-gate = <0xa0 4>;
- div-reg = <0xa4 6 3>;
- };
-
- can1_clk: can1_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&per_base_clk>;
- clk-gate = <0xa0 5>;
- div-reg = <0xa4 9 3>;
- };
-
- gpio_db_clk: gpio_db_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&per_base_clk>;
- clk-gate = <0xa0 6>;
- div-reg = <0xa8 0 24>;
- };
-
- h2f_user1_clk: h2f_user1_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&h2f_usr1_clk>;
- clk-gate = <0xa0 7>;
- };
-
- sdmmc_clk: sdmmc_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
- clk-gate = <0xa0 8>;
- clk-phase = <0 135>;
- };
-
- sdmmc_clk_divided: sdmmc_clk_divided {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&sdmmc_clk>;
- clk-gate = <0xa0 8>;
- fixed-divider = <4>;
- };
-
- nand_x_clk: nand_x_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
- clk-gate = <0xa0 9>;
- };
-
- nand_clk: nand_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
- clk-gate = <0xa0 10>;
- fixed-divider = <4>;
- };
-
- qspi_clk: qspi_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
- clk-gate = <0xa0 11>;
- fixed-divider = <2>;
- };
-
- ddr_dqs_clk_gate: ddr_dqs_clk_gate {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&ddr_dqs_clk>;
- clk-gate = <0xd8 0>;
- };
-
- ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&ddr_2x_dqs_clk>;
- clk-gate = <0xd8 1>;
- };
-
- ddr_dq_clk_gate: ddr_dq_clk_gate {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&ddr_dq_clk>;
- clk-gate = <0xd8 2>;
- };
-
- h2f_user2_clk: h2f_user2_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&h2f_usr2_clk>;
- clk-gate = <0xd8 3>;
- };
-
- };
- };
-
- gmac0: ethernet@ff700000 {
- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
- altr,sysmgr-syscon = <&sysmgr 0x60 0>;
- reg = <0xff700000 0x2000>;
- interrupts = <0 115 4>;
- interrupt-names = "macirq";
- mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac0_clk>;
- clock-names = "stmmaceth";
- resets = <&rst EMAC0_RESET>;
- reset-names = "stmmaceth";
- snps,multicast-filter-bins = <256>;
- snps,perfect-filter-entries = <128>;
- tx-fifo-depth = <4096>;
- rx-fifo-depth = <4096>;
- status = "disabled";
- };
-
- gmac1: ethernet@ff702000 {
- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
- altr,sysmgr-syscon = <&sysmgr 0x60 2>;
- reg = <0xff702000 0x2000>;
- interrupts = <0 120 4>;
- interrupt-names = "macirq";
- mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac1_clk>;
- clock-names = "stmmaceth";
- resets = <&rst EMAC1_RESET>;
- reset-names = "stmmaceth";
- snps,multicast-filter-bins = <256>;
- snps,perfect-filter-entries = <128>;
- tx-fifo-depth = <4096>;
- rx-fifo-depth = <4096>;
- status = "disabled";
- };
-
- hps_0_fpgamgr: fpgamgr@0xff706000 {
- compatible = "altr,fpga-mgr-1.0", "altr,fpga-mgr";
- transport = "mmio";
- reg = <0xFF706000 0x1000
- 0xFFB90000 0x1000>;
- interrupts = <0 175 4>;
- };
-
- hps_fpgabridge0: fpgabridge@0 {
- compatible = "altr,socfpga-hps2fpga-bridge";
- label = "hps2fpga";
- resets = <&rst HPS2FPGA_RESET>;
- reset-names = "hps2fpga";
- clocks = <&l4_main_clk>;
- };
-
- hps_fpgabridge1: fpgabridge@1 {
- compatible = "altr,socfpga-lwhps2fpga-bridge";
- label = "lwhps2fpga";
- resets = <&rst LWHPS2FPGA_RESET>;
- reset-names = "lwhps2fpga";
- clocks = <&l4_main_clk>;
- };
-
- hps_fpgabridge2: fpgabridge@2 {
- compatible = "altr,socfpga-fpga2hps-bridge";
- label = "fpga2hps";
- resets = <&rst FPGA2HPS_RESET>;
- reset-names = "fpga2hps";
- clocks = <&l4_main_clk>;
- };
-
- i2c0: i2c@ffc04000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc04000 0x1000>;
- clocks = <&l4_sp_clk>;
- interrupts = <0 158 0x4>;
- status = "disabled";
- };
-
- i2c1: i2c@ffc05000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc05000 0x1000>;
- clocks = <&l4_sp_clk>;
- interrupts = <0 159 0x4>;
- status = "disabled";
- };
-
- i2c2: i2c@ffc06000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc06000 0x1000>;
- clocks = <&l4_sp_clk>;
- interrupts = <0 160 0x4>;
- status = "disabled";
- };
-
- i2c3: i2c@ffc07000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc07000 0x1000>;
- clocks = <&l4_sp_clk>;
- interrupts = <0 161 0x4>;
- status = "disabled";
- };
-
- gpio0: gpio@ff708000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dw-apb-gpio";
- reg = <0xff708000 0x1000>;
- clocks = <&l4_mp_clk>;
- status = "disabled";
-
- porta: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- snps,nr-gpios = <29>;
- reg = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <0 164 4>;
- };
- };
-
- gpio1: gpio@ff709000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dw-apb-gpio";
- reg = <0xff709000 0x1000>;
- clocks = <&l4_mp_clk>;
- status = "disabled";
-
- portb: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- snps,nr-gpios = <29>;
- reg = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <0 165 4>;
- };
- };
-
- gpio2: gpio@ff70a000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dw-apb-gpio";
- reg = <0xff70a000 0x1000>;
- clocks = <&l4_mp_clk>;
- status = "disabled";
-
- portc: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- snps,nr-gpios = <27>;
- reg = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <0 166 4>;
- };
- };
-
- sdr: sdr@ffc25000 {
- compatible = "syscon";
- reg = <0xffc25000 0x1000>;
- };
-
- sdramedac {
- compatible = "altr,sdram-edac";
- altr,sdr-syscon = <&sdr>;
- interrupts = <0 39 4>;
- };
-
- L2: l2-cache@fffef000 {
- compatible = "arm,pl310-cache", "syscon";
- reg = <0xfffef000 0x1000>;
- interrupts = <0 38 0x04>;
- cache-unified;
- cache-level = <2>;
- arm,tag-latency = <1 1 1>;
- arm,data-latency = <2 1 1>;
- prefetch-data = <1>;
- prefetch-instr = <1>;
- };
-
- mmc: dwmmc0@ff704000 {
- compatible = "altr,socfpga-dw-mshc";
- reg = <0xff704000 0x1000>;
- interrupts = <0 139 4>;
- fifo-depth = <0x400>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
- clock-names = "biu", "ciu";
- };
-
- nand: nand@ff900000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "denali,denali-nand-dt";
- reg = <0xff900000 0x100000>, <0xffb80000 0x10000>;
- reg-names = "nand_data", "denali_reg";
- interrupts = <0 144 4>;
- dma-mask = <0xffffffff>;
- clocks = <&nand_clk>;
- have-hw-ecc-fixup;
- status = "disabled";
-
- partition@nand-boot {
- /* 8MB for raw data. */
- label = "NAND Flash Boot Area 8MB";
- reg = <0x0 0x800000>;
- };
- partition@nand-rootfs {
- /* 128MB jffs2 root filesystem. */
- label = "NAND Flash jffs2 Root Filesystem 128MB";
- reg = <0x800000 0x8000000>;
- };
- partition@nand-128 {
- label = "NAND Flash 128 MB";
- reg = <0x8800000 0x8000000>;
- };
- partition@nand-64 {
- label = "NAND Flash 64 MB";
- reg = <0x10800000 0x4000000>;
- };
- partition@nand-32 {
- label = "NAND Flash 32 MB";
- reg = <0x14800000 0x2000000>;
- };
- partition@nand-16 {
- label = "NAND Flash 16 MB";
- reg = <0x16800000 0x1000000>;
- };
- };
-
- ocram: sram@ffff0000 {
- compatible = "mmio-sram";
- reg = <0xffff0000 0x10000>;
- };
-
- pmu {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "arm,cortex-a9-pmu";
- interrupts = <0 176 4>, <0 177 4>;
- ranges;
-
- cti0: cti0@ff118000 {
- compatible = "arm,coresight-cti";
- reg = <0xff118000 0x100>;
- };
-
- cti1: cti1@ff119000 {
- compatible = "arm,coresight-cti";
- reg = <0xff119000 0x100>;
- };
- };
-
- sdrctl@0xffc25000 {
- compatible = "altr,sdr-ctl", "syscon";
- reg = <0xffc25000 0x1000>;
- };
-
- l2edac@xffd08140 {
- compatible = "altr,l2-edac";
- reg = <0xffd08140 0x4>;
- interrupts = <0 36 1>, <0 37 1>;
- };
-
- ocramedac@ffd08144 {
- compatible = "altr,ocram-edac";
- reg = <0xffd08144 0x4>;
- iram = <&ocram>;
- interrupts = <0 178 1>, <0 179 1>;
- };
-
- l3regs@0xff800000 {
- compatible = "altr,l3regs", "syscon";
- reg = <0xff800000 0x1000>;
- };
-
- qspi: spi@ff705000 {
- compatible = "cdns,qspi-nor";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xff705000 0x1000>,
- <0xffa00000 0x1000>;
- interrupts = <0 151 4>;
- clocks = <&qspi_clk>;
- is-decoded-cs = <1>;
- fifo-depth = <128>;
- status = "disabled";
- m25p,fast-read;
- };
-
- spi0: spi@fff00000 {
- compatible = "snps,dw-apb-ssi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xfff00000 0x1000>;
- interrupts = <0 154 4>;
- num-cs = <4>;
- tx-dma-channel = <&pdma 16>;
- rx-dma-channel = <&pdma 17>;
- clocks = <&per_base_clk>;
- status = "disabled";
- };
-
- scu: snoop-control-unit@fffec000 {
- compatible = "arm,cortex-a9-scu";
- reg = <0xfffec000 0x100>;
- };
-
- spi1: spi@fff01000 {
- compatible = "snps,dw-apb-ssi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xfff01000 0x1000>;
- interrupts = <0 155 4>;
- num-cs = <4>;
- tx-dma-channel = <&pdma 20>;
- rx-dma-channel = <&pdma 21>;
- clocks = <&per_base_clk>;
- status = "disabled";
- };
-
- /* Local timer */
- timer@fffec600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0xfffec600 0x100>;
- interrupts = <1 13 0xf04>;
- clocks = <&mpu_periph_clk>;
- };
-
- timer0: timer0@ffc08000 {
- compatible = "snps,dw-apb-timer";
- interrupts = <0 167 4>;
- reg = <0xffc08000 0x1000>;
- clocks = <&l4_sp_clk>;
- clock-names = "timer";
- };
-
- timer1: timer1@ffc09000 {
- compatible = "snps,dw-apb-timer";
- interrupts = <0 168 4>;
- reg = <0xffc09000 0x1000>;
- clocks = <&l4_sp_clk>;
- clock-names = "timer";
- };
-
- timer2: timer2@ffd00000 {
- compatible = "snps,dw-apb-timer";
- interrupts = <0 169 4>;
- reg = <0xffd00000 0x1000>;
- clocks = <&osc1>;
- clock-names = "timer";
- };
-
- timer3: timer3@ffd01000 {
- compatible = "snps,dw-apb-timer";
- interrupts = <0 170 4>;
- reg = <0xffd01000 0x1000>;
- clocks = <&osc1>;
- clock-names = "timer";
- };
-
- uart0: serial0@ffc02000 {
- compatible = "snps,dw-apb-uart";
- reg = <0xffc02000 0x1000>;
- interrupts = <0 162 4>;
- reg-shift = <2>;
- reg-io-width = <4>;
- /*clocks = <&l4_sp_clk>;*/
- clock-frequency = <100000000>;
- dmas = <&pdma 28>,
- <&pdma 29>;
- dma-names = "tx", "rx";
- };
-
- uart1: serial1@ffc03000 {
- compatible = "snps,dw-apb-uart";
- reg = <0xffc03000 0x1000>;
- interrupts = <0 163 4>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&l4_sp_clk>;
- dmas = <&pdma 30>,
- <&pdma 31>;
- dma-names = "tx", "rx";
- };
-
- rst: rstmgr@ffd05000 {
- #reset-cells = <1>;
- compatible = "altr,rst-mgr";
- reg = <0xffd05000 0x1000>;
- altr,modrst-offset = <0x10>;
- };
-
- usbphy0: usbphy@0 {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- status = "okay";
- };
-
- usb0: usb@ffb00000 {
- compatible = "snps,dwc2";
- reg = <0xffb00000 0xffff>;
- interrupts = <0 125 4>;
- clocks = <&usb_mp_clk>;
- clock-names = "otg";
- phys = <&usbphy0>;
- phy-names = "usb2-phy";
- status = "disabled";
- };
-
- usb1: usb@ffb40000 {
- compatible = "snps,dwc2";
- reg = <0xffb40000 0xffff>;
- interrupts = <0 128 4>;
- clocks = <&usb_mp_clk>;
- clock-names = "otg";
- phys = <&usbphy0>;
- phy-names = "usb2-phy";
- status = "disabled";
- };
-
- watchdog0: watchdog@ffd02000 {
- compatible = "snps,dw-wdt";
- reg = <0xffd02000 0x1000>;
- interrupts = <0 171 4>;
- clocks = <&osc1>;
- status = "disabled";
- };
-
- watchdog1: watchdog@ffd03000 {
- compatible = "snps,dw-wdt";
- reg = <0xffd03000 0x1000>;
- interrupts = <0 172 4>;
- clocks = <&osc1>;
- status = "disabled";
- };
-
- sysmgr: sysmgr@ffd08000 {
- compatible = "altr,sys-mgr", "syscon";
- reg = <0xffd08000 0x4000>;
- };
- };
-};
--
2.43.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 04/11] ARM: dts: socfpga: use upstream SA2 device tree
2025-09-17 15:22 ` [PATCH 04/11] ARM: dts: socfpga: use upstream SA2 device tree David Picard
@ 2025-09-18 6:32 ` Sascha Hauer
2025-09-18 10:09 ` David Picard
0 siblings, 1 reply; 30+ messages in thread
From: Sascha Hauer @ 2025-09-18 6:32 UTC (permalink / raw)
To: David Picard; +Cc: BAREBOX, Ahmad Fatoum
On Wed, Sep 17, 2025 at 05:22:07PM +0200, David Picard wrote:
> From: Ahmad Fatoum <ahmad@a3f.at>
>
> The device trees from the Enclustra BSP are outdated and not compatible
> with what barebox expects. Drop them and use the upstream SoC device
> tree imported from Linux instead. For the board itself, we import the
> device tree in the most recent posting[1] to the kernel mailing lists.
>
> [1]: https://lore.kernel.org/all/20241116131025.114542-1-l.rubusch@gmail.com/
>
> Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
> ---
> arch/arm/dts/socfpga_cyclone5_mercury_sa2.dts | 18 +-
> arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi | 150 ++++
> dts/src/arm/intel/socfpga/skeleton.dtsi | 13 -
> .../intel/socfpga/socfpga_cyclone5_enclustra.dtsi | 69 --
> .../intel/socfpga/socfpga_cyclone5_mercury_sa2.dts | 128 ---
> dts/src/arm/intel/socfpga/socfpga_enclustra.dtsi | 971 ---------------------
> 6 files changed, 152 insertions(+), 1197 deletions(-)
Please squash this into the previous commit. Or, to put it differently,
don't introduce files that you remove just in the next step.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 04/11] ARM: dts: socfpga: use upstream SA2 device tree
2025-09-18 6:32 ` Sascha Hauer
@ 2025-09-18 10:09 ` David Picard
2025-09-18 10:20 ` Ahmad Fatoum
0 siblings, 1 reply; 30+ messages in thread
From: David Picard @ 2025-09-18 10:09 UTC (permalink / raw)
To: Sascha Hauer; +Cc: BAREBOX, Ahmad Fatoum
I tried to squash, but it kicked Ahmad off the author list...
Le 18/09/2025 à 08:32, Sascha Hauer a écrit :
> On Wed, Sep 17, 2025 at 05:22:07PM +0200, David Picard wrote:
>> From: Ahmad Fatoum <ahmad@a3f.at>
>>
>> The device trees from the Enclustra BSP are outdated and not compatible
>> with what barebox expects. Drop them and use the upstream SoC device
>> tree imported from Linux instead. For the board itself, we import the
>> device tree in the most recent posting[1] to the kernel mailing lists.
>>
>> [1]: https://lore.kernel.org/all/20241116131025.114542-1-l.rubusch@gmail.com/
>>
>> Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
>> ---
>> arch/arm/dts/socfpga_cyclone5_mercury_sa2.dts | 18 +-
>> arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi | 150 ++++
>> dts/src/arm/intel/socfpga/skeleton.dtsi | 13 -
>> .../intel/socfpga/socfpga_cyclone5_enclustra.dtsi | 69 --
>> .../intel/socfpga/socfpga_cyclone5_mercury_sa2.dts | 128 ---
>> dts/src/arm/intel/socfpga/socfpga_enclustra.dtsi | 971 ---------------------
>> 6 files changed, 152 insertions(+), 1197 deletions(-)
> Please squash this into the previous commit. Or, to put it differently,
> don't introduce files that you remove just in the next step.
>
> Sascha
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 04/11] ARM: dts: socfpga: use upstream SA2 device tree
2025-09-18 10:09 ` David Picard
@ 2025-09-18 10:20 ` Ahmad Fatoum
0 siblings, 0 replies; 30+ messages in thread
From: Ahmad Fatoum @ 2025-09-18 10:20 UTC (permalink / raw)
To: David Picard, Sascha Hauer; +Cc: BAREBOX, Ahmad Fatoum
Hi David,
On 9/18/25 12:09 PM, David Picard wrote:
> I tried to squash, but it kicked Ahmad off the author list...
That's no issue. If you want to credit me, you can add a
Co-developed-by: Ahmad Fatoum <ahmad@a3f.at>
into the squashed commit directly before my S-o-b with your S-o-b at the
end.
Cheers,
Ahmad
>
> Le 18/09/2025 à 08:32, Sascha Hauer a écrit :
>> On Wed, Sep 17, 2025 at 05:22:07PM +0200, David Picard wrote:
>>> From: Ahmad Fatoum <ahmad@a3f.at>
>>>
>>> The device trees from the Enclustra BSP are outdated and not compatible
>>> with what barebox expects. Drop them and use the upstream SoC device
>>> tree imported from Linux instead. For the board itself, we import the
>>> device tree in the most recent posting[1] to the kernel mailing lists.
>>>
>>> [1]: https://lore.kernel.org/all/20241116131025.114542-1-
>>> l.rubusch@gmail.com/
>>>
>>> Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
>>> ---
>>> arch/arm/dts/socfpga_cyclone5_mercury_sa2.dts | 18 +-
>>> arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi | 150 ++++
>>> dts/src/arm/intel/socfpga/skeleton.dtsi | 13 -
>>> .../intel/socfpga/socfpga_cyclone5_enclustra.dtsi | 69 --
>>> .../intel/socfpga/socfpga_cyclone5_mercury_sa2.dts | 128 ---
>>> dts/src/arm/intel/socfpga/socfpga_enclustra.dtsi | 971
>>> ---------------------
>>> 6 files changed, 152 insertions(+), 1197 deletions(-)
>> Please squash this into the previous commit. Or, to put it differently,
>> don't introduce files that you remove just in the next step.
>>
>> Sascha
>>
>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 05/11] ARM: dts: socfpga: adapt upstream SA2 device tree
2025-09-17 15:22 [PATCH 00/11] ARM: boards: add support for Enclustra Mercury SA2 David Picard
` (3 preceding siblings ...)
2025-09-17 15:22 ` [PATCH 04/11] ARM: dts: socfpga: use upstream SA2 device tree David Picard
@ 2025-09-17 15:22 ` David Picard
2025-09-17 15:22 ` [PATCH 06/11] boards: enclustra-sa2: read MAC address from EEPROM David Picard
` (5 subsequent siblings)
10 siblings, 0 replies; 30+ messages in thread
From: David Picard @ 2025-09-17 15:22 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX; +Cc: David Picard
Signed-off-by: David Picard <david.picard@clermont.in2p3.fr>
---
arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi | 25 +++++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi b/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi
index 73bd75fcf224fbf31fce27dda6566d4bfe37d624..52a9d1a6c396fb3df56acbaf99d40594dea19944 100644
--- a/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi
@@ -9,9 +9,14 @@
#include <arm/intel/socfpga/socfpga_cyclone5.dtsi>
+/ {
+ barebox,deep-probe;
+};
+
/ {
model = "Enclustra Mercury+ SA2";
- compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+ compatible = "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2", "altr,socfpga-cyclone5", "altr,socfpga";
+
chosen {
stdout-path = "serial0:115200n8";
@@ -57,7 +62,8 @@ isl12020: rtc@6f {
reg = <0x6f>;
};
- atsha204a: crypto@64 {
+ atsha204a: atsha204a@64 {
+ status = "okay";
compatible = "atmel,atsha204a";
reg = <0x64>;
};
@@ -125,6 +131,21 @@ mdio0 {
phy3: ethernet-phy@3 {
reg = <3>;
+ /*
+ Ethernet PHY reset pin (active low, GPIO44) :
+ - 1st field: GPIO controller phandle
+ - 2nd field: GPIO line offset
+ - 3rd field: flags (see gpio.txt)
+
+ Reference:
+ - Cyclone 5 HPS technical reference, table 23-1: GPIO44 is on controller
+ GPIO1, whose 1st line is GPIO29. The offset is thus 44 - 29 = 15.
+ - Linux documentation:
+ - Documentation/devicetree/bindings/gpio/gpio.txt
+ - Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml
+ */
+ reset-gpios = <&portb 15 0x01>;
+
/* Add 2ns RX clock delay (1.2ns + 0.78ns)*/
rxc-skew-ps = <1680>;
rxd0-skew-ps = <420>;
--
2.43.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 06/11] boards: enclustra-sa2: read MAC address from EEPROM
2025-09-17 15:22 [PATCH 00/11] ARM: boards: add support for Enclustra Mercury SA2 David Picard
` (4 preceding siblings ...)
2025-09-17 15:22 ` [PATCH 05/11] ARM: dts: socfpga: adapt " David Picard
@ 2025-09-17 15:22 ` David Picard
2025-09-17 17:06 ` Alexander Shiyan
2025-09-18 6:18 ` Sascha Hauer
2025-09-17 15:22 ` [PATCH 07/11] gpio: dw: support numbering via aliases David Picard
` (4 subsequent siblings)
10 siblings, 2 replies; 30+ messages in thread
From: David Picard @ 2025-09-17 15:22 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX; +Cc: David Picard
Signed-off-by: David Picard <david.picard@clermont.in2p3.fr>
---
arch/arm/boards/enclustra-sa2/Makefile | 2 +-
arch/arm/boards/enclustra-sa2/atsha204a.c | 436 ++++++++++++++++++++++++++++++
arch/arm/boards/enclustra-sa2/atsha204a.h | 19 ++
arch/arm/boards/enclustra-sa2/board.c | 51 +++-
arch/arm/boards/enclustra-sa2/crc16.c | 65 +++++
arch/arm/boards/enclustra-sa2/crc16.h | 28 ++
arch/arm/mach-socfpga/Kconfig | 1 +
7 files changed, 598 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boards/enclustra-sa2/Makefile b/arch/arm/boards/enclustra-sa2/Makefile
index 8c927fe291a6b3eb20a32a2db96c73f231ab4697..1448ea1266aa24a5b0404cb6379f8c2d76573079 100644
--- a/arch/arm/boards/enclustra-sa2/Makefile
+++ b/arch/arm/boards/enclustra-sa2/Makefile
@@ -1,2 +1,2 @@
-obj-y += lowlevel.o board.o
+obj-y += lowlevel.o board.o atsha204a.o crc16.o
pbl-y += lowlevel.o
diff --git a/arch/arm/boards/enclustra-sa2/atsha204a.c b/arch/arm/boards/enclustra-sa2/atsha204a.c
new file mode 100644
index 0000000000000000000000000000000000000000..3f445de06e73c5bdf27d2d0fc81dc6d939d5cd17
--- /dev/null
+++ b/arch/arm/boards/enclustra-sa2/atsha204a.c
@@ -0,0 +1,436 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "atsha204a.h"
+#include <stdio.h>
+#include <driver.h>
+#include <linux/libfdt.h>
+#include <linux/kernel.h> /* ARRAY_SIZE */
+#include <linux/bitrev.h> /* bitrev16 */
+#include <i2c/i2c.h>
+#include "crc16.h"
+
+#define ATSHA204A_TWLO_US (60)
+#define ATSHA204A_TWHI_US (2500)
+#define ATSHA204A_EXECTIME_US (5000)
+#define ATSHA204A_TRANSACTION_TIMEOUT (100000)
+#define ATSHA204A_TRANSACTION_RETRY (5)
+
+enum atsha204a_status {
+ ATSHA204A_STATUS_SUCCES = 0x00,
+ ATSHA204A_STATUS_MISCOMPARE = 0x01,
+ ATSHA204A_STATUS_PARSE_ERROR = 0x03,
+ ATSHA204A_STATUS_EXEC_ERROR = 0x0F,
+ ATSHA204A_STATUS_AFTER_WAKE = 0x11,
+ ATSHA204A_STATUS_CRC_ERROR = 0xFF,
+};
+
+enum atsha204a_func {
+ ATSHA204A_FUNC_RESET = 0x00,
+ ATSHA204A_FUNC_SLEEP = 0x01,
+ ATSHA204A_FUNC_IDLE = 0x02,
+ ATSHA204A_FUNC_COMMAND = 0x03,
+};
+
+enum atsha204a_zone {
+ ATSHA204A_ZONE_CONFIG = 0,
+ ATSHA204A_ZONE_OTP = 1,
+ ATSHA204A_ZONE_DATA = 2,
+};
+
+enum atsha204a_cmd {
+ ATSHA204A_CMD_READ = 0x02,
+ ATSHA204A_CMD_RANDOM = 0x1B,
+};
+
+/**
+ * @brief A response from the device to the host
+ */
+struct atsha204a_resp {
+ uint8_t length; /**< Number of bytes in the struct, including \a
+ length and \a code */
+ uint8_t code; /**< Op code that must match the last command */
+ uint8_t data[82]; /**< Data buffer */
+} __packed;
+
+struct atsha204a_req {
+ u8 function;
+ u8 length;
+ u8 command;
+ u8 param1;
+ u16 param2;
+ u8 data[78];
+} __packed;
+
+/**
+ * @brief Calculate a CRC
+ * @param[in] buffer Data on which the CRC must be calculated
+ * @param[in] len Number of bytes in \a buffer
+ *
+ * For example, afer wake-up, the data read from the device is `0x04 0x11 0x33
+ *0x43`.
+ * The 1st byte is the packet length, the 2nd byte is the op code and the last
+ * 2 bytes are the CRC, with the bytes swapped.
+ * The function must be called with the 1st 2 bytes and if it returns 0x4333,
+ * then the CRC is valid.
+ *
+ * @return The CRC.
+ */
+static inline u16 atsha204a_crc16(const u8 *buffer, size_t len)
+{
+ debug("%s() >> len = %u, buffer =", __func__, len);
+ for (size_t i = 0 ; i < len ; i++)
+ debug(" 0x%02x", buffer[i]);
+ debug("\n");
+ return bitrev16(crc16(0, buffer, len));
+}
+
+/**
+ * @brief Get the device from the devicetree
+ * @return A pointer to the device if found, or \t NULL otherwise.
+ */
+static struct device *atsha204a_get_dev(void)
+{
+ struct device *dev;
+ struct i2c_client *client;
+
+ dev = get_device_by_name("atsha204a0");
+ if (dev == NULL) {
+ printf("%s() >> ERROR: can't find device\n", __func__);
+ return NULL;
+ }
+ client = to_i2c_client(dev);
+ debug("%s() >> ATASHA204a found at I2C address 0x%02x\n", __func__,
+ client->addr);
+
+ return dev;
+}
+
+/**
+ * @brief Send one message to the device
+ * @param[in] dev A pointer to the device, returned by #atsha204a_get_dev()
+ * @param[in] buf The data to send
+ * @param[in] len The number of bytes in \a buf
+ * @return 0 on success, a negative value from `asm-generic/errno.h` on error.
+ */
+static int atsha204a_send(struct device *dev, const uint8_t *buf, uint8_t len)
+{
+ int ret;
+ struct i2c_client *client;
+
+ client = to_i2c_client(dev);
+ struct i2c_msg msg[] = {
+ {
+ .addr = client->addr,
+ .buf = (uint8_t *)buf,
+ .len = len,
+ }
+ };
+ debug("%s() >> dev addr = 0x%02x\n", __func__, client->addr);
+
+ ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/**
+ * @brief Read from the device
+ * @param[in] dev A pointer to the device, returned by #atsha204a_get_dev()
+ * @param[in] buf The data to send
+ * @param[in] len The number of bytes in \a buf
+ * @return 0 on success, a negative value from `asm-generic/errno.h` on error.
+ */
+static int atsha204a_recv(struct device *dev, uint8_t *buf, uint8_t len)
+{
+ int ret;
+ struct i2c_client *client;
+
+ client = to_i2c_client(dev);
+ /* flags: this is a read operation and generate a stop condition */
+ struct i2c_msg msg[] = {
+ {
+ .addr = client->addr,
+ .buf = (uint8_t *)buf,
+ .len = len,
+ .flags = I2C_M_RD | I2C_M_STOP,
+ }
+ };
+
+ ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
+ if (ret < 0) {
+ printf("%s() >> ERROR: ret = %d\n", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * @brief Read from the device and check the CRC
+ * @param[in] dev A pointer to the device, returned by #atsha204a_get_dev()
+ * @param[in] resp The response from the device
+ * @return 0 on success, a negative value from `asm-generic/errno.h` on error.
+ */
+static int atsha204a_recv_resp(struct device *dev, struct atsha204a_resp *resp)
+{
+ int ret;
+ uint16_t resp_crc, computed_crc;
+ uint8_t *p = (uint8_t *)resp;
+
+ ret = atsha204a_recv(dev, p, 4);
+ if (ret)
+ return ret;
+ debug("%s() >> resp:", __func__);
+ for (size_t i = 0 ; i < 4 ; i++)
+ debug(" 0x%02x", p[i]);
+ debug(
+ "\n%s() >> length=0x%02x, code=0x%02x, data[0]=0x%02x, data[1]=0x%02x\n",
+ __func__,
+ resp->length, resp->code, resp->data[0], resp->data[1]);
+
+ if (resp->length > 4) {
+ if (resp->length > sizeof(*resp)) {
+ printf("%s() >> ERROR: resp->length %d > 4\n", __func__,
+ resp->length);
+ return -EMSGSIZE;
+ }
+ ret = atsha204a_recv(dev, p + 4, resp->length - 4);
+ if (ret)
+ return ret;
+ }
+
+ debug("%s() >> checking CRC... resp->length = %d\n", __func__,
+ resp->length);
+ resp_crc = (uint16_t)p[resp->length - 2]
+ | (((uint16_t)p[resp->length - 1]) << 8);
+ computed_crc = atsha204a_crc16(p, resp->length - 2);
+
+ if (resp_crc != computed_crc) {
+ printf(
+ "%s() >> ERROR: Invalid CRC. Received: 0x%04x; computed: 0x%04x\n",
+ __func__,
+ resp_crc, computed_crc);
+ return -EBADMSG;
+ }
+ debug("%s() >> CRC OK: 0x%04x\n", __func__, resp_crc);
+ return 0;
+}
+
+/**
+ * @brief Put the device to sleep
+ * @param[in] dev A pointer to the device, returned by #atsha204a_get_dev()
+ * @return 0 on success, a negative value from `asm-generic/errno.h` on error.
+ */
+static int atsha204a_sleep(struct device *dev)
+{
+ int ret;
+ uint8_t req = ATSHA204A_FUNC_SLEEP;
+
+ for (int i = 1 ; i < 10 ; i++) {
+ ret = atsha204a_send(dev, &req, 1);
+ if (!ret) {
+ debug("%s() >> sleeping! Trial #%d\n", __func__, i);
+ break;
+ }
+ udelay(ATSHA204A_EXECTIME_US);
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Wake up the device
+ * @param[in] dev A pointer to the device, returned by #atsha204a_get_dev()
+ *
+ * See datasheet §5.3.2 Synchronization Procedures.
+ *
+ * @return 0 on success, a negative value from `asm-generic/errno.h` on error.
+ */
+static int atsha204a_wakeup(struct device *dev)
+{
+ uint8_t buf = 0x00;
+ struct atsha204a_resp resp;
+ int ret;
+ struct i2c_client *client;
+
+ client = to_i2c_client(dev);
+
+ for (int i = 1; i <= 10; i++) {
+ /*
+ * The device ignores any levels or transitions on the SCL pin
+ * when the device is idle, asleep or during waking up.
+ * Generate the wake condition: set SDA low for at least t_WLO.
+ */
+ struct i2c_msg msg;
+
+ msg.addr = 0;
+ msg.flags = I2C_M_IGNORE_NAK;
+ msg.len = 1;
+ msg.buf = &buf;
+ /* don't check errors: there is always one */
+ i2c_transfer(client->adapter, &msg, 1);
+
+ udelay(ATSHA204A_TWLO_US + ATSHA204A_TWHI_US);
+
+ ret = atsha204a_recv_resp(dev, &resp);
+ if (ret == -EBADMSG) {
+ debug("%s() >> WARN: CRC error. Retrying...\n", __func__);
+ continue; /* retry on CRC error */
+ } else if (ret) {
+ printf("%s() >> ERROR: no response\n", __func__);
+ return ret;
+ }
+
+ if (resp.code != ATSHA204A_STATUS_AFTER_WAKE) {
+ printf(
+ "%s() >> ERROR: bad response, code = %02x, expected = 0x11\n",
+ __func__, resp.code);
+ return -EBADMSG;
+ }
+
+ return 0;
+ }
+
+ return -ETIMEDOUT;
+}
+
+static void atsha204a_req_crc32(struct atsha204a_req *req)
+{
+ u8 *p = (u8 *)req;
+ u16 computed_crc;
+ u16 *crc_ptr = (u16 *)&p[req->length - 1];
+
+ /* The buffer to crc16 starts at byte 1, not 0 */
+ computed_crc = atsha204a_crc16(p + 1, req->length - 2);
+
+ *crc_ptr = cpu_to_le16(computed_crc);
+}
+
+static int atsha204a_transaction(struct device *dev, struct atsha204a_req *req,
+ struct atsha204a_resp *resp)
+{
+ int ret, timeout = ATSHA204A_TRANSACTION_TIMEOUT;
+
+ ret = atsha204a_send(dev, (u8 *)req, req->length + 1);
+ if (ret) {
+ printf("%s() >> ERROR: transaction send failed\n", __func__);
+ return -EBUSY;
+ }
+
+ do {
+ udelay(ATSHA204A_EXECTIME_US);
+ ret = atsha204a_recv_resp(dev, resp);
+ if (!ret || ret == -EMSGSIZE || ret == -EBADMSG)
+ break;
+
+ debug("%s() >> polling for response "
+ "(timeout = %d)\n", __func__, timeout);
+
+ timeout -= ATSHA204A_EXECTIME_US;
+ } while (timeout > 0);
+
+ if (timeout <= 0) {
+ printf("%s() >> ERROR: transaction timed out\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ return ret;
+}
+
+static int atsha204a_read(struct device *dev, enum atsha204a_zone zone,
+ bool read32,
+ u16 addr, u8 *buffer)
+{
+ int res, retry = ATSHA204A_TRANSACTION_RETRY;
+ struct atsha204a_req req;
+ struct atsha204a_resp resp;
+
+ req.function = ATSHA204A_FUNC_COMMAND;
+ req.length = 7;
+ req.command = ATSHA204A_CMD_READ;
+
+ req.param1 = (u8)zone;
+ if (read32)
+ req.param1 |= 0x80;
+
+ req.param2 = cpu_to_le16(addr);
+
+ atsha204a_req_crc32(&req);
+
+ do {
+ res = atsha204a_transaction(dev, &req, &resp);
+ if (!res)
+ break;
+
+ debug("ATSHA204A read retry (%d)\n", retry);
+ retry--;
+ atsha204a_wakeup(dev);
+ } while (retry >= 0);
+
+ if (res) {
+ debug("ATSHA204A read failed\n");
+ return res;
+ }
+
+ if (resp.length != (read32 ? 32 : 4) + 3) {
+ debug("ATSHA204A read bad response length (%d)\n",
+ resp.length);
+ return -EBADMSG;
+ }
+
+ memcpy(buffer, ((u8 *)&resp) + 1, read32 ? 32 : 4);
+
+ return 0;
+}
+
+int atsha204_get_mac(uint8_t *buffer)
+{
+ int ret;
+ uint8_t data[4];
+ struct device *dev;
+
+ dev = atsha204a_get_dev();
+ if (dev == NULL)
+ return -ENODEV;
+
+ /* put the device to sleep to make sure it is in a defined state */
+ ret = atsha204a_sleep(dev);
+ if (ret) {
+ printf("%s() >> ERROR: can't put the device to sleep; ret = %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = atsha204a_wakeup(dev);
+ if (ret) {
+ printf("%s() >> ERROR: can't wake up the device; ret = %d\n", __func__,
+ ret);
+ return ret;
+ }
+
+ ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+ 4, data);
+ if (ret)
+ return ret;
+ for (int i = 0; i < 4; i++)
+ buffer[i] = data[i];
+
+ ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+ 5, data);
+ if (ret)
+ return ret;
+ buffer[4] = data[0];
+ buffer[5] = data[1];
+
+ atsha204a_sleep(dev);
+ debug("%s() >> MAC address: ", __func__);
+ for (int i = 0; i <= 5; i++) {
+ debug("%02x", buffer[i]);
+ if (i != 5)
+ debug(":");
+ }
+ debug("\n");
+
+ return 0;
+}
diff --git a/arch/arm/boards/enclustra-sa2/atsha204a.h b/arch/arm/boards/enclustra-sa2/atsha204a.h
new file mode 100644
index 0000000000000000000000000000000000000000..5062c7c07c587994c90a1ba8c3de5baeae94badb
--- /dev/null
+++ b/arch/arm/boards/enclustra-sa2/atsha204a.h
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#pragma once
+
+#include <linux/types.h>
+
+/**
+ * @brief Read the board MAC address from EEPROM
+ * @param[out] buffer A 6-byte buffer set to the MAC address on success
+ *
+ * If the MAC address is 20:B0:F7:0A:6C:08, `buffer[0]` equals 0x20.
+ *
+ * Read from the one-time programmable zone (OTP) of the chip:
+ * - 4 bytes at address 0x10 (32-bit word address 0x04)
+ * - 2 bytes at address 0x14 (32-bit word address 0x04)
+ *
+ * @return 0 on success, a negative value from `asm-generic/errno.h` on error.
+ */
+int atsha204_get_mac(uint8_t *buffer);
diff --git a/arch/arm/boards/enclustra-sa2/board.c b/arch/arm/boards/enclustra-sa2/board.c
index 834d0ab91871d0329af20f89a13af65e194b21c3..4629ca8c08b3046bd0bdc2f09a24d6cc006794b0 100644
--- a/arch/arm/boards/enclustra-sa2/board.c
+++ b/arch/arm/boards/enclustra-sa2/board.c
@@ -10,6 +10,11 @@
#include <fcntl.h>
#include <fs.h>
#include <mach/socfpga/cyclone5-regs.h>
+#include <net.h>
+#include "atsha204a.h"
+
+/** Enclustra's MAC address vendor prefix is 20:B0:F7 */
+#define ENCLUSTRA_PREFIX (0x20b0f7)
/*
* Ethernet PHY: Microchip/Micrel KSZ9031RNX
@@ -19,14 +24,54 @@ static int phy_fixup(struct phy_device *dev)
return 0;
}
+static void set_mac_addr(void)
+{
+ uint8_t hwaddr[6] = { 0, 0, 0, 0, 0, 0 };
+ uint32_t hwaddr_prefix;
+ /* backup MAC addresses, used if the actual one can't be read from EEPROM:
+ */
+ const uint8_t enclustra_ethaddr_def1[] = { 0x20, 0xB0, 0xF7, 0x01, 0x02,
+ 0x03 };
+
+ /* 2nd backup MAC address if required later
+ const uint8_t enclustra_ethaddr_def2[] = { 0x20, 0xB0, 0xF7, 0x01, 0x02,
+ 0x04 };
+ */
+
+ if (atsha204_get_mac(hwaddr)) {
+ printf(
+ "%s() >> ERROR: can't read MAC address from EEPROM, using default address\n",
+ __func__);
+ eth_register_ethaddr(0, enclustra_ethaddr_def1);
+ return;
+ }
+
+ debug("MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n",
+ hwaddr[0], hwaddr[1], hwaddr[2],
+ hwaddr[3], hwaddr[4], hwaddr[5]);
+
+ /* check vendor prefix and set the environment variable */
+ hwaddr_prefix = (hwaddr[0] << 16) | (hwaddr[1] << 8) | (hwaddr[2]);
+ if (hwaddr_prefix == ENCLUSTRA_PREFIX)
+ eth_register_ethaddr(0, hwaddr);
+ else {
+ printf(
+ "ERROR: invalid MAC address vendor prefix, using default address\n");
+ eth_register_ethaddr(0, enclustra_ethaddr_def1);
+ }
+}
+
static int socfpga_init(void)
{
- if (!of_machine_is_compatible("altr,socfpga-cyclone5"))
+ if (!of_machine_is_compatible("enclustra,mercury-sa2"))
return 0;
if (IS_ENABLED(CONFIG_PHYLIB))
- phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, phy_fixup);
+ phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
+ phy_fixup);
+
+ set_mac_addr();
return 0;
}
-console_initcall(socfpga_init);
+late_initcall(socfpga_init);
diff --git a/arch/arm/boards/enclustra-sa2/crc16.c b/arch/arm/boards/enclustra-sa2/crc16.c
new file mode 100644
index 0000000000000000000000000000000000000000..a94659df00fec8a61b6a0ab6497ebd925e720b4c
--- /dev/null
+++ b/arch/arm/boards/enclustra-sa2/crc16.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * crc16.c
+ */
+
+#include <linux/types.h>
+#include <linux/module.h>
+#include "crc16.h"
+
+/** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
+u16 const crc16_table[256] = {
+ 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
+ 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
+ 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
+ 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
+ 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
+ 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
+ 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
+ 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
+ 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
+ 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441,
+ 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41,
+ 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840,
+ 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41,
+ 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40,
+ 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640,
+ 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041,
+ 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240,
+ 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441,
+ 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41,
+ 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840,
+ 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41,
+ 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40,
+ 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640,
+ 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041,
+ 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241,
+ 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440,
+ 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40,
+ 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841,
+ 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40,
+ 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41,
+ 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641,
+ 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040
+};
+EXPORT_SYMBOL(crc16_table);
+
+/**
+ * crc16 - compute the CRC-16 for the data buffer
+ * @crc: previous CRC value
+ * @buffer: data pointer
+ * @len: number of bytes in the buffer
+ *
+ * Returns the updated CRC value.
+ */
+u16 crc16(u16 crc, u8 const *buffer, size_t len)
+{
+ while (len--)
+ crc = crc16_byte(crc, *buffer++);
+ return crc;
+}
+EXPORT_SYMBOL(crc16);
+
+MODULE_DESCRIPTION("CRC16 calculations");
+MODULE_LICENSE("GPL");
+
diff --git a/arch/arm/boards/enclustra-sa2/crc16.h b/arch/arm/boards/enclustra-sa2/crc16.h
new file mode 100644
index 0000000000000000000000000000000000000000..9fa74529b31787ba2434326d9ff02913c8cdf740
--- /dev/null
+++ b/arch/arm/boards/enclustra-sa2/crc16.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * crc16.h - CRC-16 routine
+ *
+ * Implements the standard CRC-16:
+ * Width 16
+ * Poly 0x8005 (x^16 + x^15 + x^2 + 1)
+ * Init 0
+ *
+ * Copyright (c) 2005 Ben Gardner <bgardner@wabtec.com>
+ */
+
+#ifndef __CRC16_H
+#define __CRC16_H
+
+#include <linux/types.h>
+
+extern u16 const crc16_table[256];
+
+extern u16 crc16(u16 crc, const u8 *buffer, size_t len);
+
+static inline u16 crc16_byte(u16 crc, const u8 data)
+{
+ return (crc >> 8) ^ crc16_table[(crc ^ data) & 0xff];
+}
+
+#endif /* __CRC16_H */
+
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index a4f859ebf3d7956697d180e15f50b3495cd4c472..fbd7d5c4abb1c6d598adf9209535f6f8fbd060e2 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -36,6 +36,7 @@ config MACH_SOCFPGA_ENCLUSTRA_AA1
config MACH_SOCFPGA_ENCLUSTRA_SA2
select ARCH_SOCFPGA_CYCLONE5
+ select BITREV
bool "Enclustra SA2"
config MACH_SOCFPGA_REFLEX_ACHILLES
--
2.43.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 06/11] boards: enclustra-sa2: read MAC address from EEPROM
2025-09-17 15:22 ` [PATCH 06/11] boards: enclustra-sa2: read MAC address from EEPROM David Picard
@ 2025-09-17 17:06 ` Alexander Shiyan
2025-09-18 6:18 ` Sascha Hauer
1 sibling, 0 replies; 30+ messages in thread
From: Alexander Shiyan @ 2025-09-17 17:06 UTC (permalink / raw)
To: David Picard; +Cc: BAREBOX
Hello.
I think we can bring the crc16() procedure into the public location
(/crypto?, /lib?).
ср, 17 сент. 2025 г. в 18:51, David Picard <david.picard@clermont.in2p3.fr>:
>
> Signed-off-by: David Picard <david.picard@clermont.in2p3.fr>
> ---
> arch/arm/boards/enclustra-sa2/Makefile | 2 +-
> arch/arm/boards/enclustra-sa2/atsha204a.c | 436 ++++++++++++++++++++++++++++++
> arch/arm/boards/enclustra-sa2/atsha204a.h | 19 ++
> arch/arm/boards/enclustra-sa2/board.c | 51 +++-
> arch/arm/boards/enclustra-sa2/crc16.c | 65 +++++
> arch/arm/boards/enclustra-sa2/crc16.h | 28 ++
> arch/arm/mach-socfpga/Kconfig | 1 +
> 7 files changed, 598 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/boards/enclustra-sa2/Makefile b/arch/arm/boards/enclustra-sa2/Makefile
> index 8c927fe291a6b3eb20a32a2db96c73f231ab4697..1448ea1266aa24a5b0404cb6379f8c2d76573079 100644
> --- a/arch/arm/boards/enclustra-sa2/Makefile
> +++ b/arch/arm/boards/enclustra-sa2/Makefile
> @@ -1,2 +1,2 @@
> -obj-y += lowlevel.o board.o
> +obj-y += lowlevel.o board.o atsha204a.o crc16.o
> pbl-y += lowlevel.o
> diff --git a/arch/arm/boards/enclustra-sa2/atsha204a.c b/arch/arm/boards/enclustra-sa2/atsha204a.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..3f445de06e73c5bdf27d2d0fc81dc6d939d5cd17
> --- /dev/null
> +++ b/arch/arm/boards/enclustra-sa2/atsha204a.c
> @@ -0,0 +1,436 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +#include "atsha204a.h"
> +#include <stdio.h>
> +#include <driver.h>
> +#include <linux/libfdt.h>
> +#include <linux/kernel.h> /* ARRAY_SIZE */
> +#include <linux/bitrev.h> /* bitrev16 */
> +#include <i2c/i2c.h>
> +#include "crc16.h"
> +
> +#define ATSHA204A_TWLO_US (60)
> +#define ATSHA204A_TWHI_US (2500)
> +#define ATSHA204A_EXECTIME_US (5000)
> +#define ATSHA204A_TRANSACTION_TIMEOUT (100000)
> +#define ATSHA204A_TRANSACTION_RETRY (5)
> +
> +enum atsha204a_status {
> + ATSHA204A_STATUS_SUCCES = 0x00,
> + ATSHA204A_STATUS_MISCOMPARE = 0x01,
> + ATSHA204A_STATUS_PARSE_ERROR = 0x03,
> + ATSHA204A_STATUS_EXEC_ERROR = 0x0F,
> + ATSHA204A_STATUS_AFTER_WAKE = 0x11,
> + ATSHA204A_STATUS_CRC_ERROR = 0xFF,
> +};
> +
> +enum atsha204a_func {
> + ATSHA204A_FUNC_RESET = 0x00,
> + ATSHA204A_FUNC_SLEEP = 0x01,
> + ATSHA204A_FUNC_IDLE = 0x02,
> + ATSHA204A_FUNC_COMMAND = 0x03,
> +};
> +
> +enum atsha204a_zone {
> + ATSHA204A_ZONE_CONFIG = 0,
> + ATSHA204A_ZONE_OTP = 1,
> + ATSHA204A_ZONE_DATA = 2,
> +};
> +
> +enum atsha204a_cmd {
> + ATSHA204A_CMD_READ = 0x02,
> + ATSHA204A_CMD_RANDOM = 0x1B,
> +};
> +
> +/**
> + * @brief A response from the device to the host
> + */
> +struct atsha204a_resp {
> + uint8_t length; /**< Number of bytes in the struct, including \a
> + length and \a code */
> + uint8_t code; /**< Op code that must match the last command */
> + uint8_t data[82]; /**< Data buffer */
> +} __packed;
> +
> +struct atsha204a_req {
> + u8 function;
> + u8 length;
> + u8 command;
> + u8 param1;
> + u16 param2;
> + u8 data[78];
> +} __packed;
> +
> +/**
> + * @brief Calculate a CRC
> + * @param[in] buffer Data on which the CRC must be calculated
> + * @param[in] len Number of bytes in \a buffer
> + *
> + * For example, afer wake-up, the data read from the device is `0x04 0x11 0x33
> + *0x43`.
> + * The 1st byte is the packet length, the 2nd byte is the op code and the last
> + * 2 bytes are the CRC, with the bytes swapped.
> + * The function must be called with the 1st 2 bytes and if it returns 0x4333,
> + * then the CRC is valid.
> + *
> + * @return The CRC.
> + */
> +static inline u16 atsha204a_crc16(const u8 *buffer, size_t len)
> +{
> + debug("%s() >> len = %u, buffer =", __func__, len);
> + for (size_t i = 0 ; i < len ; i++)
> + debug(" 0x%02x", buffer[i]);
> + debug("\n");
> + return bitrev16(crc16(0, buffer, len));
> +}
> +
> +/**
> + * @brief Get the device from the devicetree
> + * @return A pointer to the device if found, or \t NULL otherwise.
> + */
> +static struct device *atsha204a_get_dev(void)
> +{
> + struct device *dev;
> + struct i2c_client *client;
> +
> + dev = get_device_by_name("atsha204a0");
> + if (dev == NULL) {
> + printf("%s() >> ERROR: can't find device\n", __func__);
> + return NULL;
> + }
> + client = to_i2c_client(dev);
> + debug("%s() >> ATASHA204a found at I2C address 0x%02x\n", __func__,
> + client->addr);
> +
> + return dev;
> +}
> +
> +/**
> + * @brief Send one message to the device
> + * @param[in] dev A pointer to the device, returned by #atsha204a_get_dev()
> + * @param[in] buf The data to send
> + * @param[in] len The number of bytes in \a buf
> + * @return 0 on success, a negative value from `asm-generic/errno.h` on error.
> + */
> +static int atsha204a_send(struct device *dev, const uint8_t *buf, uint8_t len)
> +{
> + int ret;
> + struct i2c_client *client;
> +
> + client = to_i2c_client(dev);
> + struct i2c_msg msg[] = {
> + {
> + .addr = client->addr,
> + .buf = (uint8_t *)buf,
> + .len = len,
> + }
> + };
> + debug("%s() >> dev addr = 0x%02x\n", __func__, client->addr);
> +
> + ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +
> +/**
> + * @brief Read from the device
> + * @param[in] dev A pointer to the device, returned by #atsha204a_get_dev()
> + * @param[in] buf The data to send
> + * @param[in] len The number of bytes in \a buf
> + * @return 0 on success, a negative value from `asm-generic/errno.h` on error.
> + */
> +static int atsha204a_recv(struct device *dev, uint8_t *buf, uint8_t len)
> +{
> + int ret;
> + struct i2c_client *client;
> +
> + client = to_i2c_client(dev);
> + /* flags: this is a read operation and generate a stop condition */
> + struct i2c_msg msg[] = {
> + {
> + .addr = client->addr,
> + .buf = (uint8_t *)buf,
> + .len = len,
> + .flags = I2C_M_RD | I2C_M_STOP,
> + }
> + };
> +
> + ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
> + if (ret < 0) {
> + printf("%s() >> ERROR: ret = %d\n", __func__, ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * @brief Read from the device and check the CRC
> + * @param[in] dev A pointer to the device, returned by #atsha204a_get_dev()
> + * @param[in] resp The response from the device
> + * @return 0 on success, a negative value from `asm-generic/errno.h` on error.
> + */
> +static int atsha204a_recv_resp(struct device *dev, struct atsha204a_resp *resp)
> +{
> + int ret;
> + uint16_t resp_crc, computed_crc;
> + uint8_t *p = (uint8_t *)resp;
> +
> + ret = atsha204a_recv(dev, p, 4);
> + if (ret)
> + return ret;
> + debug("%s() >> resp:", __func__);
> + for (size_t i = 0 ; i < 4 ; i++)
> + debug(" 0x%02x", p[i]);
> + debug(
> + "\n%s() >> length=0x%02x, code=0x%02x, data[0]=0x%02x, data[1]=0x%02x\n",
> + __func__,
> + resp->length, resp->code, resp->data[0], resp->data[1]);
> +
> + if (resp->length > 4) {
> + if (resp->length > sizeof(*resp)) {
> + printf("%s() >> ERROR: resp->length %d > 4\n", __func__,
> + resp->length);
> + return -EMSGSIZE;
> + }
> + ret = atsha204a_recv(dev, p + 4, resp->length - 4);
> + if (ret)
> + return ret;
> + }
> +
> + debug("%s() >> checking CRC... resp->length = %d\n", __func__,
> + resp->length);
> + resp_crc = (uint16_t)p[resp->length - 2]
> + | (((uint16_t)p[resp->length - 1]) << 8);
> + computed_crc = atsha204a_crc16(p, resp->length - 2);
> +
> + if (resp_crc != computed_crc) {
> + printf(
> + "%s() >> ERROR: Invalid CRC. Received: 0x%04x; computed: 0x%04x\n",
> + __func__,
> + resp_crc, computed_crc);
> + return -EBADMSG;
> + }
> + debug("%s() >> CRC OK: 0x%04x\n", __func__, resp_crc);
> + return 0;
> +}
> +
> +/**
> + * @brief Put the device to sleep
> + * @param[in] dev A pointer to the device, returned by #atsha204a_get_dev()
> + * @return 0 on success, a negative value from `asm-generic/errno.h` on error.
> + */
> +static int atsha204a_sleep(struct device *dev)
> +{
> + int ret;
> + uint8_t req = ATSHA204A_FUNC_SLEEP;
> +
> + for (int i = 1 ; i < 10 ; i++) {
> + ret = atsha204a_send(dev, &req, 1);
> + if (!ret) {
> + debug("%s() >> sleeping! Trial #%d\n", __func__, i);
> + break;
> + }
> + udelay(ATSHA204A_EXECTIME_US);
> + }
> +
> + return ret;
> +}
> +
> +/**
> + * @brief Wake up the device
> + * @param[in] dev A pointer to the device, returned by #atsha204a_get_dev()
> + *
> + * See datasheet §5.3.2 Synchronization Procedures.
> + *
> + * @return 0 on success, a negative value from `asm-generic/errno.h` on error.
> + */
> +static int atsha204a_wakeup(struct device *dev)
> +{
> + uint8_t buf = 0x00;
> + struct atsha204a_resp resp;
> + int ret;
> + struct i2c_client *client;
> +
> + client = to_i2c_client(dev);
> +
> + for (int i = 1; i <= 10; i++) {
> + /*
> + * The device ignores any levels or transitions on the SCL pin
> + * when the device is idle, asleep or during waking up.
> + * Generate the wake condition: set SDA low for at least t_WLO.
> + */
> + struct i2c_msg msg;
> +
> + msg.addr = 0;
> + msg.flags = I2C_M_IGNORE_NAK;
> + msg.len = 1;
> + msg.buf = &buf;
> + /* don't check errors: there is always one */
> + i2c_transfer(client->adapter, &msg, 1);
> +
> + udelay(ATSHA204A_TWLO_US + ATSHA204A_TWHI_US);
> +
> + ret = atsha204a_recv_resp(dev, &resp);
> + if (ret == -EBADMSG) {
> + debug("%s() >> WARN: CRC error. Retrying...\n", __func__);
> + continue; /* retry on CRC error */
> + } else if (ret) {
> + printf("%s() >> ERROR: no response\n", __func__);
> + return ret;
> + }
> +
> + if (resp.code != ATSHA204A_STATUS_AFTER_WAKE) {
> + printf(
> + "%s() >> ERROR: bad response, code = %02x, expected = 0x11\n",
> + __func__, resp.code);
> + return -EBADMSG;
> + }
> +
> + return 0;
> + }
> +
> + return -ETIMEDOUT;
> +}
> +
> +static void atsha204a_req_crc32(struct atsha204a_req *req)
> +{
> + u8 *p = (u8 *)req;
> + u16 computed_crc;
> + u16 *crc_ptr = (u16 *)&p[req->length - 1];
> +
> + /* The buffer to crc16 starts at byte 1, not 0 */
> + computed_crc = atsha204a_crc16(p + 1, req->length - 2);
> +
> + *crc_ptr = cpu_to_le16(computed_crc);
> +}
> +
> +static int atsha204a_transaction(struct device *dev, struct atsha204a_req *req,
> + struct atsha204a_resp *resp)
> +{
> + int ret, timeout = ATSHA204A_TRANSACTION_TIMEOUT;
> +
> + ret = atsha204a_send(dev, (u8 *)req, req->length + 1);
> + if (ret) {
> + printf("%s() >> ERROR: transaction send failed\n", __func__);
> + return -EBUSY;
> + }
> +
> + do {
> + udelay(ATSHA204A_EXECTIME_US);
> + ret = atsha204a_recv_resp(dev, resp);
> + if (!ret || ret == -EMSGSIZE || ret == -EBADMSG)
> + break;
> +
> + debug("%s() >> polling for response "
> + "(timeout = %d)\n", __func__, timeout);
> +
> + timeout -= ATSHA204A_EXECTIME_US;
> + } while (timeout > 0);
> +
> + if (timeout <= 0) {
> + printf("%s() >> ERROR: transaction timed out\n", __func__);
> + return -ETIMEDOUT;
> + }
> +
> + return ret;
> +}
> +
> +static int atsha204a_read(struct device *dev, enum atsha204a_zone zone,
> + bool read32,
> + u16 addr, u8 *buffer)
> +{
> + int res, retry = ATSHA204A_TRANSACTION_RETRY;
> + struct atsha204a_req req;
> + struct atsha204a_resp resp;
> +
> + req.function = ATSHA204A_FUNC_COMMAND;
> + req.length = 7;
> + req.command = ATSHA204A_CMD_READ;
> +
> + req.param1 = (u8)zone;
> + if (read32)
> + req.param1 |= 0x80;
> +
> + req.param2 = cpu_to_le16(addr);
> +
> + atsha204a_req_crc32(&req);
> +
> + do {
> + res = atsha204a_transaction(dev, &req, &resp);
> + if (!res)
> + break;
> +
> + debug("ATSHA204A read retry (%d)\n", retry);
> + retry--;
> + atsha204a_wakeup(dev);
> + } while (retry >= 0);
> +
> + if (res) {
> + debug("ATSHA204A read failed\n");
> + return res;
> + }
> +
> + if (resp.length != (read32 ? 32 : 4) + 3) {
> + debug("ATSHA204A read bad response length (%d)\n",
> + resp.length);
> + return -EBADMSG;
> + }
> +
> + memcpy(buffer, ((u8 *)&resp) + 1, read32 ? 32 : 4);
> +
> + return 0;
> +}
> +
> +int atsha204_get_mac(uint8_t *buffer)
> +{
> + int ret;
> + uint8_t data[4];
> + struct device *dev;
> +
> + dev = atsha204a_get_dev();
> + if (dev == NULL)
> + return -ENODEV;
> +
> + /* put the device to sleep to make sure it is in a defined state */
> + ret = atsha204a_sleep(dev);
> + if (ret) {
> + printf("%s() >> ERROR: can't put the device to sleep; ret = %d\n",
> + __func__, ret);
> + return ret;
> + }
> +
> + ret = atsha204a_wakeup(dev);
> + if (ret) {
> + printf("%s() >> ERROR: can't wake up the device; ret = %d\n", __func__,
> + ret);
> + return ret;
> + }
> +
> + ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
> + 4, data);
> + if (ret)
> + return ret;
> + for (int i = 0; i < 4; i++)
> + buffer[i] = data[i];
> +
> + ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
> + 5, data);
> + if (ret)
> + return ret;
> + buffer[4] = data[0];
> + buffer[5] = data[1];
> +
> + atsha204a_sleep(dev);
> + debug("%s() >> MAC address: ", __func__);
> + for (int i = 0; i <= 5; i++) {
> + debug("%02x", buffer[i]);
> + if (i != 5)
> + debug(":");
> + }
> + debug("\n");
> +
> + return 0;
> +}
> diff --git a/arch/arm/boards/enclustra-sa2/atsha204a.h b/arch/arm/boards/enclustra-sa2/atsha204a.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..5062c7c07c587994c90a1ba8c3de5baeae94badb
> --- /dev/null
> +++ b/arch/arm/boards/enclustra-sa2/atsha204a.h
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +#pragma once
> +
> +#include <linux/types.h>
> +
> +/**
> + * @brief Read the board MAC address from EEPROM
> + * @param[out] buffer A 6-byte buffer set to the MAC address on success
> + *
> + * If the MAC address is 20:B0:F7:0A:6C:08, `buffer[0]` equals 0x20.
> + *
> + * Read from the one-time programmable zone (OTP) of the chip:
> + * - 4 bytes at address 0x10 (32-bit word address 0x04)
> + * - 2 bytes at address 0x14 (32-bit word address 0x04)
> + *
> + * @return 0 on success, a negative value from `asm-generic/errno.h` on error.
> + */
> +int atsha204_get_mac(uint8_t *buffer);
> diff --git a/arch/arm/boards/enclustra-sa2/board.c b/arch/arm/boards/enclustra-sa2/board.c
> index 834d0ab91871d0329af20f89a13af65e194b21c3..4629ca8c08b3046bd0bdc2f09a24d6cc006794b0 100644
> --- a/arch/arm/boards/enclustra-sa2/board.c
> +++ b/arch/arm/boards/enclustra-sa2/board.c
> @@ -10,6 +10,11 @@
> #include <fcntl.h>
> #include <fs.h>
> #include <mach/socfpga/cyclone5-regs.h>
> +#include <net.h>
> +#include "atsha204a.h"
> +
> +/** Enclustra's MAC address vendor prefix is 20:B0:F7 */
> +#define ENCLUSTRA_PREFIX (0x20b0f7)
>
> /*
> * Ethernet PHY: Microchip/Micrel KSZ9031RNX
> @@ -19,14 +24,54 @@ static int phy_fixup(struct phy_device *dev)
> return 0;
> }
>
> +static void set_mac_addr(void)
> +{
> + uint8_t hwaddr[6] = { 0, 0, 0, 0, 0, 0 };
> + uint32_t hwaddr_prefix;
> + /* backup MAC addresses, used if the actual one can't be read from EEPROM:
> + */
> + const uint8_t enclustra_ethaddr_def1[] = { 0x20, 0xB0, 0xF7, 0x01, 0x02,
> + 0x03 };
> +
> + /* 2nd backup MAC address if required later
> + const uint8_t enclustra_ethaddr_def2[] = { 0x20, 0xB0, 0xF7, 0x01, 0x02,
> + 0x04 };
> + */
> +
> + if (atsha204_get_mac(hwaddr)) {
> + printf(
> + "%s() >> ERROR: can't read MAC address from EEPROM, using default address\n",
> + __func__);
> + eth_register_ethaddr(0, enclustra_ethaddr_def1);
> + return;
> + }
> +
> + debug("MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n",
> + hwaddr[0], hwaddr[1], hwaddr[2],
> + hwaddr[3], hwaddr[4], hwaddr[5]);
> +
> + /* check vendor prefix and set the environment variable */
> + hwaddr_prefix = (hwaddr[0] << 16) | (hwaddr[1] << 8) | (hwaddr[2]);
> + if (hwaddr_prefix == ENCLUSTRA_PREFIX)
> + eth_register_ethaddr(0, hwaddr);
> + else {
> + printf(
> + "ERROR: invalid MAC address vendor prefix, using default address\n");
> + eth_register_ethaddr(0, enclustra_ethaddr_def1);
> + }
> +}
> +
> static int socfpga_init(void)
> {
> - if (!of_machine_is_compatible("altr,socfpga-cyclone5"))
> + if (!of_machine_is_compatible("enclustra,mercury-sa2"))
> return 0;
>
> if (IS_ENABLED(CONFIG_PHYLIB))
> - phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, phy_fixup);
> + phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
> + phy_fixup);
> +
> + set_mac_addr();
>
> return 0;
> }
> -console_initcall(socfpga_init);
> +late_initcall(socfpga_init);
> diff --git a/arch/arm/boards/enclustra-sa2/crc16.c b/arch/arm/boards/enclustra-sa2/crc16.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..a94659df00fec8a61b6a0ab6497ebd925e720b4c
> --- /dev/null
> +++ b/arch/arm/boards/enclustra-sa2/crc16.c
> @@ -0,0 +1,65 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * crc16.c
> + */
> +
> +#include <linux/types.h>
> +#include <linux/module.h>
> +#include "crc16.h"
> +
> +/** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
> +u16 const crc16_table[256] = {
> + 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
> + 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
> + 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
> + 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
> + 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
> + 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
> + 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
> + 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
> + 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
> + 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441,
> + 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41,
> + 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840,
> + 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41,
> + 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40,
> + 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640,
> + 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041,
> + 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240,
> + 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441,
> + 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41,
> + 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840,
> + 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41,
> + 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40,
> + 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640,
> + 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041,
> + 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241,
> + 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440,
> + 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40,
> + 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841,
> + 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40,
> + 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41,
> + 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641,
> + 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040
> +};
> +EXPORT_SYMBOL(crc16_table);
> +
> +/**
> + * crc16 - compute the CRC-16 for the data buffer
> + * @crc: previous CRC value
> + * @buffer: data pointer
> + * @len: number of bytes in the buffer
> + *
> + * Returns the updated CRC value.
> + */
> +u16 crc16(u16 crc, u8 const *buffer, size_t len)
> +{
> + while (len--)
> + crc = crc16_byte(crc, *buffer++);
> + return crc;
> +}
> +EXPORT_SYMBOL(crc16);
> +
> +MODULE_DESCRIPTION("CRC16 calculations");
> +MODULE_LICENSE("GPL");
> +
> diff --git a/arch/arm/boards/enclustra-sa2/crc16.h b/arch/arm/boards/enclustra-sa2/crc16.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..9fa74529b31787ba2434326d9ff02913c8cdf740
> --- /dev/null
> +++ b/arch/arm/boards/enclustra-sa2/crc16.h
> @@ -0,0 +1,28 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * crc16.h - CRC-16 routine
> + *
> + * Implements the standard CRC-16:
> + * Width 16
> + * Poly 0x8005 (x^16 + x^15 + x^2 + 1)
> + * Init 0
> + *
> + * Copyright (c) 2005 Ben Gardner <bgardner@wabtec.com>
> + */
> +
> +#ifndef __CRC16_H
> +#define __CRC16_H
> +
> +#include <linux/types.h>
> +
> +extern u16 const crc16_table[256];
> +
> +extern u16 crc16(u16 crc, const u8 *buffer, size_t len);
> +
> +static inline u16 crc16_byte(u16 crc, const u8 data)
> +{
> + return (crc >> 8) ^ crc16_table[(crc ^ data) & 0xff];
> +}
> +
> +#endif /* __CRC16_H */
> +
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index a4f859ebf3d7956697d180e15f50b3495cd4c472..fbd7d5c4abb1c6d598adf9209535f6f8fbd060e2 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -36,6 +36,7 @@ config MACH_SOCFPGA_ENCLUSTRA_AA1
>
> config MACH_SOCFPGA_ENCLUSTRA_SA2
> select ARCH_SOCFPGA_CYCLONE5
> + select BITREV
> bool "Enclustra SA2"
>
> config MACH_SOCFPGA_REFLEX_ACHILLES
>
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH 06/11] boards: enclustra-sa2: read MAC address from EEPROM
2025-09-17 15:22 ` [PATCH 06/11] boards: enclustra-sa2: read MAC address from EEPROM David Picard
2025-09-17 17:06 ` Alexander Shiyan
@ 2025-09-18 6:18 ` Sascha Hauer
2025-09-18 14:01 ` David Picard
1 sibling, 1 reply; 30+ messages in thread
From: Sascha Hauer @ 2025-09-18 6:18 UTC (permalink / raw)
To: David Picard; +Cc: BAREBOX
Hi David,
On Wed, Sep 17, 2025 at 05:22:09PM +0200, David Picard wrote:
> Signed-off-by: David Picard <david.picard@clermont.in2p3.fr>
> ---
> arch/arm/boards/enclustra-sa2/Makefile | 2 +-
> arch/arm/boards/enclustra-sa2/atsha204a.c | 436 ++++++++++++++++++++++++++++++
> arch/arm/boards/enclustra-sa2/atsha204a.h | 19 ++
> arch/arm/boards/enclustra-sa2/board.c | 51 +++-
> arch/arm/boards/enclustra-sa2/crc16.c | 65 +++++
> arch/arm/boards/enclustra-sa2/crc16.h | 28 ++
> arch/arm/mach-socfpga/Kconfig | 1 +
> 7 files changed, 598 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/boards/enclustra-sa2/Makefile b/arch/arm/boards/enclustra-sa2/Makefile
> index 8c927fe291a6b3eb20a32a2db96c73f231ab4697..1448ea1266aa24a5b0404cb6379f8c2d76573079 100644
> --- a/arch/arm/boards/enclustra-sa2/Makefile
> +++ b/arch/arm/boards/enclustra-sa2/Makefile
> @@ -1,2 +1,2 @@
> -obj-y += lowlevel.o board.o
> +obj-y += lowlevel.o board.o atsha204a.o crc16.o
> pbl-y += lowlevel.o
> diff --git a/arch/arm/boards/enclustra-sa2/atsha204a.c b/arch/arm/boards/enclustra-sa2/atsha204a.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..3f445de06e73c5bdf27d2d0fc81dc6d939d5cd17
> --- /dev/null
> +++ b/arch/arm/boards/enclustra-sa2/atsha204a.c
This looks like you should rather adopt the Linux driver from
drivers/crypto/atmel-sha204a.c.
Maybe you can even create a NVMEM cell for the MAC address and then no
board specific code would be needed for retrieving the MAC.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 06/11] boards: enclustra-sa2: read MAC address from EEPROM
2025-09-18 6:18 ` Sascha Hauer
@ 2025-09-18 14:01 ` David Picard
2025-09-18 14:12 ` Sascha Hauer
0 siblings, 1 reply; 30+ messages in thread
From: David Picard @ 2025-09-18 14:01 UTC (permalink / raw)
To: Sascha Hauer; +Cc: BAREBOX
Well, I'm not sure. The Linux driver only supports random number generation.
https://elixir.bootlin.com/linux/v6.16.7/source/drivers/crypto/Kconfig#L487
Le 18/09/2025 à 08:18, Sascha Hauer a écrit :
> This looks like you should rather adopt the Linux driver from
> drivers/crypto/atmel-sha204a.c.
>
> Maybe you can even create a NVMEM cell for the MAC address and then no
> board specific code would be needed for retrieving the MAC.
>
> Sascha
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 06/11] boards: enclustra-sa2: read MAC address from EEPROM
2025-09-18 14:01 ` David Picard
@ 2025-09-18 14:12 ` Sascha Hauer
2025-09-18 15:07 ` David Picard
0 siblings, 1 reply; 30+ messages in thread
From: Sascha Hauer @ 2025-09-18 14:12 UTC (permalink / raw)
To: David Picard; +Cc: BAREBOX
On Thu, Sep 18, 2025 at 04:01:54PM +0200, David Picard wrote:
> Well, I'm not sure. The Linux driver only supports random number generation.
> https://elixir.bootlin.com/linux/v6.16.7/source/drivers/crypto/Kconfig#L487
Look at the driver itself. The OTP area is registered as a sysfs entry
there, see otp_show() and atmel_sha204a_otp_read(). It seems the Kconfig
entry wasn't updated when adding OTP support.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 06/11] boards: enclustra-sa2: read MAC address from EEPROM
2025-09-18 14:12 ` Sascha Hauer
@ 2025-09-18 15:07 ` David Picard
2025-09-22 13:15 ` Sascha Hauer
0 siblings, 1 reply; 30+ messages in thread
From: David Picard @ 2025-09-18 15:07 UTC (permalink / raw)
To: Sascha Hauer; +Cc: BAREBOX
The driver has cascaded dependencies: CRYPTO_DEV_ATMEL_I2C, CRYPTO_ECDH,
CRC16, HW_RANDOM
Bringing the Linux driver and friends into Barebox is definitely way
beyond my competence...
David
Le 18/09/2025 à 16:12, Sascha Hauer a écrit :
> On Thu, Sep 18, 2025 at 04:01:54PM +0200, David Picard wrote:
>> Well, I'm not sure. The Linux driver only supports random number generation.
>> https://elixir.bootlin.com/linux/v6.16.7/source/drivers/crypto/Kconfig#L487
> Look at the driver itself. The OTP area is registered as a sysfs entry
> there, see otp_show() and atmel_sha204a_otp_read(). It seems the Kconfig
> entry wasn't updated when adding OTP support.
>
> Sascha
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 06/11] boards: enclustra-sa2: read MAC address from EEPROM
2025-09-18 15:07 ` David Picard
@ 2025-09-22 13:15 ` Sascha Hauer
2025-09-23 9:07 ` David Picard
0 siblings, 1 reply; 30+ messages in thread
From: Sascha Hauer @ 2025-09-22 13:15 UTC (permalink / raw)
To: David Picard; +Cc: BAREBOX
Hi David,
On Thu, Sep 18, 2025 at 05:07:53PM +0200, David Picard wrote:
> The driver has cascaded dependencies: CRYPTO_DEV_ATMEL_I2C, CRYPTO_ECDH,
> CRC16, HW_RANDOM
>
> Bringing the Linux driver and friends into Barebox is definitely way beyond
> my competence...
I did a quick port of the driver and just sent it to the list. Please
give it a try. I ported only the OTP part for now as the hwrng seems to
be mostly useless.
I couldn't test it due to lack of hardware, but I hope that at least I
did it good enough for you to debug it ;)
Regards,
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 06/11] boards: enclustra-sa2: read MAC address from EEPROM
2025-09-22 13:15 ` Sascha Hauer
@ 2025-09-23 9:07 ` David Picard
2025-09-23 9:40 ` Sascha Hauer
0 siblings, 1 reply; 30+ messages in thread
From: David Picard @ 2025-09-23 9:07 UTC (permalink / raw)
To: Sascha Hauer; +Cc: BAREBOX
Hi,
The driver crashes and causes immediate reset.
I could track it as far as this line:
https://git.pengutronix.de/cgit/barebox/tree/drivers/nvmem/core.c#n473
Boot log and some more details: https://paste.debian.net/1397772/
David
Le 22/09/2025 à 15:15, Sascha Hauer a écrit :
> Hi David,
>
> On Thu, Sep 18, 2025 at 05:07:53PM +0200, David Picard wrote:
>> The driver has cascaded dependencies: CRYPTO_DEV_ATMEL_I2C, CRYPTO_ECDH,
>> CRC16, HW_RANDOM
>>
>> Bringing the Linux driver and friends into Barebox is definitely way beyond
>> my competence...
> I did a quick port of the driver and just sent it to the list. Please
> give it a try. I ported only the OTP part for now as the hwrng seems to
> be mostly useless.
>
> I couldn't test it due to lack of hardware, but I hope that at least I
> did it good enough for you to debug it ;)
>
> Regards,
> Sascha
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 07/11] gpio: dw: support numbering via aliases
2025-09-17 15:22 [PATCH 00/11] ARM: boards: add support for Enclustra Mercury SA2 David Picard
` (5 preceding siblings ...)
2025-09-17 15:22 ` [PATCH 06/11] boards: enclustra-sa2: read MAC address from EEPROM David Picard
@ 2025-09-17 15:22 ` David Picard
2025-09-18 6:35 ` Sascha Hauer
2025-09-17 15:22 ` [PATCH 08/11] gpio: dw: make deep probe compatible David Picard
` (3 subsequent siblings)
10 siblings, 1 reply; 30+ messages in thread
From: David Picard @ 2025-09-17 15:22 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX; +Cc: David Picard, Ahmad Fatoum
From: Ahmad Fatoum <a.fatoum@pengutronix.de>
This device driver is OF-only, so reflect that in the Kconfig and have
it parse aliases if available to derive its id.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/gpio/Kconfig | 1 +
drivers/gpio/gpio-dw.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 7caa1aa96eb3c65982f7ecea3af07c8388bf7349..17d5587ea8cf46b1c356d5c11e1ea2c35ba8f269 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -201,6 +201,7 @@ config GPIO_TEGRA
config GPIO_DESIGNWARE
tristate "Synopsys DesignWare GPIO driver"
+ depends on OF_GPIO
help
Say Y or M here to build support for the Synopsys DesignWare APB
GPIO block.
diff --git a/drivers/gpio/gpio-dw.c b/drivers/gpio/gpio-dw.c
index e6eba6b423f5e997960ea39aff641718a8b0af42..98668c0a2d548e8dbac6e88180da25d28ae108e4 100644
--- a/drivers/gpio/gpio-dw.c
+++ b/drivers/gpio/gpio-dw.c
@@ -114,6 +114,8 @@ static int dw_gpio_add_port(struct device *dev, struct device_node *node,
chip = xzalloc(sizeof(*chip));
chip->chip.ops = &dw_gpio_ops;
+
+ dev->id = of_alias_get_id(dev->device_node, "gpio");
if (dev->id < 0)
chip->chip.base = DEVICE_ID_DYNAMIC;
else
@@ -181,7 +183,7 @@ MODULE_DEVICE_TABLE(of, dwgpio_match);
static struct driver dwgpio_driver = {
.name = "dw-apb-gpio",
.probe = dw_gpio_probe,
- .of_compatible = DRV_OF_COMPAT(dwgpio_match),
+ .of_compatible = dwgpio_match,
};
postcore_platform_driver(dwgpio_driver);
--
2.43.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 07/11] gpio: dw: support numbering via aliases
2025-09-17 15:22 ` [PATCH 07/11] gpio: dw: support numbering via aliases David Picard
@ 2025-09-18 6:35 ` Sascha Hauer
0 siblings, 0 replies; 30+ messages in thread
From: Sascha Hauer @ 2025-09-18 6:35 UTC (permalink / raw)
To: David Picard; +Cc: BAREBOX, Ahmad Fatoum
On Wed, Sep 17, 2025 at 05:22:10PM +0200, David Picard wrote:
> From: Ahmad Fatoum <a.fatoum@pengutronix.de>
>
> This device driver is OF-only, so reflect that in the Kconfig and have
> it parse aliases if available to derive its id.
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> drivers/gpio/Kconfig | 1 +
> drivers/gpio/gpio-dw.c | 4 +++-
> 2 files changed, 4 insertions(+), 1 deletion(-)
This patch is already upstream. Please rebase your series on master.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 08/11] gpio: dw: make deep probe compatible
2025-09-17 15:22 [PATCH 00/11] ARM: boards: add support for Enclustra Mercury SA2 David Picard
` (6 preceding siblings ...)
2025-09-17 15:22 ` [PATCH 07/11] gpio: dw: support numbering via aliases David Picard
@ 2025-09-17 15:22 ` David Picard
2025-09-17 15:22 ` [PATCH 09/11] boards: enclustra-sa2: enable bridges David Picard
` (2 subsequent siblings)
10 siblings, 0 replies; 30+ messages in thread
From: David Picard @ 2025-09-17 15:22 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX; +Cc: David Picard, Ahmad Fatoum
From: Ahmad Fatoum <a.fatoum@pengutronix.de>
When deep probing GPIO controller, we expect struct gpio_chip::dev to be
bound to a driver.
This is currently not the case as the driver for the parent nodes
creates devices for the child nodes and never binds a driver to them.
As the child nodes have compatibles themselves too, let's match against
proper drivers.
Reported-by: David Picard <david.picard@clermont.in2p3.fr>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/gpio/gpio-dw.c | 44 +++++++++++++++++++++++++-------------------
1 file changed, 25 insertions(+), 19 deletions(-)
diff --git a/drivers/gpio/gpio-dw.c b/drivers/gpio/gpio-dw.c
index 98668c0a2d548e8dbac6e88180da25d28ae108e4..688b2536be2bbfe28e9d173b7f907e6d89ba8de4 100644
--- a/drivers/gpio/gpio-dw.c
+++ b/drivers/gpio/gpio-dw.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <linux/device.h>
#include <errno.h>
#include <io.h>
#include <gpio.h>
@@ -104,9 +105,9 @@ static struct gpio_ops dw_gpio_ops = {
.set = dw_gpio_set,
};
-static int dw_gpio_add_port(struct device *dev, struct device_node *node,
- struct dw_gpio *parent)
+static int dw_gpio_add_port(struct device *dev)
{
+ struct dw_gpio *parent = dev_get_drvdata(dev->parent);
struct dw_gpio_instance *chip;
uint32_t config1, config2;
int ngpio, ret;
@@ -130,17 +131,7 @@ static int dw_gpio_add_port(struct device *dev, struct device_node *node,
chip->parent = parent;
chip->chip.ngpio = ngpio;
- chip->chip.dev = add_generic_device("dw-port", DEVICE_ID_DYNAMIC, NULL,
- dev->resource[0].start,
- resource_size(&dev->resource[0]),
- IORESOURCE_MEM, NULL);
-
- if (!chip->chip.dev) {
- dev_err(dev, "unable to add device\n");
- return -ENODEV;
- }
-
- chip->chip.dev->of_node = node;
+ chip->chip.dev = dev;
ret = gpiochip_add(&chip->chip);
if (ret)
@@ -152,11 +143,22 @@ static int dw_gpio_add_port(struct device *dev, struct device_node *node,
return 0;
}
+static struct of_device_id dwgpio_port_match[] = {
+ { .compatible = "snps,dw-apb-gpio-port" },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, dwgpio_port_match);
+
+static struct driver dwgpio_port_driver = {
+ .name = "dw-apb-gpio-port",
+ .probe = dw_gpio_add_port,
+ .of_compatible = dwgpio_port_match,
+};
+
static int dw_gpio_probe(struct device *dev)
{
struct resource *iores;
struct dw_gpio *gpio;
- struct device_node *node;
gpio = xzalloc(sizeof(*gpio));
@@ -165,13 +167,12 @@ static int dw_gpio_probe(struct device *dev)
return PTR_ERR(iores);
gpio->regs = IOMEM(iores->start);
- for_each_child_of_node(dev->of_node, node)
- dw_gpio_add_port(dev, node, gpio);
+ dev_set_drvdata(dev, gpio);
- return 0;
+ return of_platform_populate(dev->of_node, NULL, dev);
}
-static __maybe_unused struct of_device_id dwgpio_match[] = {
+static struct of_device_id dwgpio_match[] = {
{
.compatible = "snps,dw-apb-gpio",
}, {
@@ -186,4 +187,9 @@ static struct driver dwgpio_driver = {
.of_compatible = dwgpio_match,
};
-postcore_platform_driver(dwgpio_driver);
+static int __init dwgpio_driver_register(void)
+{
+ platform_driver_register(&dwgpio_port_driver);
+ return platform_driver_register(&dwgpio_driver);
+}
+postcore_initcall(dwgpio_driver_register);
--
2.43.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 09/11] boards: enclustra-sa2: enable bridges
2025-09-17 15:22 [PATCH 00/11] ARM: boards: add support for Enclustra Mercury SA2 David Picard
` (7 preceding siblings ...)
2025-09-17 15:22 ` [PATCH 08/11] gpio: dw: make deep probe compatible David Picard
@ 2025-09-17 15:22 ` David Picard
2025-09-18 6:37 ` Sascha Hauer
2025-09-17 15:22 ` [PATCH 10/11] boards: enclustra-sa2: configure SI5338 David Picard
2025-09-17 15:22 ` [PATCH 11/11] boards: enclustra-sa2: enable SI5338 David Picard
10 siblings, 1 reply; 30+ messages in thread
From: David Picard @ 2025-09-17 15:22 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX; +Cc: David Picard
Enable the lw-fpga2hps and fpga2hps bridges.
Signed-off-by: David Picard <david.picard@clermont.in2p3.fr>
---
arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi b/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi
index 52a9d1a6c396fb3df56acbaf99d40594dea19944..fa80b7c63d28d17a24d63ac3ee87531ad320ddb1 100644
--- a/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi
@@ -52,6 +52,16 @@ &osc1 {
clock-frequency = <50000000>;
};
+&fpga_bridge0 {
+ status = "okay";
+ bridge-enable = <0x1>;
+};
+
+&fpga_bridge1 {
+ status = "okay";
+ bridge-enable = <0x1>;
+};
+
&i2c_encl {
i2c-sda-hold-time-ns = <300>;
clock-frequency = <100000>;
--
2.43.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 10/11] boards: enclustra-sa2: configure SI5338
2025-09-17 15:22 [PATCH 00/11] ARM: boards: add support for Enclustra Mercury SA2 David Picard
` (8 preceding siblings ...)
2025-09-17 15:22 ` [PATCH 09/11] boards: enclustra-sa2: enable bridges David Picard
@ 2025-09-17 15:22 ` David Picard
2025-09-18 7:09 ` Sascha Hauer
2025-09-17 15:22 ` [PATCH 11/11] boards: enclustra-sa2: enable SI5338 David Picard
10 siblings, 1 reply; 30+ messages in thread
From: David Picard @ 2025-09-17 15:22 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX; +Cc: David Picard
Configure the SI5338 clock generator on the ST1 baseboard.
Signed-off-by: David Picard <david.picard@clermont.in2p3.fr>
---
arch/arm/boards/enclustra-sa2/Makefile | 2 +-
.../boards/enclustra-sa2/Si5338-RevB-Registers.h | 433 +++++++++++++++++++++
arch/arm/boards/enclustra-sa2/board.c | 6 +
arch/arm/boards/enclustra-sa2/si5338_config.c | 326 ++++++++++++++++
arch/arm/boards/enclustra-sa2/si5338_config.h | 22 ++
arch/arm/mach-socfpga/Kconfig | 4 +
6 files changed, 792 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boards/enclustra-sa2/Makefile b/arch/arm/boards/enclustra-sa2/Makefile
index 1448ea1266aa24a5b0404cb6379f8c2d76573079..187af1d72f026589eda92fc1c981040b0f43c98d 100644
--- a/arch/arm/boards/enclustra-sa2/Makefile
+++ b/arch/arm/boards/enclustra-sa2/Makefile
@@ -1,2 +1,2 @@
-obj-y += lowlevel.o board.o atsha204a.o crc16.o
+obj-y += lowlevel.o board.o atsha204a.o crc16.o si5338_config.o
pbl-y += lowlevel.o
diff --git a/arch/arm/boards/enclustra-sa2/Si5338-RevB-Registers.h b/arch/arm/boards/enclustra-sa2/Si5338-RevB-Registers.h
new file mode 100644
index 0000000000000000000000000000000000000000..ea9093e8601835e01391b4b19aa98787c4861b41
--- /dev/null
+++ b/arch/arm/boards/enclustra-sa2/Si5338-RevB-Registers.h
@@ -0,0 +1,433 @@
+//Register map for use with AN428 (JumpStart)
+//http://www.skyworksinc.com/timing
+//#BEGIN_HEADER
+//Date = Friday, June 09, 2023 5:03 PM
+//File version = 3
+//Software Name = ClockBuilder Pro
+//Software version = 4.9.0.0
+//Software date = 4 24, 2023
+//Chip = Si533x
+//Part Number = Si533x
+//#END_HEADER
+//Input Frequency (MHz) = 24.000000000
+//Input Type = CMOS_SSTL_HSTL
+//P1 = 1
+//Input Mux = RefClk
+//FDBK Input Frequency (MHz) = 24.000000000
+//FDBK Input Type = OFF
+//P2 = 1
+//FDBK Mux = NoClk
+//PFD Input Frequency (MHz) = 24.000000000
+//VCO Frequency (GHz) = 2.500000
+//N = 104 1/6 (104.1667)
+//Internal feedback enabled
+//Output Clock 0
+// Output Frequency (MHz) = 125.000000000
+// Mux Selection = IDn
+// MultiSynth = 20 (20.0000)
+// R = 1
+//Output Clock 1
+// Output is off
+//Output Clock 2
+// Output is off
+//Output Clock 3
+// Output Frequency (MHz) = 100.000000000
+// Mux Selection = IDn
+// MultiSynth = 25 (25.0000)
+// R = 1
+//Driver 0
+// Enabled
+// Powered on
+// Output voltage = 3.30
+// Output type = 3.3V LVDS
+// Output state when disabled = Tristate
+//Driver 1
+// Disabled
+// Powered off
+// Output voltage = 3.30
+// Output type = 3.3V LVDS
+// Output state when disabled = StopLow
+//Driver 2
+// Disabled
+// Powered off
+// Output voltage = 3.30
+// Output type = 3.3V LVDS
+// Output state when disabled = StopLow
+//Driver 3
+// Enabled
+// Powered on
+// Output voltage = 3.30
+// Output type = 3.3V CMOS on A
+// Output state when disabled = Tristate
+//Clock 0 phase inc/dec step size (ns) = 0.000
+//Clock 1 phase inc/dec step size (ns) = 0.000
+//Clock 2 phase inc/dec step size (ns) = 0.000
+//Clock 3 phase inc/dec step size (ns) = 0.000
+//Phase increment and decrement pin control is off
+//Frequency increment and decrement pin control is off
+//Frequency increment and decrement is disabled
+//Initial phase offset 0 (ns) = 0.000
+//Initial phase offset 1 (ns) = 0.000
+//Initial phase offset 2 (ns) = 0.000
+//Initial phase offset 3 (ns) = 0.000
+//SSC is disabled
+
+#define NUM_REGS_MAX 350
+
+typedef struct Reg_Data {
+ unsigned char Reg_Addr;
+ unsigned char Reg_Val;
+ unsigned char Reg_Mask;
+} Reg_Data;
+
+Reg_Data const Reg_Store[NUM_REGS_MAX] = {
+ { 0, 0x00, 0x00 },
+ { 1, 0x00, 0x00 },
+ { 2, 0x00, 0x00 },
+ { 3, 0x00, 0x00 },
+ { 4, 0x00, 0x00 },
+ { 5, 0x00, 0x00 },
+ { 6, 0x08, 0x1D },
+ { 7, 0x00, 0x00 },
+ { 8, 0x70, 0x00 },
+ { 9, 0x0F, 0x00 },
+ { 10, 0x00, 0x00 },
+ { 11, 0x00, 0x00 },
+ { 12, 0x00, 0x00 },
+ { 13, 0x00, 0x00 },
+ { 14, 0x00, 0x00 },
+ { 15, 0x00, 0x00 },
+ { 16, 0x00, 0x00 },
+ { 17, 0x00, 0x00 },
+ { 18, 0x00, 0x00 },
+ { 19, 0x00, 0x00 },
+ { 20, 0x00, 0x00 },
+ { 21, 0x00, 0x00 },
+ { 22, 0x00, 0x00 },
+ { 23, 0x00, 0x00 },
+ { 24, 0x00, 0x00 },
+ { 25, 0x00, 0x00 },
+ { 26, 0x00, 0x00 },
+ { 27, 0x70, 0x80 },
+ { 28, 0x0B, 0xFF },
+ { 29, 0x08, 0xFF },
+ { 30, 0xB0, 0xFF },
+ { 31, 0xC0, 0xFF },
+ { 32, 0xE3, 0xFF },
+ { 33, 0xE3, 0xFF },
+ { 34, 0xC0, 0xFF },
+ { 35, 0x00, 0xFF },
+ { 36, 0x06, 0x1F },
+ { 37, 0x00, 0x1F },
+ { 38, 0x00, 0x1F },
+ { 39, 0x01, 0x1F },
+ { 40, 0x63, 0xFF },
+ { 41, 0x0C, 0x7F },
+ { 42, 0x37, 0x3F },
+ { 43, 0x00, 0x00 },
+ { 44, 0x00, 0x00 },
+ { 45, 0x00, 0xFF },
+ { 46, 0x00, 0xFF },
+ { 47, 0x14, 0x3F },
+ { 48, 0x3C, 0xFF },
+ { 49, 0x00, 0xFF },
+ { 50, 0xC4, 0xFF },
+ { 51, 0x07, 0xFF },
+ { 52, 0x10, 0xFF },
+ { 53, 0x00, 0xFF },
+ { 54, 0x08, 0xFF },
+ { 55, 0x00, 0xFF },
+ { 56, 0x00, 0xFF },
+ { 57, 0x00, 0xFF },
+ { 58, 0x00, 0xFF },
+ { 59, 0x01, 0xFF },
+ { 60, 0x00, 0xFF },
+ { 61, 0x00, 0xFF },
+ { 62, 0x00, 0x3F },
+ { 63, 0x10, 0xFF },
+ { 64, 0x00, 0xFF },
+ { 65, 0x00, 0xFF },
+ { 66, 0x00, 0xFF },
+ { 67, 0x00, 0xFF },
+ { 68, 0x00, 0xFF },
+ { 69, 0x00, 0xFF },
+ { 70, 0x00, 0xFF },
+ { 71, 0x00, 0xFF },
+ { 72, 0x00, 0xFF },
+ { 73, 0x00, 0x3F },
+ { 74, 0x10, 0xFF },
+ { 75, 0x00, 0xFF },
+ { 76, 0x00, 0xFF },
+ { 77, 0x00, 0xFF },
+ { 78, 0x00, 0xFF },
+ { 79, 0x00, 0xFF },
+ { 80, 0x00, 0xFF },
+ { 81, 0x00, 0xFF },
+ { 82, 0x00, 0xFF },
+ { 83, 0x00, 0xFF },
+ { 84, 0x00, 0x3F },
+ { 85, 0x10, 0xFF },
+ { 86, 0x80, 0xFF },
+ { 87, 0x0A, 0xFF },
+ { 88, 0x00, 0xFF },
+ { 89, 0x00, 0xFF },
+ { 90, 0x00, 0xFF },
+ { 91, 0x00, 0xFF },
+ { 92, 0x01, 0xFF },
+ { 93, 0x00, 0xFF },
+ { 94, 0x00, 0xFF },
+ { 95, 0x00, 0x3F },
+ { 96, 0x10, 0x00 },
+ { 97, 0x15, 0xFF },
+ { 98, 0x32, 0xFF },
+ { 99, 0x08, 0xFF },
+ { 100, 0x00, 0xFF },
+ { 101, 0x00, 0xFF },
+ { 102, 0x00, 0xFF },
+ { 103, 0x06, 0xFF },
+ { 104, 0x00, 0xFF },
+ { 105, 0x00, 0xFF },
+ { 106, 0x80, 0xBF },
+ { 107, 0x00, 0xFF },
+ { 108, 0x00, 0xFF },
+ { 109, 0x00, 0xFF },
+ { 110, 0x00, 0xFF },
+ { 111, 0x00, 0xFF },
+ { 112, 0x00, 0xFF },
+ { 113, 0x00, 0xFF },
+ { 114, 0x40, 0xFF },
+ { 115, 0x00, 0xFF },
+ { 116, 0x80, 0xFF },
+ { 117, 0x00, 0xFF },
+ { 118, 0x40, 0xFF },
+ { 119, 0x00, 0xFF },
+ { 120, 0x00, 0xFF },
+ { 121, 0x00, 0xFF },
+ { 122, 0x00, 0xFF },
+ { 123, 0x00, 0xFF },
+ { 124, 0x00, 0xFF },
+ { 125, 0x00, 0xFF },
+ { 126, 0x00, 0xFF },
+ { 127, 0x00, 0xFF },
+ { 128, 0x00, 0xFF },
+ { 129, 0x00, 0x0F },
+ { 130, 0x00, 0x0F },
+ { 131, 0x00, 0xFF },
+ { 132, 0x00, 0xFF },
+ { 133, 0x00, 0xFF },
+ { 134, 0x00, 0xFF },
+ { 135, 0x00, 0xFF },
+ { 136, 0x00, 0xFF },
+ { 137, 0x00, 0xFF },
+ { 138, 0x00, 0xFF },
+ { 139, 0x00, 0xFF },
+ { 140, 0x00, 0xFF },
+ { 141, 0x00, 0xFF },
+ { 142, 0x00, 0xFF },
+ { 143, 0x00, 0xFF },
+ { 144, 0x00, 0xFF },
+ { 145, 0x00, 0x00 },
+ { 146, 0xFF, 0x00 },
+ { 147, 0x00, 0x00 },
+ { 148, 0x00, 0x00 },
+ { 149, 0x00, 0x00 },
+ { 150, 0x00, 0x00 },
+ { 151, 0x00, 0x00 },
+ { 152, 0x00, 0xFF },
+ { 153, 0x00, 0xFF },
+ { 154, 0x00, 0xFF },
+ { 155, 0x00, 0xFF },
+ { 156, 0x00, 0xFF },
+ { 157, 0x00, 0xFF },
+ { 158, 0x00, 0x0F },
+ { 159, 0x00, 0x0F },
+ { 160, 0x00, 0xFF },
+ { 161, 0x00, 0xFF },
+ { 162, 0x00, 0xFF },
+ { 163, 0x00, 0xFF },
+ { 164, 0x00, 0xFF },
+ { 165, 0x00, 0xFF },
+ { 166, 0x00, 0xFF },
+ { 167, 0x00, 0xFF },
+ { 168, 0x00, 0xFF },
+ { 169, 0x00, 0xFF },
+ { 170, 0x00, 0xFF },
+ { 171, 0x00, 0xFF },
+ { 172, 0x00, 0xFF },
+ { 173, 0x00, 0xFF },
+ { 174, 0x00, 0xFF },
+ { 175, 0x00, 0xFF },
+ { 176, 0x00, 0xFF },
+ { 177, 0x00, 0xFF },
+ { 178, 0x00, 0xFF },
+ { 179, 0x00, 0xFF },
+ { 180, 0x00, 0xFF },
+ { 181, 0x00, 0x0F },
+ { 182, 0x00, 0xFF },
+ { 183, 0x00, 0xFF },
+ { 184, 0x00, 0xFF },
+ { 185, 0x00, 0xFF },
+ { 186, 0x00, 0xFF },
+ { 187, 0x00, 0xFF },
+ { 188, 0x00, 0xFF },
+ { 189, 0x00, 0xFF },
+ { 190, 0x00, 0xFF },
+ { 191, 0x00, 0xFF },
+ { 192, 0x00, 0xFF },
+ { 193, 0x00, 0xFF },
+ { 194, 0x00, 0xFF },
+ { 195, 0x00, 0xFF },
+ { 196, 0x00, 0xFF },
+ { 197, 0x00, 0xFF },
+ { 198, 0x00, 0xFF },
+ { 199, 0x00, 0xFF },
+ { 200, 0x00, 0xFF },
+ { 201, 0x00, 0xFF },
+ { 202, 0x00, 0xFF },
+ { 203, 0x00, 0x0F },
+ { 204, 0x00, 0xFF },
+ { 205, 0x00, 0xFF },
+ { 206, 0x00, 0xFF },
+ { 207, 0x00, 0xFF },
+ { 208, 0x00, 0xFF },
+ { 209, 0x00, 0xFF },
+ { 210, 0x00, 0xFF },
+ { 211, 0x00, 0xFF },
+ { 212, 0x00, 0xFF },
+ { 213, 0x00, 0xFF },
+ { 214, 0x00, 0xFF },
+ { 215, 0x00, 0xFF },
+ { 216, 0x00, 0xFF },
+ { 217, 0x00, 0xFF },
+ { 218, 0x00, 0x00 },
+ { 219, 0x00, 0x00 },
+ { 220, 0x00, 0x00 },
+ { 221, 0x0D, 0x00 },
+ { 222, 0x00, 0x00 },
+ { 223, 0x00, 0x00 },
+ { 224, 0xF4, 0x00 },
+ { 225, 0xF0, 0x00 },
+ { 226, 0x00, 0x00 },
+ { 227, 0x00, 0x00 },
+ { 228, 0x00, 0x00 },
+ { 229, 0x00, 0x00 },
+ { 231, 0x00, 0x00 },
+ { 232, 0x00, 0x00 },
+ { 233, 0x00, 0x00 },
+ { 234, 0x00, 0x00 },
+ { 235, 0x00, 0x00 },
+ { 236, 0x00, 0x00 },
+ { 237, 0x00, 0x00 },
+ { 238, 0x14, 0x00 },
+ { 239, 0x00, 0x00 },
+ { 240, 0x00, 0x00 },
+ { 242, 0x02, 0x02 },
+ { 243, 0xF0, 0x00 },
+ { 244, 0x00, 0x00 },
+ { 245, 0x00, 0x00 },
+ { 247, 0x00, 0x00 },
+ { 248, 0x00, 0x00 },
+ { 249, 0xA8, 0x00 },
+ { 250, 0x00, 0x00 },
+ { 251, 0x84, 0x00 },
+ { 252, 0x00, 0x00 },
+ { 253, 0x00, 0x00 },
+ { 254, 0x00, 0x00 },
+ { 255, 1, 0xFF }, // set page bit to 1
+ { 0, 0x00, 0x00 },
+ { 1, 0x00, 0x00 },
+ { 2, 0x00, 0x00 },
+ { 3, 0x00, 0x00 },
+ { 4, 0x00, 0x00 },
+ { 5, 0x00, 0x00 },
+ { 6, 0x00, 0x00 },
+ { 7, 0x00, 0x00 },
+ { 8, 0x00, 0x00 },
+ { 9, 0x00, 0x00 },
+ { 10, 0x00, 0x00 },
+ { 11, 0x00, 0x00 },
+ { 12, 0x00, 0x00 },
+ { 13, 0x00, 0x00 },
+ { 14, 0x00, 0x00 },
+ { 15, 0x00, 0x00 },
+ { 16, 0x00, 0x00 },
+ { 17, 0x01, 0x00 },
+ { 18, 0x00, 0x00 },
+ { 19, 0x00, 0x00 },
+ { 20, 0x90, 0x00 },
+ { 21, 0x31, 0x00 },
+ { 22, 0x00, 0x00 },
+ { 23, 0x00, 0x00 },
+ { 24, 0x01, 0x00 },
+ { 25, 0x00, 0x00 },
+ { 26, 0x00, 0x00 },
+ { 27, 0x00, 0x00 },
+ { 28, 0x00, 0x00 },
+ { 29, 0x00, 0x00 },
+ { 30, 0x00, 0x00 },
+ { 31, 0x00, 0xFF },
+ { 32, 0x00, 0xFF },
+ { 33, 0x01, 0xFF },
+ { 34, 0x00, 0xFF },
+ { 35, 0x00, 0xFF },
+ { 36, 0x90, 0xFF },
+ { 37, 0x31, 0xFF },
+ { 38, 0x00, 0xFF },
+ { 39, 0x00, 0xFF },
+ { 40, 0x01, 0xFF },
+ { 41, 0x00, 0xFF },
+ { 42, 0x00, 0xFF },
+ { 43, 0x00, 0x0F },
+ { 44, 0x00, 0x00 },
+ { 45, 0x00, 0x00 },
+ { 46, 0x00, 0x00 },
+ { 47, 0x00, 0xFF },
+ { 48, 0x00, 0xFF },
+ { 49, 0x01, 0xFF },
+ { 50, 0x00, 0xFF },
+ { 51, 0x00, 0xFF },
+ { 52, 0x90, 0xFF },
+ { 53, 0x31, 0xFF },
+ { 54, 0x00, 0xFF },
+ { 55, 0x00, 0xFF },
+ { 56, 0x01, 0xFF },
+ { 57, 0x00, 0xFF },
+ { 58, 0x00, 0xFF },
+ { 59, 0x00, 0x0F },
+ { 60, 0x00, 0x00 },
+ { 61, 0x00, 0x00 },
+ { 62, 0x00, 0x00 },
+ { 63, 0x00, 0xFF },
+ { 64, 0x00, 0xFF },
+ { 65, 0x01, 0xFF },
+ { 66, 0x00, 0xFF },
+ { 67, 0x00, 0xFF },
+ { 68, 0x90, 0xFF },
+ { 69, 0x31, 0xFF },
+ { 70, 0x00, 0xFF },
+ { 71, 0x00, 0xFF },
+ { 72, 0x01, 0xFF },
+ { 73, 0x00, 0xFF },
+ { 74, 0x00, 0xFF },
+ { 75, 0x00, 0x0F },
+ { 76, 0x00, 0x00 },
+ { 77, 0x00, 0x00 },
+ { 78, 0x00, 0x00 },
+ { 79, 0x00, 0xFF },
+ { 80, 0x00, 0xFF },
+ { 81, 0x00, 0xFF },
+ { 82, 0x00, 0xFF },
+ { 83, 0x00, 0xFF },
+ { 84, 0x90, 0xFF },
+ { 85, 0x31, 0xFF },
+ { 86, 0x00, 0xFF },
+ { 87, 0x00, 0xFF },
+ { 88, 0x01, 0xFF },
+ { 89, 0x00, 0xFF },
+ { 90, 0x00, 0xFF },
+ { 91, 0x00, 0x0F },
+ { 92, 0x00, 0x00 },
+ { 93, 0x00, 0x00 },
+ { 94, 0x00, 0x00 },
+ { 255, 0, 0xFF } }; // set page bit to 0
+//End of file
diff --git a/arch/arm/boards/enclustra-sa2/board.c b/arch/arm/boards/enclustra-sa2/board.c
index 4629ca8c08b3046bd0bdc2f09a24d6cc006794b0..be3274e2ee54bbc50c9e65bf587e40f0e3519dc3 100644
--- a/arch/arm/boards/enclustra-sa2/board.c
+++ b/arch/arm/boards/enclustra-sa2/board.c
@@ -12,6 +12,7 @@
#include <mach/socfpga/cyclone5-regs.h>
#include <net.h>
#include "atsha204a.h"
+#include "si5338_config.h"
/** Enclustra's MAC address vendor prefix is 20:B0:F7 */
#define ENCLUSTRA_PREFIX (0x20b0f7)
@@ -72,6 +73,11 @@ static int socfpga_init(void)
set_mac_addr();
+#ifdef CONFIG_MACH_SOCFPGA_ENCLUSTRA_SA2_SI5338
+ /* configure clock generator on the Enclustra ST1 baseboard: */
+ si5338_init();
+#endif
+
return 0;
}
late_initcall(socfpga_init);
diff --git a/arch/arm/boards/enclustra-sa2/si5338_config.c b/arch/arm/boards/enclustra-sa2/si5338_config.c
new file mode 100644
index 0000000000000000000000000000000000000000..34174f429d5b72934164c726e4a0f309af482f54
--- /dev/null
+++ b/arch/arm/boards/enclustra-sa2/si5338_config.c
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <i2c/i2c.h>
+#include <clock.h>
+#include <linux/kernel.h> /* ARRAY_SIZE */
+#include "si5338_config.h"
+#include "Si5338-RevB-Registers.h"
+
+/**
+ * @brief Get the device from the devicetree
+ * @return A pointer to the device if found, or \t NULL otherwise.
+ */
+static struct device *get_dev(void)
+{
+ struct device *dev;
+ struct i2c_client *client;
+
+ dev = get_device_by_name("si53380");
+ if (dev == NULL) {
+ printf("%s() >> ERROR: can't find device SI5338\n", __func__);
+ return NULL;
+ }
+ client = to_i2c_client(dev);
+ debug("%s() >> SI5338 found at I2C address 0x%02x\n", __func__,
+ client->addr);
+
+ return dev;
+}
+
+/**
+ * @brief Write a single byte to a register in the SI5338
+ * @param[in] dev The I²C device.
+ * @param[in] addr The register address.
+ * @param[in] data The byte to be written to the register.
+ * @return 0 on success, a negative value from `asm-generic/errno.h` on error.
+ */
+static int i2c_write_simple(struct device *dev, u8 addr, u8 data)
+{
+ int ret;
+ struct i2c_client *client;
+
+ client = to_i2c_client(dev);
+ u8 buffer[2];
+
+ buffer[0] = addr;
+ buffer[1] = data;
+
+ struct i2c_msg msg[] = {
+ {
+ .addr = client->addr,
+ .buf = buffer,
+ .len = 2,
+ .flags = 0,
+ }
+ };
+ debug("%s() >> dev addr = 0x%02x\n", __func__, client->addr);
+
+ ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
+ if (ret < 0) {
+ printf("%s() >> ERROR: SI5338 write failed addr: %02x, data: %02x\n",
+ __func__, addr,
+ data);
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * @brief Change some bits in a register in the SI5338
+ * @param[in] dev The I²C device.
+ * @param[in] addr The register address.
+ * @param[in] data The byte to be written to the register.
+ * @param[in] mask Sets which bits in the register will change.
+ *
+ * The bits in the register are allowed to change if the corresponding bit in \a
+ *mask is 1.
+ *
+ * @return 0 on success, a negative value from `asm-generic/errno.h` on error.
+ */
+static int i2c_write_masked(struct device *dev, u8 addr, u8 data, u8 mask)
+{
+ if (mask == 0x00)
+ return 0;
+ if (mask == 0xff)
+ return i2c_write_simple(dev, addr, data);
+
+ int ret;
+ struct i2c_client *client;
+
+ client = to_i2c_client(dev);
+ u8 buffer[2];
+
+ buffer[0] = addr;
+ buffer[1] = data;
+ struct i2c_msg msg[] = {
+ {
+ .addr = client->addr,
+ .buf = buffer,
+ .len = 2,
+ .flags = I2C_M_RD,
+ }
+ };
+
+ ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
+ if (ret < 0) {
+ printf("%s() >> ERROR: SI5338 read failed addr: %02x\n", __func__,
+ addr);
+ return ret;
+ }
+ msg[0].buf[1] &= ~mask;
+ msg[0].buf[1] |= data & mask;
+ msg[0].flags &= ~I2C_M_RD;
+ ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
+ if (ret < 0) {
+ printf("%s() >> ERROR: SI5338 write failed addr: %02x, data: %02x\n",
+ __func__, addr,
+ data);
+ return ret;
+ }
+ return 0;
+}
+
+/**
+ * @brief Read a single byte from a register in the SI5338
+ * @param[in] dev The I²C device.
+ * @param[in] addr The register address.
+ * @param[out] data The byte read from the register.
+ * @return 0 on success, a negative value from `asm-generic/errno.h` on error.
+ */
+static int i2c_read_register(struct device *dev, u8 addr, u8 *data)
+{
+ int ret;
+ struct i2c_client *client;
+
+ client = to_i2c_client(dev);
+ u8 buffer[2];
+
+ buffer[0] = addr;
+ buffer[1] = 0x00;
+ struct i2c_msg msg[] = {
+ {
+ .addr = client->addr,
+ .buf = buffer,
+ .len = 2,
+ .flags = I2C_M_RD,
+ }
+ };
+
+ ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
+ if (ret < 0) {
+ printf("%s() >> ERROR: SI5338 read failed addr: %02x\n", __func__,
+ addr);
+ return ret;
+ }
+ *data = msg[0].buf[1];
+
+ return 0;
+}
+
+/**
+ * @brief Validate input clock status
+ * @param[in] dev The I²C device.
+ *
+ * Loop until the \c LOS_CLKIN bit is clear.
+ *
+ * @return 0 on success, a negative value from `asm-generic/errno.h` on error.
+ */
+static int check_input_clock(struct device *dev)
+{
+ // validate input clock status
+ int ret;
+ struct i2c_client *client;
+
+ client = to_i2c_client(dev);
+ u8 buffer[2] = { 218, 0 };
+ struct i2c_msg msg[] = {
+ {
+ .addr = client->addr,
+ .buf = buffer,
+ .len = 2,
+ .flags = I2C_M_RD,
+ }
+ };
+
+ do {
+ ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
+ if (ret < 0) {
+ printf("%s() >> ERROR: SI5338 read failed addr: %02x\n", __func__,
+ msg[0].addr);
+ return ret;
+ }
+ } while (msg[0].buf[1] & 0x04);
+
+ return 0;
+}
+
+/**
+ * @brief Check output PLL status
+ * @param[in] dev The I²C device.
+ *
+ * Loop until the \c PLL_LOL, \c LOS_CLKIN and \c SYS_CAL bits are clear.
+ *
+ * @return 0 on success, a negative value from `asm-generic/errno.h` on error
+ * (-EIO if too many trials).
+ */
+static int check_pll(struct device *dev)
+{
+ int ret;
+ int try = 0;
+ u8 data;
+
+ do {
+ ret = i2c_read_register(dev, 218, &data);
+ if (ret < 0)
+ return ret;
+ mdelay(100);
+ try++;
+ if (try > 10) {
+ printf("%s() >> ERROR: SI5338 PLL is not locking\n", __func__);
+ return -EIO;
+ }
+ } while (data & 0x15);
+
+ return 0;
+}
+
+int si5338_init(void)
+{
+ unsigned char buf[1];
+ struct device *dev;
+ int ret;
+
+ dev = get_dev();
+ if (dev == NULL)
+ return -ENODEV;
+
+ /* Set PAGE_SEL bit to 0. If bit is 1, registers with address
+ * greater than 255 can be addressed.
+ */
+ if (i2c_write_simple(dev, 255, 0x00))
+ return -1;
+
+ // disable outputs
+ if (i2c_write_masked(dev, 230, 0x10, 0x10))
+ return -1;
+
+ // pause lol
+ if (i2c_write_masked(dev, 241, 0x80, 0x80))
+ return -1;
+
+ // write new configuration
+ for (int i = 0; i < NUM_REGS_MAX; i++)
+ if (i2c_write_masked(dev, Reg_Store[i].Reg_Addr, Reg_Store[i].Reg_Val,
+ Reg_Store[i].Reg_Mask))
+ return -1;
+
+ ret = check_input_clock(dev);
+ if (ret)
+ return ret;
+
+ // configure PLL for locking
+ ret = i2c_write_masked(dev, 49, 0, 0x80);
+ if (ret)
+ return ret;
+
+ // initiate locking of PLL
+ ret = i2c_write_simple(dev, 246, 0x02);
+ if (ret)
+ return ret;
+
+ // wait 25ms (100ms to be on the safe side)
+ mdelay(100);
+
+ // restart lol
+ ret = i2c_write_masked(dev, 241, 0x65, 0xff);
+ if (ret)
+ return ret;
+
+ ret = check_pll(dev);
+ if (ret)
+ return ret;
+
+ // copy fcal values to active registers: FCAL[17:16]
+ ret = i2c_read_register(dev, 237, buf);
+ if (ret)
+ return ret;
+ ret = i2c_write_masked(dev, 47, buf[0], 0x03);
+ if (ret)
+ return ret;
+
+ // copy fcal values to active registers: FCAL[15:8]
+ ret = i2c_read_register(dev, 236, buf);
+ if (ret)
+ return ret;
+ ret = i2c_write_simple(dev, 46, buf[0]);
+ if (ret)
+ return ret;
+
+ // copy fcal values to active registers: FCAL[7:0]
+ ret = i2c_read_register(dev, 235, buf);
+ if (ret)
+ return ret;
+ ret = i2c_write_simple(dev, 45, buf[0]);
+ if (ret)
+ return ret;
+
+ // Must write 000101b to these bits if the device is not factory programmed
+ ret = i2c_write_masked(dev, 47, 0x14, 0xFC);
+ if (ret)
+ return ret;
+
+ // set PLL to use FCAL values
+ ret = i2c_write_masked(dev, 49, 0x80, 0x80);
+ if (ret)
+ return ret;
+
+ // enable outputs
+ ret = i2c_write_simple(dev, 230, 0x00);
+ if (ret)
+ return ret;
+
+ printf("SI5338 init successful\n");
+
+ return 0;
+}
diff --git a/arch/arm/boards/enclustra-sa2/si5338_config.h b/arch/arm/boards/enclustra-sa2/si5338_config.h
new file mode 100644
index 0000000000000000000000000000000000000000..2acbba1dae11ada786182473a933e2eacd18ac67
--- /dev/null
+++ b/arch/arm/boards/enclustra-sa2/si5338_config.h
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/*
+ * Initialize the Si5338 clock generator.
+ *
+ * Datasheet: https://www.skyworksinc.com/en/application-pages/-/media/SkyWorks/SL/documents/public/data-sheets/Si5338.pdf
+ * Reference manual: https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/reference-manuals/Si5338-RM.pdf
+ */
+
+#pragma once
+
+/**
+ * @brief Initialize the SI5338
+ *
+ * Get the I²C address from the devicetree and write the registers of the
+ * SI5338 after the configuration in \c Si5338-RevB-Registers.h, generated
+ * by [ClockBuilder Pro](https://www.skyworksinc.com/Application-Pages/Clockbuilder-Pro-Software).
+ *
+ * @return 0 on success, a negative value from `asm-generic/errno.h` on error.
+ */
+
+int si5338_init(void);
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index fbd7d5c4abb1c6d598adf9209535f6f8fbd060e2..5060fc9b72af39d9e3d8ab3eca4b6fae37e62cef 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -39,6 +39,10 @@ config MACH_SOCFPGA_ENCLUSTRA_SA2
select BITREV
bool "Enclustra SA2"
+config MACH_SOCFPGA_ENCLUSTRA_SA2_SI5338
+ depends on MACH_SOCFPGA_ENCLUSTRA_SA2
+ bool "Configure the SI5338 clock generator on ST1 baseboard"
+
config MACH_SOCFPGA_REFLEX_ACHILLES
select ARCH_SOCFPGA_ARRIA10
bool "Reflex Achilles"
--
2.43.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 10/11] boards: enclustra-sa2: configure SI5338
2025-09-17 15:22 ` [PATCH 10/11] boards: enclustra-sa2: configure SI5338 David Picard
@ 2025-09-18 7:09 ` Sascha Hauer
2025-09-18 13:23 ` David Picard
0 siblings, 1 reply; 30+ messages in thread
From: Sascha Hauer @ 2025-09-18 7:09 UTC (permalink / raw)
To: David Picard; +Cc: BAREBOX
On Wed, Sep 17, 2025 at 05:22:13PM +0200, David Picard wrote:
> Configure the SI5338 clock generator on the ST1 baseboard.
>
> Signed-off-by: David Picard <david.picard@clermont.in2p3.fr>
> ---
> arch/arm/boards/enclustra-sa2/Makefile | 2 +-
> .../boards/enclustra-sa2/Si5338-RevB-Registers.h | 433 +++++++++++++++++++++
> arch/arm/boards/enclustra-sa2/board.c | 6 +
> arch/arm/boards/enclustra-sa2/si5338_config.c | 326 ++++++++++++++++
> arch/arm/boards/enclustra-sa2/si5338_config.h | 22 ++
> arch/arm/mach-socfpga/Kconfig | 4 +
> 6 files changed, 792 insertions(+), 1 deletion(-)
>
> +/**
> + * @brief Write a single byte to a register in the SI5338
> + * @param[in] dev The I²C device.
> + * @param[in] addr The register address.
> + * @param[in] data The byte to be written to the register.
> + * @return 0 on success, a negative value from `asm-generic/errno.h` on error.
> + */
> +static int i2c_write_simple(struct device *dev, u8 addr, u8 data)
> +{
> + int ret;
> + struct i2c_client *client;
> +
> + client = to_i2c_client(dev);
> + u8 buffer[2];
> +
> + buffer[0] = addr;
> + buffer[1] = data;
> +
> + struct i2c_msg msg[] = {
> + {
> + .addr = client->addr,
> + .buf = buffer,
> + .len = 2,
> + .flags = 0,
> + }
> + };
> + debug("%s() >> dev addr = 0x%02x\n", __func__, client->addr);
> +
> + ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
> + if (ret < 0) {
> + printf("%s() >> ERROR: SI5338 write failed addr: %02x, data: %02x\n",
> + __func__, addr,
> + data);
> + return ret;
> + }
> +
> + return 0;
> +}
This looks like it could greatly benefit from regmap. Look for
regmap_init_i2c(). It will give you most of the boiler plate here for
free.
The above will become regmap_write()
> +
> +/**
> + * @brief Change some bits in a register in the SI5338
> + * @param[in] dev The I²C device.
> + * @param[in] addr The register address.
> + * @param[in] data The byte to be written to the register.
> + * @param[in] mask Sets which bits in the register will change.
> + *
> + * The bits in the register are allowed to change if the corresponding bit in \a
> + *mask is 1.
> + *
> + * @return 0 on success, a negative value from `asm-generic/errno.h` on error.
> + */
> +static int i2c_write_masked(struct device *dev, u8 addr, u8 data, u8 mask)
Could be replaced by regmap_update_bits(), regmap_set_bits(),
regmap_clear_bits().
> +static int i2c_read_register(struct device *dev, u8 addr, u8 *data)
regmap_read()
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index fbd7d5c4abb1c6d598adf9209535f6f8fbd060e2..5060fc9b72af39d9e3d8ab3eca4b6fae37e62cef 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -39,6 +39,10 @@ config MACH_SOCFPGA_ENCLUSTRA_SA2
> select BITREV
> bool "Enclustra SA2"
>
> +config MACH_SOCFPGA_ENCLUSTRA_SA2_SI5338
> + depends on MACH_SOCFPGA_ENCLUSTRA_SA2
> + bool "Configure the SI5338 clock generator on ST1 baseboard"
> +
Why is this optional? Is this not available on all board variants?
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 11/11] boards: enclustra-sa2: enable SI5338
2025-09-17 15:22 [PATCH 00/11] ARM: boards: add support for Enclustra Mercury SA2 David Picard
` (9 preceding siblings ...)
2025-09-17 15:22 ` [PATCH 10/11] boards: enclustra-sa2: configure SI5338 David Picard
@ 2025-09-17 15:22 ` David Picard
10 siblings, 0 replies; 30+ messages in thread
From: David Picard @ 2025-09-17 15:22 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX; +Cc: David Picard
The clock generator SI5338 is not implemented on the SA2 module itself,
but on e.g. the ST1 baseboard.
Signed-off-by: David Picard <david.picard@clermont.in2p3.fr>
---
arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi b/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi
index fa80b7c63d28d17a24d63ac3ee87531ad320ddb1..81d4a4b0bc556e562a2ef336961d6cd3f3f86af0 100644
--- a/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi
@@ -77,6 +77,12 @@ atsha204a: atsha204a@64 {
compatible = "atmel,atsha204a";
reg = <0x64>;
};
+
+ si5338: si5338@70 {
+ status = "okay";
+ compatible = "silabs,si5338";
+ reg = <0x70>;
+ };
};
&i2c_encl_fpga {
--
2.43.0
^ permalink raw reply related [flat|nested] 30+ messages in thread