From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH 7/9] drm/i915/dsb: s/intel_dsb_wait_vblank_delay/intel_dsb_wait_for_scl_lines
Date: Mon, 22 Sep 2025 13:32:40 +0300 [thread overview]
Message-ID: <aNElyOcbD6F8h7It@intel.com> (raw)
In-Reply-To: <20250921043535.2012978-8-ankit.k.nautiyal@intel.com>
On Sun, Sep 21, 2025 at 10:05:33AM +0530, Ankit Nautiyal wrote:
> The helper intel_dsb_wait_vblank_delay() is used in DSB to wait for SCL
> lines after the send push operation. Rename it to
> intel_dsb_wait_for_scl_lines() to align with the semantics.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dsb.c | 11 +++++------
> drivers/gpu/drm/i915/display/intel_dsb.h | 4 ++--
> 4 files changed, 9 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 671db6926e4c..4defd2425837 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -2013,7 +2013,7 @@ void intel_color_prepare_commit(struct intel_atomic_state *state,
>
> if (crtc_state->use_dsb && intel_color_uses_chained_dsb(crtc_state)) {
> intel_vrr_send_push(crtc_state->dsb_color, crtc_state);
> - intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color);
> + intel_dsb_wait_for_scl_lines(state, crtc_state->dsb_color);
> intel_vrr_check_push_sent(crtc_state->dsb_color, crtc_state);
> intel_dsb_interrupt(crtc_state->dsb_color);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 455bbebb50a5..bfeec3706f35 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7268,7 +7268,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
> intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
>
> intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
> - intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);
> + intel_dsb_wait_for_scl_lines(state, new_crtc_state->dsb_commit);
> intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
> new_crtc_state);
> intel_dsb_interrupt(new_crtc_state->dsb_commit);
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index dfe928aefdcd..400dcc87a992 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -115,8 +115,8 @@ static bool pre_commit_is_vrr_active(struct intel_atomic_state *state,
> return old_crtc_state->vrr.enable && !intel_crtc_vrr_disabling(state, crtc);
> }
>
> -static int dsb_vblank_delay(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +static int dsb_scl_delay(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> const struct intel_crtc_state *crtc_state =
> intel_pre_commit_crtc_state(state, crtc);
> @@ -815,15 +815,14 @@ void intel_dsb_chain(struct intel_atomic_state *state,
> wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0);
> }
>
> -void intel_dsb_wait_vblank_delay(struct intel_atomic_state *state,
> - struct intel_dsb *dsb)
> +void intel_dsb_wait_for_scl_lines(struct intel_atomic_state *state,
> + struct intel_dsb *dsb)
I'd leave this name as is for now. Or perhaps we should call it
intel_dsb_wait_for_delayed_vblank().
The actual behaviour of this will need to be slightly different between
the different timings generators/refresh rate modes so it can't just
wait for SCL lines in all the cases.
> {
> struct intel_crtc *crtc = dsb->crtc;
> const struct intel_crtc_state *crtc_state =
> intel_pre_commit_crtc_state(state, crtc);
> int usecs = intel_scanlines_to_usecs(&crtc_state->hw.adjusted_mode,
> - dsb_vblank_delay(state, crtc));
> -
> + dsb_scl_delay(state, crtc));
> intel_dsb_wait_usec(dsb, usecs);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
> index c8f4499916eb..1cb5ba1a0534 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
> @@ -48,8 +48,8 @@ void intel_dsb_nonpost_end(struct intel_dsb *dsb);
> void intel_dsb_interrupt(struct intel_dsb *dsb);
> void intel_dsb_wait_usec(struct intel_dsb *dsb, int count);
> void intel_dsb_wait_vblanks(struct intel_dsb *dsb, int count);
> -void intel_dsb_wait_vblank_delay(struct intel_atomic_state *state,
> - struct intel_dsb *dsb);
> +void intel_dsb_wait_for_scl_lines(struct intel_atomic_state *state,
> + struct intel_dsb *dsb);
> void intel_dsb_wait_scanline_in(struct intel_atomic_state *state,
> struct intel_dsb *dsb,
> int lower, int upper);
> --
> 2.45.2
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2025-09-22 10:32 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-21 4:35 [PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic Ankit Nautiyal
2025-09-21 4:35 ` [PATCH 1/9] drm/i915/psr: s/intel_psr_min_vblank_delay/intel_psr_min_set_context_latency Ankit Nautiyal
2025-09-22 9:51 ` Ville Syrjälä
2025-09-21 4:35 ` [PATCH 2/9] drm/i915/display: Add set_context_latency to crtc_state->vrr Ankit Nautiyal
2025-09-22 10:00 ` Ville Syrjälä
2025-09-23 10:47 ` Nautiyal, Ankit K
2025-09-21 4:35 ` [PATCH 3/9] drm/i915/display: Use VBLANK_START to get the vblank delay for TGL Ankit Nautiyal
2025-09-22 10:07 ` Ville Syrjälä
2025-09-22 10:20 ` Nautiyal, Ankit K
2025-09-22 11:01 ` Ville Syrjälä
2025-09-21 4:35 ` [PATCH 4/9] drm/i915/vrr: Use set_context_latency instead of intel_vrr_real_vblank_delay() Ankit Nautiyal
2025-09-22 10:14 ` Ville Syrjälä
2025-09-23 10:48 ` Nautiyal, Ankit K
2025-09-21 4:35 ` [PATCH 5/9] drm/i915/vrr: s/intel_vrr_vblank_delay/intel_vrr_scl_delay Ankit Nautiyal
2025-09-21 4:35 ` [PATCH 6/9] drm/i915/display: Use set context latency in evasion logic Ankit Nautiyal
2025-09-22 10:18 ` Ville Syrjälä
2025-09-22 11:19 ` Ville Syrjälä
2025-09-22 11:30 ` Ville Syrjälä
2025-09-23 10:50 ` Nautiyal, Ankit K
2025-09-21 4:35 ` [PATCH 7/9] drm/i915/dsb: s/intel_dsb_wait_vblank_delay/intel_dsb_wait_for_scl_lines Ankit Nautiyal
2025-09-22 10:32 ` Ville Syrjälä [this message]
2025-09-23 10:52 ` Nautiyal, Ankit K
2025-09-21 4:35 ` [PATCH 8/9] drm/i915/display: Wait for scl start instead of dsb_wait_vblanks Ankit Nautiyal
2025-09-22 10:26 ` Ville Syrjälä
2025-09-22 13:34 ` Nautiyal, Ankit K
2025-09-22 13:44 ` Ville Syrjälä
2025-09-22 13:49 ` Ville Syrjälä
2025-09-22 14:04 ` Ville Syrjälä
2025-09-23 10:55 ` Nautiyal, Ankit K
2025-09-21 4:35 ` [PATCH 9/9] drm/i915/vrr: Clamp guardband as per hardware and timing constraints Ankit Nautiyal
2025-09-22 10:57 ` Ville Syrjälä
2025-09-23 10:32 ` Nautiyal, Ankit K
2025-09-23 11:45 ` Ville Syrjälä
2025-09-21 4:58 ` ✓ CI.KUnit: success for Introduce set_context_latency and refactor VRR/DSB timing logic Patchwork
2025-09-21 5:13 ` ✗ CI.checksparse: warning " Patchwork
2025-09-21 5:33 ` ✗ Xe.CI.BAT: failure " Patchwork
2025-09-21 6:04 ` ✗ i915.CI.BAT: " Patchwork
2025-09-21 6:47 ` ✗ Xe.CI.Full: " Patchwork
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