From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH 3/9] drm/i915/display: Use VBLANK_START to get the vblank delay for TGL
Date: Mon, 22 Sep 2025 13:07:45 +0300 [thread overview]
Message-ID: <aNEf8XAdjowLeBUk@intel.com> (raw)
In-Reply-To: <20250921043535.2012978-4-ankit.k.nautiyal@intel.com>
On Sun, Sep 21, 2025 at 10:05:29AM +0530, Ankit Nautiyal wrote:
> For TGL the TRANS_SET_CONTEXT_LATENCY doesn't exist to account for SCL.
> However, the VBLANK_START-VACTIVE diffence plays an identical role here ie.
> it can be used to create the SCL window ahead of the undelayed vblank.
>
> While readback there is no specific register to read out the SCL, so use
> the same helper intel_crtc_compute_scl() and reduce the vblank_start by
> this amount.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 5a7794387ea2..455bbebb50a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2822,6 +2822,16 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
> adjusted_mode->crtc_vblank_end += 1;
> }
>
> + if (DISPLAY_VER(display) == 12) {
> + /*
> + * There is no specific register for SCL for TGL.
> + * Derive the value from the helper intel_crtc_set_context_latency().
> + * crtc_vblank_start needs to be reduced with this amount.
> + */
> + pipe_config->set_context_latency = intel_crtc_set_context_latency(pipe_config);
That thing *computes* the SCL, it doesn't teel us what the
current hw value is.
> + adjusted_mode->crtc_vblank_start -= pipe_config->set_context_latency;
> + }
> +
> if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder)) {
> pipe_config->set_context_latency =
> intel_de_read(display,
I think this whole thing needs to look something like this:
if (DISPLAY_VER >= 13 && !dsi) {
set_context_latency = read(TRANS_SET_CONTEXT_LATENCY);
crtc_vblank_start = crtc_vdisplay + set_set_context_latency;
} else if (DISPLAY_VER >= 12) {
set_context_latency = crtc_vblank_start - crtc_vdisplay;
}
That'll also cover DSI (not that the DSI code itself is actually
ready for SCL...).
And I think you need to squash this into the set_context_latency
patch. Otherwise we'll get state checker mismatches on TGL in
between.
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2025-09-22 10:07 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-21 4:35 [PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic Ankit Nautiyal
2025-09-21 4:35 ` [PATCH 1/9] drm/i915/psr: s/intel_psr_min_vblank_delay/intel_psr_min_set_context_latency Ankit Nautiyal
2025-09-22 9:51 ` Ville Syrjälä
2025-09-21 4:35 ` [PATCH 2/9] drm/i915/display: Add set_context_latency to crtc_state->vrr Ankit Nautiyal
2025-09-22 10:00 ` Ville Syrjälä
2025-09-23 10:47 ` Nautiyal, Ankit K
2025-09-21 4:35 ` [PATCH 3/9] drm/i915/display: Use VBLANK_START to get the vblank delay for TGL Ankit Nautiyal
2025-09-22 10:07 ` Ville Syrjälä [this message]
2025-09-22 10:20 ` Nautiyal, Ankit K
2025-09-22 11:01 ` Ville Syrjälä
2025-09-21 4:35 ` [PATCH 4/9] drm/i915/vrr: Use set_context_latency instead of intel_vrr_real_vblank_delay() Ankit Nautiyal
2025-09-22 10:14 ` Ville Syrjälä
2025-09-23 10:48 ` Nautiyal, Ankit K
2025-09-21 4:35 ` [PATCH 5/9] drm/i915/vrr: s/intel_vrr_vblank_delay/intel_vrr_scl_delay Ankit Nautiyal
2025-09-21 4:35 ` [PATCH 6/9] drm/i915/display: Use set context latency in evasion logic Ankit Nautiyal
2025-09-22 10:18 ` Ville Syrjälä
2025-09-22 11:19 ` Ville Syrjälä
2025-09-22 11:30 ` Ville Syrjälä
2025-09-23 10:50 ` Nautiyal, Ankit K
2025-09-21 4:35 ` [PATCH 7/9] drm/i915/dsb: s/intel_dsb_wait_vblank_delay/intel_dsb_wait_for_scl_lines Ankit Nautiyal
2025-09-22 10:32 ` Ville Syrjälä
2025-09-23 10:52 ` Nautiyal, Ankit K
2025-09-21 4:35 ` [PATCH 8/9] drm/i915/display: Wait for scl start instead of dsb_wait_vblanks Ankit Nautiyal
2025-09-22 10:26 ` Ville Syrjälä
2025-09-22 13:34 ` Nautiyal, Ankit K
2025-09-22 13:44 ` Ville Syrjälä
2025-09-22 13:49 ` Ville Syrjälä
2025-09-22 14:04 ` Ville Syrjälä
2025-09-23 10:55 ` Nautiyal, Ankit K
2025-09-21 4:35 ` [PATCH 9/9] drm/i915/vrr: Clamp guardband as per hardware and timing constraints Ankit Nautiyal
2025-09-22 10:57 ` Ville Syrjälä
2025-09-23 10:32 ` Nautiyal, Ankit K
2025-09-23 11:45 ` Ville Syrjälä
2025-09-21 4:58 ` ✓ CI.KUnit: success for Introduce set_context_latency and refactor VRR/DSB timing logic Patchwork
2025-09-21 5:13 ` ✗ CI.checksparse: warning " Patchwork
2025-09-21 5:33 ` ✗ Xe.CI.BAT: failure " Patchwork
2025-09-21 6:04 ` ✗ i915.CI.BAT: " Patchwork
2025-09-21 6:47 ` ✗ Xe.CI.Full: " Patchwork
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