Re: [RFC PATCH 07/16] hw/arm/tegra241-cmdqv: Add read emulation support for registers

[Nicolin Chen <nicolinc@nvidia.com>]

On Wed, Dec 10, 2025 at 01:37:28PM +0000, Shameer Kolothum wrote:
> +/* Note that offset aligns down to 0x10000 */
> +static uint64_t tegra241_cmdqv_read_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset,
> +                                          int index)
> +{
> +    uint32_t *ptr = NULL;
> +    uint64_t off;
> +
> +    /*
> +     * Each VCMDQ instance occupies a 128 byte region (0x80).
> +     * The hardware layout is:
> +     *   vcmdq_page0 + (index * 0x80) + (offset - 0x10000)
> +     */
> +    if (cmdqv->vcmdq_page0) {
> +        off = (0x80 * index) + (offset - 0x10000);
> +        ptr = (uint32_t *)(cmdqv->vcmdq_page0 + off);
> +    }
> +
> +    switch (offset) {
> +    case A_VCMDQ0_CONS_INDX:
> +        if (ptr) {
> +            cmdqv->vcmdq_cons_indx[index] = *ptr;
> +        }
> +        return cmdqv->vcmdq_cons_indx[index];

I forgot the details. But this seems a deadcode:
+        if (ptr) {
+            cmdqv->vcmdq_cons_indx[index] = *ptr;
+        }
?

> +/* i = [0, 0], j = [0, 3] */
> +#define A_VINTFi_LVCMDQ_ERR_MAP_(i, j)                               \
> +    REG32(VINTF##i##_LVCMDQ_ERR_MAP_##j, 0x10c0 + j * 4 + i * 0x100) \
> +    FIELD(VINTF##i##_LVCMDQ_ERR_MAP_##j, LVCMDQ_ERR_MAP, 0, 32)
> +
> +        A_VINTFi_LVCMDQ_ERR_MAP_(0, 0)
> +    /* Omitting [0][1~2] as not being directly called */
> +    A_VINTFi_LVCMDQ_ERR_MAP_(0, 3)

The indentations at 0 is odd related to 3. And should fix all the
following macros too.

Nicolin