From: Nicolin Chen via <qemu-arm@nongnu.org>
To: Eric Auger <eric.auger@redhat.com>
Cc: Shameer Kolothum <skolothumtho@nvidia.com>, <qemu-arm@nongnu.org>,
<qemu-devel@nongnu.org>, <peter.maydell@linaro.org>,
<nathanc@nvidia.com>, <mochs@nvidia.com>, <jgg@nvidia.com>,
<jonathan.cameron@huawei.com>, <zhangfei.gao@linaro.org>,
<zhenzhong.duan@intel.com>, <kjaju@nvidia.com>
Subject: Re: [RFC PATCH 06/16] hw/arm/tegra241-cmdqv: Map VINTF Page0 into guest
Date: Mon, 26 Jan 2026 16:04:31 -0800 [thread overview]
Message-ID: <aXgBD/N+aOVNlcGb@Asurada-Nvidia> (raw)
In-Reply-To: <58f0ca59-b08c-44cd-b469-f152271c14f6@redhat.com>
On Mon, Jan 26, 2026 at 02:48:55PM +0100, Eric Auger wrote:
> > + name = g_strdup_printf("%s vcmdq", memory_region_name(&cmdqv->mmio_cmdqv));
> > + memory_region_init_ram_device_ptr(&cmdqv->mmio_vcmdq_page,
> > + memory_region_owner(&cmdqv->mmio_cmdqv),
> > + name, 0x10000, cmdqv->vcmdq_page0);
> > + memory_region_add_subregion_overlap(&cmdqv->mmio_cmdqv, 0x10000,
> > + &cmdqv->mmio_vcmdq_page, 1);
> > + g_free(name);
> > +
> > + name = g_strdup_printf("%s vintf", memory_region_name(&cmdqv->mmio_cmdqv));
> > + memory_region_init_ram_device_ptr(&cmdqv->mmio_vintf_page,
> > + memory_region_owner(&cmdqv->mmio_cmdqv),
> > + name, 0x10000, cmdqv->vcmdq_page0);
> I don't get why we need/have 2 RAM devices pointing to the same @ptr
> = cmdqv->vcmdq_page0. Is 0x10000 ~ VCMDQ_REG_PAGE_SIZE?
The first one is for "vcmdq" and the second one is for "vintf".
Explaining below...
> The names of the MRs are quite confusing: If my understanding is correct
> we have;
>
> cmdqv->mmio_cmdqv (0x50000 sized) which as the container for the 2 subregions.
> Then within that one we have 2 subregions, one at offset 0x10000 (mmio_vcmdq_page
> ), one at offset 0x30000 (cmdqv->mmio_vintf_page).
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c?h=v6.19-rc7#n19
It's defined in the kernel driver (yea, we should clarify in the
QEMU code as well).
So, the MMIO regions look like this:
1st 64 KB page -- Global CMDQV registers
2nd 64 KB page -- Global VCMDQ registers Page0 (mmap)
3rd 64 KB page -- Global VCMDQ registers Page1 (trap)
4th 64 KB page -- VINTF0 Logical VCMDQ registers Page0 (mmap)
5th 64 KB page -- VINTF0 Logical VCMDQ registers Page1 (trap)
In real hardware, there will be 6th 64KB and beyond, for VINTF1
and others. But, we're omitting here in QEMU as only VINTF0 will
be supported -- kernel only exposes one VINTF per VM as well.
(Yes, we should clarify this too.)
> I have difficulties to link that with the commit message
>
> "Tegra241 CMDQV assigns each VINTF a 128KB MMIO region split into two
> 64 KB pages:
> - Page0: guest accessible control/status registers for all VCMDQs
> - Page1:configuration registers ../.."
> Those 2 pages, are they part of mmio_vcmdq_page?
Not exactly. Both the global VCMDQ region and VINTF region have
their own pages (at 0x10000 and 0x30000).
Here, it duplicates the mapping to 0x10000 (Global VCMDQ page0)
and 0x30000 (VINTF0 page0) for simplification, because we only
support VINTF0 in this case.
There is a little catch in this implementation. The real physical
mapping between a global VCMDQ and a logical VCMDQ happens when
QEMU calls HW_QUEUE ioctl. So, the mmap'd page0 doesn't have any
real VCMDQ backing up the emulated VCMDQ. So, perhaps QEMU should
trap the page0 and delay the memory_region_init_ram_device_ptr()
until the HW_QUEUE ioctl is done?
There might be also a corner case: when the kernel exposes two
physical VCMDQs, but the guest OS only uses one, i.e. QEMU only
allocates one HW_QUEUE for VCMDQ0 but doesn't allocate VCMDQ1.
In such a case, the VTINF0 page0 should be able to control the
logical VCMDQ0 only, while the global page0 should control both.
We are getting away this corner case with any guest OS running
Linux kernel because it only accesses VTINF pages. But likely we
should do something about it..
> Then you talk about 0x30000 :VINTF register I guess this is the second cmdqv->mmio_vintf_page
>
> Well I am confused at this stage of the reading.
>
> Also without any spec, this is difficult to understand. Is there any public doc?
It seems that Red Hat can get the doc under NDA..
Thanks
Nicolin
WARNING: multiple messages have this Message-ID (diff)
From: Nicolin Chen via qemu development <qemu-devel@nongnu.org>
To: Eric Auger <eric.auger@redhat.com>
Cc: Shameer Kolothum <skolothumtho@nvidia.com>, <qemu-arm@nongnu.org>,
<qemu-devel@nongnu.org>, <peter.maydell@linaro.org>,
<nathanc@nvidia.com>, <mochs@nvidia.com>, <jgg@nvidia.com>,
<jonathan.cameron@huawei.com>, <zhangfei.gao@linaro.org>,
<zhenzhong.duan@intel.com>, <kjaju@nvidia.com>
Subject: Re: [RFC PATCH 06/16] hw/arm/tegra241-cmdqv: Map VINTF Page0 into guest
Date: Mon, 26 Jan 2026 16:04:31 -0800 [thread overview]
Message-ID: <aXgBD/N+aOVNlcGb@Asurada-Nvidia> (raw)
In-Reply-To: <58f0ca59-b08c-44cd-b469-f152271c14f6@redhat.com>
On Mon, Jan 26, 2026 at 02:48:55PM +0100, Eric Auger wrote:
> > + name = g_strdup_printf("%s vcmdq", memory_region_name(&cmdqv->mmio_cmdqv));
> > + memory_region_init_ram_device_ptr(&cmdqv->mmio_vcmdq_page,
> > + memory_region_owner(&cmdqv->mmio_cmdqv),
> > + name, 0x10000, cmdqv->vcmdq_page0);
> > + memory_region_add_subregion_overlap(&cmdqv->mmio_cmdqv, 0x10000,
> > + &cmdqv->mmio_vcmdq_page, 1);
> > + g_free(name);
> > +
> > + name = g_strdup_printf("%s vintf", memory_region_name(&cmdqv->mmio_cmdqv));
> > + memory_region_init_ram_device_ptr(&cmdqv->mmio_vintf_page,
> > + memory_region_owner(&cmdqv->mmio_cmdqv),
> > + name, 0x10000, cmdqv->vcmdq_page0);
> I don't get why we need/have 2 RAM devices pointing to the same @ptr
> = cmdqv->vcmdq_page0. Is 0x10000 ~ VCMDQ_REG_PAGE_SIZE?
The first one is for "vcmdq" and the second one is for "vintf".
Explaining below...
> The names of the MRs are quite confusing: If my understanding is correct
> we have;
>
> cmdqv->mmio_cmdqv (0x50000 sized) which as the container for the 2 subregions.
> Then within that one we have 2 subregions, one at offset 0x10000 (mmio_vcmdq_page
> ), one at offset 0x30000 (cmdqv->mmio_vintf_page).
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c?h=v6.19-rc7#n19
It's defined in the kernel driver (yea, we should clarify in the
QEMU code as well).
So, the MMIO regions look like this:
1st 64 KB page -- Global CMDQV registers
2nd 64 KB page -- Global VCMDQ registers Page0 (mmap)
3rd 64 KB page -- Global VCMDQ registers Page1 (trap)
4th 64 KB page -- VINTF0 Logical VCMDQ registers Page0 (mmap)
5th 64 KB page -- VINTF0 Logical VCMDQ registers Page1 (trap)
In real hardware, there will be 6th 64KB and beyond, for VINTF1
and others. But, we're omitting here in QEMU as only VINTF0 will
be supported -- kernel only exposes one VINTF per VM as well.
(Yes, we should clarify this too.)
> I have difficulties to link that with the commit message
>
> "Tegra241 CMDQV assigns each VINTF a 128KB MMIO region split into two
> 64 KB pages:
> - Page0: guest accessible control/status registers for all VCMDQs
> - Page1:configuration registers ../.."
> Those 2 pages, are they part of mmio_vcmdq_page?
Not exactly. Both the global VCMDQ region and VINTF region have
their own pages (at 0x10000 and 0x30000).
Here, it duplicates the mapping to 0x10000 (Global VCMDQ page0)
and 0x30000 (VINTF0 page0) for simplification, because we only
support VINTF0 in this case.
There is a little catch in this implementation. The real physical
mapping between a global VCMDQ and a logical VCMDQ happens when
QEMU calls HW_QUEUE ioctl. So, the mmap'd page0 doesn't have any
real VCMDQ backing up the emulated VCMDQ. So, perhaps QEMU should
trap the page0 and delay the memory_region_init_ram_device_ptr()
until the HW_QUEUE ioctl is done?
There might be also a corner case: when the kernel exposes two
physical VCMDQs, but the guest OS only uses one, i.e. QEMU only
allocates one HW_QUEUE for VCMDQ0 but doesn't allocate VCMDQ1.
In such a case, the VTINF0 page0 should be able to control the
logical VCMDQ0 only, while the global page0 should control both.
We are getting away this corner case with any guest OS running
Linux kernel because it only accesses VTINF pages. But likely we
should do something about it..
> Then you talk about 0x30000 :VINTF register I guess this is the second cmdqv->mmio_vintf_page
>
> Well I am confused at this stage of the reading.
>
> Also without any spec, this is difficult to understand. Is there any public doc?
It seems that Red Hat can get the doc under NDA..
Thanks
Nicolin
next prev parent reply other threads:[~2026-01-27 0:05 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-10 13:37 [RFC PATCH 00/16] hw/arm: Introduce Tegra241 CMDQV support for accelerated SMMUv3 Shameer Kolothum
2025-12-10 13:37 ` [RFC PATCH 01/16] backends/iommufd: Update iommufd_backend_get_device_info Shameer Kolothum
2025-12-29 18:39 ` Nicolin Chen
2025-12-30 8:41 ` Shameer Kolothum
2026-01-12 13:27 ` Eric Auger
2025-12-10 13:37 ` [RFC PATCH 02/16] backends/iommufd: Update iommufd_backend_alloc_viommu to allow user ptr Shameer Kolothum
2025-12-29 18:44 ` Nicolin Chen
2026-01-12 13:34 ` Eric Auger
2025-12-10 13:37 ` [RFC PATCH 03/16] backends/iommufd: Introduce iommufd_backend_alloc_hw_queue Shameer Kolothum
2026-01-12 13:41 ` Eric Auger
2025-12-10 13:37 ` [RFC PATCH 04/16] backends/iommufd: Introduce iommufd_backend_viommu_mmap Shameer Kolothum
2025-12-29 18:52 ` Nicolin Chen
2026-01-12 14:57 ` Eric Auger
2025-12-10 13:37 ` [RFC PATCH 05/16] hw/arm/tegra241-cmdqv: Add initial Tegra241 CMDQ-Virtualisation support Shameer Kolothum
2025-12-29 19:07 ` Nicolin Chen
2025-12-30 9:00 ` Shameer Kolothum
2026-01-12 15:28 ` Eric Auger
2026-01-13 14:41 ` Shameer Kolothum
2026-01-13 17:56 ` Nicolin Chen
2026-01-26 13:30 ` Eric Auger
2026-01-26 14:22 ` Eric Auger
2025-12-10 13:37 ` [RFC PATCH 06/16] hw/arm/tegra241-cmdqv: Map VINTF Page0 into guest Shameer Kolothum
2025-12-29 19:28 ` Nicolin Chen
2026-01-26 13:48 ` Eric Auger
2026-01-26 15:46 ` Shameer Kolothum
2026-01-27 0:04 ` Nicolin Chen via [this message]
2026-01-27 0:04 ` Nicolin Chen via qemu development
2026-01-27 13:23 ` Eric Auger
2026-01-27 19:36 ` Nicolin Chen via
2026-01-27 19:36 ` Nicolin Chen via qemu development
2026-01-26 13:58 ` Eric Auger
2025-12-10 13:37 ` [RFC PATCH 07/16] hw/arm/tegra241-cmdqv: Add read emulation support for registers Shameer Kolothum
2025-12-29 19:42 ` Nicolin Chen
2026-01-26 15:13 ` Eric Auger
2026-01-26 19:10 ` Nicolin Chen
2025-12-10 13:37 ` [RFC PATCH 08/16] system/physmem: Add helper to check whether a guest PA maps to RAM Shameer Kolothum
2026-01-12 15:35 ` Eric Auger
2025-12-10 13:37 ` [RFC PATCH 09/16] hw/arm/tegra241-cmdqv:: Add write emulation for registers Shameer Kolothum
2026-01-26 15:18 ` Eric Auger
2025-12-10 13:37 ` [RFC PATCH 10/16] hw/arm/tegra241-cmdqv: Allocate vEVENTQ object Shameer Kolothum
2025-12-29 19:49 ` Nicolin Chen
2025-12-30 9:47 ` Shameer Kolothum
2025-12-30 17:54 ` Nicolin Chen
2025-12-30 18:10 ` Shameer Kolothum
2025-12-30 18:22 ` Nicolin Chen
2025-12-30 18:30 ` Shameer Kolothum
2025-12-10 13:37 ` [RFC PATCH 11/16] hw/arm/tegra241-cmdqv: Read and propagate Tegra241 CMDQV errors Shameer Kolothum
2025-12-29 19:52 ` Nicolin Chen
2026-01-26 15:19 ` Eric Auger
2025-12-10 13:37 ` [RFC PATCH 12/16] hw/arm/tegra241-cmdqv: Add reset handler Shameer Kolothum
2025-12-10 13:37 ` [RFC PATCH 13/16] hw/arm/tegra241-cmdqv: Limit queue size based on backend page size Shameer Kolothum
2025-12-29 19:57 ` Nicolin Chen
2025-12-10 13:37 ` [RFC PATCH 14/16] virt-acpi-build: Rename AcpiIortSMMUv3Dev to AcpiSMMUv3Dev Shameer Kolothum
2025-12-29 19:59 ` Nicolin Chen
2026-01-26 15:25 ` Eric Auger
2025-12-10 13:37 ` [RFC PATCH 15/16] hw/arm/virt-acpi: Advertise Tegra241 CMDQV nodes in DSDT Shameer Kolothum
2025-12-29 20:11 ` Nicolin Chen
2025-12-30 10:13 ` Shameer Kolothum
2025-12-30 18:11 ` Nicolin Chen
2025-12-30 18:23 ` Nicolin Chen
2025-12-30 19:13 ` Shameer Kolothum
2026-01-26 15:28 ` Eric Auger
2026-01-27 0:42 ` Nicolin Chen
2025-12-10 13:37 ` [RFC PATCH 16/16] hw/arm/smmuv3: Add tegra241-cmdqv property for SMMUv3 device Shameer Kolothum
2025-12-29 20:14 ` Nicolin Chen
2025-12-11 17:54 ` [RFC PATCH 00/16] hw/arm: Introduce Tegra241 CMDQV support for accelerated SMMUv3 Eric Auger
2025-12-12 0:23 ` Shameer Kolothum
2025-12-17 19:32 ` Shameer Kolothum
2026-01-12 15:44 ` Eric Auger
2026-01-13 15:23 ` Shameer Kolothum
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