From: Nicolin Chen <nicolinc@nvidia.com>
To: Shameer Kolothum <skolothumtho@nvidia.com>
Cc: "qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"eric.auger@redhat.com" <eric.auger@redhat.com>,
"peter.maydell@linaro.org" <peter.maydell@linaro.org>,
Nathan Chen <nathanc@nvidia.com>, Matt Ochs <mochs@nvidia.com>,
Jason Gunthorpe <jgg@nvidia.com>,
"jonathan.cameron@huawei.com" <jonathan.cameron@huawei.com>,
"zhangfei.gao@linaro.org" <zhangfei.gao@linaro.org>,
"zhenzhong.duan@intel.com" <zhenzhong.duan@intel.com>,
Krishnakant Jaju <kjaju@nvidia.com>
Subject: Re: [RFC PATCH 15/16] hw/arm/virt-acpi: Advertise Tegra241 CMDQV nodes in DSDT
Date: Tue, 30 Dec 2025 10:23:45 -0800 [thread overview]
Message-ID: <aVQYsTJPNmYPY3VH@Asurada-Nvidia> (raw)
In-Reply-To: <aVQVxrGenUgN7MNS@Asurada-Nvidia>
On Tue, Dec 30, 2025 at 10:11:20AM -0800, Nicolin Chen wrote:
> On Tue, Dec 30, 2025 at 02:13:12AM -0800, Shameer Kolothum wrote:
> >
> >
> > > -----Original Message-----
> > > From: Nicolin Chen <nicolinc@nvidia.com>
> > > Sent: 29 December 2025 20:11
> > > To: Shameer Kolothum <skolothumtho@nvidia.com>
> > > Cc: qemu-arm@nongnu.org; qemu-devel@nongnu.org;
> > > eric.auger@redhat.com; peter.maydell@linaro.org; Nathan Chen
> > > <nathanc@nvidia.com>; Matt Ochs <mochs@nvidia.com>; Jason Gunthorpe
> > > <jgg@nvidia.com>; jonathan.cameron@huawei.com;
> > > zhangfei.gao@linaro.org; zhenzhong.duan@intel.com; Krishnakant Jaju
> > > <kjaju@nvidia.com>
> > > Subject: Re: [RFC PATCH 15/16] hw/arm/virt-acpi: Advertise Tegra241
> > > CMDQV nodes in DSDT
> > >
> > > On Wed, Dec 10, 2025 at 01:37:36PM +0000, Shameer Kolothum wrote:
> > > > +static int smmuv3_cmdqv_devices(Object *obj, void *opaque)
> > > > +{
> > > > + VirtMachineState *vms = VIRT_MACHINE(qdev_get_machine());
> > > > + GArray *sdev_blob = opaque;
> > > > + PlatformBusDevice *pbus;
> > > > + AcpiSMMUv3Dev sdev;
> > > > + SysBusDevice *sbdev;
> > > > +
> > > > + if (!object_dynamic_cast(obj, TYPE_ARM_SMMUV3)) {
> > > > + return 0;
> > > > + }
> > > > +
> > > > + if (!object_property_get_bool(obj, "tegra241-cmdqv", NULL)) {
> > > > + return 0;
> > > > + }
> > > > +
> > > > + pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
> > > > + sbdev = SYS_BUS_DEVICE(obj);
> > > > + sdev.base = platform_bus_get_mmio_addr(pbus, sbdev, 1);
> > > > + sdev.base += vms->memmap[VIRT_PLATFORM_BUS].base;
> > > > + sdev.irq = platform_bus_get_irqn(pbus, sbdev, NUM_SMMU_IRQS);
> > > > + sdev.irq += vms->irqmap[VIRT_PLATFORM_BUS];
> > > > + sdev.irq += ARM_SPI_BASE;
> > > > + g_array_append_val(sdev_blob, sdev);
> > > > + return 0;
> > >
> > > This is pre-building SMMU's IORT nodes right? Maybe a different
> > > naming? And can be shared with the existing iort_smmuv3_devices?
> >
> > Not really, if you are referring about this patch here,
> > https://github.com/NVIDIA/QEMU/commit/cc3b65e6a49a9b7addf44b377d4ef1de99bfee3f
>
> Yes. I am talking about this. But you are actually pre-building an
> ACPI SMMU device array here. So, my question wasn't accurate..
>
> > I didn’t find a clean way to store the pre-built smmuv3_devs other than
> > placing them in struct AcpiBuildTables. It’s not clear we gain much by
> > restructuring things to populate and store them separately. At best,
> > it might slightly improve boot time, and if that becomes important we
> > can always add it as an optimization later.
> >
> > This patch enumerates SMMUv3 accel instances with CMDQV separately, uses
> > that information to build the DSDT, and then frees the device array.
>
> Oh, I missed the g_array_free() in acpi_dsdt_add_tegra241_cmdqv().
>
> Let's have a note inline and copy to the commit message too.
>
> > > We do so, because we need to link CMDQV's DSDT node to the SMMU's
> > > IORT node but it is created in build_iort() that is called after
> > > build_dsdt().
> >
> > Hmm..not sure I get that. Does this mean IORT has a link to DSDT? I can't find one..
> > Maybe I missed. Please let me know.
>
> The _UID field of the DSDT node links to the Identifier field of an
> SMMU's IORT node. E.g.
>
> [DSDT] // Qemu builds DSDT first
> CMDQV0 {
> _UID = 0;
> }
>
> [IORT] // Then builds IORT
> SMMU0 {
> Identifier = 0;
> }
>
> If we are sure that the SMMU sequence is fixed every time we rebuild
> the sdev array so that IORT.Identifier matches with DSDT._UID, we'd
> be fine. That being said, we should probably make a node inline too.
Typo: node->note
> Otherwise, it would be safer to pre-build the sdev array and use the
> same array in both DSDT and IORT.
>
> Thanks
> Nicolin
next prev parent reply other threads:[~2025-12-30 18:24 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-10 13:37 [RFC PATCH 00/16] hw/arm: Introduce Tegra241 CMDQV support for accelerated SMMUv3 Shameer Kolothum
2025-12-10 13:37 ` [RFC PATCH 01/16] backends/iommufd: Update iommufd_backend_get_device_info Shameer Kolothum
2025-12-29 18:39 ` Nicolin Chen
2025-12-30 8:41 ` Shameer Kolothum
2026-01-12 13:27 ` Eric Auger
2025-12-10 13:37 ` [RFC PATCH 02/16] backends/iommufd: Update iommufd_backend_alloc_viommu to allow user ptr Shameer Kolothum
2025-12-29 18:44 ` Nicolin Chen
2026-01-12 13:34 ` Eric Auger
2025-12-10 13:37 ` [RFC PATCH 03/16] backends/iommufd: Introduce iommufd_backend_alloc_hw_queue Shameer Kolothum
2026-01-12 13:41 ` Eric Auger
2025-12-10 13:37 ` [RFC PATCH 04/16] backends/iommufd: Introduce iommufd_backend_viommu_mmap Shameer Kolothum
2025-12-29 18:52 ` Nicolin Chen
2026-01-12 14:57 ` Eric Auger
2025-12-10 13:37 ` [RFC PATCH 05/16] hw/arm/tegra241-cmdqv: Add initial Tegra241 CMDQ-Virtualisation support Shameer Kolothum
2025-12-29 19:07 ` Nicolin Chen
2025-12-30 9:00 ` Shameer Kolothum
2026-01-12 15:28 ` Eric Auger
2026-01-13 14:41 ` Shameer Kolothum
2026-01-13 17:56 ` Nicolin Chen
2026-01-26 13:30 ` Eric Auger
2026-01-26 14:22 ` Eric Auger
2025-12-10 13:37 ` [RFC PATCH 06/16] hw/arm/tegra241-cmdqv: Map VINTF Page0 into guest Shameer Kolothum
2025-12-29 19:28 ` Nicolin Chen
2026-01-26 13:48 ` Eric Auger
2026-01-26 15:46 ` Shameer Kolothum
2026-01-27 0:04 ` Nicolin Chen via
2026-01-27 0:04 ` Nicolin Chen via qemu development
2026-01-27 13:23 ` Eric Auger
2026-01-27 19:36 ` Nicolin Chen via
2026-01-27 19:36 ` Nicolin Chen via qemu development
2026-01-26 13:58 ` Eric Auger
2025-12-10 13:37 ` [RFC PATCH 07/16] hw/arm/tegra241-cmdqv: Add read emulation support for registers Shameer Kolothum
2025-12-29 19:42 ` Nicolin Chen
2026-01-26 15:13 ` Eric Auger
2026-01-26 19:10 ` Nicolin Chen
2025-12-10 13:37 ` [RFC PATCH 08/16] system/physmem: Add helper to check whether a guest PA maps to RAM Shameer Kolothum
2026-01-12 15:35 ` Eric Auger
2025-12-10 13:37 ` [RFC PATCH 09/16] hw/arm/tegra241-cmdqv:: Add write emulation for registers Shameer Kolothum
2026-01-26 15:18 ` Eric Auger
2025-12-10 13:37 ` [RFC PATCH 10/16] hw/arm/tegra241-cmdqv: Allocate vEVENTQ object Shameer Kolothum
2025-12-29 19:49 ` Nicolin Chen
2025-12-30 9:47 ` Shameer Kolothum
2025-12-30 17:54 ` Nicolin Chen
2025-12-30 18:10 ` Shameer Kolothum
2025-12-30 18:22 ` Nicolin Chen
2025-12-30 18:30 ` Shameer Kolothum
2025-12-10 13:37 ` [RFC PATCH 11/16] hw/arm/tegra241-cmdqv: Read and propagate Tegra241 CMDQV errors Shameer Kolothum
2025-12-29 19:52 ` Nicolin Chen
2026-01-26 15:19 ` Eric Auger
2025-12-10 13:37 ` [RFC PATCH 12/16] hw/arm/tegra241-cmdqv: Add reset handler Shameer Kolothum
2025-12-10 13:37 ` [RFC PATCH 13/16] hw/arm/tegra241-cmdqv: Limit queue size based on backend page size Shameer Kolothum
2025-12-29 19:57 ` Nicolin Chen
2025-12-10 13:37 ` [RFC PATCH 14/16] virt-acpi-build: Rename AcpiIortSMMUv3Dev to AcpiSMMUv3Dev Shameer Kolothum
2025-12-29 19:59 ` Nicolin Chen
2026-01-26 15:25 ` Eric Auger
2025-12-10 13:37 ` [RFC PATCH 15/16] hw/arm/virt-acpi: Advertise Tegra241 CMDQV nodes in DSDT Shameer Kolothum
2025-12-29 20:11 ` Nicolin Chen
2025-12-30 10:13 ` Shameer Kolothum
2025-12-30 18:11 ` Nicolin Chen
2025-12-30 18:23 ` Nicolin Chen [this message]
2025-12-30 19:13 ` Shameer Kolothum
2026-01-26 15:28 ` Eric Auger
2026-01-27 0:42 ` Nicolin Chen
2025-12-10 13:37 ` [RFC PATCH 16/16] hw/arm/smmuv3: Add tegra241-cmdqv property for SMMUv3 device Shameer Kolothum
2025-12-29 20:14 ` Nicolin Chen
2025-12-11 17:54 ` [RFC PATCH 00/16] hw/arm: Introduce Tegra241 CMDQV support for accelerated SMMUv3 Eric Auger
2025-12-12 0:23 ` Shameer Kolothum
2025-12-17 19:32 ` Shameer Kolothum
2026-01-12 15:44 ` Eric Auger
2026-01-13 15:23 ` Shameer Kolothum
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=aVQYsTJPNmYPY3VH@Asurada-Nvidia \
--to=nicolinc@nvidia.com \
--cc=eric.auger@redhat.com \
--cc=jgg@nvidia.com \
--cc=jonathan.cameron@huawei.com \
--cc=kjaju@nvidia.com \
--cc=mochs@nvidia.com \
--cc=nathanc@nvidia.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=skolothumtho@nvidia.com \
--cc=zhangfei.gao@linaro.org \
--cc=zhenzhong.duan@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.