[PATCH v3 0/3] target/i386: Add support for Zhaoxin Shijidadao vCPU model

[PATCH v3 0/3] target/i386: Add support for Zhaoxin Shijidadao vCPU model

[Ewan Hai]

This patchset introduces cache enumeration and a vCPU model for the
Zhaoxin "Shijidadao" architecture. The model provides two variants via
version aliases: Shijidadao-Server (v1) and Shijidadao-Client (v2).
With these additions, QEMU can expose the core identity and features
of this architecture without relying on host-passthrough.

---

Changes Since v1:
- Incorporated Zhao Liu's suggested patch that introduces the cpuid_0x1f option.
- Dropped explicit x-force-cpuid-0x1f property declarations from both
Shijidadao-Server and Shijidadao-Client models, since the new option provides
a cleaner solution.
- Updated commit messages for the Client and Server patches to remove
references to the earlier x-force-cpuid-0x1f approach.

Changes Since v2:
- Removed Zhao Liu's cpuid_0x1f patch from this series, as it has been
  merged into mainline (commit 3d4978).
- Consolidated Shijidadao-Client and Shijidadao-Server into a single CPU
  model, differentiating them via version numbers and aliases.
- Dropped the original Client v1 model, as it represents an early silicon
  revision rather than the final production version.
- Updated the missing feature comment for FEAT_C000_0001_EDX to explicitly
  list individual features instead of using a generic TODO message.

---

Ewan Hai (3):
  target/i386: Add cache model for Zhaoxin Shijidadao vCPUs
  target/i386: Introduce Zhaoxin Shijidadao CPU model
  target/i386: Fix FEAT_C000_0001_EDX comment in Yongfeng model

 target/i386/cpu.c | 252 +++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 250 insertions(+), 2 deletions(-)

-- 
2.34.1

[PATCH v3 1/3] target/i386: Add cache model for Zhaoxin Shijidadao vCPUs

[Ewan Hai]

Zhaoxin "Shijidadao" vCPUs require built-in cache enumeration in QEMU
to properly report CPUID leaf 0x4 and 0x80000005/0x80000006 when
'host-cache-info' is disabled.

This patch defines the L1/L2/L3 cache parameters for the Shijidadao
architecture, preparing for use in both client and server models.

Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
---
 target/i386/cpu.c | 99 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 99 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 37803cd724..1c85445f48 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3423,6 +3423,105 @@ static const CPUCaches yongfeng_cache_info = {
     },
 };
 
+static const CPUCaches shijidadao_cache_info = {
+    .l1d_cache = &(CPUCacheInfo) {
+        /* CPUID 0x4.0x0.EAX */
+        .type = DATA_CACHE,
+        .level = 1,
+        .self_init = true,
+
+        /* CPUID 0x4.0x0.EBX */
+        .line_size = 64,
+        .partitions = 1,
+        .associativity = 8,
+
+        /* CPUID 0x4.0x0.ECX */
+        .sets = 64,
+
+        /* CPUID 0x4.0x0.EDX */
+        .no_invd_sharing = false,
+        .inclusive = false,
+        .complex_indexing = false,
+
+        /* CPUID 0x80000005.ECX */
+        .lines_per_tag = 1,
+        .size = 32 * KiB,
+
+        .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+    },
+    .l1i_cache = &(CPUCacheInfo) {
+        /* CPUID 0x4.0x1.EAX */
+        .type = INSTRUCTION_CACHE,
+        .level = 1,
+        .self_init = true,
+
+        /* CPUID 0x4.0x1.EBX */
+        .line_size = 64,
+        .partitions = 1,
+        .associativity = 16,
+
+        /* CPUID 0x4.0x1.ECX */
+        .sets = 64,
+
+        /* CPUID 0x4.0x1.EDX */
+        .no_invd_sharing = false,
+        .inclusive = false,
+        .complex_indexing = false,
+
+        /* CPUID 0x80000005.EDX */
+        .lines_per_tag = 1,
+        .size = 64 * KiB,
+
+        .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+    },
+    .l2_cache = &(CPUCacheInfo) {
+        /* CPUID 0x4.0x2.EAX */
+        .type = UNIFIED_CACHE,
+        .level = 2,
+        .self_init = true,
+
+        /* CPUID 0x4.0x2.EBX */
+        .line_size = 64,
+        .partitions = 1,
+        .associativity = 8,
+
+        /* CPUID 0x4.0x2.ECX */
+        .sets = 1024,
+
+        /* CPUID 0x4.0x2.EDX */
+        .no_invd_sharing = false,
+        .inclusive = true,
+        .complex_indexing = false,
+
+        /* CPUID 0x80000006.ECX */
+        .size = 512 * KiB,
+
+        .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+    },
+    .l3_cache = &(CPUCacheInfo) {
+        /* CPUID 0x4.0x3.EAX */
+        .type = UNIFIED_CACHE,
+        .level = 3,
+        .self_init = true,
+
+        /* CPUID 0x4.0x3.EBX */
+        .line_size = 64,
+        .partitions = 1,
+        .associativity = 16,
+
+        /* CPUID 0x4.0x3.ECX */
+        .sets = 32768,
+
+        /* CPUID 0x4.0x3.EDX */
+        .no_invd_sharing = false,
+        .inclusive = true,
+        .complex_indexing = false,
+
+        .size = 32 * MiB,
+        .share_level = CPU_TOPOLOGY_LEVEL_DIE,
+    },
+};
+
 /* The following VMX features are not supported by KVM and are left out in the
  * CPU definitions:
  *
-- 
2.34.1

[PATCH v3 2/3] target/i386: Introduce Zhaoxin Shijidadao CPU model

[Ewan Hai]

Introduce the Zhaoxin Shijidadao CPU model with two versions:

- v1 (alias: Shijidadao-Server) - Server variant with CORE_CAPABILITY
  and SPLIT_LOCK_DETECT support
- v2 (alias: Shijidadao-Client) - Client variant with different FMS
  (model=0x6b, stepping=1) and without CORE_CAPABILITY features

The model_id for both variants is 'Zhaoxin Shijidadao Processor'.

Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
---
 target/i386/cpu.c | 149 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 149 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1c85445f48..34e3e66344 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7144,6 +7144,155 @@ static const X86CPUDefinition builtin_x86_defs[] = {
         .model_id = "AMD EPYC-Turin Processor",
         .cache_info = &epyc_turin_cache_info,
     },
+    {
+        .name = "Shijidadao",
+        .level = 0x1f,
+        .vendor = CPUID_VENDOR_ZHAOXIN1,
+        .family = 7,
+        .model = 0x7b,
+        .stepping = 0,
+        .cpuid_0x1f = true,
+        /* missing: CPUID_HT, CPUID_TM, CPUID_PBE */
+        .features[FEAT_1_EDX] =
+            CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+            CPUID_ACPI | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
+            CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
+            CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
+            CPUID_PSE | CPUID_DE | CPUID_VME | CPUID_FP87,
+        /*
+         * missing: CPUID_EXT_OSXSAVE, CPUID_EXT_XTPR, CPUID_EXT_TM2,
+         * CPUID_EXT_EST, CPUID_EXT_SMX, CPUID_EXT_VMX
+         */
+        .features[FEAT_1_ECX] =
+            CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
+            CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_TSC_DEADLINE_TIMER |
+            CPUID_EXT_POPCNT | CPUID_EXT_MOVBE | CPUID_EXT_X2APIC |
+            CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_PCID |
+            CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
+            CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
+        .features[FEAT_7_0_EBX] =
+            CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_RDSEED |
+            CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_SMEP |
+            CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_FSGSBASE,
+        /* missing: CPUID_7_0_ECX_OSPKE */
+        .features[FEAT_7_0_ECX] =
+            CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_UMIP,
+        .features[FEAT_7_0_EDX] =
+            CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL |
+            CPUID_7_0_EDX_CORE_CAPABILITY,
+        .features[FEAT_CORE_CAPABILITY] =
+            MSR_CORE_CAP_SPLIT_LOCK_DETECT,
+        .features[FEAT_8000_0001_EDX] =
+            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
+            CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
+        .features[FEAT_8000_0001_ECX] =
+            CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
+        .features[FEAT_8000_0007_EDX] = CPUID_APM_INVTSC,
+        /*
+         * missing: SM2/SM2_EN, CCS/CCS_EN, PARALLAX/PARALLAX_EN,
+         * TM3/TM3_EN, RNG2/RNG2_EN, PHE2/PHE2_EN, RSA/RSA_EN
+         */
+        .features[FEAT_C000_0001_EDX] =
+            CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM |
+            CPUID_C000_0001_EDX_PHE_EN | CPUID_C000_0001_EDX_PHE |
+            CPUID_C000_0001_EDX_ACE2 |
+            CPUID_C000_0001_EDX_XCRYPT_EN | CPUID_C000_0001_EDX_XCRYPT |
+            CPUID_C000_0001_EDX_XSTORE_EN | CPUID_C000_0001_EDX_XSTORE,
+        .features[FEAT_XSAVE] =
+            CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1 |
+            CPUID_XSAVE_XSAVES,
+        .features[FEAT_ARCH_CAPABILITIES] =
+            MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY |
+            MSR_ARCH_CAP_MDS_NO | MSR_ARCH_CAP_PSCHANGE_MC_NO |
+            MSR_ARCH_CAP_SSB_NO,
+        .features[FEAT_VMX_PROCBASED_CTLS] =
+            VMX_CPU_BASED_VIRTUAL_INTR_PENDING | VMX_CPU_BASED_HLT_EXITING |
+            VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_INVLPG_EXITING |
+            VMX_CPU_BASED_MWAIT_EXITING | VMX_CPU_BASED_RDPMC_EXITING |
+            VMX_CPU_BASED_RDTSC_EXITING | VMX_CPU_BASED_CR3_LOAD_EXITING |
+            VMX_CPU_BASED_CR3_STORE_EXITING | VMX_CPU_BASED_CR8_LOAD_EXITING |
+            VMX_CPU_BASED_CR8_STORE_EXITING | VMX_CPU_BASED_TPR_SHADOW |
+            VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_MOV_DR_EXITING |
+            VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
+            VMX_CPU_BASED_MONITOR_TRAP_FLAG | VMX_CPU_BASED_USE_MSR_BITMAPS |
+            VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
+            VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
+        /*
+         * missing: VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING,
+         * VMX_SECONDARY_EXEC_TSC_SCALING
+         */
+        .features[FEAT_VMX_SECONDARY_CTLS] =
+            VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
+            VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
+            VMX_SECONDARY_EXEC_RDTSCP | VMX_SECONDARY_EXEC_ENABLE_VPID |
+            VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
+            VMX_SECONDARY_EXEC_WBINVD_EXITING |
+            VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
+            VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
+            VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
+            VMX_SECONDARY_EXEC_RDRAND_EXITING |
+            VMX_SECONDARY_EXEC_ENABLE_INVPCID |
+            VMX_SECONDARY_EXEC_ENABLE_VMFUNC |
+            VMX_SECONDARY_EXEC_SHADOW_VMCS |
+            VMX_SECONDARY_EXEC_XSAVES      |
+            VMX_SECONDARY_EXEC_ENABLE_PML,
+        .features[FEAT_VMX_PINBASED_CTLS] =
+            VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
+            VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER |
+            VMX_PIN_BASED_POSTED_INTR,
+        .features[FEAT_VMX_EXIT_CTLS] =
+            VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE |
+            VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
+            VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
+            VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
+            VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
+        /* missing: VMX_VM_ENTRY_SMM, VMX_VM_ENTRY_DEACT_DUAL_MONITOR */
+        .features[FEAT_VMX_ENTRY_CTLS] =
+            VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
+            VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
+            VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER,
+        /*
+         * missing: MSR_VMX_MISC_ACTIVITY_SHUTDOWN,
+         * MSR_VMX_MISC_ACTIVITY_WAIT_SIPI
+         */
+        .features[FEAT_VMX_MISC] =
+            MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
+            MSR_VMX_MISC_VMWRITE_VMEXIT,
+        /* missing: MSR_VMX_EPT_UC */
+        .features[FEAT_VMX_EPT_VPID_CAPS] =
+            MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 |
+            MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
+            MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
+            MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
+            MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID |
+            MSR_VMX_EPT_INVVPID_ALL_CONTEXT | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
+            MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
+        .features[FEAT_VMX_BASIC] =
+            MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
+        .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
+        .xlevel = 0x80000008,
+        .model_id = "Zhaoxin Shijidadao Processor",
+        .cache_info = &shijidadao_cache_info,
+        .versions = (X86CPUVersionDefinition[]) {
+            {
+                .version = 1,
+                .alias = "Shijidadao-Server",
+            },
+            {
+                .version = 2,
+                .alias = "Shijidadao-Client",
+                .note = "client variant",
+                .props = (PropValue[]) {
+                    { "model", "0x6b" },
+                    { "stepping", "1" },
+                    { "core-capability", "off" },
+                    { "split-lock-detect", "off" },
+                    { /* end of list */ }
+                },
+            },
+            { /* end of list */ }
+        }
+    },
 };
 
 /*
-- 
2.34.1

[PATCH v3 3/3] target/i386: Fix FEAT_C000_0001_EDX comment in Yongfeng model

[Ewan Hai]

Update the comment for FEAT_C000_0001_EDX in YongFeng CPU model to
accurately list the missing features instead of the generic TODO message.

As background, current Zhaoxin CPUs implement several CPUID.(EAX=0xC0000001,
ECX=0):EDX feature bits that are not yet defined in the Linux kernel, for
example SM2/SM2_EN, SM3/SM4 and their enable bits, PARALLAX/PARALLAX_EN,
TM3/TM3_EN, RNG2/RNG2_EN, PHE2/PHE2_EN, and RSA/RSA_EN.

We previously tried to upstream all these extra feature bits in one patch
(https://lore.kernel.org/all/20230414095334.8743-1-TonyWWang-oc@zhaoxin.com/),
but the maintainer rejected it because there was no in-tree code using these
features yet. So our current plan is to add the CPUID bits together with real
kernel users step by step, Once full or partial in-tree implementations of
these features are merged, we will update these definitions accordingly and
potentially introduce corresponding support in QEMU.

Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
---
 target/i386/cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 34e3e66344..10603eeb31 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6958,8 +6958,8 @@ static const X86CPUDefinition builtin_x86_defs[] = {
             CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
         .features[FEAT_8000_0007_EDX] = CPUID_APM_INVTSC,
         /*
-         * TODO: When the Linux kernel introduces other existing definitions
-         * for this leaf, remember to update the definitions here.
+         * missing: SM2/SM2_EN, CCS/CCS_EN, PARALLAX/PARALLAX_EN,
+         * TM3/TM3_EN, RNG2/RNG2_EN, PHE2/PHE2_EN, RSA/RSA_EN
          */
         .features[FEAT_C000_0001_EDX] =
             CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM |
-- 
2.34.1

Re: [PATCH v3 1/3] target/i386: Add cache model for Zhaoxin Shijidadao vCPUs

[Zhao Liu]

On Thu, Jan 08, 2026 at 09:10:26PM -0500, Ewan Hai wrote:
> Date: Thu, 8 Jan 2026 21:10:26 -0500
> From: Ewan Hai <ewanhai-oc@zhaoxin.com>
> Subject: [PATCH v3 1/3] target/i386: Add cache model for Zhaoxin Shijidadao
>  vCPUs
> X-Mailer: git-send-email 2.34.1
> 
> Zhaoxin "Shijidadao" vCPUs require built-in cache enumeration in QEMU
> to properly report CPUID leaf 0x4 and 0x80000005/0x80000006 when
> 'host-cache-info' is disabled.
> 
> This patch defines the L1/L2/L3 cache parameters for the Shijidadao
> architecture, preparing for use in both client and server models.
> 
> Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
> ---
>  target/i386/cpu.c | 99 +++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 99 insertions(+)

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

Re: [PATCH v3 2/3] target/i386: Introduce Zhaoxin Shijidadao CPU model

[Zhao Liu]

On Thu, Jan 08, 2026 at 09:10:27PM -0500, Ewan Hai wrote:
> Date: Thu, 8 Jan 2026 21:10:27 -0500
> From: Ewan Hai <ewanhai-oc@zhaoxin.com>
> Subject: [PATCH v3 2/3] target/i386: Introduce Zhaoxin Shijidadao CPU model
> X-Mailer: git-send-email 2.34.1
> 
> Introduce the Zhaoxin Shijidadao CPU model with two versions:
> 
> - v1 (alias: Shijidadao-Server) - Server variant with CORE_CAPABILITY
>   and SPLIT_LOCK_DETECT support
> - v2 (alias: Shijidadao-Client) - Client variant with different FMS
>   (model=0x6b, stepping=1) and without CORE_CAPABILITY features
> 
> The model_id for both variants is 'Zhaoxin Shijidadao Processor'.
> 
> Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
> ---
>  target/i386/cpu.c | 149 ++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 149 insertions(+)

LGTM,

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

Re: [PATCH v3 3/3] target/i386: Fix FEAT_C000_0001_EDX comment in Yongfeng model

[Zhao Liu]

On Thu, Jan 08, 2026 at 09:10:28PM -0500, Ewan Hai wrote:
> Date: Thu, 8 Jan 2026 21:10:28 -0500
> From: Ewan Hai <ewanhai-oc@zhaoxin.com>
> Subject: [PATCH v3 3/3] target/i386: Fix FEAT_C000_0001_EDX comment in
>  Yongfeng model
> X-Mailer: git-send-email 2.34.1
> 
> Update the comment for FEAT_C000_0001_EDX in YongFeng CPU model to
> accurately list the missing features instead of the generic TODO message.
> 
> As background, current Zhaoxin CPUs implement several CPUID.(EAX=0xC0000001,
> ECX=0):EDX feature bits that are not yet defined in the Linux kernel, for
> example SM2/SM2_EN, SM3/SM4 and their enable bits, PARALLAX/PARALLAX_EN,
> TM3/TM3_EN, RNG2/RNG2_EN, PHE2/PHE2_EN, and RSA/RSA_EN.
> 
> We previously tried to upstream all these extra feature bits in one patch
> (https://lore.kernel.org/all/20230414095334.8743-1-TonyWWang-oc@zhaoxin.com/),
> but the maintainer rejected it because there was no in-tree code using these
> features yet. So our current plan is to add the CPUID bits together with real
> kernel users step by step, Once full or partial in-tree implementations of
> these features are merged, we will update these definitions accordingly and
> potentially introduce corresponding support in QEMU.
> 
> Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
> ---
>  target/i386/cpu.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Good cleanup,

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

Re: [PATCH v3 3/3] target/i386: Fix FEAT_C000_0001_EDX comment in Yongfeng model

[Paolo Bonzini]

On 1/9/26 03:10, Ewan Hai wrote:
> Update the comment for FEAT_C000_0001_EDX in YongFeng CPU model to
> accurately list the missing features instead of the generic TODO message.
> 
> As background, current Zhaoxin CPUs implement several CPUID.(EAX=0xC0000001,
> ECX=0):EDX feature bits that are not yet defined in the Linux kernel, for
> example SM2/SM2_EN, SM3/SM4 and their enable bits, PARALLAX/PARALLAX_EN,
> TM3/TM3_EN, RNG2/RNG2_EN, PHE2/PHE2_EN, and RSA/RSA_EN.
> 
> We previously tried to upstream all these extra feature bits in one patch
> (https://lore.kernel.org/all/20230414095334.8743-1-TonyWWang-oc@zhaoxin.com/),
> but the maintainer rejected it because there was no in-tree code using these
> features yet. So our current plan is to add the CPUID bits together with real
> kernel users step by step, Once full or partial in-tree implementations of
> these features are merged, we will update these definitions accordingly and
> potentially introduce corresponding support in QEMU.

KVM now has a mechanism for introducing feature bits separately from the 
kernel.  Feel free to resumit using that mechanism, then we can include 
them from the beginning in Shinjidadao.

Thanks,

Paolo
> 
> Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
> ---
>   target/i386/cpu.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 34e3e66344..10603eeb31 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -6958,8 +6958,8 @@ static const X86CPUDefinition builtin_x86_defs[] = {
>               CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
>           .features[FEAT_8000_0007_EDX] = CPUID_APM_INVTSC,
>           /*
> -         * TODO: When the Linux kernel introduces other existing definitions
> -         * for this leaf, remember to update the definitions here.
> +         * missing: SM2/SM2_EN, CCS/CCS_EN, PARALLAX/PARALLAX_EN,
> +         * TM3/TM3_EN, RNG2/RNG2_EN, PHE2/PHE2_EN, RSA/RSA_EN
>            */
>           .features[FEAT_C000_0001_EDX] =
>               CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM |

Re: [PATCH v3 3/3] target/i386: Fix FEAT_C000_0001_EDX comment in Yongfeng model

[Ewan Hai]

On 2/7/26 9:44 PM, Paolo Bonzini wrote:
> 
> 
> On 1/9/26 03:10, Ewan Hai wrote:
>> Update the comment for FEAT_C000_0001_EDX in YongFeng CPU model to
>> accurately list the missing features instead of the generic TODO message.
>>
>> As background, current Zhaoxin CPUs implement several CPUID.(EAX=0xC0000001,
>> ECX=0):EDX feature bits that are not yet defined in the Linux kernel, for
>> example SM2/SM2_EN, SM3/SM4 and their enable bits, PARALLAX/PARALLAX_EN,
>> TM3/TM3_EN, RNG2/RNG2_EN, PHE2/PHE2_EN, and RSA/RSA_EN.
>>
>> We previously tried to upstream all these extra feature bits in one patch
>> (https://lore.kernel.org/all/20230414095334.8743-1-TonyWWang-oc@zhaoxin.com/),
>> but the maintainer rejected it because there was no in-tree code using these
>> features yet. So our current plan is to add the CPUID bits together with real
>> kernel users step by step, Once full or partial in-tree implementations of
>> these features are merged, we will update these definitions accordingly and
>> potentially introduce corresponding support in QEMU.
> 
> KVM now has a mechanism for introducing feature bits separately from the
> kernel.  Feel free to resumit using that mechanism, then we can include
> them from the beginning in Shinjidadao.
> 
> Thanks,
> 
> Paolo

Hi Paolo,

Thanks for pointing out that KVM has a mechanism for introducing feature bits
independently from the kernel.

Before I start working on the patches, I'd like to clarify a few things:

1. Which specific mechanism are you referring to?
   a) The kvm_only_cpuid_leafs enum + kvm_cpu_cap_init_kvm_defined()?
   b) Or some other approach, given that CPUID_C000_0001_EDX is already
      a kernel-defined leaf (word 5)?

2. Should this independent introduction be limited to CPUID_C000_0001_EDX only
For other feature words, I assume they still need to be handled on a
case-by-case basis depending on their semantics and QEMU support status, correct?

For context: I want to add SM2/SM3/SM4/RNG2/PHE2/RSA etc. bits to
0xC0000001.EDX, but these features don't have in-tree kernel users yet.

Thanks,
Ewan

>> Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
>> ---
>>   target/i386/cpu.c | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index 34e3e66344..10603eeb31 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -6958,8 +6958,8 @@ static const X86CPUDefinition builtin_x86_defs[] = {
>>               CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
>>           .features[FEAT_8000_0007_EDX] = CPUID_APM_INVTSC,
>>           /*
>> -         * TODO: When the Linux kernel introduces other existing definitions
>> -         * for this leaf, remember to update the definitions here.
>> +         * missing: SM2/SM2_EN, CCS/CCS_EN, PARALLAX/PARALLAX_EN,
>> +         * TM3/TM3_EN, RNG2/RNG2_EN, PHE2/PHE2_EN, RSA/RSA_EN
>>            */
>>           .features[FEAT_C000_0001_EDX] =
>>               CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM |
> 

Re: [PATCH v3 3/3] target/i386: Fix FEAT_C000_0001_EDX comment in Yongfeng model

[Paolo Bonzini]

On 2/9/26 09:15, Ewan Hai wrote:
> On 2/7/26 9:44 PM, Paolo Bonzini wrote:
>>
>>
>> On 1/9/26 03:10, Ewan Hai wrote:
>>> Update the comment for FEAT_C000_0001_EDX in YongFeng CPU model to
>>> accurately list the missing features instead of the generic TODO message.
>>>
>>> As background, current Zhaoxin CPUs implement several CPUID.(EAX=0xC0000001,
>>> ECX=0):EDX feature bits that are not yet defined in the Linux kernel, for
>>> example SM2/SM2_EN, SM3/SM4 and their enable bits, PARALLAX/PARALLAX_EN,
>>> TM3/TM3_EN, RNG2/RNG2_EN, PHE2/PHE2_EN, and RSA/RSA_EN.
>>>
>>> We previously tried to upstream all these extra feature bits in one patch
>>> (https://lore.kernel.org/all/20230414095334.8743-1-TonyWWang-oc@zhaoxin.com/),
>>> but the maintainer rejected it because there was no in-tree code using these
>>> features yet. So our current plan is to add the CPUID bits together with real
>>> kernel users step by step, Once full or partial in-tree implementations of
>>> these features are merged, we will update these definitions accordingly and
>>> potentially introduce corresponding support in QEMU.
>>
>> KVM now has a mechanism for introducing feature bits separately from the
>> kernel.  Feel free to resumit using that mechanism, then we can include
>> them from the beginning in Shinjidadao.
>>
>> Thanks,
>>
>> Paolo
> 
> Hi Paolo,
> 
> Thanks for pointing out that KVM has a mechanism for introducing feature bits
> independently from the kernel.
> 
> Before I start working on the patches, I'd like to clarify a few things:
> 
> 1. Which specific mechanism are you referring to?
>     a) The kvm_only_cpuid_leafs enum + kvm_cpu_cap_init_kvm_defined()?
>     b) Or some other approach, given that CPUID_C000_0001_EDX is already
>        a kernel-defined leaf (word 5)?

You can just add X86_FEATURE_* in arch/x86/kvm/reverse_cpuid.h.  For 
example:

/* Intel-defined sub-features, CPUID level 0x00000007:1 (EDX) */
#define X86_FEATURE_AVX_VNNI_INT8       KVM_X86_FEATURE(CPUID_7_1_EDX, 4)
#define X86_FEATURE_AVX_NE_CONVERT      KVM_X86_FEATURE(CPUID_7_1_EDX, 5)
#define X86_FEATURE_AMX_COMPLEX         KVM_X86_FEATURE(CPUID_7_1_EDX, 8)
#define X86_FEATURE_AVX_VNNI_INT16      KVM_X86_FEATURE(CPUID_7_1_EDX, 10)
#define X86_FEATURE_PREFETCHITI         KVM_X86_FEATURE(CPUID_7_1_EDX, 14)
#define X86_FEATURE_AVX10               KVM_X86_FEATURE(CPUID_7_1_EDX, 19)


Paolo

> 2. Should this independent introduction be limited to CPUID_C000_0001_EDX only
> For other feature words, I assume they still need to be handled on a
> case-by-case basis depending on their semantics and QEMU support status, correct?
> 
> For context: I want to add SM2/SM3/SM4/RNG2/PHE2/RSA etc. bits to
> 0xC0000001.EDX, but these features don't have in-tree kernel users yet.
> 
> Thanks,
> Ewan
> 
>>> Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
>>> ---
>>>    target/i386/cpu.c | 4 ++--
>>>    1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>>> index 34e3e66344..10603eeb31 100644
>>> --- a/target/i386/cpu.c
>>> +++ b/target/i386/cpu.c
>>> @@ -6958,8 +6958,8 @@ static const X86CPUDefinition builtin_x86_defs[] = {
>>>                CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
>>>            .features[FEAT_8000_0007_EDX] = CPUID_APM_INVTSC,
>>>            /*
>>> -         * TODO: When the Linux kernel introduces other existing definitions
>>> -         * for this leaf, remember to update the definitions here.
>>> +         * missing: SM2/SM2_EN, CCS/CCS_EN, PARALLAX/PARALLAX_EN,
>>> +         * TM3/TM3_EN, RNG2/RNG2_EN, PHE2/PHE2_EN, RSA/RSA_EN
>>>             */
>>>            .features[FEAT_C000_0001_EDX] =
>>>                CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM |
>>
> 
> 
> 

Re: [PATCH v3 3/3] target/i386: Fix FEAT_C000_0001_EDX comment in Yongfeng model

[Ewan Hai]

On 2/9/26 4:48 PM, Paolo Bonzini wrote:
> 
> 
> On 2/9/26 09:15, Ewan Hai wrote:
>> On 2/7/26 9:44 PM, Paolo Bonzini wrote:
>>>
>>>
>>> On 1/9/26 03:10, Ewan Hai wrote:
>>>> Update the comment for FEAT_C000_0001_EDX in YongFeng CPU model to
>>>> accurately list the missing features instead of the generic TODO message.
>>>>
>>>> As background, current Zhaoxin CPUs implement several CPUID.(EAX=0xC0000001,
>>>> ECX=0):EDX feature bits that are not yet defined in the Linux kernel, for
>>>> example SM2/SM2_EN, SM3/SM4 and their enable bits, PARALLAX/PARALLAX_EN,
>>>> TM3/TM3_EN, RNG2/RNG2_EN, PHE2/PHE2_EN, and RSA/RSA_EN.
>>>>
>>>> We previously tried to upstream all these extra feature bits in one patch
>>>> (https://lore.kernel.org/all/20230414095334.8743-1-TonyWWang-oc@zhaoxin.com/),
>>>> but the maintainer rejected it because there was no in-tree code using these
>>>> features yet. So our current plan is to add the CPUID bits together with real
>>>> kernel users step by step, Once full or partial in-tree implementations of
>>>> these features are merged, we will update these definitions accordingly and
>>>> potentially introduce corresponding support in QEMU.
>>>
>>> KVM now has a mechanism for introducing feature bits separately from the
>>> kernel.  Feel free to resumit using that mechanism, then we can include
>>> them from the beginning in Shinjidadao.
>>>
>>> Thanks,
>>>
>>> Paolo
>>
>> Hi Paolo,
>>
>> Thanks for pointing out that KVM has a mechanism for introducing feature bits
>> independently from the kernel.
>>
>> Before I start working on the patches, I'd like to clarify a few things:
>>
>> 1. Which specific mechanism are you referring to?
>>     a) The kvm_only_cpuid_leafs enum + kvm_cpu_cap_init_kvm_defined()?
>>     b) Or some other approach, given that CPUID_C000_0001_EDX is already
>>        a kernel-defined leaf (word 5)?
> 
> You can just add X86_FEATURE_* in arch/x86/kvm/reverse_cpuid.h.  For
> example:
> 
> /* Intel-defined sub-features, CPUID level 0x00000007:1 (EDX) */
> #define X86_FEATURE_AVX_VNNI_INT8       KVM_X86_FEATURE(CPUID_7_1_EDX, 4)
> #define X86_FEATURE_AVX_NE_CONVERT      KVM_X86_FEATURE(CPUID_7_1_EDX, 5)
> #define X86_FEATURE_AMX_COMPLEX         KVM_X86_FEATURE(CPUID_7_1_EDX, 8)
> #define X86_FEATURE_AVX_VNNI_INT16      KVM_X86_FEATURE(CPUID_7_1_EDX, 10)
> #define X86_FEATURE_PREFETCHITI         KVM_X86_FEATURE(CPUID_7_1_EDX, 14)
> #define X86_FEATURE_AVX10               KVM_X86_FEATURE(CPUID_7_1_EDX, 19)
> 
> 
> Paolo
> 

Got it. Thanks!