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* [PATCH 0/6] or1k: Rename the architecture from openrisc
@ 2026-02-05  3:02 Richard Henderson
  2026-02-05  3:02 ` [PATCH 1/6] target/or1k: Rename " Richard Henderson
                   ` (8 more replies)
  0 siblings, 9 replies; 17+ messages in thread
From: Richard Henderson @ 2026-02-05  3:02 UTC (permalink / raw)
  To: qemu-devel; +Cc: pierrick.bouvier, shorne

We have an odd mix of 'openrisc' and 'or1k' in use.
Standardize TARGET_ARCH and all of the filenames to use 'or1k'.


r~


Richard Henderson (6):
  target/or1k: Rename from openrisc
  include/hw/or1k: Rename from openrisc
  hw/or1k: Rename from openrisc
  tests/tcg/or1k: Rename from openrisc
  docs/system/or1k: Rename from openrisc
  hw/or1k: Rename or1k-sim.c from openrisc_sim.c

 include/exec/poison.h                              |  2 +-
 include/hw/{openrisc => or1k}/boot.h               |  6 +++---
 include/system/arch_init.h                         |  2 +-
 include/user/abitypes.h                            |  2 +-
 linux-user/{openrisc => or1k}/sockbits.h           |  0
 linux-user/{openrisc => or1k}/target_cpu.h         |  0
 linux-user/{openrisc => or1k}/target_elf.h         |  0
 linux-user/{openrisc => or1k}/target_errno_defs.h  |  0
 linux-user/{openrisc => or1k}/target_fcntl.h       |  0
 linux-user/{openrisc => or1k}/target_mman.h        |  0
 linux-user/{openrisc => or1k}/target_prctl.h       |  0
 linux-user/{openrisc => or1k}/target_proc.h        |  0
 linux-user/{openrisc => or1k}/target_ptrace.h      |  0
 linux-user/{openrisc => or1k}/target_resource.h    |  0
 linux-user/{openrisc => or1k}/target_signal.h      |  0
 linux-user/{openrisc => or1k}/target_structs.h     |  0
 linux-user/{openrisc => or1k}/target_syscall.h     |  0
 linux-user/{openrisc => or1k}/termbits.h           |  0
 linux-user/syscall_defs.h                          |  4 ++--
 target/{openrisc => or1k}/cpu-param.h              |  0
 target/{openrisc => or1k}/cpu-qom.h                |  0
 target/{openrisc => or1k}/cpu.h                    |  0
 target/{openrisc => or1k}/exception.h              |  0
 target/{openrisc => or1k}/helper.h                 |  0
 hw/{openrisc => or1k}/boot.c                       |  2 +-
 hw/{openrisc => or1k}/cputimer.c                   |  0
 hw/{openrisc/openrisc_sim.c => or1k/or1k-sim.c}    |  2 +-
 hw/{openrisc => or1k}/virt.c                       |  2 +-
 linux-user/{openrisc => or1k}/cpu_loop.c           |  0
 linux-user/{openrisc => or1k}/elfload.c            |  0
 linux-user/{openrisc => or1k}/signal.c             |  0
 system/qdev-monitor.c                              |  2 +-
 target/{openrisc => or1k}/cpu.c                    |  0
 target/{openrisc => or1k}/disas.c                  |  0
 target/{openrisc => or1k}/exception.c              |  0
 target/{openrisc => or1k}/exception_helper.c       |  0
 target/{openrisc => or1k}/fpu_helper.c             |  0
 target/{openrisc => or1k}/gdbstub.c                |  0
 target/{openrisc => or1k}/interrupt.c              |  0
 target/{openrisc => or1k}/interrupt_helper.c       |  0
 target/{openrisc => or1k}/machine.c                |  0
 target/{openrisc => or1k}/mmu.c                    |  0
 target/{openrisc => or1k}/sys_helper.c             |  0
 target/{openrisc => or1k}/translate.c              |  0
 tests/tcg/{openrisc => or1k}/test_add.c            |  0
 tests/tcg/{openrisc => or1k}/test_addc.c           |  0
 tests/tcg/{openrisc => or1k}/test_addi.c           |  0
 tests/tcg/{openrisc => or1k}/test_addic.c          |  0
 tests/tcg/{openrisc => or1k}/test_and_or.c         |  0
 tests/tcg/{openrisc => or1k}/test_bf.c             |  0
 tests/tcg/{openrisc => or1k}/test_bnf.c            |  0
 tests/tcg/{openrisc => or1k}/test_div.c            |  0
 tests/tcg/{openrisc => or1k}/test_divu.c           |  0
 tests/tcg/{openrisc => or1k}/test_extx.c           |  0
 tests/tcg/{openrisc => or1k}/test_fx.c             |  0
 tests/tcg/{openrisc => or1k}/test_j.c              |  0
 tests/tcg/{openrisc => or1k}/test_jal.c            |  0
 tests/tcg/{openrisc => or1k}/test_lf_add.c         |  0
 tests/tcg/{openrisc => or1k}/test_lf_div.c         |  0
 tests/tcg/{openrisc => or1k}/test_lf_eqs.c         |  0
 tests/tcg/{openrisc => or1k}/test_lf_ges.c         |  0
 tests/tcg/{openrisc => or1k}/test_lf_gts.c         |  0
 tests/tcg/{openrisc => or1k}/test_lf_les.c         |  0
 tests/tcg/{openrisc => or1k}/test_lf_lts.c         |  0
 tests/tcg/{openrisc => or1k}/test_lf_mul.c         |  0
 tests/tcg/{openrisc => or1k}/test_lf_nes.c         |  0
 tests/tcg/{openrisc => or1k}/test_lf_rem.c         |  0
 tests/tcg/{openrisc => or1k}/test_lf_sub.c         |  0
 tests/tcg/{openrisc => or1k}/test_logic.c          |  0
 tests/tcg/{openrisc => or1k}/test_lx.c             |  0
 tests/tcg/{openrisc => or1k}/test_movhi.c          |  0
 tests/tcg/{openrisc => or1k}/test_mul.c            |  0
 tests/tcg/{openrisc => or1k}/test_muli.c           |  0
 tests/tcg/{openrisc => or1k}/test_mulu.c           |  0
 tests/tcg/{openrisc => or1k}/test_sfeq.c           |  0
 tests/tcg/{openrisc => or1k}/test_sfeqi.c          |  0
 tests/tcg/{openrisc => or1k}/test_sfges.c          |  0
 tests/tcg/{openrisc => or1k}/test_sfgesi.c         |  0
 tests/tcg/{openrisc => or1k}/test_sfgeu.c          |  0
 tests/tcg/{openrisc => or1k}/test_sfgeui.c         |  0
 tests/tcg/{openrisc => or1k}/test_sfgts.c          |  0
 tests/tcg/{openrisc => or1k}/test_sfgtsi.c         |  0
 tests/tcg/{openrisc => or1k}/test_sfgtu.c          |  0
 tests/tcg/{openrisc => or1k}/test_sfgtui.c         |  0
 tests/tcg/{openrisc => or1k}/test_sfles.c          |  0
 tests/tcg/{openrisc => or1k}/test_sflesi.c         |  0
 tests/tcg/{openrisc => or1k}/test_sfleu.c          |  0
 tests/tcg/{openrisc => or1k}/test_sfleui.c         |  0
 tests/tcg/{openrisc => or1k}/test_sflts.c          |  0
 tests/tcg/{openrisc => or1k}/test_sfltsi.c         |  0
 tests/tcg/{openrisc => or1k}/test_sfltu.c          |  0
 tests/tcg/{openrisc => or1k}/test_sfltui.c         |  0
 tests/tcg/{openrisc => or1k}/test_sfne.c           |  0
 tests/tcg/{openrisc => or1k}/test_sfnei.c          |  0
 tests/tcg/{openrisc => or1k}/test_sub.c            |  0
 MAINTAINERS                                        | 14 +++++++-------
 configs/targets/or1k-linux-user.mak                |  2 +-
 configs/targets/or1k-softmmu.mak                   |  2 +-
 docs/system/{openrisc => or1k}/cpu-features.rst    |  0
 docs/system/{openrisc => or1k}/emulation.rst       |  0
 docs/system/{openrisc => or1k}/or1k-sim.rst        |  0
 docs/system/{openrisc => or1k}/virt.rst            |  0
 .../{target-openrisc.rst => target-or1k.rst}       |  8 ++++----
 docs/system/targets.rst                            |  2 +-
 hw/Kconfig                                         |  2 +-
 hw/meson.build                                     |  2 +-
 hw/{openrisc => or1k}/Kconfig                      |  4 ++--
 hw/{openrisc => or1k}/meson.build                  |  4 ++--
 linux-user/meson.build                             |  2 +-
 linux-user/openrisc/meson.build                    |  5 -----
 linux-user/or1k/meson.build                        |  5 +++++
 linux-user/{openrisc => or1k}/syscall.tbl          |  0
 linux-user/{openrisc => or1k}/syscallhdr.sh        |  0
 target/Kconfig                                     |  2 +-
 target/meson.build                                 |  2 +-
 target/{openrisc => or1k}/Kconfig                  |  2 +-
 target/{openrisc => or1k}/insns.decode             |  0
 target/{openrisc => or1k}/meson.build              |  4 ++--
 tests/tcg/{openrisc => or1k}/Makefile              |  0
 119 files changed, 43 insertions(+), 43 deletions(-)
 rename include/hw/{openrisc => or1k}/boot.h (93%)
 rename linux-user/{openrisc => or1k}/sockbits.h (100%)
 rename linux-user/{openrisc => or1k}/target_cpu.h (100%)
 rename linux-user/{openrisc => or1k}/target_elf.h (100%)
 rename linux-user/{openrisc => or1k}/target_errno_defs.h (100%)
 rename linux-user/{openrisc => or1k}/target_fcntl.h (100%)
 rename linux-user/{openrisc => or1k}/target_mman.h (100%)
 rename linux-user/{openrisc => or1k}/target_prctl.h (100%)
 rename linux-user/{openrisc => or1k}/target_proc.h (100%)
 rename linux-user/{openrisc => or1k}/target_ptrace.h (100%)
 rename linux-user/{openrisc => or1k}/target_resource.h (100%)
 rename linux-user/{openrisc => or1k}/target_signal.h (100%)
 rename linux-user/{openrisc => or1k}/target_structs.h (100%)
 rename linux-user/{openrisc => or1k}/target_syscall.h (100%)
 rename linux-user/{openrisc => or1k}/termbits.h (100%)
 rename target/{openrisc => or1k}/cpu-param.h (100%)
 rename target/{openrisc => or1k}/cpu-qom.h (100%)
 rename target/{openrisc => or1k}/cpu.h (100%)
 rename target/{openrisc => or1k}/exception.h (100%)
 rename target/{openrisc => or1k}/helper.h (100%)
 rename hw/{openrisc => or1k}/boot.c (99%)
 rename hw/{openrisc => or1k}/cputimer.c (100%)
 rename hw/{openrisc/openrisc_sim.c => or1k/or1k-sim.c} (99%)
 rename hw/{openrisc => or1k}/virt.c (99%)
 rename linux-user/{openrisc => or1k}/cpu_loop.c (100%)
 rename linux-user/{openrisc => or1k}/elfload.c (100%)
 rename linux-user/{openrisc => or1k}/signal.c (100%)
 rename target/{openrisc => or1k}/cpu.c (100%)
 rename target/{openrisc => or1k}/disas.c (100%)
 rename target/{openrisc => or1k}/exception.c (100%)
 rename target/{openrisc => or1k}/exception_helper.c (100%)
 rename target/{openrisc => or1k}/fpu_helper.c (100%)
 rename target/{openrisc => or1k}/gdbstub.c (100%)
 rename target/{openrisc => or1k}/interrupt.c (100%)
 rename target/{openrisc => or1k}/interrupt_helper.c (100%)
 rename target/{openrisc => or1k}/machine.c (100%)
 rename target/{openrisc => or1k}/mmu.c (100%)
 rename target/{openrisc => or1k}/sys_helper.c (100%)
 rename target/{openrisc => or1k}/translate.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_add.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_addc.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_addi.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_addic.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_and_or.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_bf.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_bnf.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_div.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_divu.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_extx.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_fx.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_j.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_jal.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_lf_add.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_lf_div.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_lf_eqs.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_lf_ges.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_lf_gts.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_lf_les.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_lf_lts.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_lf_mul.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_lf_nes.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_lf_rem.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_lf_sub.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_logic.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_lx.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_movhi.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_mul.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_muli.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_mulu.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sfeq.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sfeqi.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sfges.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sfgesi.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sfgeu.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sfgeui.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sfgts.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sfgtsi.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sfgtu.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sfgtui.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sfles.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sflesi.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sfleu.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sfleui.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sflts.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sfltsi.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sfltu.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sfltui.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sfne.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sfnei.c (100%)
 rename tests/tcg/{openrisc => or1k}/test_sub.c (100%)
 rename docs/system/{openrisc => or1k}/cpu-features.rst (100%)
 rename docs/system/{openrisc => or1k}/emulation.rst (100%)
 rename docs/system/{openrisc => or1k}/or1k-sim.rst (100%)
 rename docs/system/{openrisc => or1k}/virt.rst (100%)
 rename docs/system/{target-openrisc.rst => target-or1k.rst} (96%)
 rename hw/{openrisc => or1k}/Kconfig (89%)
 rename hw/{openrisc => or1k}/meson.build (60%)
 delete mode 100644 linux-user/openrisc/meson.build
 create mode 100644 linux-user/or1k/meson.build
 rename linux-user/{openrisc => or1k}/syscall.tbl (100%)
 rename linux-user/{openrisc => or1k}/syscallhdr.sh (100%)
 rename target/{openrisc => or1k}/Kconfig (76%)
 rename target/{openrisc => or1k}/insns.decode (100%)
 rename target/{openrisc => or1k}/meson.build (79%)
 rename tests/tcg/{openrisc => or1k}/Makefile (100%)

-- 
2.43.0



^ permalink raw reply	[flat|nested] 17+ messages in thread

end of thread, other threads:[~2026-02-06 21:37 UTC | newest]

Thread overview: 17+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-02-05  3:02 [PATCH 0/6] or1k: Rename the architecture from openrisc Richard Henderson
2026-02-05  3:02 ` [PATCH 1/6] target/or1k: Rename " Richard Henderson
2026-02-05 15:46   ` Philippe Mathieu-Daudé
2026-02-05  3:02 ` [PATCH 2/6] include/hw/or1k: " Richard Henderson
2026-02-06 11:15   ` Stafford Horne
2026-02-05  3:02 ` [PATCH 3/6] hw/or1k: " Richard Henderson
2026-02-05 15:43   ` Philippe Mathieu-Daudé
2026-02-05  3:02 ` [PATCH 4/6] tests/tcg/or1k: " Richard Henderson
2026-02-06 11:16   ` Stafford Horne
2026-02-05  3:02 ` [PATCH 5/6] docs/system/or1k: " Richard Henderson
2026-02-06 11:18   ` Stafford Horne
2026-02-05  3:02 ` [PATCH 6/6] hw/or1k: Rename or1k-sim.c from openrisc_sim.c Richard Henderson
2026-02-06 11:19   ` Stafford Horne
2026-02-05  5:23 ` [PATCH 0/6] or1k: Rename the architecture from openrisc Pierrick Bouvier
2026-02-05 15:39 ` Philippe Mathieu-Daudé
2026-02-05 15:47   ` Philippe Mathieu-Daudé
2026-02-06 21:37 ` Philippe Mathieu-Daudé

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