[PATCH 5.10.y-cip 0/4] arm64: dts: renesas: Add max-frequency to SDHI nodes

[PATCH 5.10.y-cip 0/4] arm64: dts: renesas: Add max-frequency to SDHI nodes

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Hi All,

This patch series aims to add the max-frequency property set to
133333333 Hz (133.33 MHz) to both SDHI0 and SDHI1 MMC controller nodes in
the RZ/G2{L,LC,UL}/RZ/V2L device tree.

This change results in approximately 33% performance improvement as
it sets the SD clk to 100 MHz instead of the max 133 MHz.

All the patches in this series are cherry-picked from mainline.

Biju Das (4):
  arm64: dts: renesas: r9a07g043: Add max-frequency to SDHI nodes
  arm64: dts: renesas: r9a07g044: Rename SDHI clocks
  arm64: dts: renesas: r9a07g044: Add max-frequency to SDHI nodes
  arm64: dts: renesas: r9a07g054: Add max-frequency to SDHI nodes

 arch/arm64/boot/dts/renesas/r9a07g043.dtsi |  2 ++
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 10 ++++++----
 arch/arm64/boot/dts/renesas/r9a07g054.dtsi |  2 ++
 3 files changed, 10 insertions(+), 4 deletions(-)

-- 
2.43.0

[PATCH 5.10.y-cip 1/4] arm64: dts: renesas: r9a07g043: Add max-frequency to SDHI nodes

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

[ Upstream commit f82892de7f4878f54a4035be06f3acc6e6449616 ]

Add the max-frequency property set to 133333333 Hz (133.33 MHz) to both
SDHI0 and SDHI1 MMC controller nodes in the RZ/{G2UL,Five} (r9a07g043)
device tree, increasing performance by ca. 33%.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260520115144.60067-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 7b07bcb3be88..5aff8345d690 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -655,6 +655,7 @@ sdhi0: mmc@11c00000 {
 				 <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
 				 <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
+			max-frequency = <133333333>;
 			resets = <&cpg R9A07G043_SDHI0_IXRST>;
 			power-domains = <&cpg>;
 			status = "disabled";
@@ -671,6 +672,7 @@ sdhi1: mmc@11c10000 {
 				 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
 				 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
+			max-frequency = <133333333>;
 			resets = <&cpg R9A07G043_SDHI1_IXRST>;
 			power-domains = <&cpg>;
 			status = "disabled";
-- 
2.43.0

[PATCH 5.10.y-cip 2/4] arm64: dts: renesas: r9a07g044: Rename SDHI clocks

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

[ Upstream commit fee3eae1334a454a8c2e16313a374cc53ff722d8 ]

Rename the below SDHI clocks to match with the clocks used in driver.

     imclk->core
     clk_hs->clkh
     imclk2->cd

Also re-arrange the clocks to match with the sorting order used in the
binding document.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Link: https://lore.kernel.org/r/20211122103905.14439-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 327e7bf983a7..3fcce6324097 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -1055,10 +1055,10 @@ sdhi0: mmc@11c00000 {
 			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
-				 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
 				 <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
+				 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
 				 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
-			clock-names = "imclk", "imclk2", "clk_hs", "aclk";
+			clock-names = "core", "clkh", "cd", "aclk";
 			resets = <&cpg R9A07G044_SDHI0_IXRST>;
 			power-domains = <&cpg>;
 			status = "disabled";
@@ -1071,10 +1071,10 @@ sdhi1: mmc@11c10000 {
 			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
-				 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
 				 <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
+				 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
 				 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
-			clock-names = "imclk", "imclk2", "clk_hs", "aclk";
+			clock-names = "core", "clkh", "cd", "aclk";
 			resets = <&cpg R9A07G044_SDHI1_IXRST>;
 			power-domains = <&cpg>;
 			status = "disabled";
-- 
2.43.0

[PATCH 5.10.y-cip 3/4] arm64: dts: renesas: r9a07g044: Add max-frequency to SDHI nodes

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

[ Upstream commit 1b3c392bd655af31a414fc82382cec13e090a997 ]

Add the max-frequency property set to 133333333 Hz (133.33 MHz) to both
SDHI0 and SDHI1 MMC controller nodes in the RZ/{G2L,G2LC} (r9a07g044)
device tree, increasing performance by ca. 33%.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260520115144.60067-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 3fcce6324097..e14728d70cfb 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -1059,6 +1059,7 @@ sdhi0: mmc@11c00000 {
 				 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
 				 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
+			max-frequency = <133333333>;
 			resets = <&cpg R9A07G044_SDHI0_IXRST>;
 			power-domains = <&cpg>;
 			status = "disabled";
@@ -1075,6 +1076,7 @@ sdhi1: mmc@11c10000 {
 				 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
 				 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
+			max-frequency = <133333333>;
 			resets = <&cpg R9A07G044_SDHI1_IXRST>;
 			power-domains = <&cpg>;
 			status = "disabled";
-- 
2.43.0

[PATCH 5.10.y-cip 4/4] arm64: dts: renesas: r9a07g054: Add max-frequency to SDHI nodes

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

[ Upstream commit dcbbb1266043d1d7ca1f129d2ca58a6ce8e04cbb ]

Add the max-frequency property set to 133333333 Hz (133.33 MHz) to both
SDHI0 and SDHI1 MMC controller nodes in the RZ/V2L (r9a07g054) device
tree, increasing performance by ca. 33%.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260520115144.60067-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 4417135c5134..60f82f403fed 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -1067,6 +1067,7 @@ sdhi0: mmc@11c00000 {
 				 <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
 				 <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
+			max-frequency = <133333333>;
 			resets = <&cpg R9A07G054_SDHI0_IXRST>;
 			power-domains = <&cpg>;
 			status = "disabled";
@@ -1083,6 +1084,7 @@ sdhi1: mmc@11c10000 {
 				 <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
 				 <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
+			max-frequency = <133333333>;
 			resets = <&cpg R9A07G054_SDHI1_IXRST>;
 			power-domains = <&cpg>;
 			status = "disabled";
-- 
2.43.0

Re: [PATCH 5.10.y-cip 0/4] arm64: dts: renesas: Add max-frequency to SDHI nodes

[Pavel Machek]

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Hi!

> This patch series aims to add the max-frequency property set to
> 133333333 Hz (133.33 MHz) to both SDHI0 and SDHI1 MMC controller nodes in
> the RZ/G2{L,LC,UL}/RZ/V2L device tree.
> 
> This change results in approximately 33% performance improvement as
> it sets the SD clk to 100 MHz instead of the max 133 MHz.
> 
> All the patches in this series are cherry-picked from mainline.

Ok, so as I understand it, we don't need this for 6.1-cip and others,
because it is already in mainline 6.1, so no backport is needed.

Best regards,
								Pavel

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Re: [PATCH 5.10.y-cip 0/4] arm64: dts: renesas: Add max-frequency to SDHI nodes

[Biju Das]

Hi Pavel,

Thanks for the  feedback.

On Mon, Jul 13, 2026 at 10:09 PM Pavel Machek <pavel@nabladev.com> wrote:
>
> Hi!
>
> > This patch series aims to add the max-frequency property set to
> > 133333333 Hz (133.33 MHz) to both SDHI0 and SDHI1 MMC controller nodes in
> > the RZ/G2{L,LC,UL}/RZ/V2L device tree.
> >
> > This change results in approximately 33% performance improvement as
> > it sets the SD clk to 100 MHz instead of the max 133 MHz.
> >
> > All the patches in this series are cherry-picked from mainline.
>
> Ok, so as I understand it, we don't need this for 6.1-cip and others,
> because it is already in mainline 6.1, so no backport is needed.

We recently (7.2-rc1) upstreamed this patch.

Yesterday, a job in Lava setup showed the problem in 5.10-y cip. So,
just to fix that issue, I sent these patches
Soon I will be sending patches for  6.1 and 6.12-cip.

Cheers,
Biju

Re: [PATCH 5.10.y-cip 0/4] arm64: dts: renesas: Add max-frequency to SDHI nodes

[Pavel Machek]

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Hi!

> > > This patch series aims to add the max-frequency property set to
> > > 133333333 Hz (133.33 MHz) to both SDHI0 and SDHI1 MMC controller nodes in
> > > the RZ/G2{L,LC,UL}/RZ/V2L device tree.
> > >
> > > This change results in approximately 33% performance improvement as
> > > it sets the SD clk to 100 MHz instead of the max 133 MHz.
> > >
> > > All the patches in this series are cherry-picked from mainline.
> >
> > Ok, so as I understand it, we don't need this for 6.1-cip and others,
> > because it is already in mainline 6.1, so no backport is needed.
> 
> We recently (7.2-rc1) upstreamed this patch.
> 
> Yesterday, a job in Lava setup showed the problem in 5.10-y cip. So,
> just to fix that issue, I sent these patches
> Soon I will be sending patches for  6.1 and 6.12-cip.

Aha, one of patches was older and that confused me.

So 6.1 and 6.12 versions are just performance improvements, and 5.10
fixes a bug, too?

Thanks and best regards,
								Pavel

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Re: [PATCH 5.10.y-cip 0/4] arm64: dts: renesas: Add max-frequency to SDHI nodes

[Pavel Machek]

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Hi!

> This patch series aims to add the max-frequency property set to
> 133333333 Hz (133.33 MHz) to both SDHI0 and SDHI1 MMC controller nodes in
> the RZ/G2{L,LC,UL}/RZ/V2L device tree.
> 
> This change results in approximately 33% performance improvement as
> it sets the SD clk to 100 MHz instead of the max 133 MHz.
> 
> All the patches in this series are cherry-picked from mainline.

This looks okay to me.

Reviewed-by: Pavel Machek <pavel@nabladev.com>

I can apply the series if it passes testing and there are no other
comments.

Best regards,
                                                                Pavel

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Re: [PATCH 5.10.y-cip 0/4] arm64: dts: renesas: Add max-frequency to SDHI nodes

[Pavel Machek]

[-- Attachment #1: Type: text/plain, Size: 455 bytes --]

Hi!

> This patch series aims to add the max-frequency property set to
> 133333333 Hz (133.33 MHz) to both SDHI0 and SDHI1 MMC controller nodes in
> the RZ/G2{L,LC,UL}/RZ/V2L device tree.
> 
> This change results in approximately 33% performance improvement as
> it sets the SD clk to 100 MHz instead of the max 133 MHz.
> 
> All the patches in this series are cherry-picked from mainline.

Thank you, applied.

Best regards,
								Pavel

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