[PATCH v2 0/4] RISC-V: ACPI: Add PPTT support

[PATCH v2 0/4] RISC-V: ACPI: Add PPTT support

[Sunil V L]

Hi all,

This series adds ACPI Processor Properties Topology Table (PPTT) support to
the RISC-V virt machine. PPTT allows the guest to discover the processor and
cache topology exposed by the machine, which is useful for making better
scheduling and cache-management decisions.

The implementation describes the RISC-V virt cache hierarchy with separate
L1 instruction and data caches, followed by unified L2 and L3 caches. It also
enables the corresponding cache and cluster properties in the machine SMP
description and wires the generated PPTT into the existing ACPI table
build.

Unlike ARM, RISC-V doesn't have a way to discover the Cache
topology from registers. Hence, I am hardcoding default values for the
cache topology structures. These cache topology structures are added in
virt.c itself so that a future series can add support for DT as well. In
future, it can be enhanced to support vendor cpu/soc specific cache
information to override this default hardcoded cache details.

The series also updates the bios-tables-test data and removes the temporary
PPTT entry from the allowed-diff list. The generated table is 96 bytes and
describes the package, cluster, and processor hierarchy for the virt machine.

This work follows the discussion and earlier work shared here:
https://lists.gnu.org/archive/html/qemu-riscv/2024-01/msg00928.html

I have retained the contribution from Sia Jee Heng and added his
Signed-off-by tag to the relevant patch.

To enable cache structures in the PPTT, one should use similar to below
command line option.

-M virt,smp-cache.0.cache=l1d,smp-cache.0.topology=core,smp-cache.1.cache=l1i,smp-cache.1.topology=core,smp-cache.2.cache=l2,smp-cache.2.topology=cluster,smp-cache.3.cache=l3,smp-cache.3.topology=socket

lscpu -C in linux can be used to display these cache structures.

Changes from v1:
	1) Replaced loop with memcpy
	2) Made virt_caches static in virt.c
	3) Added Daniel's RB tags

Sunil V L (4):

Sunil V L (4):
  tests/qtest/bios-tables-test: Allow PPTT for RISC-V
  hw/riscv/virt: Add ACPI PPTT table
  tests/qtest/bios-tables-test: Update riscv64 virt PPTT golden
    reference
  MAINTAINERS: Update Sunil's email id

 MAINTAINERS                       |   2 +-
 hw/riscv/virt-acpi-build.c        |   7 ++++
 hw/riscv/virt.c                   |  51 ++++++++++++++++++++++++++++++
 include/hw/riscv/virt.h           |   4 +++
 tests/data/acpi/riscv64/virt/PPTT | Bin 0 -> 96 bytes
 5 files changed, 63 insertions(+), 1 deletion(-)
 create mode 100644 tests/data/acpi/riscv64/virt/PPTT

-- 
2.43.0

[PATCH v2 1/4] tests/qtest/bios-tables-test: Allow PPTT for RISC-V

[Sunil V L]

Allow changes to the riscv64 virt board to add PPTT support.

Signed-off-by: Sunil V L <sunilvl@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
 tests/data/acpi/riscv64/virt/PPTT           | 0
 tests/qtest/bios-tables-test-allowed-diff.h | 1 +
 2 files changed, 1 insertion(+)
 create mode 100644 tests/data/acpi/riscv64/virt/PPTT

diff --git a/tests/data/acpi/riscv64/virt/PPTT b/tests/data/acpi/riscv64/virt/PPTT
new file mode 100644
index 000000000000..e69de29bb2d1
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8bf4..94be7a69a22e 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,2 @@
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/riscv64/virt/PPTT",
-- 
2.43.0

[PATCH v2 2/4] hw/riscv/virt: Add ACPI PPTT table

[Sunil V L]

Generate the Processor Properties Topology Table (PPTT) for the RISC-V
virt machine.

Describe the machine using separate L1 data and instruction caches plus
unified L2 and L3 caches, and enable the corresponding cache and cluster
SMP properties.

Signed-off-by: Sunil V L <sunilvl@oss.qualcomm.com>
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
---
 hw/riscv/virt-acpi-build.c |  7 ++++++
 hw/riscv/virt.c            | 51 ++++++++++++++++++++++++++++++++++++++
 include/hw/riscv/virt.h    |  4 +++
 3 files changed, 62 insertions(+)

diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 0475dcb5c601..8254f1294a72 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -882,7 +882,10 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
     unsigned dsdt, xsdt;
     GArray *tables_blob = tables->table_data;
     MachineState *ms = MACHINE(s);
+    CPUCoreCaches caches[CPU_MAX_CACHES];
+    unsigned int num_caches;
 
+    num_caches = virt_get_caches(caches);
     table_offsets = g_array_new(false, true,
                                 sizeof(uint32_t));
 
@@ -909,6 +912,10 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
         build_rimt(tables_blob, tables->linker, s);
     }
 
+    acpi_add_table(table_offsets, tables_blob);
+    build_pptt(tables_blob, tables->linker, ms, s->oem_id,
+               s->oem_table_id, num_caches, caches);
+
     acpi_add_table(table_offsets, tables_blob);
 
     if (ms->acpi_spcr_enabled) {
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index d4b501802f60..c84b17a40125 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -109,6 +109,45 @@ static const MemMapEntry virt_memmap[] = {
     [VIRT_DRAM] =         { 0x80000000,           0x0 },
 };
 
+static CPUCoreCaches virt_caches[] = {
+    {
+        .type = DATA_CACHE,
+        .sets = 256,
+        .size = 64 * KiB,
+        .level = 1,
+        .linesize = 64,
+        .attributes = 0x0,
+        .associativity = 4,
+    },
+    {
+        .type = INSTRUCTION_CACHE,
+        .sets = 256,
+        .size = 64 * KiB,
+        .level = 1,
+        .linesize = 64,
+        .attributes = 0x0,
+        .associativity = 4,
+    },
+    {
+        .type = UNIFIED_CACHE,
+        .sets = 4096,
+        .size = 2048 * KiB,
+        .level = 2,
+        .linesize = 64,
+        .attributes = 0x0,
+        .associativity = 8,
+    },
+    {
+        .type = UNIFIED_CACHE,
+        .sets = 8192,
+        .size = 4096 * KiB,
+        .level = 3,
+        .linesize = 64,
+        .attributes = 0x0,
+        .associativity = 8,
+    },
+};
+
 /* PCIe high mmio is fixed for RV32 */
 #define VIRT32_HIGH_PCIE_MMIO_BASE  0x300000000ULL
 #define VIRT32_HIGH_PCIE_MMIO_SIZE  (4 * GiB)
@@ -140,6 +179,12 @@ static void virt_flash_map(RISCVVirtState *s,
                          sysmem, VIRT_FLASH_SECTOR_SIZE);
 }
 
+unsigned int virt_get_caches(CPUCoreCaches *caches)
+{
+    memcpy(caches, virt_caches, sizeof(virt_caches));
+    return ARRAY_SIZE(virt_caches);
+}
+
 static void create_fdt_socket_plic(RISCVVirtState *s,
                                    int socket,
                                    uint32_t *phandle, uint32_t *intc_phandles,
@@ -1144,6 +1189,12 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data)
     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
     mc->numa_mem_supported = true;
+    mc->smp_props.clusters_supported = true;
+    mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] = true;
+    mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] = true;
+    mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] = true;
+    mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] = true;
+
     /* platform instead of architectural choice */
     mc->cpu_cluster_has_numa_boundary = true;
     mc->default_ram_id = "riscv_virt_board.ram";
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index e516898f9ad9..1e498a4f5f6e 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -121,10 +121,14 @@ enum {
 #define VIRT_PLIC_SIZE(__num_context) \
     (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE)
 
+#define CPU_MAX_CACHES 16
+
 bool virt_is_acpi_enabled(RISCVVirtState *s);
 bool virt_is_iommu_sys_enabled(RISCVVirtState *s);
 void virt_acpi_setup(RISCVVirtState *vms);
 
+unsigned int virt_get_caches(CPUCoreCaches *caches);
+
 /*
  * The virt machine physical address space used by some of the devices
  * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
-- 
2.43.0

Re: [PATCH v2 2/4] hw/riscv/virt: Add ACPI PPTT table

[Daniel Henrique Barboza]

On 10/15/2026 3:49 AM, Sunil V L wrote:
> Generate the Processor Properties Topology Table (PPTT) for the RISC-V
> virt machine.
> 
> Describe the machine using separate L1 data and instruction caches plus
> unified L2 and L3 caches, and enable the corresponding cache and cluster
> SMP properties.
> 
> Signed-off-by: Sunil V L <sunilvl@oss.qualcomm.com>
> Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   hw/riscv/virt-acpi-build.c |  7 ++++++
>   hw/riscv/virt.c            | 51 ++++++++++++++++++++++++++++++++++++++
>   include/hw/riscv/virt.h    |  4 +++
>   3 files changed, 62 insertions(+)
> 
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index 0475dcb5c601..8254f1294a72 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -882,7 +882,10 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
>       unsigned dsdt, xsdt;
>       GArray *tables_blob = tables->table_data;
>       MachineState *ms = MACHINE(s);
> +    CPUCoreCaches caches[CPU_MAX_CACHES];
> +    unsigned int num_caches;
>   
> +    num_caches = virt_get_caches(caches);
>       table_offsets = g_array_new(false, true,
>                                   sizeof(uint32_t));
>   
> @@ -909,6 +912,10 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
>           build_rimt(tables_blob, tables->linker, s);
>       }
>   
> +    acpi_add_table(table_offsets, tables_blob);
> +    build_pptt(tables_blob, tables->linker, ms, s->oem_id,
> +               s->oem_table_id, num_caches, caches);
> +
>       acpi_add_table(table_offsets, tables_blob);
>   
>       if (ms->acpi_spcr_enabled) {
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index d4b501802f60..c84b17a40125 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -109,6 +109,45 @@ static const MemMapEntry virt_memmap[] = {
>       [VIRT_DRAM] =         { 0x80000000,           0x0 },
>   };
>   
> +static CPUCoreCaches virt_caches[] = {
> +    {
> +        .type = DATA_CACHE,
> +        .sets = 256,
> +        .size = 64 * KiB,
> +        .level = 1,
> +        .linesize = 64,
> +        .attributes = 0x0,
> +        .associativity = 4,
> +    },
> +    {
> +        .type = INSTRUCTION_CACHE,
> +        .sets = 256,
> +        .size = 64 * KiB,
> +        .level = 1,
> +        .linesize = 64,
> +        .attributes = 0x0,
> +        .associativity = 4,
> +    },
> +    {
> +        .type = UNIFIED_CACHE,
> +        .sets = 4096,
> +        .size = 2048 * KiB,
> +        .level = 2,
> +        .linesize = 64,
> +        .attributes = 0x0,
> +        .associativity = 8,
> +    },
> +    {
> +        .type = UNIFIED_CACHE,
> +        .sets = 8192,
> +        .size = 4096 * KiB,
> +        .level = 3,
> +        .linesize = 64,
> +        .attributes = 0x0,
> +        .associativity = 8,
> +    },
> +};
> +
>   /* PCIe high mmio is fixed for RV32 */
>   #define VIRT32_HIGH_PCIE_MMIO_BASE  0x300000000ULL
>   #define VIRT32_HIGH_PCIE_MMIO_SIZE  (4 * GiB)
> @@ -140,6 +179,12 @@ static void virt_flash_map(RISCVVirtState *s,
>                            sysmem, VIRT_FLASH_SECTOR_SIZE);
>   }
>   
> +unsigned int virt_get_caches(CPUCoreCaches *caches)
> +{
> +    memcpy(caches, virt_caches, sizeof(virt_caches));
> +    return ARRAY_SIZE(virt_caches);
> +}
> +
>   static void create_fdt_socket_plic(RISCVVirtState *s,
>                                      int socket,
>                                      uint32_t *phandle, uint32_t *intc_phandles,
> @@ -1144,6 +1189,12 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data)
>       mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
>       mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
>       mc->numa_mem_supported = true;
> +    mc->smp_props.clusters_supported = true;
> +    mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] = true;
> +    mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] = true;
> +    mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] = true;
> +    mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] = true;
> +
>       /* platform instead of architectural choice */
>       mc->cpu_cluster_has_numa_boundary = true;
>       mc->default_ram_id = "riscv_virt_board.ram";
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index e516898f9ad9..1e498a4f5f6e 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -121,10 +121,14 @@ enum {
>   #define VIRT_PLIC_SIZE(__num_context) \
>       (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE)
>   
> +#define CPU_MAX_CACHES 16
> +
>   bool virt_is_acpi_enabled(RISCVVirtState *s);
>   bool virt_is_iommu_sys_enabled(RISCVVirtState *s);
>   void virt_acpi_setup(RISCVVirtState *vms);
>   
> +unsigned int virt_get_caches(CPUCoreCaches *caches);
> +
>   /*
>    * The virt machine physical address space used by some of the devices
>    * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,

[PATCH v2 3/4] tests/qtest/bios-tables-test: Update riscv64 virt PPTT golden reference

[Sunil V L]

Update the RISC-V PPTT reference to match the actual PPTT generated by
QEMU.

Diffs from iasl:

+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20230628 (64-bit version)
+ * Copyright (c) 2000 - 2023 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-DN3NW3, Sun Oct 11 23:01:04 2026
+ *
+ * ACPI Data Table [PPTT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength]  FieldName : FieldValue (in hex)
+ */
+
+[000h 0000 004h]                   Signature : "PPTT"    [Processor Properties Topology Table]
+[004h 0004 004h]                Table Length : 00000060
+[008h 0008 001h]                    Revision : 02
+[009h 0009 001h]                    Checksum : 27
+[00Ah 0010 006h]                      Oem ID : "BOCHS "
+[010h 0016 008h]                Oem Table ID : "BXPC    "
+[018h 0024 004h]                Oem Revision : 00000001
+[01Ch 0028 004h]             Asl Compiler ID : "BXPC"
+[020h 0032 004h]       Asl Compiler Revision : 00000001
+
+
+[024h 0036 001h]               Subtable Type : 00 [Processor Hierarchy Node]
+[025h 0037 001h]                      Length : 14
+[026h 0038 002h]                    Reserved : 0000
+[028h 0040 004h]       Flags (decoded below) : 00000011
+                            Physical package : 1
+                     ACPI Processor ID valid : 0
+                       Processor is a thread : 0
+                              Node is a leaf : 0
+                    Identical Implementation : 1
+[02Ch 0044 004h]                      Parent : 00000000
+[030h 0048 004h]           ACPI Processor ID : 00000000
+[034h 0052 004h]     Private Resource Number : 00000000
+
+[038h 0056 001h]               Subtable Type : 00 [Processor Hierarchy Node]
+[039h 0057 001h]                      Length : 14
+[03Ah 0058 002h]                    Reserved : 0000
+[03Ch 0060 004h]       Flags (decoded below) : 00000011
+                            Physical package : 1
+                     ACPI Processor ID valid : 0
+                       Processor is a thread : 0
+                              Node is a leaf : 0
+                    Identical Implementation : 1
+[040h 0064 004h]                      Parent : 00000024
+[044h 0068 004h]           ACPI Processor ID : 00000000
+[048h 0072 004h]     Private Resource Number : 00000000
+
+[04Ch 0076 001h]               Subtable Type : 00 [Processor Hierarchy Node]
+[04Dh 0077 001h]                      Length : 14
+[04Eh 0078 002h]                    Reserved : 0000
+[050h 0080 004h]       Flags (decoded below) : 0000000A
+                            Physical package : 0
+                     ACPI Processor ID valid : 1
+                       Processor is a thread : 0
+                              Node is a leaf : 1
+                    Identical Implementation : 0
+[054h 0084 004h]                      Parent : 00000038
+[058h 0088 004h]           ACPI Processor ID : 00000000
+[05Ch 0092 004h]     Private Resource Number : 00000000
+
+Raw Table Data: Length 96 (0x60)
+
+    0000: 50 50 54 54 60 00 00 00 02 27 42 4F 43 48 53 20  // PPTT`....'BOCHS
+    0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43  // BXPC    ....BXPC
+    0020: 01 00 00 00 00 14 00 00 11 00 00 00 00 00 00 00  // ................
+    0030: 00 00 00 00 00 00 00 00 00 14 00 00 11 00 00 00  // ................
+    0040: 24 00 00 00 00 00 00 00 00 00 00 00 00 14 00 00  // $...............
+    0050: 0A 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00  // ....8...........

Signed-off-by: Sunil V L <sunilvl@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
 tests/data/acpi/riscv64/virt/PPTT           | Bin 0 -> 96 bytes
 tests/qtest/bios-tables-test-allowed-diff.h |   1 -
 2 files changed, 1 deletion(-)

diff --git a/tests/data/acpi/riscv64/virt/PPTT b/tests/data/acpi/riscv64/virt/PPTT
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..15598a9b8a3cc0cdd50bc1f77c73ae0ba728a272 100644
GIT binary patch
literal 96
zcmWFt2nk7GU|?WUck*}k2v%^42yj*a0!E-1hz+6{L>L$ZK{PUeim9N9aRK=jNMZmJ
Cwg&+K

literal 0
HcmV?d00001

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 94be7a69a22e..dfb8523c8bf4 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,2 +1 @@
 /* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/riscv64/virt/PPTT",
-- 
2.43.0

[PATCH v2 4/4] MAINTAINERS: Update Sunil's email id

[Sunil V L]

Update my email ID to qualcomm.

Signed-off-by: Sunil V L <sunilvl@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 8cc426451c2f..5c2282088610 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2335,7 +2335,7 @@ S: Orphan
 F: hw/arm/virt-acpi-build.c
 
 RISC-V ACPI Subsystem
-M: Sunil V L <sunilvl@ventanamicro.com>
+M: Sunil V L <sunilvl@oss.qualcomm.com>
 L: qemu-riscv@nongnu.org
 S: Maintained
 F: hw/riscv/virt-acpi-build.c
-- 
2.43.0

Re: [PATCH v2 0/4] RISC-V: ACPI: Add PPTT support

[Drew Fustini]

On Thu, Oct 15, 2026 at 12:19:53PM +0530, Sunil V L wrote:
> Hi all,
> 
> This series adds ACPI Processor Properties Topology Table (PPTT) support to
> the RISC-V virt machine. PPTT allows the guest to discover the processor and
> cache topology exposed by the machine, which is useful for making better
> scheduling and cache-management decisions.

Thanks for picking up PPTT support. I can now rebase the RQSC support
[1] on this series.

However, RQSC actually needs PPTT revision 3, because it adds cache IDs
to the PPTT. The RQSC table references a capacity controller's cache by
the PPTT cache ID. In Linux, find_acpi_cache_level_from_id() and
acpi_pptt_get_cpumask_from_cache_id() return -ENOENT if PPTT rev < 3.

There is a new MPAM series by Jinjie Ruan which contains the patch
"[PATCH 04/37] hw/acpi: Build PPTT rev 3 with cache IDs for MPAM
cross-references" [2]. It bumps build_pptt() to revision 3 and gives
every cache node an ID.

I could just base the RQSC series on this PPTT series and that patch
03/37. But maybe there is a better way to coordinate adding PPTT v3?

Thanks,
Drew

[1] https://lore.kernel.org/all/20260202-riscv-rqsc-v1-0-dcf448a3ed73@kernel.org/
[2] https://lore.kernel.org/all/tencent_F9C68A515AC6C40BE2C32DB314E14CCB7106@qq.com/

Re: [PATCH v2 0/4] RISC-V: ACPI: Add PPTT support

[Daniel Henrique Barboza]

Hi Drew!

On 10/20/2026 7:29 PM, Drew Fustini wrote:
> On Thu, Oct 15, 2026 at 12:19:53PM +0530, Sunil V L wrote:
>> Hi all,
>>
>> This series adds ACPI Processor Properties Topology Table (PPTT) support to
>> the RISC-V virt machine. PPTT allows the guest to discover the processor and
>> cache topology exposed by the machine, which is useful for making better
>> scheduling and cache-management decisions.
> 
> Thanks for picking up PPTT support. I can now rebase the RQSC support
> [1] on this series.
> 
> However, RQSC actually needs PPTT revision 3, because it adds cache IDs
> to the PPTT. The RQSC table references a capacity controller's cache by
> the PPTT cache ID. In Linux, find_acpi_cache_level_from_id() and
> acpi_pptt_get_cpumask_from_cache_id() return -ENOENT if PPTT rev < 3.
> 
> There is a new MPAM series by Jinjie Ruan which contains the patch
> "[PATCH 04/37] hw/acpi: Build PPTT rev 3 with cache IDs for MPAM
> cross-references" [2]. It bumps build_pptt() to revision 3 and gives
> every cache node an ID.
> 
> I could just base the RQSC series on this PPTT series and that patch
> 03/37. But maybe there is a better way to coordinate adding PPTT v3?

This PPTT support is acked and I believe we'll queue it in riscv-to-apply.next
shortly.

As for the PPTT rev3 patch in the "Add Arm MPAM emulation", my suggestion is
to put that on top of your series (i.e. your series will contain that patch).
That ARM series has 37 patches and might take awhile to go through, and your
work relies only on patch 04 ...  which happens to be an arch agnostic patch.
I believe it's fine for us to push it via the riscv queue.

I see that the author from the ARM series is CCed here.  Jinjie Ruan, are you
okay with us pushing your patch via the RISC-V tree?  It'll unblock Drew's work
and you'll have one less patch to worry about in your ARM MPAM work.


Thanks,
Daniel





> 
> Thanks,
> Drew
> 
> [1] https://lore.kernel.org/all/20260202-riscv-rqsc-v1-0-dcf448a3ed73@kernel.org/
> [2] https://lore.kernel.org/all/tencent_F9C68A515AC6C40BE2C32DB314E14CCB7106@qq.com/

Re: [PATCH v2 0/4] RISC-V: ACPI: Add PPTT support

[Jinjie Ruan]

在 2026/10/21 8:39, Daniel Henrique Barboza 写道:
> Hi Drew!
> 
> On 10/20/2026 7:29 PM, Drew Fustini wrote:
>> On Thu, Oct 15, 2026 at 12:19:53PM +0530, Sunil V L wrote:
>>> Hi all,
>>>
>>> This series adds ACPI Processor Properties Topology Table (PPTT)
>>> support to
>>> the RISC-V virt machine. PPTT allows the guest to discover the
>>> processor and
>>> cache topology exposed by the machine, which is useful for making better
>>> scheduling and cache-management decisions.
>>
>> Thanks for picking up PPTT support. I can now rebase the RQSC support
>> [1] on this series.
>>
>> However, RQSC actually needs PPTT revision 3, because it adds cache IDs
>> to the PPTT. The RQSC table references a capacity controller's cache by
>> the PPTT cache ID. In Linux, find_acpi_cache_level_from_id() and
>> acpi_pptt_get_cpumask_from_cache_id() return -ENOENT if PPTT rev < 3.
>>
>> There is a new MPAM series by Jinjie Ruan which contains the patch
>> "[PATCH 04/37] hw/acpi: Build PPTT rev 3 with cache IDs for MPAM
>> cross-references" [2]. It bumps build_pptt() to revision 3 and gives
>> every cache node an ID.
>>
>> I could just base the RQSC series on this PPTT series and that patch
>> 03/37. But maybe there is a better way to coordinate adding PPTT v3?
> 
> This PPTT support is acked and I believe we'll queue it in riscv-to-
> apply.next
> shortly.
> 
> As for the PPTT rev3 patch in the "Add Arm MPAM emulation", my
> suggestion is
> to put that on top of your series (i.e. your series will contain that
> patch).
> That ARM series has 37 patches and might take awhile to go through, and
> your
> work relies only on patch 04 ...  which happens to be an arch agnostic
> patch.
> I believe it's fine for us to push it via the riscv queue.
> 
> I see that the author from the ARM series is CCed here.  Jinjie Ruan,
> are you
> okay with us pushing your patch via the RISC-V tree?  It'll unblock
> Drew's work
> and you'll have one less patch to worry about in your ARM MPAM work.

Hi Daniel,

I'm fine to do so.

> 
> 
> Thanks,
> Daniel
> 
> 
> 
> 
> 
>>
>> Thanks,
>> Drew
>>
>> [1] https://lore.kernel.org/all/20260202-riscv-rqsc-v1-0-
>> dcf448a3ed73@kernel.org/
>> [2] https://lore.kernel.org/all/
>> tencent_F9C68A515AC6C40BE2C32DB314E14CCB7106@qq.com/
> 

-- 
Best regards,
Jinjie

Re: [PATCH v2 0/4] RISC-V: ACPI: Add PPTT support

[Alistair Francis]

On Thu, 2026-10-15 at 12:19 +0530, Sunil V L wrote:
> Hi all,
> 
> This series adds ACPI Processor Properties Topology Table (PPTT)
> support to
> the RISC-V virt machine. PPTT allows the guest to discover the
> processor and
> cache topology exposed by the machine, which is useful for making
> better
> scheduling and cache-management decisions.
> 
> The implementation describes the RISC-V virt cache hierarchy with
> separate
> L1 instruction and data caches, followed by unified L2 and L3 caches.
> It also
> enables the corresponding cache and cluster properties in the machine
> SMP
> description and wires the generated PPTT into the existing ACPI table
> build.
> 
> Unlike ARM, RISC-V doesn't have a way to discover the Cache
> topology from registers. Hence, I am hardcoding default values for
> the
> cache topology structures. These cache topology structures are added
> in
> virt.c itself so that a future series can add support for DT as well.
> In
> future, it can be enhanced to support vendor cpu/soc specific cache
> information to override this default hardcoded cache details.

Why not add a vendor cpu/soc specific one to a vendor board? That way
it actually model hardware instead of just providing the guest some
made up information.

I feel like you should describe why we want this somewhere in the
series

> 
> The series also updates the bios-tables-test data and removes the
> temporary
> PPTT entry from the allowed-diff list. The generated table is 96
> bytes and
> describes the package, cluster, and processor hierarchy for the virt
> machine.
> 
> This work follows the discussion and earlier work shared here:
> https://lists.gnu.org/archive/html/qemu-riscv/2024-01/msg00928.html
> 
> I have retained the contribution from Sia Jee Heng and added his
> Signed-off-by tag to the relevant patch.
> 
> To enable cache structures in the PPTT, one should use similar to
> below
> command line option.
> 
> -M virt,smp-cache.0.cache=l1d,smp-cache.0.topology=core,smp-
> cache.1.cache=l1i,smp-cache.1.topology=core,smp-cache.2.cache=l2,smp-
> cache.2.topology=cluster,smp-cache.3.cache=l3,smp-
> cache.3.topology=socket

Obviously :P

Let's at least add this to the virt machine docs so it's useful for
someone.

Alistair

> 
> lscpu -C in linux can be used to display these cache structures.
> 
> Changes from v1:
> 	1) Replaced loop with memcpy
> 	2) Made virt_caches static in virt.c
> 	3) Added Daniel's RB tags
> 
> Sunil V L (4):
> 
> Sunil V L (4):
>   tests/qtest/bios-tables-test: Allow PPTT for RISC-V
>   hw/riscv/virt: Add ACPI PPTT table
>   tests/qtest/bios-tables-test: Update riscv64 virt PPTT golden
>     reference
>   MAINTAINERS: Update Sunil's email id
> 
>  MAINTAINERS                       |   2 +-
>  hw/riscv/virt-acpi-build.c        |   7 ++++
>  hw/riscv/virt.c                   |  51
> ++++++++++++++++++++++++++++++
>  include/hw/riscv/virt.h           |   4 +++
>  tests/data/acpi/riscv64/virt/PPTT | Bin 0 -> 96 bytes
>  5 files changed, 63 insertions(+), 1 deletion(-)
>  create mode 100644 tests/data/acpi/riscv64/virt/PPTT

Re: [PATCH v2 0/4] RISC-V: ACPI: Add PPTT support

[Sunil V L]

On Thu, Oct 22, 2026 at 10:23 AM Alistair Francis
<Alistair.Francis@wdc.com> wrote:
>
> On Thu, 2026-10-15 at 12:19 +0530, Sunil V L wrote:
> > Hi all,
> >
> > This series adds ACPI Processor Properties Topology Table (PPTT)
> > support to
> > the RISC-V virt machine. PPTT allows the guest to discover the
> > processor and
> > cache topology exposed by the machine, which is useful for making
> > better
> > scheduling and cache-management decisions.
> >
> > The implementation describes the RISC-V virt cache hierarchy with
> > separate
> > L1 instruction and data caches, followed by unified L2 and L3 caches.
> > It also
> > enables the corresponding cache and cluster properties in the machine
> > SMP
> > description and wires the generated PPTT into the existing ACPI table
> > build.
> >
> > Unlike ARM, RISC-V doesn't have a way to discover the Cache
> > topology from registers. Hence, I am hardcoding default values for
> > the
> > cache topology structures. These cache topology structures are added
> > in
> > virt.c itself so that a future series can add support for DT as well.
> > In
> > future, it can be enhanced to support vendor cpu/soc specific cache
> > information to override this default hardcoded cache details.
>
> Why not add a vendor cpu/soc specific one to a vendor board? That way
> it actually model hardware instead of just providing the guest some
> made up information.
>
Thanks for the feedback!

Just to make sure I understand your suggestion correctly: should we avoid
defining a hardcoded cache topology for the generic CPU on virt, and generate
PPTT cache information only for CPU models that provide an appropriate cache
hierarchy?

I can certainly omit the cache information for the generic CPU. The consequence
is that Drew's CBQRI series, which requires cache information, would need a
suitable CPU model before it can be used with virt. Drew, please share
your thoughts.

> I feel like you should describe why we want this somewhere in the
> series
>
Sure. Let me update the cover letter why PPTT support is required.

> >
> > The series also updates the bios-tables-test data and removes the
> > temporary
> > PPTT entry from the allowed-diff list. The generated table is 96
> > bytes and
> > describes the package, cluster, and processor hierarchy for the virt
> > machine.
> >
> > This work follows the discussion and earlier work shared here:
> > https://lists.gnu.org/archive/html/qemu-riscv/2024-01/msg00928.html
> >
> > I have retained the contribution from Sia Jee Heng and added his
> > Signed-off-by tag to the relevant patch.
> >
> > To enable cache structures in the PPTT, one should use similar to
> > below
> > command line option.
> >
> > -M virt,smp-cache.0.cache=l1d,smp-cache.0.topology=core,smp-
> > cache.1.cache=l1i,smp-cache.1.topology=core,smp-cache.2.cache=l2,smp-
> > cache.2.topology=cluster,smp-cache.3.cache=l3,smp-
> > cache.3.topology=socket
>
> Obviously :P
>
> Let's at least add this to the virt machine docs so it's useful for
> someone.
>
Sure.

Thanks,
Sunil

Re: [PATCH v2 0/4] RISC-V: ACPI: Add PPTT support

[Drew Fustini]

On Fri, Oct 23, 2026 at 05:28:31PM +0530, Sunil V L wrote:
> On Thu, Oct 22, 2026 at 10:23 AM Alistair Francis
> <Alistair.Francis@wdc.com> wrote:
> >
> > On Thu, 2026-10-15 at 12:19 +0530, Sunil V L wrote:
> > > Hi alil,
> > >
> > > This series adds ACPI Processor Properties Topology Table (PPTT)
[..]
> > > future, it can be enhanced to support vendor cpu/soc specific cache
> > > information to override this default hardcoded cache details.
> >
> > Why not add a vendor cpu/soc specific one to a vendor board? That way
> > it actually model hardware instead of just providing the guest some
> > made up information.
> >
> Thanks for the feedback!
> 
> Just to make sure I understand your suggestion correctly: should we avoid
> defining a hardcoded cache topology for the generic CPU on virt, and generate
> PPTT cache information only for CPU models that provide an appropriate cache
> hierarchy?
> 
> I can certainly omit the cache information for the generic CPU. The consequence
> is that Drew's CBQRI series, which requires cache information, would need a
> suitable CPU model before it can be used with virt. Drew, please share
> your thoughts.

RQSC is a RISC-V standard so I think it would be nice for the generic
cpu to have a set of caches defined. This would allow the ACPI virt
machine to produce a PPTT with cache IDs that RQSC can reference, and it
would simplify testing for the RISC-V QoS support that I am trying to
upstream into Linux.

Thanks,
Drew