[PATCH v2 00/15] Add display driver for MT8188 VDOSYS1

[PATCH v2 00/15] Add display driver for MT8188 VDOSYS1

[Hsiao Chien Sung]

Support MT8188 VDOSYS1 in display driver.

v2:
- Separate dt-bindings by modules
- Support reset bit mapping in mmsys driver
- Remove redundant compatibles of MT8188 because it shares the same
  configuration with MT8195

Hsiao Chien Sung (15):
  dt-bindings: display: mediatek: ethdr: Add compatible for MT8188
  dt-bindings: display: mediatek: mdp-rdma: Add compatible for MT8188
  dt-bindings: display: mediatek: merge: Add compatible for MT8188
  dt-bindings: display: mediatek: padding: Add documentation for MT8188
  dt-bindings: arm: mediatek: Add compatible for MT8188
  dt-bindings: reset: mt8188: Add VDOSYS0 reset control bits
  dt-bindings: reset: mt8188: Add VDOSYS1 reset control bits
  soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys
  soc: mediatek: Support MT8188 VDOSYS1 PADDING in mtk-mmsys
  soc: mediatek: Support reset bit mapping in mmsys driver
  soc: mediatek: Add MT8188 VDO0 reset bit map
  soc: mediatek: Add MT8188 VDO1 reset bit map
  drm/mediatek: Support MT8188 VDOSYS1 in display driver
  drm/mediatek: Improve compatibility of display driver
  drm/mediatek: Support MT8188 VDOSYS1 PADDING in display driver

 .../bindings/arm/mediatek/mediatek,mmsys.yaml |   1 +
 .../display/mediatek/mediatek,ethdr.yaml      |   6 +-
 .../display/mediatek/mediatek,mdp-rdma.yaml   |   6 +-
 .../display/mediatek/mediatek,merge.yaml      |   3 +
 .../display/mediatek/mediatek,padding.yaml    |  81 +++++++
 drivers/gpu/drm/mediatek/Makefile             |   3 +-
 drivers/gpu/drm/mediatek/mtk_disp_drv.h       |   3 +
 .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c   | 170 +++++++++-----
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        |   4 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   2 +-
 drivers/gpu/drm/mediatek/mtk_padding.c        | 127 +++++++++++
 drivers/soc/mediatek/mt8188-mmsys.h           | 210 ++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c              |  26 +++
 drivers/soc/mediatek/mtk-mmsys.h              |  30 +++
 drivers/soc/mediatek/mtk-mutex.c              |  51 +++++
 include/dt-bindings/reset/mt8188-resets.h     |  75 +++++++
 include/linux/soc/mediatek/mtk-mmsys.h        |   8 +
 17 files changed, 751 insertions(+), 55 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
 create mode 100644 drivers/gpu/drm/mediatek/mtk_padding.c

--
2.18.0


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[PATCH v2 00/15] Add display driver for MT8188 VDOSYS1

[Hsiao Chien Sung]

Support MT8188 VDOSYS1 in display driver.

v2:
- Separate dt-bindings by modules
- Support reset bit mapping in mmsys driver
- Remove redundant compatibles of MT8188 because it shares the same
  configuration with MT8195

Hsiao Chien Sung (15):
  dt-bindings: display: mediatek: ethdr: Add compatible for MT8188
  dt-bindings: display: mediatek: mdp-rdma: Add compatible for MT8188
  dt-bindings: display: mediatek: merge: Add compatible for MT8188
  dt-bindings: display: mediatek: padding: Add documentation for MT8188
  dt-bindings: arm: mediatek: Add compatible for MT8188
  dt-bindings: reset: mt8188: Add VDOSYS0 reset control bits
  dt-bindings: reset: mt8188: Add VDOSYS1 reset control bits
  soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys
  soc: mediatek: Support MT8188 VDOSYS1 PADDING in mtk-mmsys
  soc: mediatek: Support reset bit mapping in mmsys driver
  soc: mediatek: Add MT8188 VDO0 reset bit map
  soc: mediatek: Add MT8188 VDO1 reset bit map
  drm/mediatek: Support MT8188 VDOSYS1 in display driver
  drm/mediatek: Improve compatibility of display driver
  drm/mediatek: Support MT8188 VDOSYS1 PADDING in display driver

 .../bindings/arm/mediatek/mediatek,mmsys.yaml |   1 +
 .../display/mediatek/mediatek,ethdr.yaml      |   6 +-
 .../display/mediatek/mediatek,mdp-rdma.yaml   |   6 +-
 .../display/mediatek/mediatek,merge.yaml      |   3 +
 .../display/mediatek/mediatek,padding.yaml    |  81 +++++++
 drivers/gpu/drm/mediatek/Makefile             |   3 +-
 drivers/gpu/drm/mediatek/mtk_disp_drv.h       |   3 +
 .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c   | 170 +++++++++-----
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        |   4 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   2 +-
 drivers/gpu/drm/mediatek/mtk_padding.c        | 127 +++++++++++
 drivers/soc/mediatek/mt8188-mmsys.h           | 210 ++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c              |  26 +++
 drivers/soc/mediatek/mtk-mmsys.h              |  30 +++
 drivers/soc/mediatek/mtk-mutex.c              |  51 +++++
 include/dt-bindings/reset/mt8188-resets.h     |  75 +++++++
 include/linux/soc/mediatek/mtk-mmsys.h        |   8 +
 17 files changed, 751 insertions(+), 55 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
 create mode 100644 drivers/gpu/drm/mediatek/mtk_padding.c

--
2.18.0

[PATCH v2 01/15] dt-bindings: display: mediatek: ethdr: Add compatible for MT8188

[Hsiao Chien Sung]

Add compatible name for MediaTek MT8188 ETHDR.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 .../bindings/display/mediatek/mediatek,ethdr.yaml           | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
index 801fa66ae615..677882348ede 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
@@ -23,7 +23,11 @@ description:

 properties:
   compatible:
-    const: mediatek,mt8195-disp-ethdr
+    oneOf:
+      - const: mediatek,mt8195-disp-ethdr
+      - items:
+          - const: mediatek,mt8188-disp-ethdr
+          - const: mediatek,mt8195-disp-ethdr

   reg:
     maxItems: 7
--
2.18.0


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[PATCH v2 01/15] dt-bindings: display: mediatek: ethdr: Add compatible for MT8188

[Hsiao Chien Sung]

Add compatible name for MediaTek MT8188 ETHDR.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 .../bindings/display/mediatek/mediatek,ethdr.yaml           | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
index 801fa66ae615..677882348ede 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
@@ -23,7 +23,11 @@ description:

 properties:
   compatible:
-    const: mediatek,mt8195-disp-ethdr
+    oneOf:
+      - const: mediatek,mt8195-disp-ethdr
+      - items:
+          - const: mediatek,mt8188-disp-ethdr
+          - const: mediatek,mt8195-disp-ethdr

   reg:
     maxItems: 7
--
2.18.0

Re: [PATCH v2 01/15] dt-bindings: display: mediatek: ethdr: Add compatible for MT8188

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> Add compatible name for MediaTek MT8188 ETHDR.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>   .../bindings/display/mediatek/mediatek,ethdr.yaml           | 6 +++++-
>   1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
> index 801fa66ae615..677882348ede 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
> @@ -23,7 +23,11 @@ description:
> 
>   properties:
>     compatible:
> -    const: mediatek,mt8195-disp-ethdr
> +    oneOf:
> +      - const: mediatek,mt8195-disp-ethdr
> +      - items:
> +          - const: mediatek,mt8188-disp-ethdr
> +          - const: mediatek,mt8195-disp-ethdr
> 

Is MT8188's ETHDR fully compatible with MT8195's ETHDR?

If it is, you're not adding a mt8188 specific compatible string in the driver and
this means that the devicetree will look like:

	compatible = "mediatek,mt8195-disp-ethdr", "mediatek,mt8188-disp-ethdr"

...so the proposed doc change works.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

>     reg:
>       maxItems: 7
> --
> 2.18.0
> 



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Re: [PATCH v2 01/15] dt-bindings: display: mediatek: ethdr: Add compatible for MT8188

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> Add compatible name for MediaTek MT8188 ETHDR.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>   .../bindings/display/mediatek/mediatek,ethdr.yaml           | 6 +++++-
>   1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
> index 801fa66ae615..677882348ede 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
> @@ -23,7 +23,11 @@ description:
> 
>   properties:
>     compatible:
> -    const: mediatek,mt8195-disp-ethdr
> +    oneOf:
> +      - const: mediatek,mt8195-disp-ethdr
> +      - items:
> +          - const: mediatek,mt8188-disp-ethdr
> +          - const: mediatek,mt8195-disp-ethdr
> 

Is MT8188's ETHDR fully compatible with MT8195's ETHDR?

If it is, you're not adding a mt8188 specific compatible string in the driver and
this means that the devicetree will look like:

	compatible = "mediatek,mt8195-disp-ethdr", "mediatek,mt8188-disp-ethdr"

...so the proposed doc change works.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

>     reg:
>       maxItems: 7
> --
> 2.18.0
> 

Re: [PATCH v2 01/15] dt-bindings: display: mediatek: ethdr: Add compatible for MT8188

[Shawn Sung (宋孝謙)]

Hi Angelo,
 
Yes, MT8188 ETHDR is fully compatible with MT8195, so we didn't add its
compatible name to the driver but just listed it in dt-bindings.
 
May I double check with you that
I see there is a short description regarding "items" object:
> # items is a list of possible values for the property. The number of
> # values is determined by the number of elements in the list.
> # Order in lists is significant, order in dicts is not
in https://docs.kernel.org/devicetree/bindings/writing-schema.html
 
So does the compatible has to be:
"mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-
ethdr" rather than in reversed order?
 
However, I couldn't find any description mentions the order in
Documentation/devicetree/bindings/writing-schema.rst
Not sure if the order in "items" object does not matter after then.
 
Thanks,
Hsiao Chien Sung


On Wed, 2023-06-14 at 13:41 +0200, AngeloGioacchino Del Regno wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> > Add compatible name for MediaTek MT8188 ETHDR.
> > 
> > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > ---
> >   .../bindings/display/mediatek/mediatek,ethdr.yaml           | 6
> +++++-
> >   1 file changed, 5 insertions(+), 1 deletion(-)
> > 
> > diff --git
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
> aml
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
> aml
> > index 801fa66ae615..677882348ede 100644
> > ---
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
> aml
> > +++
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
> aml
> > @@ -23,7 +23,11 @@ description:
> > 
> >   properties:
> >     compatible:
> > -    const: mediatek,mt8195-disp-ethdr
> > +    oneOf:
> > +      - const: mediatek,mt8195-disp-ethdr
> > +      - items:
> > +          - const: mediatek,mt8188-disp-ethdr
> > +          - const: mediatek,mt8195-disp-ethdr
> > 
> 
> Is MT8188's ETHDR fully compatible with MT8195's ETHDR?
> 
> If it is, you're not adding a mt8188 specific compatible string in
> the driver and
> this means that the devicetree will look like:
> 
> compatible = "mediatek,mt8195-disp-ethdr", "mediatek,mt8188-disp-
> ethdr"
> 
> ...so the proposed doc change works.
> 
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> 
> >     reg:
> >       maxItems: 7
> > --
> > 2.18.0
> > 
> 
> 
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Re: [PATCH v2 01/15] dt-bindings: display: mediatek: ethdr: Add compatible for MT8188

[Shawn Sung (宋孝謙)]

Hi Angelo,
 
Yes, MT8188 ETHDR is fully compatible with MT8195, so we didn't add its
compatible name to the driver but just listed it in dt-bindings.
 
May I double check with you that
I see there is a short description regarding "items" object:
> # items is a list of possible values for the property. The number of
> # values is determined by the number of elements in the list.
> # Order in lists is significant, order in dicts is not
in https://docs.kernel.org/devicetree/bindings/writing-schema.html
 
So does the compatible has to be:
"mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-
ethdr" rather than in reversed order?
 
However, I couldn't find any description mentions the order in
Documentation/devicetree/bindings/writing-schema.rst
Not sure if the order in "items" object does not matter after then.
 
Thanks,
Hsiao Chien Sung


On Wed, 2023-06-14 at 13:41 +0200, AngeloGioacchino Del Regno wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> > Add compatible name for MediaTek MT8188 ETHDR.
> > 
> > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > ---
> >   .../bindings/display/mediatek/mediatek,ethdr.yaml           | 6
> +++++-
> >   1 file changed, 5 insertions(+), 1 deletion(-)
> > 
> > diff --git
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
> aml
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
> aml
> > index 801fa66ae615..677882348ede 100644
> > ---
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
> aml
> > +++
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
> aml
> > @@ -23,7 +23,11 @@ description:
> > 
> >   properties:
> >     compatible:
> > -    const: mediatek,mt8195-disp-ethdr
> > +    oneOf:
> > +      - const: mediatek,mt8195-disp-ethdr
> > +      - items:
> > +          - const: mediatek,mt8188-disp-ethdr
> > +          - const: mediatek,mt8195-disp-ethdr
> > 
> 
> Is MT8188's ETHDR fully compatible with MT8195's ETHDR?
> 
> If it is, you're not adding a mt8188 specific compatible string in
> the driver and
> this means that the devicetree will look like:
> 
> compatible = "mediatek,mt8195-disp-ethdr", "mediatek,mt8188-disp-
> ethdr"
> 
> ...so the proposed doc change works.
> 
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> 
> >     reg:
> >       maxItems: 7
> > --
> > 2.18.0
> > 
> 
> 

Re: [PATCH v2 01/15] dt-bindings: display: mediatek: ethdr: Add compatible for MT8188

[AngeloGioacchino Del Regno]

Il 15/06/23 07:51, Shawn Sung (宋孝謙) ha scritto:
> Hi Angelo,
>   
> Yes, MT8188 ETHDR is fully compatible with MT8195, so we didn't add its
> compatible name to the driver but just listed it in dt-bindings.
>   
> May I double check with you that
> I see there is a short description regarding "items" object:
>> # items is a list of possible values for the property. The number of
>> # values is determined by the number of elements in the list.
>> # Order in lists is significant, order in dicts is not
> in https://docs.kernel.org/devicetree/bindings/writing-schema.html
>   
> So does the compatible has to be:
> "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-
> ethdr" rather than in reversed order?
>   
> However, I couldn't find any description mentions the order in
> Documentation/devicetree/bindings/writing-schema.rst
> Not sure if the order in "items" object does not matter after then.
>   

No the order doesn't matter in that sense. If you check the other bindings,
you'll see that the rule is to order by name, which your change as well does.

It's fine.

P.S.: In case you didn't know, `make dt_binding_check` and `make dtbs_check`
       will validate your bindings and your devicetrees against the bindings.

Regards,
Angelo

> Thanks,
> Hsiao Chien Sung
> 
> 
> On Wed, 2023-06-14 at 13:41 +0200, AngeloGioacchino Del Regno wrote:
>>   	
>> External email : Please do not click links or open attachments until
>> you have verified the sender or the content.
>>   Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
>>> Add compatible name for MediaTek MT8188 ETHDR.
>>>
>>> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
>>> ---
>>>    .../bindings/display/mediatek/mediatek,ethdr.yaml           | 6
>> +++++-
>>>    1 file changed, 5 insertions(+), 1 deletion(-)
>>>
>>> diff --git
>> a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
>> aml
>> b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
>> aml
>>> index 801fa66ae615..677882348ede 100644
>>> ---
>> a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
>> aml
>>> +++
>> b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
>> aml
>>> @@ -23,7 +23,11 @@ description:
>>>
>>>    properties:
>>>      compatible:
>>> -    const: mediatek,mt8195-disp-ethdr
>>> +    oneOf:
>>> +      - const: mediatek,mt8195-disp-ethdr
>>> +      - items:
>>> +          - const: mediatek,mt8188-disp-ethdr
>>> +          - const: mediatek,mt8195-disp-ethdr
>>>
>>
>> Is MT8188's ETHDR fully compatible with MT8195's ETHDR?
>>
>> If it is, you're not adding a mt8188 specific compatible string in
>> the driver and
>> this means that the devicetree will look like:
>>
>> compatible = "mediatek,mt8195-disp-ethdr", "mediatek,mt8188-disp-
>> ethdr"
>>
>> ...so the proposed doc change works.
>>
>> Reviewed-by: AngeloGioacchino Del Regno <
>> angelogioacchino.delregno@collabora.com>
>>
>>>      reg:
>>>        maxItems: 7
>>> --
>>> 2.18.0
>>>
>>
>>


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Re: [PATCH v2 01/15] dt-bindings: display: mediatek: ethdr: Add compatible for MT8188

[AngeloGioacchino Del Regno]

Il 15/06/23 07:51, Shawn Sung (宋孝謙) ha scritto:
> Hi Angelo,
>   
> Yes, MT8188 ETHDR is fully compatible with MT8195, so we didn't add its
> compatible name to the driver but just listed it in dt-bindings.
>   
> May I double check with you that
> I see there is a short description regarding "items" object:
>> # items is a list of possible values for the property. The number of
>> # values is determined by the number of elements in the list.
>> # Order in lists is significant, order in dicts is not
> in https://docs.kernel.org/devicetree/bindings/writing-schema.html
>   
> So does the compatible has to be:
> "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-
> ethdr" rather than in reversed order?
>   
> However, I couldn't find any description mentions the order in
> Documentation/devicetree/bindings/writing-schema.rst
> Not sure if the order in "items" object does not matter after then.
>   

No the order doesn't matter in that sense. If you check the other bindings,
you'll see that the rule is to order by name, which your change as well does.

It's fine.

P.S.: In case you didn't know, `make dt_binding_check` and `make dtbs_check`
       will validate your bindings and your devicetrees against the bindings.

Regards,
Angelo

> Thanks,
> Hsiao Chien Sung
> 
> 
> On Wed, 2023-06-14 at 13:41 +0200, AngeloGioacchino Del Regno wrote:
>>   	
>> External email : Please do not click links or open attachments until
>> you have verified the sender or the content.
>>   Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
>>> Add compatible name for MediaTek MT8188 ETHDR.
>>>
>>> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
>>> ---
>>>    .../bindings/display/mediatek/mediatek,ethdr.yaml           | 6
>> +++++-
>>>    1 file changed, 5 insertions(+), 1 deletion(-)
>>>
>>> diff --git
>> a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
>> aml
>> b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
>> aml
>>> index 801fa66ae615..677882348ede 100644
>>> ---
>> a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
>> aml
>>> +++
>> b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
>> aml
>>> @@ -23,7 +23,11 @@ description:
>>>
>>>    properties:
>>>      compatible:
>>> -    const: mediatek,mt8195-disp-ethdr
>>> +    oneOf:
>>> +      - const: mediatek,mt8195-disp-ethdr
>>> +      - items:
>>> +          - const: mediatek,mt8188-disp-ethdr
>>> +          - const: mediatek,mt8195-disp-ethdr
>>>
>>
>> Is MT8188's ETHDR fully compatible with MT8195's ETHDR?
>>
>> If it is, you're not adding a mt8188 specific compatible string in
>> the driver and
>> this means that the devicetree will look like:
>>
>> compatible = "mediatek,mt8195-disp-ethdr", "mediatek,mt8188-disp-
>> ethdr"
>>
>> ...so the proposed doc change works.
>>
>> Reviewed-by: AngeloGioacchino Del Regno <
>> angelogioacchino.delregno@collabora.com>
>>
>>>      reg:
>>>        maxItems: 7
>>> --
>>> 2.18.0
>>>
>>
>>

Re: [PATCH v2 01/15] dt-bindings: display: mediatek: ethdr: Add compatible for MT8188

[Krzysztof Kozlowski]

On 14/06/2023 09:31, Hsiao Chien Sung wrote:
> Add compatible name for MediaTek MT8188 ETHDR.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  .../bindings/display/mediatek/mediatek,ethdr.yaml           | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


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Re: [PATCH v2 01/15] dt-bindings: display: mediatek: ethdr: Add compatible for MT8188

[Krzysztof Kozlowski]

On 14/06/2023 09:31, Hsiao Chien Sung wrote:
> Add compatible name for MediaTek MT8188 ETHDR.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  .../bindings/display/mediatek/mediatek,ethdr.yaml           | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH v2 02/15] dt-bindings: display: mediatek: mdp-rdma: Add compatible for MT8188

[Hsiao Chien Sung]

Add compatible name for MediaTek MT8188 MDP-RDMA.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 .../bindings/display/mediatek/mediatek,mdp-rdma.yaml        | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
index dd12e2ff685c..7570a0684967 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
@@ -21,7 +21,11 @@ description:

 properties:
   compatible:
-    const: mediatek,mt8195-vdo1-rdma
+    oneOf:
+      - const: mediatek,mt8195-vdo1-rdma
+      - items:
+          - const: mediatek,mt8188-vdo1-rdma
+          - const: mediatek,mt8195-vdo1-rdma

   reg:
     maxItems: 1
--
2.18.0


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[PATCH v2 02/15] dt-bindings: display: mediatek: mdp-rdma: Add compatible for MT8188

[Hsiao Chien Sung]

Add compatible name for MediaTek MT8188 MDP-RDMA.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 .../bindings/display/mediatek/mediatek,mdp-rdma.yaml        | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
index dd12e2ff685c..7570a0684967 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
@@ -21,7 +21,11 @@ description:

 properties:
   compatible:
-    const: mediatek,mt8195-vdo1-rdma
+    oneOf:
+      - const: mediatek,mt8195-vdo1-rdma
+      - items:
+          - const: mediatek,mt8188-vdo1-rdma
+          - const: mediatek,mt8195-vdo1-rdma

   reg:
     maxItems: 1
--
2.18.0

Re: [PATCH v2 02/15] dt-bindings: display: mediatek: mdp-rdma: Add compatible for MT8188

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> Add compatible name for MediaTek MT8188 MDP-RDMA.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


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Re: [PATCH v2 02/15] dt-bindings: display: mediatek: mdp-rdma: Add compatible for MT8188

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> Add compatible name for MediaTek MT8188 MDP-RDMA.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH v2 02/15] dt-bindings: display: mediatek: mdp-rdma: Add compatible for MT8188

[Krzysztof Kozlowski]

On 14/06/2023 09:31, Hsiao Chien Sung wrote:
> Add compatible name for MediaTek MT8188 MDP-RDMA.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  .../bindings/display/mediatek/mediatek,mdp-rdma.yaml        | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


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Re: [PATCH v2 02/15] dt-bindings: display: mediatek: mdp-rdma: Add compatible for MT8188

[Krzysztof Kozlowski]

On 14/06/2023 09:31, Hsiao Chien Sung wrote:
> Add compatible name for MediaTek MT8188 MDP-RDMA.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

(Apologies if it comes twice)

Best regards,
Krzysztof


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Re: [PATCH v2 02/15] dt-bindings: display: mediatek: mdp-rdma: Add compatible for MT8188

[Krzysztof Kozlowski]

On 14/06/2023 09:31, Hsiao Chien Sung wrote:
> Add compatible name for MediaTek MT8188 MDP-RDMA.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

(Apologies if it comes twice)

Best regards,
Krzysztof

[PATCH v2 03/15] dt-bindings: display: mediatek: merge: Add compatible for MT8188

[Hsiao Chien Sung]

Add compatible name for MediaTek MT8188 MERGE.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 .../devicetree/bindings/display/mediatek/mediatek,merge.yaml   | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index eead5cb8636e..5c678695162e 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -27,6 +27,9 @@ properties:
       - items:
           - const: mediatek,mt6795-disp-merge
           - const: mediatek,mt8173-disp-merge
+      - items:
+          - const: mediatek,mt8188-disp-merge
+          - const: mediatek,mt8195-disp-merge

   reg:
     maxItems: 1
--
2.18.0


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[PATCH v2 03/15] dt-bindings: display: mediatek: merge: Add compatible for MT8188

[Hsiao Chien Sung]

Add compatible name for MediaTek MT8188 MERGE.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 .../devicetree/bindings/display/mediatek/mediatek,merge.yaml   | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index eead5cb8636e..5c678695162e 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -27,6 +27,9 @@ properties:
       - items:
           - const: mediatek,mt6795-disp-merge
           - const: mediatek,mt8173-disp-merge
+      - items:
+          - const: mediatek,mt8188-disp-merge
+          - const: mediatek,mt8195-disp-merge

   reg:
     maxItems: 1
--
2.18.0

Re: [PATCH v2 03/15] dt-bindings: display: mediatek: merge: Add compatible for MT8188

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> Add compatible name for MediaTek MT8188 MERGE.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>



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Re: [PATCH v2 03/15] dt-bindings: display: mediatek: merge: Add compatible for MT8188

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> Add compatible name for MediaTek MT8188 MERGE.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH v2 03/15] dt-bindings: display: mediatek: merge: Add compatible for MT8188

[Krzysztof Kozlowski]

On 14/06/2023 09:31, Hsiao Chien Sung wrote:
> Add compatible name for MediaTek MT8188 MERGE.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  .../devicetree/bindings/display/mediatek/mediatek,merge.yaml   | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> index eead5cb8636e..5c678695162e 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> @@ -27,6 +27,9 @@ properties:
>        - items:
>            - const: mediatek,mt6795-disp-merge
>            - const: mediatek,mt8173-disp-merge
> +      - items:
> +          - const: mediatek,mt8188-disp-merge
> +          - const: mediatek,mt8195-disp-merge

Linux next has something entirely different. I don't know the base here,
but it's really, really different and it suggests you should add mt8188
to an enum with mt8173.

Best regards,
Krzysztof


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Re: [PATCH v2 03/15] dt-bindings: display: mediatek: merge: Add compatible for MT8188

[Krzysztof Kozlowski]

On 14/06/2023 09:31, Hsiao Chien Sung wrote:
> Add compatible name for MediaTek MT8188 MERGE.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  .../devicetree/bindings/display/mediatek/mediatek,merge.yaml   | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> index eead5cb8636e..5c678695162e 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> @@ -27,6 +27,9 @@ properties:
>        - items:
>            - const: mediatek,mt6795-disp-merge
>            - const: mediatek,mt8173-disp-merge
> +      - items:
> +          - const: mediatek,mt8188-disp-merge
> +          - const: mediatek,mt8195-disp-merge

Linux next has something entirely different. I don't know the base here,
but it's really, really different and it suggests you should add mt8188
to an enum with mt8173.

Best regards,
Krzysztof

Re: [PATCH v2 03/15] dt-bindings: display: mediatek: merge: Add compatible for MT8188

[Shawn Sung (宋孝謙)]

Hi Krzysztof,

Thanks for the reminder, because MT8188 is not related to MT8173, I’ll
keep it as it is for now, however, I do find that MT8195 doesn’t exist
in this dt-bindings which it should be, so there may be conflicts when
this series is going to be merged.

Best regards,
Hsiao Chien Sung

On Thu, 2023-06-15 at 10:28 +0200, Krzysztof Kozlowski wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  On 14/06/2023 09:31, Hsiao Chien Sung wrote:
> > Add compatible name for MediaTek MT8188 MERGE.
> > 
> > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > ---
> >  .../devicetree/bindings/display/mediatek/mediatek,merge.yaml   | 3
> +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.y
> aml
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.y
> aml
> > index eead5cb8636e..5c678695162e 100644
> > ---
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.y
> aml
> > +++
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.y
> aml
> > @@ -27,6 +27,9 @@ properties:
> >        - items:
> >            - const: mediatek,mt6795-disp-merge
> >            - const: mediatek,mt8173-disp-merge
> > +      - items:
> > +          - const: mediatek,mt8188-disp-merge
> > +          - const: mediatek,mt8195-disp-merge
> 
> Linux next has something entirely different. I don't know the base
> here,
> but it's really, really different and it suggests you should add
> mt8188
> to an enum with mt8173.
> 
> Best regards,
> Krzysztof
> 
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Re: [PATCH v2 03/15] dt-bindings: display: mediatek: merge: Add compatible for MT8188

[Shawn Sung (宋孝謙)]

Hi Krzysztof,

Thanks for the reminder, because MT8188 is not related to MT8173, I’ll
keep it as it is for now, however, I do find that MT8195 doesn’t exist
in this dt-bindings which it should be, so there may be conflicts when
this series is going to be merged.

Best regards,
Hsiao Chien Sung

On Thu, 2023-06-15 at 10:28 +0200, Krzysztof Kozlowski wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  On 14/06/2023 09:31, Hsiao Chien Sung wrote:
> > Add compatible name for MediaTek MT8188 MERGE.
> > 
> > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > ---
> >  .../devicetree/bindings/display/mediatek/mediatek,merge.yaml   | 3
> +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.y
> aml
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.y
> aml
> > index eead5cb8636e..5c678695162e 100644
> > ---
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.y
> aml
> > +++
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.y
> aml
> > @@ -27,6 +27,9 @@ properties:
> >        - items:
> >            - const: mediatek,mt6795-disp-merge
> >            - const: mediatek,mt8173-disp-merge
> > +      - items:
> > +          - const: mediatek,mt8188-disp-merge
> > +          - const: mediatek,mt8195-disp-merge
> 
> Linux next has something entirely different. I don't know the base
> here,
> but it's really, really different and it suggests you should add
> mt8188
> to an enum with mt8173.
> 
> Best regards,
> Krzysztof
> 

Re: [PATCH v2 03/15] dt-bindings: display: mediatek: merge: Add compatible for MT8188

[Krzysztof Kozlowski]

On 16/06/2023 07:29, Shawn Sung (宋孝謙) wrote:
> Hi Krzysztof,
> 
> Thanks for the reminder, because MT8188 is not related to MT8173,

How does it matter?

>  I’ll
> keep it as it is for now, however, I do find that MT8195 doesn’t exist
> in this dt-bindings which it should be, so there may be conflicts when
> this series is going to be merged.

Don't top post.

No, rebase on current next and implement my comment.

Best regards,
Krzysztof


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Re: [PATCH v2 03/15] dt-bindings: display: mediatek: merge: Add compatible for MT8188

[Krzysztof Kozlowski]

On 16/06/2023 07:29, Shawn Sung (宋孝謙) wrote:
> Hi Krzysztof,
> 
> Thanks for the reminder, because MT8188 is not related to MT8173,

How does it matter?

>  I’ll
> keep it as it is for now, however, I do find that MT8195 doesn’t exist
> in this dt-bindings which it should be, so there may be conflicts when
> this series is going to be merged.

Don't top post.

No, rebase on current next and implement my comment.

Best regards,
Krzysztof

Re: [PATCH v2 03/15] dt-bindings: display: mediatek: merge: Add compatible for MT8188

[Shawn Sung (宋孝謙)]

On Fri, 2023-06-16 at 10:07 +0200, Krzysztof Kozlowski wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  On 16/06/2023 07:29, Shawn Sung (宋孝謙) wrote:
> > Hi Krzysztof,
> > 
> > Thanks for the reminder, because MT8188 is not related to MT8173,
> 
> How does it matter?

Because MT8188 Merge is fully compatible with MT8195, we didn't add its
compatible name to the driver, but just list it in dt-bindings, and use
MT8195's compatible name to match the ID in device table. For example,
in mt8188.dtsi:

merge1: merge@1c10c000 {
        compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-
disp-merge";
        ...
};

If we add MT8188 Merge as an enum with MT8173, then our device tree
must be as below, and nothing will match in Merge driver.

merge1: merge@1c10c000 {
        compatible = "mediatek,mt8188-disp-
merge";
        ...
};

> 
> >  I’ll
> > keep it as it is for now, however, I do find that MT8195 doesn’t
> exist
> > in this dt-bindings which it should be, so there may be conflicts
> when
> > this series is going to be merged.
> 
> Don't top post.
> 
> No, rebase on current next and implement my comment.

Will rebase linux-next in the next version.

> 
> Best regards,
> Krzysztof
> 

Best regards,
Hsiao Chien Sung
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Re: [PATCH v2 03/15] dt-bindings: display: mediatek: merge: Add compatible for MT8188

[Shawn Sung (宋孝謙)]

On Fri, 2023-06-16 at 10:07 +0200, Krzysztof Kozlowski wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  On 16/06/2023 07:29, Shawn Sung (宋孝謙) wrote:
> > Hi Krzysztof,
> > 
> > Thanks for the reminder, because MT8188 is not related to MT8173,
> 
> How does it matter?

Because MT8188 Merge is fully compatible with MT8195, we didn't add its
compatible name to the driver, but just list it in dt-bindings, and use
MT8195's compatible name to match the ID in device table. For example,
in mt8188.dtsi:

merge1: merge@1c10c000 {
        compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-
disp-merge";
        ...
};

If we add MT8188 Merge as an enum with MT8173, then our device tree
must be as below, and nothing will match in Merge driver.

merge1: merge@1c10c000 {
        compatible = "mediatek,mt8188-disp-
merge";
        ...
};

> 
> >  I’ll
> > keep it as it is for now, however, I do find that MT8195 doesn’t
> exist
> > in this dt-bindings which it should be, so there may be conflicts
> when
> > this series is going to be merged.
> 
> Don't top post.
> 
> No, rebase on current next and implement my comment.

Will rebase linux-next in the next version.

> 
> Best regards,
> Krzysztof
> 

Best regards,
Hsiao Chien Sung

Re: [PATCH v2 03/15] dt-bindings: display: mediatek: merge: Add compatible for MT8188

[Krzysztof Kozlowski]

On 16/06/2023 10:40, Shawn Sung (宋孝謙) wrote:
> On Fri, 2023-06-16 at 10:07 +0200, Krzysztof Kozlowski wrote:
>>  	 
>> External email : Please do not click links or open attachments until
>> you have verified the sender or the content.
>>  On 16/06/2023 07:29, Shawn Sung (宋孝謙) wrote:
>>> Hi Krzysztof,
>>>
>>> Thanks for the reminder, because MT8188 is not related to MT8173,
>>
>> How does it matter?
> 
> Because MT8188 Merge is fully compatible with MT8195, we didn't add its
> compatible name to the driver, but just list it in dt-bindings, and use
> MT8195's compatible name to match the ID in device table. For example,
> in mt8188.dtsi:
> 
> merge1: merge@1c10c000 {
>         compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-
> disp-merge";
>         ...
> };
> 
> If we add MT8188 Merge as an enum with MT8173, then our device tree
> must be as below, and nothing will match in Merge driver.
> 
> merge1: merge@1c10c000 {
>         compatible = "mediatek,mt8188-disp-
> merge";
>         ...
> };

No, why? It would be incorrect with existing bindings. Again, on what
tree are you working?

> 
>>
>>>  I’ll
>>> keep it as it is for now, however, I do find that MT8195 doesn’t
>> exist
>>> in this dt-bindings which it should be, so there may be conflicts
>> when
>>> this series is going to be merged.
>>
>> Don't top post.
>>
>> No, rebase on current next and implement my comment.
> 
> Will rebase linux-next in the next version.

Rebase now - for this discussion.

Best regards,
Krzysztof


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Re: [PATCH v2 03/15] dt-bindings: display: mediatek: merge: Add compatible for MT8188

[Krzysztof Kozlowski]

On 16/06/2023 10:40, Shawn Sung (宋孝謙) wrote:
> On Fri, 2023-06-16 at 10:07 +0200, Krzysztof Kozlowski wrote:
>>  	 
>> External email : Please do not click links or open attachments until
>> you have verified the sender or the content.
>>  On 16/06/2023 07:29, Shawn Sung (宋孝謙) wrote:
>>> Hi Krzysztof,
>>>
>>> Thanks for the reminder, because MT8188 is not related to MT8173,
>>
>> How does it matter?
> 
> Because MT8188 Merge is fully compatible with MT8195, we didn't add its
> compatible name to the driver, but just list it in dt-bindings, and use
> MT8195's compatible name to match the ID in device table. For example,
> in mt8188.dtsi:
> 
> merge1: merge@1c10c000 {
>         compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-
> disp-merge";
>         ...
> };
> 
> If we add MT8188 Merge as an enum with MT8173, then our device tree
> must be as below, and nothing will match in Merge driver.
> 
> merge1: merge@1c10c000 {
>         compatible = "mediatek,mt8188-disp-
> merge";
>         ...
> };

No, why? It would be incorrect with existing bindings. Again, on what
tree are you working?

> 
>>
>>>  I’ll
>>> keep it as it is for now, however, I do find that MT8195 doesn’t
>> exist
>>> in this dt-bindings which it should be, so there may be conflicts
>> when
>>> this series is going to be merged.
>>
>> Don't top post.
>>
>> No, rebase on current next and implement my comment.
> 
> Will rebase linux-next in the next version.

Rebase now - for this discussion.

Best regards,
Krzysztof

Re: [PATCH v2 03/15] dt-bindings: display: mediatek: merge: Add compatible for MT8188

[Shawn Sung (宋孝謙)]

On Fri, 2023-06-16 at 11:31 +0200, Krzysztof Kozlowski wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  On 16/06/2023 10:40, Shawn Sung (宋孝謙) wrote:
> > On Fri, 2023-06-16 at 10:07 +0200, Krzysztof Kozlowski wrote:
> >>   
> >> External email : Please do not click links or open attachments
> until
> >> you have verified the sender or the content.
> >>  On 16/06/2023 07:29, Shawn Sung (宋孝謙) wrote:
> >>> Hi Krzysztof,
> >>>
> >>> Thanks for the reminder, because MT8188 is not related to MT8173,
> >>
> >> How does it matter?
> > 
> > Because MT8188 Merge is fully compatible with MT8195, we didn't add
> its
> > compatible name to the driver, but just list it in dt-bindings, and
> use
> > MT8195's compatible name to match the ID in device table. For
> example,
> > in mt8188.dtsi:
> > 
> > merge1: merge@1c10c000 {
> >         compatible = "mediatek,mt8188-disp-merge",
> "mediatek,mt8195-
> > disp-merge";
> >         ...
> > };
> > 
> > If we add MT8188 Merge as an enum with MT8173, then our device tree
> > must be as below, and nothing will match in Merge driver.
> > 
> > merge1: merge@1c10c000 {
> >         compatible = "mediatek,mt8188-disp-
> > merge";
> >         ...
> > };
> 
> No, why? It would be incorrect with existing bindings. Again, on what
> tree are you working?

Just sent a v3 that is based on next-20230616 tag of linux-next/master
branch. After checking, still not sure what is the difference between
this modification and the others in mdp-rdma and ethdr. Could you share
more information please? 

> 
> > 
> >>
> >>>  I’ll
> >>> keep it as it is for now, however, I do find that MT8195 doesn’t
> >> exist
> >>> in this dt-bindings which it should be, so there may be conflicts
> >> when
> >>> this series is going to be merged.
> >>
> >> Don't top post.
> >>
> >> No, rebase on current next and implement my comment.
> > 
> > Will rebase linux-next in the next version.
> 
> Rebase now - for this discussion.

Done. Please refer to v3.

> 
> Best regards,
> Krzysztof
> 

Thanks,
Hsiao Chien Sung
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Re: [PATCH v2 03/15] dt-bindings: display: mediatek: merge: Add compatible for MT8188

[Shawn Sung (宋孝謙)]

On Fri, 2023-06-16 at 11:31 +0200, Krzysztof Kozlowski wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  On 16/06/2023 10:40, Shawn Sung (宋孝謙) wrote:
> > On Fri, 2023-06-16 at 10:07 +0200, Krzysztof Kozlowski wrote:
> >>   
> >> External email : Please do not click links or open attachments
> until
> >> you have verified the sender or the content.
> >>  On 16/06/2023 07:29, Shawn Sung (宋孝謙) wrote:
> >>> Hi Krzysztof,
> >>>
> >>> Thanks for the reminder, because MT8188 is not related to MT8173,
> >>
> >> How does it matter?
> > 
> > Because MT8188 Merge is fully compatible with MT8195, we didn't add
> its
> > compatible name to the driver, but just list it in dt-bindings, and
> use
> > MT8195's compatible name to match the ID in device table. For
> example,
> > in mt8188.dtsi:
> > 
> > merge1: merge@1c10c000 {
> >         compatible = "mediatek,mt8188-disp-merge",
> "mediatek,mt8195-
> > disp-merge";
> >         ...
> > };
> > 
> > If we add MT8188 Merge as an enum with MT8173, then our device tree
> > must be as below, and nothing will match in Merge driver.
> > 
> > merge1: merge@1c10c000 {
> >         compatible = "mediatek,mt8188-disp-
> > merge";
> >         ...
> > };
> 
> No, why? It would be incorrect with existing bindings. Again, on what
> tree are you working?

Just sent a v3 that is based on next-20230616 tag of linux-next/master
branch. After checking, still not sure what is the difference between
this modification and the others in mdp-rdma and ethdr. Could you share
more information please? 

> 
> > 
> >>
> >>>  I’ll
> >>> keep it as it is for now, however, I do find that MT8195 doesn’t
> >> exist
> >>> in this dt-bindings which it should be, so there may be conflicts
> >> when
> >>> this series is going to be merged.
> >>
> >> Don't top post.
> >>
> >> No, rebase on current next and implement my comment.
> > 
> > Will rebase linux-next in the next version.
> 
> Rebase now - for this discussion.

Done. Please refer to v3.

> 
> Best regards,
> Krzysztof
> 

Thanks,
Hsiao Chien Sung

[PATCH v2 04/15] dt-bindings: display: mediatek: padding: Add documentation for MT8188

[Hsiao Chien Sung]

PADDING is a new hardware module on MediaTek MT8188,
Add device tree bindings documentation for it.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 .../display/mediatek/mediatek,padding.yaml    | 81 +++++++++++++++++++
 1 file changed, 81 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
new file mode 100644
index 000000000000..390a518fa2cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek PADDING
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description:
+  MediaTek PADDING provides ability to VDOSYS1 to add pixels to width and height
+  of a layer with a specified color.
+  Since MIXER in VDOSYS1 requires the width of a layer to be 2-pixel-align, or
+  4-pixel-align when ETHDR is enabled, we need PADDING to deal with odd width.
+  Please notice that even if the PADDING is in bypass mode, settings in the
+  registers must be cleared to 0, or undefined behaviors could happen.
+
+properties:
+  compatible:
+    const: mediatek,mt8188-padding
+
+  reg:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: RDMA Clock
+
+  mediatek,gce-client-reg:
+    description:
+      GCE (Global Command Engine) is a multi-core micro processor that helps
+      its clients to execute commands without interrupting CPU. This property
+      describes GCE client's information that is composed by 4 fields.
+      1. pHandle of the GCE (there may be several GCE processors)
+      2. Sub-system ID defined in the dt-binding like a user ID
+         (Please refer to include/dt-bindings/gce/<chip>-gce.h)
+      3. Offset from base address of the subsys you are at
+      4. Size of the register the client needs
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      items:
+        - description: pHandle of the GCE
+        - description: Subsys ID defined in the dt-binding
+        - description: Offset from base address of the subsys
+        - description: Size of register
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - clocks
+  - mediatek,gce-client-reg
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mediatek,mt8188-clk.h>
+    #include <dt-bindings/power/mediatek,mt8188-power.h>
+    #include <dt-bindings/gce/mt8195-gce.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        padding0: padding@1c11d000 {
+            compatible = "mediatek,mt8188-padding";
+            reg = <0 0x1c11d000 0 0x1000>;
+            clocks = <&vdosys1 CLK_VDO1_PADDING0>;
+            power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+            mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;
+        };
+    };
--
2.18.0


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[PATCH v2 04/15] dt-bindings: display: mediatek: padding: Add documentation for MT8188

[Hsiao Chien Sung]

PADDING is a new hardware module on MediaTek MT8188,
Add device tree bindings documentation for it.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 .../display/mediatek/mediatek,padding.yaml    | 81 +++++++++++++++++++
 1 file changed, 81 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
new file mode 100644
index 000000000000..390a518fa2cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek PADDING
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description:
+  MediaTek PADDING provides ability to VDOSYS1 to add pixels to width and height
+  of a layer with a specified color.
+  Since MIXER in VDOSYS1 requires the width of a layer to be 2-pixel-align, or
+  4-pixel-align when ETHDR is enabled, we need PADDING to deal with odd width.
+  Please notice that even if the PADDING is in bypass mode, settings in the
+  registers must be cleared to 0, or undefined behaviors could happen.
+
+properties:
+  compatible:
+    const: mediatek,mt8188-padding
+
+  reg:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: RDMA Clock
+
+  mediatek,gce-client-reg:
+    description:
+      GCE (Global Command Engine) is a multi-core micro processor that helps
+      its clients to execute commands without interrupting CPU. This property
+      describes GCE client's information that is composed by 4 fields.
+      1. pHandle of the GCE (there may be several GCE processors)
+      2. Sub-system ID defined in the dt-binding like a user ID
+         (Please refer to include/dt-bindings/gce/<chip>-gce.h)
+      3. Offset from base address of the subsys you are at
+      4. Size of the register the client needs
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      items:
+        - description: pHandle of the GCE
+        - description: Subsys ID defined in the dt-binding
+        - description: Offset from base address of the subsys
+        - description: Size of register
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - clocks
+  - mediatek,gce-client-reg
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mediatek,mt8188-clk.h>
+    #include <dt-bindings/power/mediatek,mt8188-power.h>
+    #include <dt-bindings/gce/mt8195-gce.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        padding0: padding@1c11d000 {
+            compatible = "mediatek,mt8188-padding";
+            reg = <0 0x1c11d000 0 0x1000>;
+            clocks = <&vdosys1 CLK_VDO1_PADDING0>;
+            power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+            mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;
+        };
+    };
--
2.18.0

Re: [PATCH v2 04/15] dt-bindings: display: mediatek: padding: Add documentation for MT8188

[Krzysztof Kozlowski]

On 14/06/2023 09:31, Hsiao Chien Sung wrote:
> PADDING is a new hardware module on MediaTek MT8188,
> Add device tree bindings documentation for it.
> 

A nit, subject: drop second/last, redundant "documentation for". The
"dt-bindings" prefix is already stating that these are bindings and
documentation.

> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  .../display/mediatek/mediatek,padding.yaml    | 81 +++++++++++++++++++
>  1 file changed, 81 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
> new file mode 100644
> index 000000000000..390a518fa2cf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
> @@ -0,0 +1,81 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek PADDING

MediaTek Foo Bar Padding

Please explain what is this. PADDING does not look like acronym. If it
is, expand it.

> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description:
> +  MediaTek PADDING provides ability to VDOSYS1 to add pixels to width and height

Expand the acronym.

> +  of a layer with a specified color.
> +  Since MIXER in VDOSYS1 requires the width of a layer to be 2-pixel-align, or
> +  4-pixel-align when ETHDR is enabled, we need PADDING to deal with odd width.
> +  Please notice that even if the PADDING is in bypass mode, settings in the
> +  registers must be cleared to 0, or undefined behaviors could happen.
> +
> +properties:
> +  compatible:
> +    const: mediatek,mt8188-padding
> +
> +  reg:
> +    maxItems: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: RDMA Clock
> +
> +  mediatek,gce-client-reg:
> +    description:
> +      GCE (Global Command Engine) is a multi-core micro processor that helps
> +      its clients to execute commands without interrupting CPU. This property
> +      describes GCE client's information that is composed by 4 fields.
> +      1. pHandle of the GCE (there may be several GCE processors)
> +      2. Sub-system ID defined in the dt-binding like a user ID
> +         (Please refer to include/dt-bindings/gce/<chip>-gce.h)
> +      3. Offset from base address of the subsys you are at
> +      4. Size of the register the client needs
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      items:
> +        - description: pHandle of the GCE

Phandle (if first in sentence) or phandle. It's not a pH unit. Fix it in
other places as well.


> +        - description: Subsys ID defined in the dt-binding
> +        - description: Offset from base address of the subsys
> +        - description: Size of register


Best regards,
Krzysztof


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Re: [PATCH v2 04/15] dt-bindings: display: mediatek: padding: Add documentation for MT8188

[Krzysztof Kozlowski]

On 14/06/2023 09:31, Hsiao Chien Sung wrote:
> PADDING is a new hardware module on MediaTek MT8188,
> Add device tree bindings documentation for it.
> 

A nit, subject: drop second/last, redundant "documentation for". The
"dt-bindings" prefix is already stating that these are bindings and
documentation.

> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  .../display/mediatek/mediatek,padding.yaml    | 81 +++++++++++++++++++
>  1 file changed, 81 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
> new file mode 100644
> index 000000000000..390a518fa2cf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
> @@ -0,0 +1,81 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek PADDING

MediaTek Foo Bar Padding

Please explain what is this. PADDING does not look like acronym. If it
is, expand it.

> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description:
> +  MediaTek PADDING provides ability to VDOSYS1 to add pixels to width and height

Expand the acronym.

> +  of a layer with a specified color.
> +  Since MIXER in VDOSYS1 requires the width of a layer to be 2-pixel-align, or
> +  4-pixel-align when ETHDR is enabled, we need PADDING to deal with odd width.
> +  Please notice that even if the PADDING is in bypass mode, settings in the
> +  registers must be cleared to 0, or undefined behaviors could happen.
> +
> +properties:
> +  compatible:
> +    const: mediatek,mt8188-padding
> +
> +  reg:
> +    maxItems: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: RDMA Clock
> +
> +  mediatek,gce-client-reg:
> +    description:
> +      GCE (Global Command Engine) is a multi-core micro processor that helps
> +      its clients to execute commands without interrupting CPU. This property
> +      describes GCE client's information that is composed by 4 fields.
> +      1. pHandle of the GCE (there may be several GCE processors)
> +      2. Sub-system ID defined in the dt-binding like a user ID
> +         (Please refer to include/dt-bindings/gce/<chip>-gce.h)
> +      3. Offset from base address of the subsys you are at
> +      4. Size of the register the client needs
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      items:
> +        - description: pHandle of the GCE

Phandle (if first in sentence) or phandle. It's not a pH unit. Fix it in
other places as well.


> +        - description: Subsys ID defined in the dt-binding
> +        - description: Offset from base address of the subsys
> +        - description: Size of register


Best regards,
Krzysztof

Re: [PATCH v2 04/15] dt-bindings: display: mediatek: padding: Add documentation for MT8188

[Shawn Sung (宋孝謙)]

Hi Krzysztof,

Got it, the new title will be “dt-bindings: display: mediatek: padding:
Add MT8188”.

Since “PADDING” is not an acronym but just padding, in this case is
used to pad or stuff pixels to layers, I’ll change all of them to
“Padding” in the next version.

For “MediaTek Foo Bar Padding” suggestion, I changed it to “MediaTek
Display Padding”, hope it could make more sense.

Thanks,
Hsiao Chien Sung

On Thu, 2023-06-15 at 10:32 +0200, Krzysztof Kozlowski wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  On 14/06/2023 09:31, Hsiao Chien Sung wrote:
> > PADDING is a new hardware module on MediaTek MT8188,
> > Add device tree bindings documentation for it.
> > 
> 
> A nit, subject: drop second/last, redundant "documentation for". The
> "dt-bindings" prefix is already stating that these are bindings and
> documentation.
> 
> > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > ---
> >  .../display/mediatek/mediatek,padding.yaml    | 81
> +++++++++++++++++++
> >  1 file changed, 81 insertions(+)
> >  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,padding.y
> aml
> > 
> > diff --git
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding
> .yaml
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding
> .yaml
> > new file mode 100644
> > index 000000000000..390a518fa2cf
> > --- /dev/null
> > +++
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding
> .yaml
> > @@ -0,0 +1,81 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: 
> http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek PADDING
> 
> MediaTek Foo Bar Padding
> 
> Please explain what is this. PADDING does not look like acronym. If
> it
> is, expand it.
> 
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description:
> > +  MediaTek PADDING provides ability to VDOSYS1 to add pixels to
> width and height
> 
> Expand the acronym.
> 
> > +  of a layer with a specified color.
> > +  Since MIXER in VDOSYS1 requires the width of a layer to be 2-
> pixel-align, or
> > +  4-pixel-align when ETHDR is enabled, we need PADDING to deal
> with odd width.
> > +  Please notice that even if the PADDING is in bypass mode,
> settings in the
> > +  registers must be cleared to 0, or undefined behaviors could
> happen.
> > +
> > +properties:
> > +  compatible:
> > +    const: mediatek,mt8188-padding
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    items:
> > +      - description: RDMA Clock
> > +
> > +  mediatek,gce-client-reg:
> > +    description:
> > +      GCE (Global Command Engine) is a multi-core micro processor
> that helps
> > +      its clients to execute commands without interrupting CPU.
> This property
> > +      describes GCE client's information that is composed by 4
> fields.
> > +      1. pHandle of the GCE (there may be several GCE processors)
> > +      2. Sub-system ID defined in the dt-binding like a user ID
> > +         (Please refer to include/dt-bindings/gce/<chip>-gce.h)
> > +      3. Offset from base address of the subsys you are at
> > +      4. Size of the register the client needs
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    items:
> > +      items:
> > +        - description: pHandle of the GCE
> 
> Phandle (if first in sentence) or phandle. It's not a pH unit. Fix it
> in
> other places as well.
> 
> 
> > +        - description: Subsys ID defined in the dt-binding
> > +        - description: Offset from base address of the subsys
> > +        - description: Size of register
> 
> 
> Best regards,
> Krzysztof
> 
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Re: [PATCH v2 04/15] dt-bindings: display: mediatek: padding: Add documentation for MT8188

[Shawn Sung (宋孝謙)]

Hi Krzysztof,

Got it, the new title will be “dt-bindings: display: mediatek: padding:
Add MT8188”.

Since “PADDING” is not an acronym but just padding, in this case is
used to pad or stuff pixels to layers, I’ll change all of them to
“Padding” in the next version.

For “MediaTek Foo Bar Padding” suggestion, I changed it to “MediaTek
Display Padding”, hope it could make more sense.

Thanks,
Hsiao Chien Sung

On Thu, 2023-06-15 at 10:32 +0200, Krzysztof Kozlowski wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  On 14/06/2023 09:31, Hsiao Chien Sung wrote:
> > PADDING is a new hardware module on MediaTek MT8188,
> > Add device tree bindings documentation for it.
> > 
> 
> A nit, subject: drop second/last, redundant "documentation for". The
> "dt-bindings" prefix is already stating that these are bindings and
> documentation.
> 
> > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > ---
> >  .../display/mediatek/mediatek,padding.yaml    | 81
> +++++++++++++++++++
> >  1 file changed, 81 insertions(+)
> >  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,padding.y
> aml
> > 
> > diff --git
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding
> .yaml
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding
> .yaml
> > new file mode 100644
> > index 000000000000..390a518fa2cf
> > --- /dev/null
> > +++
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding
> .yaml
> > @@ -0,0 +1,81 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: 
> http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek PADDING
> 
> MediaTek Foo Bar Padding
> 
> Please explain what is this. PADDING does not look like acronym. If
> it
> is, expand it.
> 
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description:
> > +  MediaTek PADDING provides ability to VDOSYS1 to add pixels to
> width and height
> 
> Expand the acronym.
> 
> > +  of a layer with a specified color.
> > +  Since MIXER in VDOSYS1 requires the width of a layer to be 2-
> pixel-align, or
> > +  4-pixel-align when ETHDR is enabled, we need PADDING to deal
> with odd width.
> > +  Please notice that even if the PADDING is in bypass mode,
> settings in the
> > +  registers must be cleared to 0, or undefined behaviors could
> happen.
> > +
> > +properties:
> > +  compatible:
> > +    const: mediatek,mt8188-padding
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    items:
> > +      - description: RDMA Clock
> > +
> > +  mediatek,gce-client-reg:
> > +    description:
> > +      GCE (Global Command Engine) is a multi-core micro processor
> that helps
> > +      its clients to execute commands without interrupting CPU.
> This property
> > +      describes GCE client's information that is composed by 4
> fields.
> > +      1. pHandle of the GCE (there may be several GCE processors)
> > +      2. Sub-system ID defined in the dt-binding like a user ID
> > +         (Please refer to include/dt-bindings/gce/<chip>-gce.h)
> > +      3. Offset from base address of the subsys you are at
> > +      4. Size of the register the client needs
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    items:
> > +      items:
> > +        - description: pHandle of the GCE
> 
> Phandle (if first in sentence) or phandle. It's not a pH unit. Fix it
> in
> other places as well.
> 
> 
> > +        - description: Subsys ID defined in the dt-binding
> > +        - description: Offset from base address of the subsys
> > +        - description: Size of register
> 
> 
> Best regards,
> Krzysztof
> 

[PATCH v2 05/15] dt-bindings: arm: mediatek: Add compatible for MT8188

[Hsiao Chien Sung]

Add compatible name for MediaTek MT8188 VDOSYS1.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 536f5a5ebd24..642fa2e4736e 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -32,6 +32,7 @@ properties:
               - mediatek,mt8183-mmsys
               - mediatek,mt8186-mmsys
               - mediatek,mt8188-vdosys0
+              - mediatek,mt8188-vdosys1
               - mediatek,mt8192-mmsys
               - mediatek,mt8195-vdosys1
               - mediatek,mt8195-vppsys0
--
2.18.0


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[PATCH v2 05/15] dt-bindings: arm: mediatek: Add compatible for MT8188

[Hsiao Chien Sung]

Add compatible name for MediaTek MT8188 VDOSYS1.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 536f5a5ebd24..642fa2e4736e 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -32,6 +32,7 @@ properties:
               - mediatek,mt8183-mmsys
               - mediatek,mt8186-mmsys
               - mediatek,mt8188-vdosys0
+              - mediatek,mt8188-vdosys1
               - mediatek,mt8192-mmsys
               - mediatek,mt8195-vdosys1
               - mediatek,mt8195-vppsys0
--
2.18.0

Re: [PATCH v2 05/15] dt-bindings: arm: mediatek: Add compatible for MT8188

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> Add compatible name for MediaTek MT8188 VDOSYS1.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


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Re: [PATCH v2 05/15] dt-bindings: arm: mediatek: Add compatible for MT8188

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> Add compatible name for MediaTek MT8188 VDOSYS1.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH v2 05/15] dt-bindings: arm: mediatek: Add compatible for MT8188

[Krzysztof Kozlowski]

On 14/06/2023 09:31, Hsiao Chien Sung wrote:
> Add compatible name for MediaTek MT8188 VDOSYS1.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


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Re: [PATCH v2 05/15] dt-bindings: arm: mediatek: Add compatible for MT8188

[Krzysztof Kozlowski]

On 14/06/2023 09:31, Hsiao Chien Sung wrote:
> Add compatible name for MediaTek MT8188 VDOSYS1.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH v2 06/15] dt-bindings: reset: mt8188: Add VDOSYS0 reset control bits

[Hsiao Chien Sung]

Add MT8188 VDOSYS0 reset control bits.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 include/dt-bindings/reset/mt8188-resets.h | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h
index 377cdfda82a9..1d92759dc67d 100644
--- a/include/dt-bindings/reset/mt8188-resets.h
+++ b/include/dt-bindings/reset/mt8188-resets.h
@@ -33,4 +33,24 @@

 #define MT8188_TOPRGU_SW_RST_NUM               24

+#define MT8188_VDO0_RST_DISP_OVL0		0
+#define MT8188_VDO0_RST_FAKE_ENG0		1
+#define MT8188_VDO0_RST_DISP_CCORR0		2
+#define MT8188_VDO0_RST_DISP_MUTEX0		3
+#define MT8188_VDO0_RST_DISP_GAMMA0		4
+#define MT8188_VDO0_RST_DISP_DITHER0		5
+#define MT8188_VDO0_RST_DISP_WDMA0		6
+#define MT8188_VDO0_RST_DISP_RDMA0		7
+#define MT8188_VDO0_RST_DSI0			8
+#define MT8188_VDO0_RST_DSI1			9
+#define MT8188_VDO0_RST_DSC_WRAP0		10
+#define MT8188_VDO0_RST_VPP_MERGE0		11
+#define MT8188_VDO0_RST_DP_INTF0		12
+#define MT8188_VDO0_RST_DISP_AAL0		13
+#define MT8188_VDO0_RST_INLINEROT0		14
+#define MT8188_VDO0_RST_APB_BUS			15
+#define MT8188_VDO0_RST_DISP_COLOR0		16
+#define MT8188_VDO0_RST_MDP_WROT0		17
+#define MT8188_VDO0_RST_DISP_RSZ0		18
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */
--
2.18.0


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[PATCH v2 06/15] dt-bindings: reset: mt8188: Add VDOSYS0 reset control bits

[Hsiao Chien Sung]

Add MT8188 VDOSYS0 reset control bits.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 include/dt-bindings/reset/mt8188-resets.h | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h
index 377cdfda82a9..1d92759dc67d 100644
--- a/include/dt-bindings/reset/mt8188-resets.h
+++ b/include/dt-bindings/reset/mt8188-resets.h
@@ -33,4 +33,24 @@

 #define MT8188_TOPRGU_SW_RST_NUM               24

+#define MT8188_VDO0_RST_DISP_OVL0		0
+#define MT8188_VDO0_RST_FAKE_ENG0		1
+#define MT8188_VDO0_RST_DISP_CCORR0		2
+#define MT8188_VDO0_RST_DISP_MUTEX0		3
+#define MT8188_VDO0_RST_DISP_GAMMA0		4
+#define MT8188_VDO0_RST_DISP_DITHER0		5
+#define MT8188_VDO0_RST_DISP_WDMA0		6
+#define MT8188_VDO0_RST_DISP_RDMA0		7
+#define MT8188_VDO0_RST_DSI0			8
+#define MT8188_VDO0_RST_DSI1			9
+#define MT8188_VDO0_RST_DSC_WRAP0		10
+#define MT8188_VDO0_RST_VPP_MERGE0		11
+#define MT8188_VDO0_RST_DP_INTF0		12
+#define MT8188_VDO0_RST_DISP_AAL0		13
+#define MT8188_VDO0_RST_INLINEROT0		14
+#define MT8188_VDO0_RST_APB_BUS			15
+#define MT8188_VDO0_RST_DISP_COLOR0		16
+#define MT8188_VDO0_RST_MDP_WROT0		17
+#define MT8188_VDO0_RST_DISP_RSZ0		18
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */
--
2.18.0

Re: [PATCH v2 06/15] dt-bindings: reset: mt8188: Add VDOSYS0 reset control bits

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> Add MT8188 VDOSYS0 reset control bits.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

Now they're sequential and starting from 0. Totally valid.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   include/dt-bindings/reset/mt8188-resets.h | 20 ++++++++++++++++++++
>   1 file changed, 20 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h
> index 377cdfda82a9..1d92759dc67d 100644
> --- a/include/dt-bindings/reset/mt8188-resets.h
> +++ b/include/dt-bindings/reset/mt8188-resets.h
> @@ -33,4 +33,24 @@
> 
>   #define MT8188_TOPRGU_SW_RST_NUM               24
> 
> +#define MT8188_VDO0_RST_DISP_OVL0		0
> +#define MT8188_VDO0_RST_FAKE_ENG0		1
> +#define MT8188_VDO0_RST_DISP_CCORR0		2
> +#define MT8188_VDO0_RST_DISP_MUTEX0		3
> +#define MT8188_VDO0_RST_DISP_GAMMA0		4
> +#define MT8188_VDO0_RST_DISP_DITHER0		5
> +#define MT8188_VDO0_RST_DISP_WDMA0		6
> +#define MT8188_VDO0_RST_DISP_RDMA0		7
> +#define MT8188_VDO0_RST_DSI0			8
> +#define MT8188_VDO0_RST_DSI1			9
> +#define MT8188_VDO0_RST_DSC_WRAP0		10
> +#define MT8188_VDO0_RST_VPP_MERGE0		11
> +#define MT8188_VDO0_RST_DP_INTF0		12
> +#define MT8188_VDO0_RST_DISP_AAL0		13
> +#define MT8188_VDO0_RST_INLINEROT0		14
> +#define MT8188_VDO0_RST_APB_BUS			15
> +#define MT8188_VDO0_RST_DISP_COLOR0		16
> +#define MT8188_VDO0_RST_MDP_WROT0		17
> +#define MT8188_VDO0_RST_DISP_RSZ0		18
> +
>   #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */
> --
> 2.18.0
> 



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Re: [PATCH v2 06/15] dt-bindings: reset: mt8188: Add VDOSYS0 reset control bits

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> Add MT8188 VDOSYS0 reset control bits.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

Now they're sequential and starting from 0. Totally valid.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   include/dt-bindings/reset/mt8188-resets.h | 20 ++++++++++++++++++++
>   1 file changed, 20 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h
> index 377cdfda82a9..1d92759dc67d 100644
> --- a/include/dt-bindings/reset/mt8188-resets.h
> +++ b/include/dt-bindings/reset/mt8188-resets.h
> @@ -33,4 +33,24 @@
> 
>   #define MT8188_TOPRGU_SW_RST_NUM               24
> 
> +#define MT8188_VDO0_RST_DISP_OVL0		0
> +#define MT8188_VDO0_RST_FAKE_ENG0		1
> +#define MT8188_VDO0_RST_DISP_CCORR0		2
> +#define MT8188_VDO0_RST_DISP_MUTEX0		3
> +#define MT8188_VDO0_RST_DISP_GAMMA0		4
> +#define MT8188_VDO0_RST_DISP_DITHER0		5
> +#define MT8188_VDO0_RST_DISP_WDMA0		6
> +#define MT8188_VDO0_RST_DISP_RDMA0		7
> +#define MT8188_VDO0_RST_DSI0			8
> +#define MT8188_VDO0_RST_DSI1			9
> +#define MT8188_VDO0_RST_DSC_WRAP0		10
> +#define MT8188_VDO0_RST_VPP_MERGE0		11
> +#define MT8188_VDO0_RST_DP_INTF0		12
> +#define MT8188_VDO0_RST_DISP_AAL0		13
> +#define MT8188_VDO0_RST_INLINEROT0		14
> +#define MT8188_VDO0_RST_APB_BUS			15
> +#define MT8188_VDO0_RST_DISP_COLOR0		16
> +#define MT8188_VDO0_RST_MDP_WROT0		17
> +#define MT8188_VDO0_RST_DISP_RSZ0		18
> +
>   #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */
> --
> 2.18.0
> 

Re: [PATCH v2 06/15] dt-bindings: reset: mt8188: Add VDOSYS0 reset control bits

[Rob Herring]

On Wed, 14 Jun 2023 15:31:16 +0800, Hsiao Chien Sung wrote:
> Add MT8188 VDOSYS0 reset control bits.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  include/dt-bindings/reset/mt8188-resets.h | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>


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Re: [PATCH v2 06/15] dt-bindings: reset: mt8188: Add VDOSYS0 reset control bits

[Rob Herring]

On Wed, 14 Jun 2023 15:31:16 +0800, Hsiao Chien Sung wrote:
> Add MT8188 VDOSYS0 reset control bits.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  include/dt-bindings/reset/mt8188-resets.h | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 06/15] dt-bindings: reset: mt8188: Add VDOSYS0 reset control bits

[Shawn Sung (宋孝謙)]

Hi Rob,

On Wed, 2023-06-21 at 19:42 -0600, Rob Herring wrote:
> >     
> > External email : Please do not click links or open attachments
> until
> > you have verified the sender or the content.
> >  
> > On Wed, 14 Jun 2023 15:31:16 +0800, Hsiao Chien Sung wrote:
> > > Add MT8188 VDOSYS0 reset control bits.
> > > 
> > > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > > ---
> > >  include/dt-bindings/reset/mt8188-resets.h | 20
> > ++++++++++++++++++++
> > >  1 file changed, 20 insertions(+)
> > > 
> >
> > Acked-by: Rob Herring <robh@kernel.org>
> >

 
Thank you for adding the tag, since the commit you acked has been
merged to a new one, could you help to check the following link again
please?

https://lore.kernel.org/all/20230627063946.14935-7-shawn.sung@mediatek.com/

Thanks,
Hsiao Chien Sung
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Re: [PATCH v2 06/15] dt-bindings: reset: mt8188: Add VDOSYS0 reset control bits

[Shawn Sung (宋孝謙)]

Hi Rob,

On Wed, 2023-06-21 at 19:42 -0600, Rob Herring wrote:
> >     
> > External email : Please do not click links or open attachments
> until
> > you have verified the sender or the content.
> >  
> > On Wed, 14 Jun 2023 15:31:16 +0800, Hsiao Chien Sung wrote:
> > > Add MT8188 VDOSYS0 reset control bits.
> > > 
> > > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > > ---
> > >  include/dt-bindings/reset/mt8188-resets.h | 20
> > ++++++++++++++++++++
> > >  1 file changed, 20 insertions(+)
> > > 
> >
> > Acked-by: Rob Herring <robh@kernel.org>
> >

 
Thank you for adding the tag, since the commit you acked has been
merged to a new one, could you help to check the following link again
please?

https://lore.kernel.org/all/20230627063946.14935-7-shawn.sung@mediatek.com/

Thanks,
Hsiao Chien Sung

[PATCH v2 07/15] dt-bindings: reset: mt8188: Add VDOSYS1 reset control bits

[Hsiao Chien Sung]

Add MT8188 VDOSYS1 reset control bits.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 include/dt-bindings/reset/mt8188-resets.h | 55 +++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h
index 1d92759dc67d..377cf62cded2 100644
--- a/include/dt-bindings/reset/mt8188-resets.h
+++ b/include/dt-bindings/reset/mt8188-resets.h
@@ -53,4 +53,59 @@
 #define MT8188_VDO0_RST_MDP_WROT0		17
 #define MT8188_VDO0_RST_DISP_RSZ0		18

+#define MT8188_VDO1_RST_SMI_LARB2		0
+#define MT8188_VDO1_RST_SMI_LARB3		1
+#define MT8188_VDO1_RST_GALS			2
+#define MT8188_VDO1_RST_FAKE_ENG0		3
+#define MT8188_VDO1_RST_FAKE_ENG1		4
+#define MT8188_VDO1_RST_MDP_RDMA0		5
+#define MT8188_VDO1_RST_MDP_RDMA1		6
+#define MT8188_VDO1_RST_MDP_RDMA2		7
+#define MT8188_VDO1_RST_MDP_RDMA3		8
+#define MT8188_VDO1_RST_VPP_MERGE0		9
+#define MT8188_VDO1_RST_VPP_MERGE1		10
+#define MT8188_VDO1_RST_VPP_MERGE2		11
+#define MT8188_VDO1_RST_VPP_MERGE3		12
+#define MT8188_VDO1_RST_VPP_MERGE4		13
+#define MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC	14
+#define MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC	15
+#define MT8188_VDO1_RST_DISP_MUTEX		16
+#define MT8188_VDO1_RST_MDP_RDMA4		17
+#define MT8188_VDO1_RST_MDP_RDMA5		18
+#define MT8188_VDO1_RST_MDP_RDMA6		19
+#define MT8188_VDO1_RST_MDP_RDMA7		20
+#define MT8188_VDO1_RST_DP_INTF1_MMCK		21
+#define MT8188_VDO1_RST_DPI0_MM_CK		22
+#define MT8188_VDO1_RST_DPI1_MM_CK		23
+#define MT8188_VDO1_RST_MERGE0_DL_ASYNC		24
+#define MT8188_VDO1_RST_MERGE1_DL_ASYNC		25
+#define MT8188_VDO1_RST_MERGE2_DL_ASYNC		26
+#define MT8188_VDO1_RST_MERGE3_DL_ASYNC		27
+#define MT8188_VDO1_RST_MERGE4_DL_ASYNC		28
+#define MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC	29
+#define MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC	30
+#define MT8188_VDO1_RST_PADDING0		31
+#define MT8188_VDO1_RST_PADDING1		32
+#define MT8188_VDO1_RST_PADDING2		33
+#define MT8188_VDO1_RST_PADDING3		34
+#define MT8188_VDO1_RST_PADDING4		35
+#define MT8188_VDO1_RST_PADDING5		36
+#define MT8188_VDO1_RST_PADDING6		37
+#define MT8188_VDO1_RST_PADDING7		38
+#define MT8188_VDO1_RST_DISP_RSZ0		39
+#define MT8188_VDO1_RST_DISP_RSZ1		40
+#define MT8188_VDO1_RST_DISP_RSZ2		41
+#define MT8188_VDO1_RST_DISP_RSZ3		42
+#define MT8188_VDO1_RST_HDR_VDO_FE0		43
+#define MT8188_VDO1_RST_HDR_GFX_FE0		44
+#define MT8188_VDO1_RST_HDR_VDO_BE		45
+#define MT8188_VDO1_RST_HDR_VDO_FE1		46
+#define MT8188_VDO1_RST_HDR_GFX_FE1		47
+#define MT8188_VDO1_RST_DISP_MIXER		48
+#define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC	49
+#define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC	50
+#define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC	51
+#define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC	52
+#define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC	53
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */
--
2.18.0


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[PATCH v2 07/15] dt-bindings: reset: mt8188: Add VDOSYS1 reset control bits

[Hsiao Chien Sung]

Add MT8188 VDOSYS1 reset control bits.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 include/dt-bindings/reset/mt8188-resets.h | 55 +++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h
index 1d92759dc67d..377cf62cded2 100644
--- a/include/dt-bindings/reset/mt8188-resets.h
+++ b/include/dt-bindings/reset/mt8188-resets.h
@@ -53,4 +53,59 @@
 #define MT8188_VDO0_RST_MDP_WROT0		17
 #define MT8188_VDO0_RST_DISP_RSZ0		18

+#define MT8188_VDO1_RST_SMI_LARB2		0
+#define MT8188_VDO1_RST_SMI_LARB3		1
+#define MT8188_VDO1_RST_GALS			2
+#define MT8188_VDO1_RST_FAKE_ENG0		3
+#define MT8188_VDO1_RST_FAKE_ENG1		4
+#define MT8188_VDO1_RST_MDP_RDMA0		5
+#define MT8188_VDO1_RST_MDP_RDMA1		6
+#define MT8188_VDO1_RST_MDP_RDMA2		7
+#define MT8188_VDO1_RST_MDP_RDMA3		8
+#define MT8188_VDO1_RST_VPP_MERGE0		9
+#define MT8188_VDO1_RST_VPP_MERGE1		10
+#define MT8188_VDO1_RST_VPP_MERGE2		11
+#define MT8188_VDO1_RST_VPP_MERGE3		12
+#define MT8188_VDO1_RST_VPP_MERGE4		13
+#define MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC	14
+#define MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC	15
+#define MT8188_VDO1_RST_DISP_MUTEX		16
+#define MT8188_VDO1_RST_MDP_RDMA4		17
+#define MT8188_VDO1_RST_MDP_RDMA5		18
+#define MT8188_VDO1_RST_MDP_RDMA6		19
+#define MT8188_VDO1_RST_MDP_RDMA7		20
+#define MT8188_VDO1_RST_DP_INTF1_MMCK		21
+#define MT8188_VDO1_RST_DPI0_MM_CK		22
+#define MT8188_VDO1_RST_DPI1_MM_CK		23
+#define MT8188_VDO1_RST_MERGE0_DL_ASYNC		24
+#define MT8188_VDO1_RST_MERGE1_DL_ASYNC		25
+#define MT8188_VDO1_RST_MERGE2_DL_ASYNC		26
+#define MT8188_VDO1_RST_MERGE3_DL_ASYNC		27
+#define MT8188_VDO1_RST_MERGE4_DL_ASYNC		28
+#define MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC	29
+#define MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC	30
+#define MT8188_VDO1_RST_PADDING0		31
+#define MT8188_VDO1_RST_PADDING1		32
+#define MT8188_VDO1_RST_PADDING2		33
+#define MT8188_VDO1_RST_PADDING3		34
+#define MT8188_VDO1_RST_PADDING4		35
+#define MT8188_VDO1_RST_PADDING5		36
+#define MT8188_VDO1_RST_PADDING6		37
+#define MT8188_VDO1_RST_PADDING7		38
+#define MT8188_VDO1_RST_DISP_RSZ0		39
+#define MT8188_VDO1_RST_DISP_RSZ1		40
+#define MT8188_VDO1_RST_DISP_RSZ2		41
+#define MT8188_VDO1_RST_DISP_RSZ3		42
+#define MT8188_VDO1_RST_HDR_VDO_FE0		43
+#define MT8188_VDO1_RST_HDR_GFX_FE0		44
+#define MT8188_VDO1_RST_HDR_VDO_BE		45
+#define MT8188_VDO1_RST_HDR_VDO_FE1		46
+#define MT8188_VDO1_RST_HDR_GFX_FE1		47
+#define MT8188_VDO1_RST_DISP_MIXER		48
+#define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC	49
+#define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC	50
+#define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC	51
+#define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC	52
+#define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC	53
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */
--
2.18.0

Re: [PATCH v2 07/15] dt-bindings: reset: mt8188: Add VDOSYS1 reset control bits

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> Add MT8188 VDOSYS1 reset control bits.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


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Re: [PATCH v2 07/15] dt-bindings: reset: mt8188: Add VDOSYS1 reset control bits

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> Add MT8188 VDOSYS1 reset control bits.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH v2 07/15] dt-bindings: reset: mt8188: Add VDOSYS1 reset control bits

[Krzysztof Kozlowski]

On 14/06/2023 09:31, Hsiao Chien Sung wrote:
> Add MT8188 VDOSYS1 reset control bits.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---

Squash it with previous. You are touch the same file adding almost the
same bits...

Best regards,
Krzysztof


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Re: [PATCH v2 07/15] dt-bindings: reset: mt8188: Add VDOSYS1 reset control bits

[Krzysztof Kozlowski]

On 14/06/2023 09:31, Hsiao Chien Sung wrote:
> Add MT8188 VDOSYS1 reset control bits.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---

Squash it with previous. You are touch the same file adding almost the
same bits...

Best regards,
Krzysztof

[PATCH v2 08/15] soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys

[Hsiao Chien Sung]

- Add register definitions for MT8188
- Add VDOSYS1 routing table
- Update MUTEX definitions accordingly
- Set VSYNC length from 0x40 (default) to 1 since ETHDR is bypassed

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/soc/mediatek/mt8188-mmsys.h | 127 ++++++++++++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c    |  13 +++
 drivers/soc/mediatek/mtk-mmsys.h    |  29 +++++++
 drivers/soc/mediatek/mtk-mutex.c    |  35 ++++++++
 4 files changed, 204 insertions(+)

diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
index 448cc3761b43..447afb72d95f 100644
--- a/drivers/soc/mediatek/mt8188-mmsys.h
+++ b/drivers/soc/mediatek/mt8188-mmsys.h
@@ -67,6 +67,57 @@
 #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE		BIT(18)
 #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0		BIT(19)

+#define MT8188_VDO1_SW0_RST_B					0x1d0
+#define MT8188_VDO1_HDR_TOP_CFG					0xd00
+#define MT8188_VDO1_MIXER_IN1_ALPHA				0xd30
+#define MT8188_VDO1_MIXER_IN1_PAD				0xd40
+#define MT8188_VDO1_MERGE0_ASYNC_CFG_WD				0xe30
+#define MT8188_VDO1_HDRBE_ASYNC_CFG_WD				0xe70
+#define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN			0xf04
+#define MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0		1
+#define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN			0xf08
+#define MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1		1
+#define MT8188_VDO1_DISP_DPI1_SEL_IN				0xf10
+#define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT		0
+#define MT8188_VDO1_DISP_DP_INTF0_SEL_IN			0xf14
+#define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT	0
+#define MT8188_VDO1_MERGE4_SOUT_SEL				0xf18
+#define MT8188_MERGE4_SOUT_TO_DPI1_SEL				BIT(2)
+#define MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL			BIT(3)
+#define MT8188_VDO1_MIXER_IN1_SEL_IN				0xf24
+#define MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT		1
+#define MT8188_VDO1_MIXER_IN2_SEL_IN				0xf28
+#define MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT		1
+#define MT8188_VDO1_MIXER_IN3_SEL_IN				0xf2c
+#define MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT		1
+#define MT8188_VDO1_MIXER_IN4_SEL_IN				0xf30
+#define MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT		1
+#define MT8188_VDO1_MIXER_OUT_SOUT_SEL				0xf34
+#define MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL			1
+#define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN			0xf3c
+#define MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2		1
+#define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL			0xf40
+#define MT8188_SOUT_TO_MIXER_IN1_SEL				1
+#define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL			0xf44
+#define MT8188_SOUT_TO_MIXER_IN2_SEL				1
+#define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL			0xf48
+#define MT8188_SOUT_TO_MIXER_IN3_SEL				1
+#define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL			0xf4c
+#define MT8188_SOUT_TO_MIXER_IN4_SEL				1
+#define MT8188_VDO1_MERGE4_ASYNC_SEL_IN				0xf50
+#define MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT		1
+#define MT8188_VDO1_MIXER_IN1_SOUT_SEL				0xf58
+#define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER			0
+#define MT8188_VDO1_MIXER_IN2_SOUT_SEL				0xf5c
+#define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER			0
+#define MT8188_VDO1_MIXER_IN3_SOUT_SEL				0xf60
+#define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER			0
+#define MT8188_VDO1_MIXER_IN4_SOUT_SEL				0xf64
+#define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER			0
+#define MT8188_VDO1_MIXER_SOUT_SEL_IN				0xf68
+#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER		0
+#define MT8188_VDO1_MIXER_VSYNC_LEN				0xd5c
+
 static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
 	{
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -146,4 +197,80 @@ static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
 	},
 };

+static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] = {
+	{
+		DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
+		MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
+		MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+	}, {
+		DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
+		MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
+		MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+	}, {
+		DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
+		MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
+		MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+	}, {
+		DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
+		MT8188_SOUT_TO_MIXER_IN1_SEL
+	}, {
+		DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
+		MT8188_SOUT_TO_MIXER_IN2_SEL
+	}, {
+		DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
+		MT8188_SOUT_TO_MIXER_IN3_SEL
+	}, {
+		DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
+		MT8188_SOUT_TO_MIXER_IN4_SEL
+	}, {
+		DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+		MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
+		MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
+	}, {
+		DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
+		MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
+	}, {
+		DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
+		MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
+	}, {
+		DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
+		MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
+	}, {
+		DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
+		MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
+	}, {
+		DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+		MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
+		MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
+	}, {
+		DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+		MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
+		MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+		MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
+		MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+		MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+		MT8188_MERGE4_SOUT_TO_DPI1_SEL
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+		MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
+		MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+		MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
+		MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL
+	}
+};
+
 #endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 9619faa796e8..3a81ef2bcc3c 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -89,6 +89,15 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
 	.num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
 };

+static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
+	.clk_driver = "clk-mt8188-vdo1",
+	.routes = mmsys_mt8188_vdo1_routing_table,
+	.num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table),
+	.sw0_rst_offset = MT8188_VDO1_SW0_RST_B,
+	.num_resets = 96,
+	.vsync_len = 1,
+};
+
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.clk_driver = "clk-mt8192-mm",
 	.routes = mmsys_mt8192_routing_table,
@@ -213,6 +222,9 @@ void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16
 			      alpha_sel << (19 + idx), cmdq_pkt);
 	mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
 			      GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode, cmdq_pkt);
+	if (mmsys->data->vsync_len)
+		mtk_mmsys_update_bits(mmsys, MT8188_VDO1_MIXER_VSYNC_LEN, ~0,
+				      mmsys->data->vsync_len, cmdq_pkt);
 }
 EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);

@@ -431,6 +443,7 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
 	{ .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data },
 	{ .compatible = "mediatek,mt8186-mmsys", .data = &mt8186_mmsys_driver_data },
 	{ .compatible = "mediatek,mt8188-vdosys0", .data = &mt8188_vdosys0_driver_data },
+	{ .compatible = "mediatek,mt8188-vdosys1", .data = &mt8188_vdosys1_driver_data },
 	{ .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data },
 	/* "mediatek,mt8195-mmsys" compatible is deprecated */
 	{ .compatible = "mediatek,mt8195-mmsys", .data = &mt8195_vdosys0_driver_data },
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 6725403d2e3a..e4ab46017430 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -86,6 +86,34 @@ struct mtk_mmsys_routes {
 	u32 val;
 };

+/**
+ * struct mtk_mmsys_driver_data - settings for the mmsys
+ * @clk_driver: Clock driver name that the mmsys is using
+ *              (defined in drivers/clk/mediatek/clk-*.c).
+ * @routes: Routing table of the mmsys.
+ *          It provides mux settings from one module to another.
+ * @num_routes: Array size of the routes.
+ * @sw0_rst_offset: Register offset for the reset control.
+ * @num_resets: Number of reset bits that are defined
+ * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe)
+ *             or VDOSYS (Video). Only VDOSYS needs to be added to drm driver.
+ * @vsync_len: VSYNC length of the MIXER.
+ *             VSYNC is usually triggered by the connector, so its length is
+ *             a fixed value as long as the frame rate is decided, but ETDHR and
+ *             MIXER generate their own VSYNC due to hardware design, therefore
+ *             MIXER has to sync with ETHDR by adjusting VSYNC length.
+ *             On MT8195, there is no such setting so we use the gap between
+ *             falling edge and rising edge of SOF (Start of Frame) signal to
+ *             do the job, but since MT8188, VSNYC_LEN setting is introduced to
+ *             solve the problem and is given 0x40 (ticks) as the default value.
+ *             Please notice that this value has to be set to 1 (minimum) if
+ *             ETHDR is bypassed, otherwise MIXER could wait too long and causing
+ *             underflow.
+ *
+ * Each MMSYS (multi-media system) may have different settings, they may use
+ * different clock sources, mux settings, reset control ...etc., and these
+ * differences are all stored here.
+ */
 struct mtk_mmsys_driver_data {
 	const char *clk_driver;
 	const struct mtk_mmsys_routes *routes;
@@ -93,6 +121,7 @@ struct mtk_mmsys_driver_data {
 	const u16 sw0_rst_offset;
 	const u32 num_resets;
 	const bool is_vppsys;
+	const u8 vsync_len;
 };

 /*
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 26f3d9a41496..11dda20eb462 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -134,6 +134,22 @@
 #define MT8188_MUTEX_MOD_DISP_POSTMASK0		24
 #define MT8188_MUTEX_MOD2_DISP_PWM0		33

+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA0	0
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA1	1
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA2	2
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA3	3
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA4	4
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5	5
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6	6
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7	7
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0	20
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1	21
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2	22
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3	23
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4	24
+#define MT8188_MUTEX_MOD_DISP1_DISP_MIXER	30
+#define MT8188_MUTEX_MOD_DISP1_DP_INTF1		39
+
 #define MT8195_MUTEX_MOD_DISP_OVL0		0
 #define MT8195_MUTEX_MOD_DISP_WDMA0		1
 #define MT8195_MUTEX_MOD_DISP_RDMA0		2
@@ -265,6 +281,7 @@
 #define MT8183_MUTEX_SOF_DPI0			2
 #define MT8188_MUTEX_SOF_DSI0			1
 #define MT8188_MUTEX_SOF_DP_INTF0		3
+#define MT8188_MUTEX_SOF_DP_INTF1		4
 #define MT8195_MUTEX_SOF_DSI0			1
 #define MT8195_MUTEX_SOF_DSI1			2
 #define MT8195_MUTEX_SOF_DP_INTF0		3
@@ -276,6 +293,7 @@
 #define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)
 #define MT8188_MUTEX_EOF_DSI0			(MT8188_MUTEX_SOF_DSI0 << 7)
 #define MT8188_MUTEX_EOF_DP_INTF0		(MT8188_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8188_MUTEX_EOF_DP_INTF1		(MT8188_MUTEX_SOF_DP_INTF1 << 7)
 #define MT8195_MUTEX_EOF_DSI0			(MT8195_MUTEX_SOF_DSI0 << 7)
 #define MT8195_MUTEX_EOF_DSI1			(MT8195_MUTEX_SOF_DSI1 << 7)
 #define MT8195_MUTEX_EOF_DP_INTF0		(MT8195_MUTEX_SOF_DP_INTF0 << 7)
@@ -446,6 +464,21 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0,
 	[DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0,
 	[DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0,
+	[DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0,
+	[DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1,
+	[DDP_COMPONENT_MDP_RDMA2] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA2,
+	[DDP_COMPONENT_MDP_RDMA3] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA3,
+	[DDP_COMPONENT_MDP_RDMA4] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA4,
+	[DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5,
+	[DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6,
+	[DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7,
+	[DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0,
+	[DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1,
+	[DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2,
+	[DDP_COMPONENT_MERGE4] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE3,
+	[DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER,
+	[DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4,
+	[DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1,
 };

 static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
@@ -606,6 +639,8 @@ static const unsigned int mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 		MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0,
 	[MUTEX_SOF_DP_INTF0] =
 		MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0,
+	[MUTEX_SOF_DP_INTF1] =
+		MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1,
 };

 static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
--
2.18.0


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[PATCH v2 08/15] soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys

[Hsiao Chien Sung]

- Add register definitions for MT8188
- Add VDOSYS1 routing table
- Update MUTEX definitions accordingly
- Set VSYNC length from 0x40 (default) to 1 since ETHDR is bypassed

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/soc/mediatek/mt8188-mmsys.h | 127 ++++++++++++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c    |  13 +++
 drivers/soc/mediatek/mtk-mmsys.h    |  29 +++++++
 drivers/soc/mediatek/mtk-mutex.c    |  35 ++++++++
 4 files changed, 204 insertions(+)

diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
index 448cc3761b43..447afb72d95f 100644
--- a/drivers/soc/mediatek/mt8188-mmsys.h
+++ b/drivers/soc/mediatek/mt8188-mmsys.h
@@ -67,6 +67,57 @@
 #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE		BIT(18)
 #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0		BIT(19)

+#define MT8188_VDO1_SW0_RST_B					0x1d0
+#define MT8188_VDO1_HDR_TOP_CFG					0xd00
+#define MT8188_VDO1_MIXER_IN1_ALPHA				0xd30
+#define MT8188_VDO1_MIXER_IN1_PAD				0xd40
+#define MT8188_VDO1_MERGE0_ASYNC_CFG_WD				0xe30
+#define MT8188_VDO1_HDRBE_ASYNC_CFG_WD				0xe70
+#define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN			0xf04
+#define MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0		1
+#define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN			0xf08
+#define MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1		1
+#define MT8188_VDO1_DISP_DPI1_SEL_IN				0xf10
+#define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT		0
+#define MT8188_VDO1_DISP_DP_INTF0_SEL_IN			0xf14
+#define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT	0
+#define MT8188_VDO1_MERGE4_SOUT_SEL				0xf18
+#define MT8188_MERGE4_SOUT_TO_DPI1_SEL				BIT(2)
+#define MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL			BIT(3)
+#define MT8188_VDO1_MIXER_IN1_SEL_IN				0xf24
+#define MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT		1
+#define MT8188_VDO1_MIXER_IN2_SEL_IN				0xf28
+#define MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT		1
+#define MT8188_VDO1_MIXER_IN3_SEL_IN				0xf2c
+#define MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT		1
+#define MT8188_VDO1_MIXER_IN4_SEL_IN				0xf30
+#define MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT		1
+#define MT8188_VDO1_MIXER_OUT_SOUT_SEL				0xf34
+#define MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL			1
+#define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN			0xf3c
+#define MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2		1
+#define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL			0xf40
+#define MT8188_SOUT_TO_MIXER_IN1_SEL				1
+#define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL			0xf44
+#define MT8188_SOUT_TO_MIXER_IN2_SEL				1
+#define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL			0xf48
+#define MT8188_SOUT_TO_MIXER_IN3_SEL				1
+#define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL			0xf4c
+#define MT8188_SOUT_TO_MIXER_IN4_SEL				1
+#define MT8188_VDO1_MERGE4_ASYNC_SEL_IN				0xf50
+#define MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT		1
+#define MT8188_VDO1_MIXER_IN1_SOUT_SEL				0xf58
+#define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER			0
+#define MT8188_VDO1_MIXER_IN2_SOUT_SEL				0xf5c
+#define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER			0
+#define MT8188_VDO1_MIXER_IN3_SOUT_SEL				0xf60
+#define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER			0
+#define MT8188_VDO1_MIXER_IN4_SOUT_SEL				0xf64
+#define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER			0
+#define MT8188_VDO1_MIXER_SOUT_SEL_IN				0xf68
+#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER		0
+#define MT8188_VDO1_MIXER_VSYNC_LEN				0xd5c
+
 static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
 	{
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -146,4 +197,80 @@ static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
 	},
 };

+static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] = {
+	{
+		DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
+		MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
+		MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+	}, {
+		DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
+		MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
+		MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+	}, {
+		DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
+		MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
+		MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+	}, {
+		DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
+		MT8188_SOUT_TO_MIXER_IN1_SEL
+	}, {
+		DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
+		MT8188_SOUT_TO_MIXER_IN2_SEL
+	}, {
+		DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
+		MT8188_SOUT_TO_MIXER_IN3_SEL
+	}, {
+		DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
+		MT8188_SOUT_TO_MIXER_IN4_SEL
+	}, {
+		DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+		MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
+		MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
+	}, {
+		DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
+		MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
+	}, {
+		DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
+		MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
+	}, {
+		DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
+		MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
+	}, {
+		DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
+		MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
+	}, {
+		DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+		MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
+		MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
+	}, {
+		DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+		MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
+		MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+		MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
+		MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+		MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+		MT8188_MERGE4_SOUT_TO_DPI1_SEL
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+		MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
+		MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+		MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
+		MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL
+	}
+};
+
 #endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 9619faa796e8..3a81ef2bcc3c 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -89,6 +89,15 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
 	.num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
 };

+static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
+	.clk_driver = "clk-mt8188-vdo1",
+	.routes = mmsys_mt8188_vdo1_routing_table,
+	.num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table),
+	.sw0_rst_offset = MT8188_VDO1_SW0_RST_B,
+	.num_resets = 96,
+	.vsync_len = 1,
+};
+
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.clk_driver = "clk-mt8192-mm",
 	.routes = mmsys_mt8192_routing_table,
@@ -213,6 +222,9 @@ void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16
 			      alpha_sel << (19 + idx), cmdq_pkt);
 	mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
 			      GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode, cmdq_pkt);
+	if (mmsys->data->vsync_len)
+		mtk_mmsys_update_bits(mmsys, MT8188_VDO1_MIXER_VSYNC_LEN, ~0,
+				      mmsys->data->vsync_len, cmdq_pkt);
 }
 EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);

@@ -431,6 +443,7 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
 	{ .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data },
 	{ .compatible = "mediatek,mt8186-mmsys", .data = &mt8186_mmsys_driver_data },
 	{ .compatible = "mediatek,mt8188-vdosys0", .data = &mt8188_vdosys0_driver_data },
+	{ .compatible = "mediatek,mt8188-vdosys1", .data = &mt8188_vdosys1_driver_data },
 	{ .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data },
 	/* "mediatek,mt8195-mmsys" compatible is deprecated */
 	{ .compatible = "mediatek,mt8195-mmsys", .data = &mt8195_vdosys0_driver_data },
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 6725403d2e3a..e4ab46017430 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -86,6 +86,34 @@ struct mtk_mmsys_routes {
 	u32 val;
 };

+/**
+ * struct mtk_mmsys_driver_data - settings for the mmsys
+ * @clk_driver: Clock driver name that the mmsys is using
+ *              (defined in drivers/clk/mediatek/clk-*.c).
+ * @routes: Routing table of the mmsys.
+ *          It provides mux settings from one module to another.
+ * @num_routes: Array size of the routes.
+ * @sw0_rst_offset: Register offset for the reset control.
+ * @num_resets: Number of reset bits that are defined
+ * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe)
+ *             or VDOSYS (Video). Only VDOSYS needs to be added to drm driver.
+ * @vsync_len: VSYNC length of the MIXER.
+ *             VSYNC is usually triggered by the connector, so its length is
+ *             a fixed value as long as the frame rate is decided, but ETDHR and
+ *             MIXER generate their own VSYNC due to hardware design, therefore
+ *             MIXER has to sync with ETHDR by adjusting VSYNC length.
+ *             On MT8195, there is no such setting so we use the gap between
+ *             falling edge and rising edge of SOF (Start of Frame) signal to
+ *             do the job, but since MT8188, VSNYC_LEN setting is introduced to
+ *             solve the problem and is given 0x40 (ticks) as the default value.
+ *             Please notice that this value has to be set to 1 (minimum) if
+ *             ETHDR is bypassed, otherwise MIXER could wait too long and causing
+ *             underflow.
+ *
+ * Each MMSYS (multi-media system) may have different settings, they may use
+ * different clock sources, mux settings, reset control ...etc., and these
+ * differences are all stored here.
+ */
 struct mtk_mmsys_driver_data {
 	const char *clk_driver;
 	const struct mtk_mmsys_routes *routes;
@@ -93,6 +121,7 @@ struct mtk_mmsys_driver_data {
 	const u16 sw0_rst_offset;
 	const u32 num_resets;
 	const bool is_vppsys;
+	const u8 vsync_len;
 };

 /*
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 26f3d9a41496..11dda20eb462 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -134,6 +134,22 @@
 #define MT8188_MUTEX_MOD_DISP_POSTMASK0		24
 #define MT8188_MUTEX_MOD2_DISP_PWM0		33

+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA0	0
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA1	1
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA2	2
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA3	3
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA4	4
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5	5
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6	6
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7	7
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0	20
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1	21
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2	22
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3	23
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4	24
+#define MT8188_MUTEX_MOD_DISP1_DISP_MIXER	30
+#define MT8188_MUTEX_MOD_DISP1_DP_INTF1		39
+
 #define MT8195_MUTEX_MOD_DISP_OVL0		0
 #define MT8195_MUTEX_MOD_DISP_WDMA0		1
 #define MT8195_MUTEX_MOD_DISP_RDMA0		2
@@ -265,6 +281,7 @@
 #define MT8183_MUTEX_SOF_DPI0			2
 #define MT8188_MUTEX_SOF_DSI0			1
 #define MT8188_MUTEX_SOF_DP_INTF0		3
+#define MT8188_MUTEX_SOF_DP_INTF1		4
 #define MT8195_MUTEX_SOF_DSI0			1
 #define MT8195_MUTEX_SOF_DSI1			2
 #define MT8195_MUTEX_SOF_DP_INTF0		3
@@ -276,6 +293,7 @@
 #define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)
 #define MT8188_MUTEX_EOF_DSI0			(MT8188_MUTEX_SOF_DSI0 << 7)
 #define MT8188_MUTEX_EOF_DP_INTF0		(MT8188_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8188_MUTEX_EOF_DP_INTF1		(MT8188_MUTEX_SOF_DP_INTF1 << 7)
 #define MT8195_MUTEX_EOF_DSI0			(MT8195_MUTEX_SOF_DSI0 << 7)
 #define MT8195_MUTEX_EOF_DSI1			(MT8195_MUTEX_SOF_DSI1 << 7)
 #define MT8195_MUTEX_EOF_DP_INTF0		(MT8195_MUTEX_SOF_DP_INTF0 << 7)
@@ -446,6 +464,21 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0,
 	[DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0,
 	[DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0,
+	[DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0,
+	[DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1,
+	[DDP_COMPONENT_MDP_RDMA2] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA2,
+	[DDP_COMPONENT_MDP_RDMA3] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA3,
+	[DDP_COMPONENT_MDP_RDMA4] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA4,
+	[DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5,
+	[DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6,
+	[DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7,
+	[DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0,
+	[DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1,
+	[DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2,
+	[DDP_COMPONENT_MERGE4] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE3,
+	[DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER,
+	[DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4,
+	[DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1,
 };

 static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
@@ -606,6 +639,8 @@ static const unsigned int mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 		MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0,
 	[MUTEX_SOF_DP_INTF0] =
 		MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0,
+	[MUTEX_SOF_DP_INTF1] =
+		MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1,
 };

 static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
--
2.18.0

Re: [PATCH v2 08/15] soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> - Add register definitions for MT8188
> - Add VDOSYS1 routing table
> - Update MUTEX definitions accordingly
> - Set VSYNC length from 0x40 (default) to 1 since ETHDR is bypassed
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

I love that you added documentation to struct mtk_mmsys_driver_data. Good job!

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   drivers/soc/mediatek/mt8188-mmsys.h | 127 ++++++++++++++++++++++++++++
>   drivers/soc/mediatek/mtk-mmsys.c    |  13 +++
>   drivers/soc/mediatek/mtk-mmsys.h    |  29 +++++++
>   drivers/soc/mediatek/mtk-mutex.c    |  35 ++++++++
>   4 files changed, 204 insertions(+)
> 
> diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
> index 448cc3761b43..447afb72d95f 100644
> --- a/drivers/soc/mediatek/mt8188-mmsys.h
> +++ b/drivers/soc/mediatek/mt8188-mmsys.h
> @@ -67,6 +67,57 @@
>   #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE		BIT(18)
>   #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0		BIT(19)
> 
> +#define MT8188_VDO1_SW0_RST_B					0x1d0
> +#define MT8188_VDO1_HDR_TOP_CFG					0xd00
> +#define MT8188_VDO1_MIXER_IN1_ALPHA				0xd30
> +#define MT8188_VDO1_MIXER_IN1_PAD				0xd40
> +#define MT8188_VDO1_MERGE0_ASYNC_CFG_WD				0xe30
> +#define MT8188_VDO1_HDRBE_ASYNC_CFG_WD				0xe70
> +#define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN			0xf04
> +#define MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0		1
> +#define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN			0xf08
> +#define MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1		1
> +#define MT8188_VDO1_DISP_DPI1_SEL_IN				0xf10
> +#define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT		0
> +#define MT8188_VDO1_DISP_DP_INTF0_SEL_IN			0xf14
> +#define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT	0
> +#define MT8188_VDO1_MERGE4_SOUT_SEL				0xf18
> +#define MT8188_MERGE4_SOUT_TO_DPI1_SEL				BIT(2)
> +#define MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL			BIT(3)
> +#define MT8188_VDO1_MIXER_IN1_SEL_IN				0xf24
> +#define MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT		1
> +#define MT8188_VDO1_MIXER_IN2_SEL_IN				0xf28
> +#define MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT		1
> +#define MT8188_VDO1_MIXER_IN3_SEL_IN				0xf2c
> +#define MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT		1
> +#define MT8188_VDO1_MIXER_IN4_SEL_IN				0xf30
> +#define MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT		1
> +#define MT8188_VDO1_MIXER_OUT_SOUT_SEL				0xf34
> +#define MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL			1
> +#define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN			0xf3c
> +#define MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2		1
> +#define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL			0xf40
> +#define MT8188_SOUT_TO_MIXER_IN1_SEL				1
> +#define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL			0xf44
> +#define MT8188_SOUT_TO_MIXER_IN2_SEL				1
> +#define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL			0xf48
> +#define MT8188_SOUT_TO_MIXER_IN3_SEL				1
> +#define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL			0xf4c
> +#define MT8188_SOUT_TO_MIXER_IN4_SEL				1
> +#define MT8188_VDO1_MERGE4_ASYNC_SEL_IN				0xf50
> +#define MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT		1
> +#define MT8188_VDO1_MIXER_IN1_SOUT_SEL				0xf58
> +#define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER			0
> +#define MT8188_VDO1_MIXER_IN2_SOUT_SEL				0xf5c
> +#define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER			0
> +#define MT8188_VDO1_MIXER_IN3_SOUT_SEL				0xf60
> +#define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER			0
> +#define MT8188_VDO1_MIXER_IN4_SOUT_SEL				0xf64
> +#define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER			0
> +#define MT8188_VDO1_MIXER_SOUT_SEL_IN				0xf68
> +#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER		0
> +#define MT8188_VDO1_MIXER_VSYNC_LEN				0xd5c
> +
>   static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
>   	{
>   		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> @@ -146,4 +197,80 @@ static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
>   	},
>   };
> 
> +static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] = {
> +	{
> +		DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
> +		MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
> +		MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
> +	}, {
> +		DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
> +		MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
> +		MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
> +	}, {
> +		DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
> +		MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
> +		MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
> +	}, {
> +		DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
> +		MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
> +		MT8188_SOUT_TO_MIXER_IN1_SEL
> +	}, {
> +		DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
> +		MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
> +		MT8188_SOUT_TO_MIXER_IN2_SEL
> +	}, {
> +		DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
> +		MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
> +		MT8188_SOUT_TO_MIXER_IN3_SEL
> +	}, {
> +		DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
> +		MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
> +		MT8188_SOUT_TO_MIXER_IN4_SEL
> +	}, {
> +		DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> +		MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
> +		MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
> +	}, {
> +		DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
> +		MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
> +		MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
> +	}, {
> +		DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
> +		MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
> +		MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
> +	}, {
> +		DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
> +		MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
> +		MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
> +	}, {
> +		DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
> +		MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
> +		MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
> +	}, {
> +		DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> +		MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
> +		MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
> +	}, {
> +		DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> +		MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
> +		MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
> +	}, {
> +		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> +		MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
> +		MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
> +	}, {
> +		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> +		MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
> +		MT8188_MERGE4_SOUT_TO_DPI1_SEL
> +	}, {
> +		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> +		MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
> +		MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
> +	}, {
> +		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> +		MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
> +		MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL
> +	}
> +};
> +
>   #endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 9619faa796e8..3a81ef2bcc3c 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -89,6 +89,15 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
>   	.num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
>   };
> 
> +static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
> +	.clk_driver = "clk-mt8188-vdo1",
> +	.routes = mmsys_mt8188_vdo1_routing_table,
> +	.num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table),
> +	.sw0_rst_offset = MT8188_VDO1_SW0_RST_B,
> +	.num_resets = 96,
> +	.vsync_len = 1,
> +};
> +
>   static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
>   	.clk_driver = "clk-mt8192-mm",
>   	.routes = mmsys_mt8192_routing_table,
> @@ -213,6 +222,9 @@ void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16
>   			      alpha_sel << (19 + idx), cmdq_pkt);
>   	mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
>   			      GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode, cmdq_pkt);
> +	if (mmsys->data->vsync_len)
> +		mtk_mmsys_update_bits(mmsys, MT8188_VDO1_MIXER_VSYNC_LEN, ~0,
> +				      mmsys->data->vsync_len, cmdq_pkt);
>   }
>   EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);
> 
> @@ -431,6 +443,7 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
>   	{ .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data },
>   	{ .compatible = "mediatek,mt8186-mmsys", .data = &mt8186_mmsys_driver_data },
>   	{ .compatible = "mediatek,mt8188-vdosys0", .data = &mt8188_vdosys0_driver_data },
> +	{ .compatible = "mediatek,mt8188-vdosys1", .data = &mt8188_vdosys1_driver_data },
>   	{ .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data },
>   	/* "mediatek,mt8195-mmsys" compatible is deprecated */
>   	{ .compatible = "mediatek,mt8195-mmsys", .data = &mt8195_vdosys0_driver_data },
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index 6725403d2e3a..e4ab46017430 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -86,6 +86,34 @@ struct mtk_mmsys_routes {
>   	u32 val;
>   };
> 
> +/**
> + * struct mtk_mmsys_driver_data - settings for the mmsys
> + * @clk_driver: Clock driver name that the mmsys is using
> + *              (defined in drivers/clk/mediatek/clk-*.c).
> + * @routes: Routing table of the mmsys.
> + *          It provides mux settings from one module to another.
> + * @num_routes: Array size of the routes.
> + * @sw0_rst_offset: Register offset for the reset control.
> + * @num_resets: Number of reset bits that are defined
> + * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe)
> + *             or VDOSYS (Video). Only VDOSYS needs to be added to drm driver.
> + * @vsync_len: VSYNC length of the MIXER.
> + *             VSYNC is usually triggered by the connector, so its length is
> + *             a fixed value as long as the frame rate is decided, but ETDHR and
> + *             MIXER generate their own VSYNC due to hardware design, therefore
> + *             MIXER has to sync with ETHDR by adjusting VSYNC length.
> + *             On MT8195, there is no such setting so we use the gap between
> + *             falling edge and rising edge of SOF (Start of Frame) signal to
> + *             do the job, but since MT8188, VSNYC_LEN setting is introduced to
> + *             solve the problem and is given 0x40 (ticks) as the default value.
> + *             Please notice that this value has to be set to 1 (minimum) if
> + *             ETHDR is bypassed, otherwise MIXER could wait too long and causing
> + *             underflow.
> + *
> + * Each MMSYS (multi-media system) may have different settings, they may use
> + * different clock sources, mux settings, reset control ...etc., and these
> + * differences are all stored here.
> + */
>   struct mtk_mmsys_driver_data {
>   	const char *clk_driver;
>   	const struct mtk_mmsys_routes *routes;
> @@ -93,6 +121,7 @@ struct mtk_mmsys_driver_data {
>   	const u16 sw0_rst_offset;
>   	const u32 num_resets;
>   	const bool is_vppsys;
> +	const u8 vsync_len;
>   };
> 
>   /*
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 26f3d9a41496..11dda20eb462 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -134,6 +134,22 @@
>   #define MT8188_MUTEX_MOD_DISP_POSTMASK0		24
>   #define MT8188_MUTEX_MOD2_DISP_PWM0		33
> 
> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA0	0
> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA1	1
> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA2	2
> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA3	3
> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA4	4
> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5	5
> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6	6
> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7	7
> +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0	20
> +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1	21
> +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2	22
> +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3	23
> +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4	24
> +#define MT8188_MUTEX_MOD_DISP1_DISP_MIXER	30
> +#define MT8188_MUTEX_MOD_DISP1_DP_INTF1		39
> +
>   #define MT8195_MUTEX_MOD_DISP_OVL0		0
>   #define MT8195_MUTEX_MOD_DISP_WDMA0		1
>   #define MT8195_MUTEX_MOD_DISP_RDMA0		2
> @@ -265,6 +281,7 @@
>   #define MT8183_MUTEX_SOF_DPI0			2
>   #define MT8188_MUTEX_SOF_DSI0			1
>   #define MT8188_MUTEX_SOF_DP_INTF0		3
> +#define MT8188_MUTEX_SOF_DP_INTF1		4
>   #define MT8195_MUTEX_SOF_DSI0			1
>   #define MT8195_MUTEX_SOF_DSI1			2
>   #define MT8195_MUTEX_SOF_DP_INTF0		3
> @@ -276,6 +293,7 @@
>   #define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)
>   #define MT8188_MUTEX_EOF_DSI0			(MT8188_MUTEX_SOF_DSI0 << 7)
>   #define MT8188_MUTEX_EOF_DP_INTF0		(MT8188_MUTEX_SOF_DP_INTF0 << 7)
> +#define MT8188_MUTEX_EOF_DP_INTF1		(MT8188_MUTEX_SOF_DP_INTF1 << 7)
>   #define MT8195_MUTEX_EOF_DSI0			(MT8195_MUTEX_SOF_DSI0 << 7)
>   #define MT8195_MUTEX_EOF_DSI1			(MT8195_MUTEX_SOF_DSI1 << 7)
>   #define MT8195_MUTEX_EOF_DP_INTF0		(MT8195_MUTEX_SOF_DP_INTF0 << 7)
> @@ -446,6 +464,21 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
>   	[DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0,
>   	[DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0,
>   	[DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0,
> +	[DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0,
> +	[DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1,
> +	[DDP_COMPONENT_MDP_RDMA2] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA2,
> +	[DDP_COMPONENT_MDP_RDMA3] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA3,
> +	[DDP_COMPONENT_MDP_RDMA4] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA4,
> +	[DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5,
> +	[DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6,
> +	[DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7,
> +	[DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0,
> +	[DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1,
> +	[DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2,
> +	[DDP_COMPONENT_MERGE4] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE3,
> +	[DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER,
> +	[DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4,
> +	[DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1,
>   };
> 
>   static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> @@ -606,6 +639,8 @@ static const unsigned int mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = {
>   		MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0,
>   	[MUTEX_SOF_DP_INTF0] =
>   		MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0,
> +	[MUTEX_SOF_DP_INTF1] =
> +		MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1,
>   };
> 
>   static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> --
> 2.18.0
> 


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Re: [PATCH v2 08/15] soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> - Add register definitions for MT8188
> - Add VDOSYS1 routing table
> - Update MUTEX definitions accordingly
> - Set VSYNC length from 0x40 (default) to 1 since ETHDR is bypassed
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

I love that you added documentation to struct mtk_mmsys_driver_data. Good job!

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   drivers/soc/mediatek/mt8188-mmsys.h | 127 ++++++++++++++++++++++++++++
>   drivers/soc/mediatek/mtk-mmsys.c    |  13 +++
>   drivers/soc/mediatek/mtk-mmsys.h    |  29 +++++++
>   drivers/soc/mediatek/mtk-mutex.c    |  35 ++++++++
>   4 files changed, 204 insertions(+)
> 
> diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
> index 448cc3761b43..447afb72d95f 100644
> --- a/drivers/soc/mediatek/mt8188-mmsys.h
> +++ b/drivers/soc/mediatek/mt8188-mmsys.h
> @@ -67,6 +67,57 @@
>   #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE		BIT(18)
>   #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0		BIT(19)
> 
> +#define MT8188_VDO1_SW0_RST_B					0x1d0
> +#define MT8188_VDO1_HDR_TOP_CFG					0xd00
> +#define MT8188_VDO1_MIXER_IN1_ALPHA				0xd30
> +#define MT8188_VDO1_MIXER_IN1_PAD				0xd40
> +#define MT8188_VDO1_MERGE0_ASYNC_CFG_WD				0xe30
> +#define MT8188_VDO1_HDRBE_ASYNC_CFG_WD				0xe70
> +#define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN			0xf04
> +#define MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0		1
> +#define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN			0xf08
> +#define MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1		1
> +#define MT8188_VDO1_DISP_DPI1_SEL_IN				0xf10
> +#define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT		0
> +#define MT8188_VDO1_DISP_DP_INTF0_SEL_IN			0xf14
> +#define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT	0
> +#define MT8188_VDO1_MERGE4_SOUT_SEL				0xf18
> +#define MT8188_MERGE4_SOUT_TO_DPI1_SEL				BIT(2)
> +#define MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL			BIT(3)
> +#define MT8188_VDO1_MIXER_IN1_SEL_IN				0xf24
> +#define MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT		1
> +#define MT8188_VDO1_MIXER_IN2_SEL_IN				0xf28
> +#define MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT		1
> +#define MT8188_VDO1_MIXER_IN3_SEL_IN				0xf2c
> +#define MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT		1
> +#define MT8188_VDO1_MIXER_IN4_SEL_IN				0xf30
> +#define MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT		1
> +#define MT8188_VDO1_MIXER_OUT_SOUT_SEL				0xf34
> +#define MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL			1
> +#define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN			0xf3c
> +#define MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2		1
> +#define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL			0xf40
> +#define MT8188_SOUT_TO_MIXER_IN1_SEL				1
> +#define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL			0xf44
> +#define MT8188_SOUT_TO_MIXER_IN2_SEL				1
> +#define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL			0xf48
> +#define MT8188_SOUT_TO_MIXER_IN3_SEL				1
> +#define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL			0xf4c
> +#define MT8188_SOUT_TO_MIXER_IN4_SEL				1
> +#define MT8188_VDO1_MERGE4_ASYNC_SEL_IN				0xf50
> +#define MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT		1
> +#define MT8188_VDO1_MIXER_IN1_SOUT_SEL				0xf58
> +#define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER			0
> +#define MT8188_VDO1_MIXER_IN2_SOUT_SEL				0xf5c
> +#define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER			0
> +#define MT8188_VDO1_MIXER_IN3_SOUT_SEL				0xf60
> +#define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER			0
> +#define MT8188_VDO1_MIXER_IN4_SOUT_SEL				0xf64
> +#define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER			0
> +#define MT8188_VDO1_MIXER_SOUT_SEL_IN				0xf68
> +#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER		0
> +#define MT8188_VDO1_MIXER_VSYNC_LEN				0xd5c
> +
>   static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
>   	{
>   		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> @@ -146,4 +197,80 @@ static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
>   	},
>   };
> 
> +static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] = {
> +	{
> +		DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
> +		MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
> +		MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
> +	}, {
> +		DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
> +		MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
> +		MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
> +	}, {
> +		DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
> +		MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
> +		MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
> +	}, {
> +		DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
> +		MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
> +		MT8188_SOUT_TO_MIXER_IN1_SEL
> +	}, {
> +		DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
> +		MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
> +		MT8188_SOUT_TO_MIXER_IN2_SEL
> +	}, {
> +		DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
> +		MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
> +		MT8188_SOUT_TO_MIXER_IN3_SEL
> +	}, {
> +		DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
> +		MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
> +		MT8188_SOUT_TO_MIXER_IN4_SEL
> +	}, {
> +		DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> +		MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
> +		MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
> +	}, {
> +		DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
> +		MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
> +		MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
> +	}, {
> +		DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
> +		MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
> +		MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
> +	}, {
> +		DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
> +		MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
> +		MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
> +	}, {
> +		DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
> +		MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
> +		MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
> +	}, {
> +		DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> +		MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
> +		MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
> +	}, {
> +		DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> +		MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
> +		MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
> +	}, {
> +		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> +		MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
> +		MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
> +	}, {
> +		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> +		MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
> +		MT8188_MERGE4_SOUT_TO_DPI1_SEL
> +	}, {
> +		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> +		MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
> +		MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
> +	}, {
> +		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> +		MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
> +		MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL
> +	}
> +};
> +
>   #endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 9619faa796e8..3a81ef2bcc3c 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -89,6 +89,15 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
>   	.num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
>   };
> 
> +static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
> +	.clk_driver = "clk-mt8188-vdo1",
> +	.routes = mmsys_mt8188_vdo1_routing_table,
> +	.num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table),
> +	.sw0_rst_offset = MT8188_VDO1_SW0_RST_B,
> +	.num_resets = 96,
> +	.vsync_len = 1,
> +};
> +
>   static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
>   	.clk_driver = "clk-mt8192-mm",
>   	.routes = mmsys_mt8192_routing_table,
> @@ -213,6 +222,9 @@ void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16
>   			      alpha_sel << (19 + idx), cmdq_pkt);
>   	mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
>   			      GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode, cmdq_pkt);
> +	if (mmsys->data->vsync_len)
> +		mtk_mmsys_update_bits(mmsys, MT8188_VDO1_MIXER_VSYNC_LEN, ~0,
> +				      mmsys->data->vsync_len, cmdq_pkt);
>   }
>   EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);
> 
> @@ -431,6 +443,7 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
>   	{ .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data },
>   	{ .compatible = "mediatek,mt8186-mmsys", .data = &mt8186_mmsys_driver_data },
>   	{ .compatible = "mediatek,mt8188-vdosys0", .data = &mt8188_vdosys0_driver_data },
> +	{ .compatible = "mediatek,mt8188-vdosys1", .data = &mt8188_vdosys1_driver_data },
>   	{ .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data },
>   	/* "mediatek,mt8195-mmsys" compatible is deprecated */
>   	{ .compatible = "mediatek,mt8195-mmsys", .data = &mt8195_vdosys0_driver_data },
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index 6725403d2e3a..e4ab46017430 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -86,6 +86,34 @@ struct mtk_mmsys_routes {
>   	u32 val;
>   };
> 
> +/**
> + * struct mtk_mmsys_driver_data - settings for the mmsys
> + * @clk_driver: Clock driver name that the mmsys is using
> + *              (defined in drivers/clk/mediatek/clk-*.c).
> + * @routes: Routing table of the mmsys.
> + *          It provides mux settings from one module to another.
> + * @num_routes: Array size of the routes.
> + * @sw0_rst_offset: Register offset for the reset control.
> + * @num_resets: Number of reset bits that are defined
> + * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe)
> + *             or VDOSYS (Video). Only VDOSYS needs to be added to drm driver.
> + * @vsync_len: VSYNC length of the MIXER.
> + *             VSYNC is usually triggered by the connector, so its length is
> + *             a fixed value as long as the frame rate is decided, but ETDHR and
> + *             MIXER generate their own VSYNC due to hardware design, therefore
> + *             MIXER has to sync with ETHDR by adjusting VSYNC length.
> + *             On MT8195, there is no such setting so we use the gap between
> + *             falling edge and rising edge of SOF (Start of Frame) signal to
> + *             do the job, but since MT8188, VSNYC_LEN setting is introduced to
> + *             solve the problem and is given 0x40 (ticks) as the default value.
> + *             Please notice that this value has to be set to 1 (minimum) if
> + *             ETHDR is bypassed, otherwise MIXER could wait too long and causing
> + *             underflow.
> + *
> + * Each MMSYS (multi-media system) may have different settings, they may use
> + * different clock sources, mux settings, reset control ...etc., and these
> + * differences are all stored here.
> + */
>   struct mtk_mmsys_driver_data {
>   	const char *clk_driver;
>   	const struct mtk_mmsys_routes *routes;
> @@ -93,6 +121,7 @@ struct mtk_mmsys_driver_data {
>   	const u16 sw0_rst_offset;
>   	const u32 num_resets;
>   	const bool is_vppsys;
> +	const u8 vsync_len;
>   };
> 
>   /*
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 26f3d9a41496..11dda20eb462 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -134,6 +134,22 @@
>   #define MT8188_MUTEX_MOD_DISP_POSTMASK0		24
>   #define MT8188_MUTEX_MOD2_DISP_PWM0		33
> 
> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA0	0
> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA1	1
> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA2	2
> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA3	3
> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA4	4
> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5	5
> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6	6
> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7	7
> +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0	20
> +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1	21
> +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2	22
> +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3	23
> +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4	24
> +#define MT8188_MUTEX_MOD_DISP1_DISP_MIXER	30
> +#define MT8188_MUTEX_MOD_DISP1_DP_INTF1		39
> +
>   #define MT8195_MUTEX_MOD_DISP_OVL0		0
>   #define MT8195_MUTEX_MOD_DISP_WDMA0		1
>   #define MT8195_MUTEX_MOD_DISP_RDMA0		2
> @@ -265,6 +281,7 @@
>   #define MT8183_MUTEX_SOF_DPI0			2
>   #define MT8188_MUTEX_SOF_DSI0			1
>   #define MT8188_MUTEX_SOF_DP_INTF0		3
> +#define MT8188_MUTEX_SOF_DP_INTF1		4
>   #define MT8195_MUTEX_SOF_DSI0			1
>   #define MT8195_MUTEX_SOF_DSI1			2
>   #define MT8195_MUTEX_SOF_DP_INTF0		3
> @@ -276,6 +293,7 @@
>   #define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)
>   #define MT8188_MUTEX_EOF_DSI0			(MT8188_MUTEX_SOF_DSI0 << 7)
>   #define MT8188_MUTEX_EOF_DP_INTF0		(MT8188_MUTEX_SOF_DP_INTF0 << 7)
> +#define MT8188_MUTEX_EOF_DP_INTF1		(MT8188_MUTEX_SOF_DP_INTF1 << 7)
>   #define MT8195_MUTEX_EOF_DSI0			(MT8195_MUTEX_SOF_DSI0 << 7)
>   #define MT8195_MUTEX_EOF_DSI1			(MT8195_MUTEX_SOF_DSI1 << 7)
>   #define MT8195_MUTEX_EOF_DP_INTF0		(MT8195_MUTEX_SOF_DP_INTF0 << 7)
> @@ -446,6 +464,21 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
>   	[DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0,
>   	[DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0,
>   	[DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0,
> +	[DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0,
> +	[DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1,
> +	[DDP_COMPONENT_MDP_RDMA2] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA2,
> +	[DDP_COMPONENT_MDP_RDMA3] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA3,
> +	[DDP_COMPONENT_MDP_RDMA4] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA4,
> +	[DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5,
> +	[DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6,
> +	[DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7,
> +	[DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0,
> +	[DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1,
> +	[DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2,
> +	[DDP_COMPONENT_MERGE4] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE3,
> +	[DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER,
> +	[DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4,
> +	[DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1,
>   };
> 
>   static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> @@ -606,6 +639,8 @@ static const unsigned int mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = {
>   		MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0,
>   	[MUTEX_SOF_DP_INTF0] =
>   		MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0,
> +	[MUTEX_SOF_DP_INTF1] =
> +		MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1,
>   };
> 
>   static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> --
> 2.18.0
> 

Re: [PATCH v2 08/15] soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys

[Shawn Sung (宋孝謙)]

Thank you for saying that. Will do more in the future.
 
I found two typos in the description.
Will fix them in the next version as well.
(ETDHR -> ETHDR, VSNYC -> VSYNC)

On Wed, 2023-06-14 at 13:21 +0200, AngeloGioacchino Del Regno wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> > - Add register definitions for MT8188
> > - Add VDOSYS1 routing table
> > - Update MUTEX definitions accordingly
> > - Set VSYNC length from 0x40 (default) to 1 since ETHDR is bypassed
> > 
> > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> 
> I love that you added documentation to struct mtk_mmsys_driver_data.
> Good job!
> 
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> 
> > ---
> >   drivers/soc/mediatek/mt8188-mmsys.h | 127
> ++++++++++++++++++++++++++++
> >   drivers/soc/mediatek/mtk-mmsys.c    |  13 +++
> >   drivers/soc/mediatek/mtk-mmsys.h    |  29 +++++++
> >   drivers/soc/mediatek/mtk-mutex.c    |  35 ++++++++
> >   4 files changed, 204 insertions(+)
> > 
> > diff --git a/drivers/soc/mediatek/mt8188-mmsys.h
> b/drivers/soc/mediatek/mt8188-mmsys.h
> > index 448cc3761b43..447afb72d95f 100644
> > --- a/drivers/soc/mediatek/mt8188-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8188-mmsys.h
> > @@ -67,6 +67,57 @@
> >   #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGEBIT(18)
> >   #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0BIT(19)
> > 
> > +#define MT8188_VDO1_SW0_RST_B0x1d0
> > +#define MT8188_VDO1_HDR_TOP_CFG0xd00
> > +#define MT8188_VDO1_MIXER_IN1_ALPHA0xd30
> > +#define MT8188_VDO1_MIXER_IN1_PAD0xd40
> > +#define MT8188_VDO1_MERGE0_ASYNC_CFG_WD0xe30
> > +#define MT8188_VDO1_HDRBE_ASYNC_CFG_WD0xe70
> > +#define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN0xf04
> > +#define MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA01
> > +#define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN0xf08
> > +#define MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA11
> > +#define MT8188_VDO1_DISP_DPI1_SEL_IN0xf10
> > +#define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT0
> > +#define MT8188_VDO1_DISP_DP_INTF0_SEL_IN0xf14
> > +#define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT0
> > +#define MT8188_VDO1_MERGE4_SOUT_SEL0xf18
> > +#define MT8188_MERGE4_SOUT_TO_DPI1_SELBIT(2)
> > +#define MT8188_MERGE4_SOUT_TO_DP_INTF0_SELBIT(3)
> > +#define MT8188_VDO1_MIXER_IN1_SEL_IN0xf24
> > +#define MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT1
> > +#define MT8188_VDO1_MIXER_IN2_SEL_IN0xf28
> > +#define MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT1
> > +#define MT8188_VDO1_MIXER_IN3_SEL_IN0xf2c
> > +#define MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT1
> > +#define MT8188_VDO1_MIXER_IN4_SEL_IN0xf30
> > +#define MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT1
> > +#define MT8188_VDO1_MIXER_OUT_SOUT_SEL0xf34
> > +#define MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL1
> > +#define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN0xf3c
> > +#define MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA21
> > +#define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL0xf40
> > +#define MT8188_SOUT_TO_MIXER_IN1_SEL1
> > +#define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL0xf44
> > +#define MT8188_SOUT_TO_MIXER_IN2_SEL1
> > +#define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL0xf48
> > +#define MT8188_SOUT_TO_MIXER_IN3_SEL1
> > +#define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL0xf4c
> > +#define MT8188_SOUT_TO_MIXER_IN4_SEL1
> > +#define MT8188_VDO1_MERGE4_ASYNC_SEL_IN0xf50
> > +#define MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT1
> > +#define MT8188_VDO1_MIXER_IN1_SOUT_SEL0xf58
> > +#define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER0
> > +#define MT8188_VDO1_MIXER_IN2_SOUT_SEL0xf5c
> > +#define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER0
> > +#define MT8188_VDO1_MIXER_IN3_SOUT_SEL0xf60
> > +#define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER0
> > +#define MT8188_VDO1_MIXER_IN4_SOUT_SEL0xf64
> > +#define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER0
> > +#define MT8188_VDO1_MIXER_SOUT_SEL_IN0xf68
> > +#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER0
> > +#define MT8188_VDO1_MIXER_VSYNC_LEN0xd5c
> > +
> >   static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[]
> = {
> >   {
> >   DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> > @@ -146,4 +197,80 @@ static const struct mtk_mmsys_routes
> mmsys_mt8188_routing_table[] = {
> >   },
> >   };
> > 
> > +static const struct mtk_mmsys_routes
> mmsys_mt8188_vdo1_routing_table[] = {
> > +{
> > +DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
> > +MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
> > +MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
> > +}, {
> > +DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
> > +MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
> > +MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
> > +}, {
> > +DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
> > +MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
> > +MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
> > +}, {
> > +DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
> > +MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
> > +MT8188_SOUT_TO_MIXER_IN1_SEL
> > +}, {
> > +DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
> > +MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
> > +MT8188_SOUT_TO_MIXER_IN2_SEL
> > +}, {
> > +DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
> > +MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
> > +MT8188_SOUT_TO_MIXER_IN3_SEL
> > +}, {
> > +DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
> > +MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
> > +MT8188_SOUT_TO_MIXER_IN4_SEL
> > +}, {
> > +DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> > +MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
> > +MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
> > +}, {
> > +DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
> > +MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
> > +MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
> > +}, {
> > +DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
> > +MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
> > +MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
> > +}, {
> > +DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
> > +MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
> > +MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
> > +}, {
> > +DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
> > +MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
> > +MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
> > +}, {
> > +DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> > +MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
> > +MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
> > +}, {
> > +DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> > +MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
> > +MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
> > +}, {
> > +DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> > +MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
> > +MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
> > +}, {
> > +DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> > +MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
> > +MT8188_MERGE4_SOUT_TO_DPI1_SEL
> > +}, {
> > +DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> > +MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
> > +MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
> > +}, {
> > +DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> > +MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
> > +MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL
> > +}
> > +};
> > +
> >   #endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> > index 9619faa796e8..3a81ef2bcc3c 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -89,6 +89,15 @@ static const struct mtk_mmsys_driver_data
> mt8188_vdosys0_driver_data = {
> >   .num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
> >   };
> > 
> > +static const struct mtk_mmsys_driver_data
> mt8188_vdosys1_driver_data = {
> > +.clk_driver = "clk-mt8188-vdo1",
> > +.routes = mmsys_mt8188_vdo1_routing_table,
> > +.num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table),
> > +.sw0_rst_offset = MT8188_VDO1_SW0_RST_B,
> > +.num_resets = 96,
> > +.vsync_len = 1,
> > +};
> > +
> >   static const struct mtk_mmsys_driver_data
> mt8192_mmsys_driver_data = {
> >   .clk_driver = "clk-mt8192-mm",
> >   .routes = mmsys_mt8192_routing_table,
> > @@ -213,6 +222,9 @@ void mtk_mmsys_mixer_in_config(struct device
> *dev, int idx, bool alpha_sel, u16
> >         alpha_sel << (19 + idx), cmdq_pkt);
> >   mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx -
> 1) * 4,
> >         GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode,
> cmdq_pkt);
> > +if (mmsys->data->vsync_len)
> > +mtk_mmsys_update_bits(mmsys, MT8188_VDO1_MIXER_VSYNC_LEN, ~0,
> > +      mmsys->data->vsync_len, cmdq_pkt);
> >   }
> >   EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);
> > 
> > @@ -431,6 +443,7 @@ static const struct of_device_id
> of_match_mtk_mmsys[] = {
> >   { .compatible = "mediatek,mt8183-mmsys", .data =
> &mt8183_mmsys_driver_data },
> >   { .compatible = "mediatek,mt8186-mmsys", .data =
> &mt8186_mmsys_driver_data },
> >   { .compatible = "mediatek,mt8188-vdosys0", .data =
> &mt8188_vdosys0_driver_data },
> > +{ .compatible = "mediatek,mt8188-vdosys1", .data =
> &mt8188_vdosys1_driver_data },
> >   { .compatible = "mediatek,mt8192-mmsys", .data =
> &mt8192_mmsys_driver_data },
> >   /* "mediatek,mt8195-mmsys" compatible is deprecated */
> >   { .compatible = "mediatek,mt8195-mmsys", .data =
> &mt8195_vdosys0_driver_data },
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> b/drivers/soc/mediatek/mtk-mmsys.h
> > index 6725403d2e3a..e4ab46017430 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -86,6 +86,34 @@ struct mtk_mmsys_routes {
> >   u32 val;
> >   };
> > 
> > +/**
> > + * struct mtk_mmsys_driver_data - settings for the mmsys
> > + * @clk_driver: Clock driver name that the mmsys is using
> > + *              (defined in drivers/clk/mediatek/clk-*.c).
> > + * @routes: Routing table of the mmsys.
> > + *          It provides mux settings from one module to another.
> > + * @num_routes: Array size of the routes.
> > + * @sw0_rst_offset: Register offset for the reset control.
> > + * @num_resets: Number of reset bits that are defined
> > + * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe)
> > + *             or VDOSYS (Video). Only VDOSYS needs to be added to
> drm driver.
> > + * @vsync_len: VSYNC length of the MIXER.
> > + *             VSYNC is usually triggered by the connector, so its
> length is
> > + *             a fixed value as long as the frame rate is decided,
> but ETDHR and
> > + *             MIXER generate their own VSYNC due to hardware
> design, therefore
> > + *             MIXER has to sync with ETHDR by adjusting VSYNC
> length.
> > + *             On MT8195, there is no such setting so we use the
> gap between
> > + *             falling edge and rising edge of SOF (Start of
> Frame) signal to
> > + *             do the job, but since MT8188, VSNYC_LEN setting is
> introduced to
> > + *             solve the problem and is given 0x40 (ticks) as the
> default value.
> > + *             Please notice that this value has to be set to 1
> (minimum) if
> > + *             ETHDR is bypassed, otherwise MIXER could wait too
> long and causing
> > + *             underflow.
> > + *
> > + * Each MMSYS (multi-media system) may have different settings,
> they may use
> > + * different clock sources, mux settings, reset control ...etc.,
> and these
> > + * differences are all stored here.
> > + */
> >   struct mtk_mmsys_driver_data {
> >   const char *clk_driver;
> >   const struct mtk_mmsys_routes *routes;
> > @@ -93,6 +121,7 @@ struct mtk_mmsys_driver_data {
> >   const u16 sw0_rst_offset;
> >   const u32 num_resets;
> >   const bool is_vppsys;
> > +const u8 vsync_len;
> >   };
> > 
> >   /*
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> > index 26f3d9a41496..11dda20eb462 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -134,6 +134,22 @@
> >   #define MT8188_MUTEX_MOD_DISP_POSTMASK024
> >   #define MT8188_MUTEX_MOD2_DISP_PWM033
> > 
> > +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA00
> > +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA11
> > +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA22
> > +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA33
> > +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA44
> > +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA55
> > +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA66
> > +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA77
> > +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE020
> > +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE121
> > +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE222
> > +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE323
> > +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE424
> > +#define MT8188_MUTEX_MOD_DISP1_DISP_MIXER30
> > +#define MT8188_MUTEX_MOD_DISP1_DP_INTF139
> > +
> >   #define MT8195_MUTEX_MOD_DISP_OVL00
> >   #define MT8195_MUTEX_MOD_DISP_WDMA01
> >   #define MT8195_MUTEX_MOD_DISP_RDMA02
> > @@ -265,6 +281,7 @@
> >   #define MT8183_MUTEX_SOF_DPI02
> >   #define MT8188_MUTEX_SOF_DSI01
> >   #define MT8188_MUTEX_SOF_DP_INTF03
> > +#define MT8188_MUTEX_SOF_DP_INTF14
> >   #define MT8195_MUTEX_SOF_DSI01
> >   #define MT8195_MUTEX_SOF_DSI12
> >   #define MT8195_MUTEX_SOF_DP_INTF03
> > @@ -276,6 +293,7 @@
> >   #define MT8183_MUTEX_EOF_DPI0(MT8183_MUTEX_SOF_DPI0 << 6)
> >   #define MT8188_MUTEX_EOF_DSI0(MT8188_MUTEX_SOF_DSI0 << 7)
> >   #define MT8188_MUTEX_EOF_DP_INTF0(MT8188_MUTEX_SOF_DP_INTF0 << 7)
> > +#define MT8188_MUTEX_EOF_DP_INTF1(MT8188_MUTEX_SOF_DP_INTF1 << 7)
> >   #define MT8195_MUTEX_EOF_DSI0(MT8195_MUTEX_SOF_DSI0 << 7)
> >   #define MT8195_MUTEX_EOF_DSI1(MT8195_MUTEX_SOF_DSI1 << 7)
> >   #define MT8195_MUTEX_EOF_DP_INTF0(MT8195_MUTEX_SOF_DP_INTF0 << 7)
> > @@ -446,6 +464,21 @@ static const unsigned int
> mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> >   [DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0,
> >   [DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0,
> >   [DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0,
> > +[DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0,
> > +[DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1,
> > +[DDP_COMPONENT_MDP_RDMA2] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA2,
> > +[DDP_COMPONENT_MDP_RDMA3] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA3,
> > +[DDP_COMPONENT_MDP_RDMA4] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA4,
> > +[DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5,
> > +[DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6,
> > +[DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7,
> > +[DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0,
> > +[DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1,
> > +[DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2,
> > +[DDP_COMPONENT_MERGE4] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE3,
> > +[DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER,
> > +[DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4,
> > +[DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1,
> >   };
> > 
> >   static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX]
> = {
> > @@ -606,6 +639,8 @@ static const unsigned int
> mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> >   MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0,
> >   [MUTEX_SOF_DP_INTF0] =
> >   MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0,
> > +[MUTEX_SOF_DP_INTF1] =
> > +MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1,
> >   };
> > 
> >   static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> > --
> > 2.18.0
> > 
> 
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Re: [PATCH v2 08/15] soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys

[Shawn Sung (宋孝謙)]

Thank you for saying that. Will do more in the future.
 
I found two typos in the description.
Will fix them in the next version as well.
(ETDHR -> ETHDR, VSNYC -> VSYNC)

On Wed, 2023-06-14 at 13:21 +0200, AngeloGioacchino Del Regno wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> > - Add register definitions for MT8188
> > - Add VDOSYS1 routing table
> > - Update MUTEX definitions accordingly
> > - Set VSYNC length from 0x40 (default) to 1 since ETHDR is bypassed
> > 
> > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> 
> I love that you added documentation to struct mtk_mmsys_driver_data.
> Good job!
> 
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> 
> > ---
> >   drivers/soc/mediatek/mt8188-mmsys.h | 127
> ++++++++++++++++++++++++++++
> >   drivers/soc/mediatek/mtk-mmsys.c    |  13 +++
> >   drivers/soc/mediatek/mtk-mmsys.h    |  29 +++++++
> >   drivers/soc/mediatek/mtk-mutex.c    |  35 ++++++++
> >   4 files changed, 204 insertions(+)
> > 
> > diff --git a/drivers/soc/mediatek/mt8188-mmsys.h
> b/drivers/soc/mediatek/mt8188-mmsys.h
> > index 448cc3761b43..447afb72d95f 100644
> > --- a/drivers/soc/mediatek/mt8188-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8188-mmsys.h
> > @@ -67,6 +67,57 @@
> >   #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGEBIT(18)
> >   #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0BIT(19)
> > 
> > +#define MT8188_VDO1_SW0_RST_B0x1d0
> > +#define MT8188_VDO1_HDR_TOP_CFG0xd00
> > +#define MT8188_VDO1_MIXER_IN1_ALPHA0xd30
> > +#define MT8188_VDO1_MIXER_IN1_PAD0xd40
> > +#define MT8188_VDO1_MERGE0_ASYNC_CFG_WD0xe30
> > +#define MT8188_VDO1_HDRBE_ASYNC_CFG_WD0xe70
> > +#define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN0xf04
> > +#define MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA01
> > +#define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN0xf08
> > +#define MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA11
> > +#define MT8188_VDO1_DISP_DPI1_SEL_IN0xf10
> > +#define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT0
> > +#define MT8188_VDO1_DISP_DP_INTF0_SEL_IN0xf14
> > +#define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT0
> > +#define MT8188_VDO1_MERGE4_SOUT_SEL0xf18
> > +#define MT8188_MERGE4_SOUT_TO_DPI1_SELBIT(2)
> > +#define MT8188_MERGE4_SOUT_TO_DP_INTF0_SELBIT(3)
> > +#define MT8188_VDO1_MIXER_IN1_SEL_IN0xf24
> > +#define MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT1
> > +#define MT8188_VDO1_MIXER_IN2_SEL_IN0xf28
> > +#define MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT1
> > +#define MT8188_VDO1_MIXER_IN3_SEL_IN0xf2c
> > +#define MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT1
> > +#define MT8188_VDO1_MIXER_IN4_SEL_IN0xf30
> > +#define MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT1
> > +#define MT8188_VDO1_MIXER_OUT_SOUT_SEL0xf34
> > +#define MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL1
> > +#define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN0xf3c
> > +#define MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA21
> > +#define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL0xf40
> > +#define MT8188_SOUT_TO_MIXER_IN1_SEL1
> > +#define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL0xf44
> > +#define MT8188_SOUT_TO_MIXER_IN2_SEL1
> > +#define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL0xf48
> > +#define MT8188_SOUT_TO_MIXER_IN3_SEL1
> > +#define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL0xf4c
> > +#define MT8188_SOUT_TO_MIXER_IN4_SEL1
> > +#define MT8188_VDO1_MERGE4_ASYNC_SEL_IN0xf50
> > +#define MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT1
> > +#define MT8188_VDO1_MIXER_IN1_SOUT_SEL0xf58
> > +#define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER0
> > +#define MT8188_VDO1_MIXER_IN2_SOUT_SEL0xf5c
> > +#define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER0
> > +#define MT8188_VDO1_MIXER_IN3_SOUT_SEL0xf60
> > +#define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER0
> > +#define MT8188_VDO1_MIXER_IN4_SOUT_SEL0xf64
> > +#define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER0
> > +#define MT8188_VDO1_MIXER_SOUT_SEL_IN0xf68
> > +#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER0
> > +#define MT8188_VDO1_MIXER_VSYNC_LEN0xd5c
> > +
> >   static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[]
> = {
> >   {
> >   DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> > @@ -146,4 +197,80 @@ static const struct mtk_mmsys_routes
> mmsys_mt8188_routing_table[] = {
> >   },
> >   };
> > 
> > +static const struct mtk_mmsys_routes
> mmsys_mt8188_vdo1_routing_table[] = {
> > +{
> > +DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
> > +MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
> > +MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
> > +}, {
> > +DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
> > +MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
> > +MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
> > +}, {
> > +DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
> > +MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
> > +MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
> > +}, {
> > +DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
> > +MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
> > +MT8188_SOUT_TO_MIXER_IN1_SEL
> > +}, {
> > +DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
> > +MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
> > +MT8188_SOUT_TO_MIXER_IN2_SEL
> > +}, {
> > +DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
> > +MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
> > +MT8188_SOUT_TO_MIXER_IN3_SEL
> > +}, {
> > +DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
> > +MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
> > +MT8188_SOUT_TO_MIXER_IN4_SEL
> > +}, {
> > +DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> > +MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
> > +MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
> > +}, {
> > +DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
> > +MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
> > +MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
> > +}, {
> > +DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
> > +MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
> > +MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
> > +}, {
> > +DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
> > +MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
> > +MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
> > +}, {
> > +DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
> > +MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
> > +MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
> > +}, {
> > +DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> > +MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
> > +MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
> > +}, {
> > +DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
> > +MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
> > +MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
> > +}, {
> > +DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> > +MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
> > +MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
> > +}, {
> > +DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
> > +MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
> > +MT8188_MERGE4_SOUT_TO_DPI1_SEL
> > +}, {
> > +DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> > +MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
> > +MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
> > +}, {
> > +DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
> > +MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
> > +MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL
> > +}
> > +};
> > +
> >   #endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> > index 9619faa796e8..3a81ef2bcc3c 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -89,6 +89,15 @@ static const struct mtk_mmsys_driver_data
> mt8188_vdosys0_driver_data = {
> >   .num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
> >   };
> > 
> > +static const struct mtk_mmsys_driver_data
> mt8188_vdosys1_driver_data = {
> > +.clk_driver = "clk-mt8188-vdo1",
> > +.routes = mmsys_mt8188_vdo1_routing_table,
> > +.num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table),
> > +.sw0_rst_offset = MT8188_VDO1_SW0_RST_B,
> > +.num_resets = 96,
> > +.vsync_len = 1,
> > +};
> > +
> >   static const struct mtk_mmsys_driver_data
> mt8192_mmsys_driver_data = {
> >   .clk_driver = "clk-mt8192-mm",
> >   .routes = mmsys_mt8192_routing_table,
> > @@ -213,6 +222,9 @@ void mtk_mmsys_mixer_in_config(struct device
> *dev, int idx, bool alpha_sel, u16
> >         alpha_sel << (19 + idx), cmdq_pkt);
> >   mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx -
> 1) * 4,
> >         GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode,
> cmdq_pkt);
> > +if (mmsys->data->vsync_len)
> > +mtk_mmsys_update_bits(mmsys, MT8188_VDO1_MIXER_VSYNC_LEN, ~0,
> > +      mmsys->data->vsync_len, cmdq_pkt);
> >   }
> >   EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);
> > 
> > @@ -431,6 +443,7 @@ static const struct of_device_id
> of_match_mtk_mmsys[] = {
> >   { .compatible = "mediatek,mt8183-mmsys", .data =
> &mt8183_mmsys_driver_data },
> >   { .compatible = "mediatek,mt8186-mmsys", .data =
> &mt8186_mmsys_driver_data },
> >   { .compatible = "mediatek,mt8188-vdosys0", .data =
> &mt8188_vdosys0_driver_data },
> > +{ .compatible = "mediatek,mt8188-vdosys1", .data =
> &mt8188_vdosys1_driver_data },
> >   { .compatible = "mediatek,mt8192-mmsys", .data =
> &mt8192_mmsys_driver_data },
> >   /* "mediatek,mt8195-mmsys" compatible is deprecated */
> >   { .compatible = "mediatek,mt8195-mmsys", .data =
> &mt8195_vdosys0_driver_data },
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> b/drivers/soc/mediatek/mtk-mmsys.h
> > index 6725403d2e3a..e4ab46017430 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -86,6 +86,34 @@ struct mtk_mmsys_routes {
> >   u32 val;
> >   };
> > 
> > +/**
> > + * struct mtk_mmsys_driver_data - settings for the mmsys
> > + * @clk_driver: Clock driver name that the mmsys is using
> > + *              (defined in drivers/clk/mediatek/clk-*.c).
> > + * @routes: Routing table of the mmsys.
> > + *          It provides mux settings from one module to another.
> > + * @num_routes: Array size of the routes.
> > + * @sw0_rst_offset: Register offset for the reset control.
> > + * @num_resets: Number of reset bits that are defined
> > + * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe)
> > + *             or VDOSYS (Video). Only VDOSYS needs to be added to
> drm driver.
> > + * @vsync_len: VSYNC length of the MIXER.
> > + *             VSYNC is usually triggered by the connector, so its
> length is
> > + *             a fixed value as long as the frame rate is decided,
> but ETDHR and
> > + *             MIXER generate their own VSYNC due to hardware
> design, therefore
> > + *             MIXER has to sync with ETHDR by adjusting VSYNC
> length.
> > + *             On MT8195, there is no such setting so we use the
> gap between
> > + *             falling edge and rising edge of SOF (Start of
> Frame) signal to
> > + *             do the job, but since MT8188, VSNYC_LEN setting is
> introduced to
> > + *             solve the problem and is given 0x40 (ticks) as the
> default value.
> > + *             Please notice that this value has to be set to 1
> (minimum) if
> > + *             ETHDR is bypassed, otherwise MIXER could wait too
> long and causing
> > + *             underflow.
> > + *
> > + * Each MMSYS (multi-media system) may have different settings,
> they may use
> > + * different clock sources, mux settings, reset control ...etc.,
> and these
> > + * differences are all stored here.
> > + */
> >   struct mtk_mmsys_driver_data {
> >   const char *clk_driver;
> >   const struct mtk_mmsys_routes *routes;
> > @@ -93,6 +121,7 @@ struct mtk_mmsys_driver_data {
> >   const u16 sw0_rst_offset;
> >   const u32 num_resets;
> >   const bool is_vppsys;
> > +const u8 vsync_len;
> >   };
> > 
> >   /*
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> > index 26f3d9a41496..11dda20eb462 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -134,6 +134,22 @@
> >   #define MT8188_MUTEX_MOD_DISP_POSTMASK024
> >   #define MT8188_MUTEX_MOD2_DISP_PWM033
> > 
> > +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA00
> > +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA11
> > +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA22
> > +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA33
> > +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA44
> > +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA55
> > +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA66
> > +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA77
> > +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE020
> > +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE121
> > +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE222
> > +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE323
> > +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE424
> > +#define MT8188_MUTEX_MOD_DISP1_DISP_MIXER30
> > +#define MT8188_MUTEX_MOD_DISP1_DP_INTF139
> > +
> >   #define MT8195_MUTEX_MOD_DISP_OVL00
> >   #define MT8195_MUTEX_MOD_DISP_WDMA01
> >   #define MT8195_MUTEX_MOD_DISP_RDMA02
> > @@ -265,6 +281,7 @@
> >   #define MT8183_MUTEX_SOF_DPI02
> >   #define MT8188_MUTEX_SOF_DSI01
> >   #define MT8188_MUTEX_SOF_DP_INTF03
> > +#define MT8188_MUTEX_SOF_DP_INTF14
> >   #define MT8195_MUTEX_SOF_DSI01
> >   #define MT8195_MUTEX_SOF_DSI12
> >   #define MT8195_MUTEX_SOF_DP_INTF03
> > @@ -276,6 +293,7 @@
> >   #define MT8183_MUTEX_EOF_DPI0(MT8183_MUTEX_SOF_DPI0 << 6)
> >   #define MT8188_MUTEX_EOF_DSI0(MT8188_MUTEX_SOF_DSI0 << 7)
> >   #define MT8188_MUTEX_EOF_DP_INTF0(MT8188_MUTEX_SOF_DP_INTF0 << 7)
> > +#define MT8188_MUTEX_EOF_DP_INTF1(MT8188_MUTEX_SOF_DP_INTF1 << 7)
> >   #define MT8195_MUTEX_EOF_DSI0(MT8195_MUTEX_SOF_DSI0 << 7)
> >   #define MT8195_MUTEX_EOF_DSI1(MT8195_MUTEX_SOF_DSI1 << 7)
> >   #define MT8195_MUTEX_EOF_DP_INTF0(MT8195_MUTEX_SOF_DP_INTF0 << 7)
> > @@ -446,6 +464,21 @@ static const unsigned int
> mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> >   [DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0,
> >   [DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0,
> >   [DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0,
> > +[DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0,
> > +[DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1,
> > +[DDP_COMPONENT_MDP_RDMA2] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA2,
> > +[DDP_COMPONENT_MDP_RDMA3] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA3,
> > +[DDP_COMPONENT_MDP_RDMA4] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA4,
> > +[DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5,
> > +[DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6,
> > +[DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7,
> > +[DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0,
> > +[DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1,
> > +[DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2,
> > +[DDP_COMPONENT_MERGE4] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE3,
> > +[DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER,
> > +[DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4,
> > +[DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1,
> >   };
> > 
> >   static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX]
> = {
> > @@ -606,6 +639,8 @@ static const unsigned int
> mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> >   MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0,
> >   [MUTEX_SOF_DP_INTF0] =
> >   MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0,
> > +[MUTEX_SOF_DP_INTF1] =
> > +MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1,
> >   };
> > 
> >   static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> > --
> > 2.18.0
> > 
> 

Re: [PATCH v2 08/15] soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys

[AngeloGioacchino Del Regno]

Il 15/06/23 08:10, Shawn Sung (宋孝謙) ha scritto:
> Thank you for saying that. Will do more in the future.
>   
> I found two typos in the description.
> Will fix them in the next version as well.
> (ETDHR -> ETHDR, VSNYC -> VSYNC)
> 

I honestly didn't immediately notice the typos. Yes please fix them.

Keep up the good work!

Regards,
Angelo

> On Wed, 2023-06-14 at 13:21 +0200, AngeloGioacchino Del Regno wrote:
>>   	
>> External email : Please do not click links or open attachments until
>> you have verified the sender or the content.
>>   Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
>>> - Add register definitions for MT8188
>>> - Add VDOSYS1 routing table
>>> - Update MUTEX definitions accordingly
>>> - Set VSYNC length from 0x40 (default) to 1 since ETHDR is bypassed
>>>
>>> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
>>
>> I love that you added documentation to struct mtk_mmsys_driver_data.
>> Good job!
>>
>> Reviewed-by: AngeloGioacchino Del Regno <
>> angelogioacchino.delregno@collabora.com>
>>
>>> ---
>>>    drivers/soc/mediatek/mt8188-mmsys.h | 127
>> ++++++++++++++++++++++++++++
>>>    drivers/soc/mediatek/mtk-mmsys.c    |  13 +++
>>>    drivers/soc/mediatek/mtk-mmsys.h    |  29 +++++++
>>>    drivers/soc/mediatek/mtk-mutex.c    |  35 ++++++++
>>>    4 files changed, 204 insertions(+)
>>>
>>> diff --git a/drivers/soc/mediatek/mt8188-mmsys.h
>> b/drivers/soc/mediatek/mt8188-mmsys.h
>>> index 448cc3761b43..447afb72d95f 100644
>>> --- a/drivers/soc/mediatek/mt8188-mmsys.h
>>> +++ b/drivers/soc/mediatek/mt8188-mmsys.h
>>> @@ -67,6 +67,57 @@
>>>    #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGEBIT(18)
>>>    #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0BIT(19)
>>>
>>> +#define MT8188_VDO1_SW0_RST_B0x1d0
>>> +#define MT8188_VDO1_HDR_TOP_CFG0xd00
>>> +#define MT8188_VDO1_MIXER_IN1_ALPHA0xd30
>>> +#define MT8188_VDO1_MIXER_IN1_PAD0xd40
>>> +#define MT8188_VDO1_MERGE0_ASYNC_CFG_WD0xe30
>>> +#define MT8188_VDO1_HDRBE_ASYNC_CFG_WD0xe70
>>> +#define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN0xf04
>>> +#define MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA01
>>> +#define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN0xf08
>>> +#define MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA11
>>> +#define MT8188_VDO1_DISP_DPI1_SEL_IN0xf10
>>> +#define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT0
>>> +#define MT8188_VDO1_DISP_DP_INTF0_SEL_IN0xf14
>>> +#define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT0
>>> +#define MT8188_VDO1_MERGE4_SOUT_SEL0xf18
>>> +#define MT8188_MERGE4_SOUT_TO_DPI1_SELBIT(2)
>>> +#define MT8188_MERGE4_SOUT_TO_DP_INTF0_SELBIT(3)
>>> +#define MT8188_VDO1_MIXER_IN1_SEL_IN0xf24
>>> +#define MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT1
>>> +#define MT8188_VDO1_MIXER_IN2_SEL_IN0xf28
>>> +#define MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT1
>>> +#define MT8188_VDO1_MIXER_IN3_SEL_IN0xf2c
>>> +#define MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT1
>>> +#define MT8188_VDO1_MIXER_IN4_SEL_IN0xf30
>>> +#define MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT1
>>> +#define MT8188_VDO1_MIXER_OUT_SOUT_SEL0xf34
>>> +#define MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL1
>>> +#define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN0xf3c
>>> +#define MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA21
>>> +#define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL0xf40
>>> +#define MT8188_SOUT_TO_MIXER_IN1_SEL1
>>> +#define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL0xf44
>>> +#define MT8188_SOUT_TO_MIXER_IN2_SEL1
>>> +#define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL0xf48
>>> +#define MT8188_SOUT_TO_MIXER_IN3_SEL1
>>> +#define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL0xf4c
>>> +#define MT8188_SOUT_TO_MIXER_IN4_SEL1
>>> +#define MT8188_VDO1_MERGE4_ASYNC_SEL_IN0xf50
>>> +#define MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT1
>>> +#define MT8188_VDO1_MIXER_IN1_SOUT_SEL0xf58
>>> +#define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER0
>>> +#define MT8188_VDO1_MIXER_IN2_SOUT_SEL0xf5c
>>> +#define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER0
>>> +#define MT8188_VDO1_MIXER_IN3_SOUT_SEL0xf60
>>> +#define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER0
>>> +#define MT8188_VDO1_MIXER_IN4_SOUT_SEL0xf64
>>> +#define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER0
>>> +#define MT8188_VDO1_MIXER_SOUT_SEL_IN0xf68
>>> +#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER0
>>> +#define MT8188_VDO1_MIXER_VSYNC_LEN0xd5c
>>> +
>>>    static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[]
>> = {
>>>    {
>>>    DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
>>> @@ -146,4 +197,80 @@ static const struct mtk_mmsys_routes
>> mmsys_mt8188_routing_table[] = {
>>>    },
>>>    };
>>>
>>> +static const struct mtk_mmsys_routes
>> mmsys_mt8188_vdo1_routing_table[] = {
>>> +{
>>> +DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
>>> +MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
>>> +MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
>>> +}, {
>>> +DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
>>> +MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
>>> +MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
>>> +}, {
>>> +DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
>>> +MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
>>> +MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
>>> +}, {
>>> +DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
>>> +MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
>>> +MT8188_SOUT_TO_MIXER_IN1_SEL
>>> +}, {
>>> +DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
>>> +MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
>>> +MT8188_SOUT_TO_MIXER_IN2_SEL
>>> +}, {
>>> +DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
>>> +MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
>>> +MT8188_SOUT_TO_MIXER_IN3_SEL
>>> +}, {
>>> +DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
>>> +MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
>>> +MT8188_SOUT_TO_MIXER_IN4_SEL
>>> +}, {
>>> +DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
>>> +MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
>>> +MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
>>> +}, {
>>> +DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
>>> +MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
>>> +MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
>>> +}, {
>>> +DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
>>> +MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
>>> +MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
>>> +}, {
>>> +DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
>>> +MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
>>> +MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
>>> +}, {
>>> +DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
>>> +MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
>>> +MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
>>> +}, {
>>> +DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
>>> +MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
>>> +MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
>>> +}, {
>>> +DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
>>> +MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
>>> +MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
>>> +}, {
>>> +DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
>>> +MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
>>> +MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
>>> +}, {
>>> +DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
>>> +MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
>>> +MT8188_MERGE4_SOUT_TO_DPI1_SEL
>>> +}, {
>>> +DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
>>> +MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
>>> +MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
>>> +}, {
>>> +DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
>>> +MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
>>> +MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL
>>> +}
>>> +};
>>> +
>>>    #endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */
>>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
>> b/drivers/soc/mediatek/mtk-mmsys.c
>>> index 9619faa796e8..3a81ef2bcc3c 100644
>>> --- a/drivers/soc/mediatek/mtk-mmsys.c
>>> +++ b/drivers/soc/mediatek/mtk-mmsys.c
>>> @@ -89,6 +89,15 @@ static const struct mtk_mmsys_driver_data
>> mt8188_vdosys0_driver_data = {
>>>    .num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
>>>    };
>>>
>>> +static const struct mtk_mmsys_driver_data
>> mt8188_vdosys1_driver_data = {
>>> +.clk_driver = "clk-mt8188-vdo1",
>>> +.routes = mmsys_mt8188_vdo1_routing_table,
>>> +.num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table),
>>> +.sw0_rst_offset = MT8188_VDO1_SW0_RST_B,
>>> +.num_resets = 96,
>>> +.vsync_len = 1,
>>> +};
>>> +
>>>    static const struct mtk_mmsys_driver_data
>> mt8192_mmsys_driver_data = {
>>>    .clk_driver = "clk-mt8192-mm",
>>>    .routes = mmsys_mt8192_routing_table,
>>> @@ -213,6 +222,9 @@ void mtk_mmsys_mixer_in_config(struct device
>> *dev, int idx, bool alpha_sel, u16
>>>          alpha_sel << (19 + idx), cmdq_pkt);
>>>    mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx -
>> 1) * 4,
>>>          GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode,
>> cmdq_pkt);
>>> +if (mmsys->data->vsync_len)
>>> +mtk_mmsys_update_bits(mmsys, MT8188_VDO1_MIXER_VSYNC_LEN, ~0,
>>> +      mmsys->data->vsync_len, cmdq_pkt);
>>>    }
>>>    EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);
>>>
>>> @@ -431,6 +443,7 @@ static const struct of_device_id
>> of_match_mtk_mmsys[] = {
>>>    { .compatible = "mediatek,mt8183-mmsys", .data =
>> &mt8183_mmsys_driver_data },
>>>    { .compatible = "mediatek,mt8186-mmsys", .data =
>> &mt8186_mmsys_driver_data },
>>>    { .compatible = "mediatek,mt8188-vdosys0", .data =
>> &mt8188_vdosys0_driver_data },
>>> +{ .compatible = "mediatek,mt8188-vdosys1", .data =
>> &mt8188_vdosys1_driver_data },
>>>    { .compatible = "mediatek,mt8192-mmsys", .data =
>> &mt8192_mmsys_driver_data },
>>>    /* "mediatek,mt8195-mmsys" compatible is deprecated */
>>>    { .compatible = "mediatek,mt8195-mmsys", .data =
>> &mt8195_vdosys0_driver_data },
>>> diff --git a/drivers/soc/mediatek/mtk-mmsys.h
>> b/drivers/soc/mediatek/mtk-mmsys.h
>>> index 6725403d2e3a..e4ab46017430 100644
>>> --- a/drivers/soc/mediatek/mtk-mmsys.h
>>> +++ b/drivers/soc/mediatek/mtk-mmsys.h
>>> @@ -86,6 +86,34 @@ struct mtk_mmsys_routes {
>>>    u32 val;
>>>    };
>>>
>>> +/**
>>> + * struct mtk_mmsys_driver_data - settings for the mmsys
>>> + * @clk_driver: Clock driver name that the mmsys is using
>>> + *              (defined in drivers/clk/mediatek/clk-*.c).
>>> + * @routes: Routing table of the mmsys.
>>> + *          It provides mux settings from one module to another.
>>> + * @num_routes: Array size of the routes.
>>> + * @sw0_rst_offset: Register offset for the reset control.
>>> + * @num_resets: Number of reset bits that are defined
>>> + * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe)
>>> + *             or VDOSYS (Video). Only VDOSYS needs to be added to
>> drm driver.
>>> + * @vsync_len: VSYNC length of the MIXER.
>>> + *             VSYNC is usually triggered by the connector, so its
>> length is
>>> + *             a fixed value as long as the frame rate is decided,
>> but ETDHR and
>>> + *             MIXER generate their own VSYNC due to hardware
>> design, therefore
>>> + *             MIXER has to sync with ETHDR by adjusting VSYNC
>> length.
>>> + *             On MT8195, there is no such setting so we use the
>> gap between
>>> + *             falling edge and rising edge of SOF (Start of
>> Frame) signal to
>>> + *             do the job, but since MT8188, VSNYC_LEN setting is
>> introduced to
>>> + *             solve the problem and is given 0x40 (ticks) as the
>> default value.
>>> + *             Please notice that this value has to be set to 1
>> (minimum) if
>>> + *             ETHDR is bypassed, otherwise MIXER could wait too
>> long and causing
>>> + *             underflow.
>>> + *
>>> + * Each MMSYS (multi-media system) may have different settings,
>> they may use
>>> + * different clock sources, mux settings, reset control ...etc.,
>> and these
>>> + * differences are all stored here.
>>> + */
>>>    struct mtk_mmsys_driver_data {
>>>    const char *clk_driver;
>>>    const struct mtk_mmsys_routes *routes;
>>> @@ -93,6 +121,7 @@ struct mtk_mmsys_driver_data {
>>>    const u16 sw0_rst_offset;
>>>    const u32 num_resets;
>>>    const bool is_vppsys;
>>> +const u8 vsync_len;
>>>    };
>>>
>>>    /*
>>> diff --git a/drivers/soc/mediatek/mtk-mutex.c
>> b/drivers/soc/mediatek/mtk-mutex.c
>>> index 26f3d9a41496..11dda20eb462 100644
>>> --- a/drivers/soc/mediatek/mtk-mutex.c
>>> +++ b/drivers/soc/mediatek/mtk-mutex.c
>>> @@ -134,6 +134,22 @@
>>>    #define MT8188_MUTEX_MOD_DISP_POSTMASK024
>>>    #define MT8188_MUTEX_MOD2_DISP_PWM033
>>>
>>> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA00
>>> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA11
>>> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA22
>>> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA33
>>> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA44
>>> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA55
>>> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA66
>>> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA77
>>> +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE020
>>> +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE121
>>> +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE222
>>> +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE323
>>> +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE424
>>> +#define MT8188_MUTEX_MOD_DISP1_DISP_MIXER30
>>> +#define MT8188_MUTEX_MOD_DISP1_DP_INTF139
>>> +
>>>    #define MT8195_MUTEX_MOD_DISP_OVL00
>>>    #define MT8195_MUTEX_MOD_DISP_WDMA01
>>>    #define MT8195_MUTEX_MOD_DISP_RDMA02
>>> @@ -265,6 +281,7 @@
>>>    #define MT8183_MUTEX_SOF_DPI02
>>>    #define MT8188_MUTEX_SOF_DSI01
>>>    #define MT8188_MUTEX_SOF_DP_INTF03
>>> +#define MT8188_MUTEX_SOF_DP_INTF14
>>>    #define MT8195_MUTEX_SOF_DSI01
>>>    #define MT8195_MUTEX_SOF_DSI12
>>>    #define MT8195_MUTEX_SOF_DP_INTF03
>>> @@ -276,6 +293,7 @@
>>>    #define MT8183_MUTEX_EOF_DPI0(MT8183_MUTEX_SOF_DPI0 << 6)
>>>    #define MT8188_MUTEX_EOF_DSI0(MT8188_MUTEX_SOF_DSI0 << 7)
>>>    #define MT8188_MUTEX_EOF_DP_INTF0(MT8188_MUTEX_SOF_DP_INTF0 << 7)
>>> +#define MT8188_MUTEX_EOF_DP_INTF1(MT8188_MUTEX_SOF_DP_INTF1 << 7)
>>>    #define MT8195_MUTEX_EOF_DSI0(MT8195_MUTEX_SOF_DSI0 << 7)
>>>    #define MT8195_MUTEX_EOF_DSI1(MT8195_MUTEX_SOF_DSI1 << 7)
>>>    #define MT8195_MUTEX_EOF_DP_INTF0(MT8195_MUTEX_SOF_DP_INTF0 << 7)
>>> @@ -446,6 +464,21 @@ static const unsigned int
>> mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
>>>    [DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0,
>>>    [DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0,
>>>    [DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0,
>>> +[DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0,
>>> +[DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1,
>>> +[DDP_COMPONENT_MDP_RDMA2] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA2,
>>> +[DDP_COMPONENT_MDP_RDMA3] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA3,
>>> +[DDP_COMPONENT_MDP_RDMA4] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA4,
>>> +[DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5,
>>> +[DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6,
>>> +[DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7,
>>> +[DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0,
>>> +[DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1,
>>> +[DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2,
>>> +[DDP_COMPONENT_MERGE4] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE3,
>>> +[DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER,
>>> +[DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4,
>>> +[DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1,
>>>    };
>>>
>>>    static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX]
>> = {
>>> @@ -606,6 +639,8 @@ static const unsigned int
>> mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = {
>>>    MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0,
>>>    [MUTEX_SOF_DP_INTF0] =
>>>    MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0,
>>> +[MUTEX_SOF_DP_INTF1] =
>>> +MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1,
>>>    };
>>>
>>>    static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
>>> --
>>> 2.18.0
>>>
>>


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Re: [PATCH v2 08/15] soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys

[AngeloGioacchino Del Regno]

Il 15/06/23 08:10, Shawn Sung (宋孝謙) ha scritto:
> Thank you for saying that. Will do more in the future.
>   
> I found two typos in the description.
> Will fix them in the next version as well.
> (ETDHR -> ETHDR, VSNYC -> VSYNC)
> 

I honestly didn't immediately notice the typos. Yes please fix them.

Keep up the good work!

Regards,
Angelo

> On Wed, 2023-06-14 at 13:21 +0200, AngeloGioacchino Del Regno wrote:
>>   	
>> External email : Please do not click links or open attachments until
>> you have verified the sender or the content.
>>   Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
>>> - Add register definitions for MT8188
>>> - Add VDOSYS1 routing table
>>> - Update MUTEX definitions accordingly
>>> - Set VSYNC length from 0x40 (default) to 1 since ETHDR is bypassed
>>>
>>> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
>>
>> I love that you added documentation to struct mtk_mmsys_driver_data.
>> Good job!
>>
>> Reviewed-by: AngeloGioacchino Del Regno <
>> angelogioacchino.delregno@collabora.com>
>>
>>> ---
>>>    drivers/soc/mediatek/mt8188-mmsys.h | 127
>> ++++++++++++++++++++++++++++
>>>    drivers/soc/mediatek/mtk-mmsys.c    |  13 +++
>>>    drivers/soc/mediatek/mtk-mmsys.h    |  29 +++++++
>>>    drivers/soc/mediatek/mtk-mutex.c    |  35 ++++++++
>>>    4 files changed, 204 insertions(+)
>>>
>>> diff --git a/drivers/soc/mediatek/mt8188-mmsys.h
>> b/drivers/soc/mediatek/mt8188-mmsys.h
>>> index 448cc3761b43..447afb72d95f 100644
>>> --- a/drivers/soc/mediatek/mt8188-mmsys.h
>>> +++ b/drivers/soc/mediatek/mt8188-mmsys.h
>>> @@ -67,6 +67,57 @@
>>>    #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGEBIT(18)
>>>    #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0BIT(19)
>>>
>>> +#define MT8188_VDO1_SW0_RST_B0x1d0
>>> +#define MT8188_VDO1_HDR_TOP_CFG0xd00
>>> +#define MT8188_VDO1_MIXER_IN1_ALPHA0xd30
>>> +#define MT8188_VDO1_MIXER_IN1_PAD0xd40
>>> +#define MT8188_VDO1_MERGE0_ASYNC_CFG_WD0xe30
>>> +#define MT8188_VDO1_HDRBE_ASYNC_CFG_WD0xe70
>>> +#define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN0xf04
>>> +#define MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA01
>>> +#define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN0xf08
>>> +#define MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA11
>>> +#define MT8188_VDO1_DISP_DPI1_SEL_IN0xf10
>>> +#define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT0
>>> +#define MT8188_VDO1_DISP_DP_INTF0_SEL_IN0xf14
>>> +#define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT0
>>> +#define MT8188_VDO1_MERGE4_SOUT_SEL0xf18
>>> +#define MT8188_MERGE4_SOUT_TO_DPI1_SELBIT(2)
>>> +#define MT8188_MERGE4_SOUT_TO_DP_INTF0_SELBIT(3)
>>> +#define MT8188_VDO1_MIXER_IN1_SEL_IN0xf24
>>> +#define MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT1
>>> +#define MT8188_VDO1_MIXER_IN2_SEL_IN0xf28
>>> +#define MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT1
>>> +#define MT8188_VDO1_MIXER_IN3_SEL_IN0xf2c
>>> +#define MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT1
>>> +#define MT8188_VDO1_MIXER_IN4_SEL_IN0xf30
>>> +#define MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT1
>>> +#define MT8188_VDO1_MIXER_OUT_SOUT_SEL0xf34
>>> +#define MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL1
>>> +#define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN0xf3c
>>> +#define MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA21
>>> +#define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL0xf40
>>> +#define MT8188_SOUT_TO_MIXER_IN1_SEL1
>>> +#define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL0xf44
>>> +#define MT8188_SOUT_TO_MIXER_IN2_SEL1
>>> +#define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL0xf48
>>> +#define MT8188_SOUT_TO_MIXER_IN3_SEL1
>>> +#define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL0xf4c
>>> +#define MT8188_SOUT_TO_MIXER_IN4_SEL1
>>> +#define MT8188_VDO1_MERGE4_ASYNC_SEL_IN0xf50
>>> +#define MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT1
>>> +#define MT8188_VDO1_MIXER_IN1_SOUT_SEL0xf58
>>> +#define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER0
>>> +#define MT8188_VDO1_MIXER_IN2_SOUT_SEL0xf5c
>>> +#define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER0
>>> +#define MT8188_VDO1_MIXER_IN3_SOUT_SEL0xf60
>>> +#define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER0
>>> +#define MT8188_VDO1_MIXER_IN4_SOUT_SEL0xf64
>>> +#define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER0
>>> +#define MT8188_VDO1_MIXER_SOUT_SEL_IN0xf68
>>> +#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER0
>>> +#define MT8188_VDO1_MIXER_VSYNC_LEN0xd5c
>>> +
>>>    static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[]
>> = {
>>>    {
>>>    DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
>>> @@ -146,4 +197,80 @@ static const struct mtk_mmsys_routes
>> mmsys_mt8188_routing_table[] = {
>>>    },
>>>    };
>>>
>>> +static const struct mtk_mmsys_routes
>> mmsys_mt8188_vdo1_routing_table[] = {
>>> +{
>>> +DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
>>> +MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
>>> +MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
>>> +}, {
>>> +DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
>>> +MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
>>> +MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
>>> +}, {
>>> +DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
>>> +MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
>>> +MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
>>> +}, {
>>> +DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
>>> +MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
>>> +MT8188_SOUT_TO_MIXER_IN1_SEL
>>> +}, {
>>> +DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
>>> +MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
>>> +MT8188_SOUT_TO_MIXER_IN2_SEL
>>> +}, {
>>> +DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
>>> +MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
>>> +MT8188_SOUT_TO_MIXER_IN3_SEL
>>> +}, {
>>> +DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
>>> +MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
>>> +MT8188_SOUT_TO_MIXER_IN4_SEL
>>> +}, {
>>> +DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
>>> +MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
>>> +MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
>>> +}, {
>>> +DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
>>> +MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
>>> +MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
>>> +}, {
>>> +DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
>>> +MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
>>> +MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
>>> +}, {
>>> +DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
>>> +MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
>>> +MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
>>> +}, {
>>> +DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
>>> +MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
>>> +MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
>>> +}, {
>>> +DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
>>> +MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
>>> +MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
>>> +}, {
>>> +DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
>>> +MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
>>> +MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
>>> +}, {
>>> +DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
>>> +MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
>>> +MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
>>> +}, {
>>> +DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
>>> +MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
>>> +MT8188_MERGE4_SOUT_TO_DPI1_SEL
>>> +}, {
>>> +DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
>>> +MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
>>> +MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
>>> +}, {
>>> +DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
>>> +MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
>>> +MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL
>>> +}
>>> +};
>>> +
>>>    #endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */
>>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
>> b/drivers/soc/mediatek/mtk-mmsys.c
>>> index 9619faa796e8..3a81ef2bcc3c 100644
>>> --- a/drivers/soc/mediatek/mtk-mmsys.c
>>> +++ b/drivers/soc/mediatek/mtk-mmsys.c
>>> @@ -89,6 +89,15 @@ static const struct mtk_mmsys_driver_data
>> mt8188_vdosys0_driver_data = {
>>>    .num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
>>>    };
>>>
>>> +static const struct mtk_mmsys_driver_data
>> mt8188_vdosys1_driver_data = {
>>> +.clk_driver = "clk-mt8188-vdo1",
>>> +.routes = mmsys_mt8188_vdo1_routing_table,
>>> +.num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table),
>>> +.sw0_rst_offset = MT8188_VDO1_SW0_RST_B,
>>> +.num_resets = 96,
>>> +.vsync_len = 1,
>>> +};
>>> +
>>>    static const struct mtk_mmsys_driver_data
>> mt8192_mmsys_driver_data = {
>>>    .clk_driver = "clk-mt8192-mm",
>>>    .routes = mmsys_mt8192_routing_table,
>>> @@ -213,6 +222,9 @@ void mtk_mmsys_mixer_in_config(struct device
>> *dev, int idx, bool alpha_sel, u16
>>>          alpha_sel << (19 + idx), cmdq_pkt);
>>>    mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx -
>> 1) * 4,
>>>          GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode,
>> cmdq_pkt);
>>> +if (mmsys->data->vsync_len)
>>> +mtk_mmsys_update_bits(mmsys, MT8188_VDO1_MIXER_VSYNC_LEN, ~0,
>>> +      mmsys->data->vsync_len, cmdq_pkt);
>>>    }
>>>    EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);
>>>
>>> @@ -431,6 +443,7 @@ static const struct of_device_id
>> of_match_mtk_mmsys[] = {
>>>    { .compatible = "mediatek,mt8183-mmsys", .data =
>> &mt8183_mmsys_driver_data },
>>>    { .compatible = "mediatek,mt8186-mmsys", .data =
>> &mt8186_mmsys_driver_data },
>>>    { .compatible = "mediatek,mt8188-vdosys0", .data =
>> &mt8188_vdosys0_driver_data },
>>> +{ .compatible = "mediatek,mt8188-vdosys1", .data =
>> &mt8188_vdosys1_driver_data },
>>>    { .compatible = "mediatek,mt8192-mmsys", .data =
>> &mt8192_mmsys_driver_data },
>>>    /* "mediatek,mt8195-mmsys" compatible is deprecated */
>>>    { .compatible = "mediatek,mt8195-mmsys", .data =
>> &mt8195_vdosys0_driver_data },
>>> diff --git a/drivers/soc/mediatek/mtk-mmsys.h
>> b/drivers/soc/mediatek/mtk-mmsys.h
>>> index 6725403d2e3a..e4ab46017430 100644
>>> --- a/drivers/soc/mediatek/mtk-mmsys.h
>>> +++ b/drivers/soc/mediatek/mtk-mmsys.h
>>> @@ -86,6 +86,34 @@ struct mtk_mmsys_routes {
>>>    u32 val;
>>>    };
>>>
>>> +/**
>>> + * struct mtk_mmsys_driver_data - settings for the mmsys
>>> + * @clk_driver: Clock driver name that the mmsys is using
>>> + *              (defined in drivers/clk/mediatek/clk-*.c).
>>> + * @routes: Routing table of the mmsys.
>>> + *          It provides mux settings from one module to another.
>>> + * @num_routes: Array size of the routes.
>>> + * @sw0_rst_offset: Register offset for the reset control.
>>> + * @num_resets: Number of reset bits that are defined
>>> + * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe)
>>> + *             or VDOSYS (Video). Only VDOSYS needs to be added to
>> drm driver.
>>> + * @vsync_len: VSYNC length of the MIXER.
>>> + *             VSYNC is usually triggered by the connector, so its
>> length is
>>> + *             a fixed value as long as the frame rate is decided,
>> but ETDHR and
>>> + *             MIXER generate their own VSYNC due to hardware
>> design, therefore
>>> + *             MIXER has to sync with ETHDR by adjusting VSYNC
>> length.
>>> + *             On MT8195, there is no such setting so we use the
>> gap between
>>> + *             falling edge and rising edge of SOF (Start of
>> Frame) signal to
>>> + *             do the job, but since MT8188, VSNYC_LEN setting is
>> introduced to
>>> + *             solve the problem and is given 0x40 (ticks) as the
>> default value.
>>> + *             Please notice that this value has to be set to 1
>> (minimum) if
>>> + *             ETHDR is bypassed, otherwise MIXER could wait too
>> long and causing
>>> + *             underflow.
>>> + *
>>> + * Each MMSYS (multi-media system) may have different settings,
>> they may use
>>> + * different clock sources, mux settings, reset control ...etc.,
>> and these
>>> + * differences are all stored here.
>>> + */
>>>    struct mtk_mmsys_driver_data {
>>>    const char *clk_driver;
>>>    const struct mtk_mmsys_routes *routes;
>>> @@ -93,6 +121,7 @@ struct mtk_mmsys_driver_data {
>>>    const u16 sw0_rst_offset;
>>>    const u32 num_resets;
>>>    const bool is_vppsys;
>>> +const u8 vsync_len;
>>>    };
>>>
>>>    /*
>>> diff --git a/drivers/soc/mediatek/mtk-mutex.c
>> b/drivers/soc/mediatek/mtk-mutex.c
>>> index 26f3d9a41496..11dda20eb462 100644
>>> --- a/drivers/soc/mediatek/mtk-mutex.c
>>> +++ b/drivers/soc/mediatek/mtk-mutex.c
>>> @@ -134,6 +134,22 @@
>>>    #define MT8188_MUTEX_MOD_DISP_POSTMASK024
>>>    #define MT8188_MUTEX_MOD2_DISP_PWM033
>>>
>>> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA00
>>> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA11
>>> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA22
>>> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA33
>>> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA44
>>> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA55
>>> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA66
>>> +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA77
>>> +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE020
>>> +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE121
>>> +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE222
>>> +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE323
>>> +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE424
>>> +#define MT8188_MUTEX_MOD_DISP1_DISP_MIXER30
>>> +#define MT8188_MUTEX_MOD_DISP1_DP_INTF139
>>> +
>>>    #define MT8195_MUTEX_MOD_DISP_OVL00
>>>    #define MT8195_MUTEX_MOD_DISP_WDMA01
>>>    #define MT8195_MUTEX_MOD_DISP_RDMA02
>>> @@ -265,6 +281,7 @@
>>>    #define MT8183_MUTEX_SOF_DPI02
>>>    #define MT8188_MUTEX_SOF_DSI01
>>>    #define MT8188_MUTEX_SOF_DP_INTF03
>>> +#define MT8188_MUTEX_SOF_DP_INTF14
>>>    #define MT8195_MUTEX_SOF_DSI01
>>>    #define MT8195_MUTEX_SOF_DSI12
>>>    #define MT8195_MUTEX_SOF_DP_INTF03
>>> @@ -276,6 +293,7 @@
>>>    #define MT8183_MUTEX_EOF_DPI0(MT8183_MUTEX_SOF_DPI0 << 6)
>>>    #define MT8188_MUTEX_EOF_DSI0(MT8188_MUTEX_SOF_DSI0 << 7)
>>>    #define MT8188_MUTEX_EOF_DP_INTF0(MT8188_MUTEX_SOF_DP_INTF0 << 7)
>>> +#define MT8188_MUTEX_EOF_DP_INTF1(MT8188_MUTEX_SOF_DP_INTF1 << 7)
>>>    #define MT8195_MUTEX_EOF_DSI0(MT8195_MUTEX_SOF_DSI0 << 7)
>>>    #define MT8195_MUTEX_EOF_DSI1(MT8195_MUTEX_SOF_DSI1 << 7)
>>>    #define MT8195_MUTEX_EOF_DP_INTF0(MT8195_MUTEX_SOF_DP_INTF0 << 7)
>>> @@ -446,6 +464,21 @@ static const unsigned int
>> mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
>>>    [DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0,
>>>    [DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0,
>>>    [DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0,
>>> +[DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0,
>>> +[DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1,
>>> +[DDP_COMPONENT_MDP_RDMA2] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA2,
>>> +[DDP_COMPONENT_MDP_RDMA3] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA3,
>>> +[DDP_COMPONENT_MDP_RDMA4] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA4,
>>> +[DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5,
>>> +[DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6,
>>> +[DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7,
>>> +[DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0,
>>> +[DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1,
>>> +[DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2,
>>> +[DDP_COMPONENT_MERGE4] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE3,
>>> +[DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER,
>>> +[DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4,
>>> +[DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1,
>>>    };
>>>
>>>    static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX]
>> = {
>>> @@ -606,6 +639,8 @@ static const unsigned int
>> mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = {
>>>    MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0,
>>>    [MUTEX_SOF_DP_INTF0] =
>>>    MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0,
>>> +[MUTEX_SOF_DP_INTF1] =
>>> +MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1,
>>>    };
>>>
>>>    static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
>>> --
>>> 2.18.0
>>>
>>

[PATCH v2 09/15] soc: mediatek: Support MT8188 VDOSYS1 PADDING in mtk-mmsys

[Hsiao Chien Sung]

- Add PADDING components
- Add MUTEX definitions for PADDING

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/soc/mediatek/mtk-mutex.c       | 16 ++++++++++++++++
 include/linux/soc/mediatek/mtk-mmsys.h |  8 ++++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 11dda20eb462..6031c7012f22 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -142,6 +142,14 @@
 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5	5
 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6	6
 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7	7
+#define MT8188_MUTEX_MOD_DISP1_PADDING0		8
+#define MT8188_MUTEX_MOD_DISP1_PADDING1		9
+#define MT8188_MUTEX_MOD_DISP1_PADDING2		10
+#define MT8188_MUTEX_MOD_DISP1_PADDING3		11
+#define MT8188_MUTEX_MOD_DISP1_PADDING4		12
+#define MT8188_MUTEX_MOD_DISP1_PADDING5		13
+#define MT8188_MUTEX_MOD_DISP1_PADDING6		14
+#define MT8188_MUTEX_MOD_DISP1_PADDING7		15
 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0	20
 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1	21
 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2	22
@@ -472,6 +480,14 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5,
 	[DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6,
 	[DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7,
+	[DDP_COMPONENT_PADDING0] = MT8188_MUTEX_MOD_DISP1_PADDING0,
+	[DDP_COMPONENT_PADDING1] = MT8188_MUTEX_MOD_DISP1_PADDING1,
+	[DDP_COMPONENT_PADDING2] = MT8188_MUTEX_MOD_DISP1_PADDING2,
+	[DDP_COMPONENT_PADDING3] = MT8188_MUTEX_MOD_DISP1_PADDING3,
+	[DDP_COMPONENT_PADDING4] = MT8188_MUTEX_MOD_DISP1_PADDING4,
+	[DDP_COMPONENT_PADDING5] = MT8188_MUTEX_MOD_DISP1_PADDING5,
+	[DDP_COMPONENT_PADDING6] = MT8188_MUTEX_MOD_DISP1_PADDING6,
+	[DDP_COMPONENT_PADDING7] = MT8188_MUTEX_MOD_DISP1_PADDING7,
 	[DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0,
 	[DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1,
 	[DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 37544ea6286d..2584c1159d8d 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -50,6 +50,14 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_MDP_RDMA5,
 	DDP_COMPONENT_MDP_RDMA6,
 	DDP_COMPONENT_MDP_RDMA7,
+	DDP_COMPONENT_PADDING0,
+	DDP_COMPONENT_PADDING1,
+	DDP_COMPONENT_PADDING2,
+	DDP_COMPONENT_PADDING3,
+	DDP_COMPONENT_PADDING4,
+	DDP_COMPONENT_PADDING5,
+	DDP_COMPONENT_PADDING6,
+	DDP_COMPONENT_PADDING7,
 	DDP_COMPONENT_MERGE0,
 	DDP_COMPONENT_MERGE1,
 	DDP_COMPONENT_MERGE2,
--
2.18.0


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[PATCH v2 09/15] soc: mediatek: Support MT8188 VDOSYS1 PADDING in mtk-mmsys

[Hsiao Chien Sung]

- Add PADDING components
- Add MUTEX definitions for PADDING

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/soc/mediatek/mtk-mutex.c       | 16 ++++++++++++++++
 include/linux/soc/mediatek/mtk-mmsys.h |  8 ++++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 11dda20eb462..6031c7012f22 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -142,6 +142,14 @@
 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5	5
 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6	6
 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7	7
+#define MT8188_MUTEX_MOD_DISP1_PADDING0		8
+#define MT8188_MUTEX_MOD_DISP1_PADDING1		9
+#define MT8188_MUTEX_MOD_DISP1_PADDING2		10
+#define MT8188_MUTEX_MOD_DISP1_PADDING3		11
+#define MT8188_MUTEX_MOD_DISP1_PADDING4		12
+#define MT8188_MUTEX_MOD_DISP1_PADDING5		13
+#define MT8188_MUTEX_MOD_DISP1_PADDING6		14
+#define MT8188_MUTEX_MOD_DISP1_PADDING7		15
 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0	20
 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1	21
 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2	22
@@ -472,6 +480,14 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5,
 	[DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6,
 	[DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7,
+	[DDP_COMPONENT_PADDING0] = MT8188_MUTEX_MOD_DISP1_PADDING0,
+	[DDP_COMPONENT_PADDING1] = MT8188_MUTEX_MOD_DISP1_PADDING1,
+	[DDP_COMPONENT_PADDING2] = MT8188_MUTEX_MOD_DISP1_PADDING2,
+	[DDP_COMPONENT_PADDING3] = MT8188_MUTEX_MOD_DISP1_PADDING3,
+	[DDP_COMPONENT_PADDING4] = MT8188_MUTEX_MOD_DISP1_PADDING4,
+	[DDP_COMPONENT_PADDING5] = MT8188_MUTEX_MOD_DISP1_PADDING5,
+	[DDP_COMPONENT_PADDING6] = MT8188_MUTEX_MOD_DISP1_PADDING6,
+	[DDP_COMPONENT_PADDING7] = MT8188_MUTEX_MOD_DISP1_PADDING7,
 	[DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0,
 	[DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1,
 	[DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 37544ea6286d..2584c1159d8d 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -50,6 +50,14 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_MDP_RDMA5,
 	DDP_COMPONENT_MDP_RDMA6,
 	DDP_COMPONENT_MDP_RDMA7,
+	DDP_COMPONENT_PADDING0,
+	DDP_COMPONENT_PADDING1,
+	DDP_COMPONENT_PADDING2,
+	DDP_COMPONENT_PADDING3,
+	DDP_COMPONENT_PADDING4,
+	DDP_COMPONENT_PADDING5,
+	DDP_COMPONENT_PADDING6,
+	DDP_COMPONENT_PADDING7,
 	DDP_COMPONENT_MERGE0,
 	DDP_COMPONENT_MERGE1,
 	DDP_COMPONENT_MERGE2,
--
2.18.0

Re: [PATCH v2 09/15] soc: mediatek: Support MT8188 VDOSYS1 PADDING in mtk-mmsys

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> - Add PADDING components
> - Add MUTEX definitions for PADDING
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>



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Re: [PATCH v2 09/15] soc: mediatek: Support MT8188 VDOSYS1 PADDING in mtk-mmsys

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> - Add PADDING components
> - Add MUTEX definitions for PADDING
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

[PATCH v2 10/15] soc: mediatek: Support reset bit mapping in mmsys driver

[Hsiao Chien Sung]

- Reset ID must starts from 0 and be consecutive, but
  the reset bits in our hardware design is not continuous,
  some bits are left unused, we need a map to solve the problem
- Use old style 1-to-1 mapping if .rst_tb is not defined

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/soc/mediatek/mtk-mmsys.c | 9 +++++++++
 drivers/soc/mediatek/mtk-mmsys.h | 1 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 3a81ef2bcc3c..13249658721f 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -314,6 +314,15 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
 	u32 offset;
 	u32 reg;

+	if (mmsys->data->rst_tb) {
+		if (id >= mmsys->data->num_resets) {
+			dev_err(rcdev->dev, "Invalid reset ID: %lu (>=%u)\n",
+				id, mmsys->data->num_resets);
+			return -EINVAL;
+		}
+		id = mmsys->data->rst_tb[id];
+	}
+
 	offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
 	id = id % MMSYS_SW_RESET_PER_REG;
 	reg = mmsys->data->sw0_rst_offset + offset;
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index e4ab46017430..e18b355527de 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -119,6 +119,7 @@ struct mtk_mmsys_driver_data {
 	const struct mtk_mmsys_routes *routes;
 	const unsigned int num_routes;
 	const u16 sw0_rst_offset;
+	const u8 *rst_tb;
 	const u32 num_resets;
 	const bool is_vppsys;
 	const u8 vsync_len;
--
2.18.0


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[PATCH v2 10/15] soc: mediatek: Support reset bit mapping in mmsys driver

[Hsiao Chien Sung]

- Reset ID must starts from 0 and be consecutive, but
  the reset bits in our hardware design is not continuous,
  some bits are left unused, we need a map to solve the problem
- Use old style 1-to-1 mapping if .rst_tb is not defined

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/soc/mediatek/mtk-mmsys.c | 9 +++++++++
 drivers/soc/mediatek/mtk-mmsys.h | 1 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 3a81ef2bcc3c..13249658721f 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -314,6 +314,15 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
 	u32 offset;
 	u32 reg;

+	if (mmsys->data->rst_tb) {
+		if (id >= mmsys->data->num_resets) {
+			dev_err(rcdev->dev, "Invalid reset ID: %lu (>=%u)\n",
+				id, mmsys->data->num_resets);
+			return -EINVAL;
+		}
+		id = mmsys->data->rst_tb[id];
+	}
+
 	offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
 	id = id % MMSYS_SW_RESET_PER_REG;
 	reg = mmsys->data->sw0_rst_offset + offset;
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index e4ab46017430..e18b355527de 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -119,6 +119,7 @@ struct mtk_mmsys_driver_data {
 	const struct mtk_mmsys_routes *routes;
 	const unsigned int num_routes;
 	const u16 sw0_rst_offset;
+	const u8 *rst_tb;
 	const u32 num_resets;
 	const bool is_vppsys;
 	const u8 vsync_len;
--
2.18.0

Re: [PATCH v2 10/15] soc: mediatek: Support reset bit mapping in mmsys driver

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> - Reset ID must starts from 0 and be consecutive, but
>    the reset bits in our hardware design is not continuous,
>    some bits are left unused, we need a map to solve the problem
> - Use old style 1-to-1 mapping if .rst_tb is not defined
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>



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Re: [PATCH v2 10/15] soc: mediatek: Support reset bit mapping in mmsys driver

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> - Reset ID must starts from 0 and be consecutive, but
>    the reset bits in our hardware design is not continuous,
>    some bits are left unused, we need a map to solve the problem
> - Use old style 1-to-1 mapping if .rst_tb is not defined
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

[PATCH v2 11/15] soc: mediatek: Add MT8188 VDO0 reset bit map

[Hsiao Chien Sung]

Add MT8188 VDO0 reset bit map.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/soc/mediatek/mt8188-mmsys.h | 26 ++++++++++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c    |  3 +++
 2 files changed, 29 insertions(+)

diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
index 447afb72d95f..c3e3c5cfe931 100644
--- a/drivers/soc/mediatek/mt8188-mmsys.h
+++ b/drivers/soc/mediatek/mt8188-mmsys.h
@@ -3,6 +3,10 @@
 #ifndef __SOC_MEDIATEK_MT8188_MMSYS_H
 #define __SOC_MEDIATEK_MT8188_MMSYS_H

+#include <dt-bindings/reset/mt8188-resets.h>
+
+#define MT8188_VDO0_SW0_RST_B				0x190
+
 #define MT8188_VDO0_OVL_MOUT_EN				0xf14
 #define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0		BIT(0)
 #define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0		BIT(1)
@@ -118,6 +122,28 @@
 #define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER		0
 #define MT8188_VDO1_MIXER_VSYNC_LEN				0xd5c

+static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
+	[MT8188_VDO0_RST_DISP_OVL0]	= 0,
+	[MT8188_VDO0_RST_FAKE_ENG0]	= 2,
+	[MT8188_VDO0_RST_DISP_CCORR0]	= 4,
+	[MT8188_VDO0_RST_DISP_MUTEX0]	= 6,
+	[MT8188_VDO0_RST_DISP_GAMMA0]	= 8,
+	[MT8188_VDO0_RST_DISP_DITHER0]	= 10,
+	[MT8188_VDO0_RST_DISP_WDMA0]	= 17,
+	[MT8188_VDO0_RST_DISP_RDMA0]	= 19,
+	[MT8188_VDO0_RST_DSI0]		= 21,
+	[MT8188_VDO0_RST_DSI1]		= 22,
+	[MT8188_VDO0_RST_DSC_WRAP0]	= 23,
+	[MT8188_VDO0_RST_VPP_MERGE0]	= 24,
+	[MT8188_VDO0_RST_DP_INTF0]	= 25,
+	[MT8188_VDO0_RST_DISP_AAL0]	= 26,
+	[MT8188_VDO0_RST_INLINEROT0]	= 27,
+	[MT8188_VDO0_RST_APB_BUS]	= 28,
+	[MT8188_VDO0_RST_DISP_COLOR0]	= 29,
+	[MT8188_VDO0_RST_MDP_WROT0]	= 30,
+	[MT8188_VDO0_RST_DISP_RSZ0]	= 31,
+};
+
 static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
 	{
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 13249658721f..88029500ed4d 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -87,6 +87,9 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
 	.clk_driver = "clk-mt8188-vdo0",
 	.routes = mmsys_mt8188_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
+	.sw0_rst_offset = MT8188_VDO0_SW0_RST_B,
+	.rst_tb = mmsys_mt8188_vdo0_rst_tb,
+	.num_resets = ARRAY_SIZE(mmsys_mt8188_vdo0_rst_tb),
 };

 static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
--
2.18.0


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[PATCH v2 11/15] soc: mediatek: Add MT8188 VDO0 reset bit map

[Hsiao Chien Sung]

Add MT8188 VDO0 reset bit map.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/soc/mediatek/mt8188-mmsys.h | 26 ++++++++++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c    |  3 +++
 2 files changed, 29 insertions(+)

diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
index 447afb72d95f..c3e3c5cfe931 100644
--- a/drivers/soc/mediatek/mt8188-mmsys.h
+++ b/drivers/soc/mediatek/mt8188-mmsys.h
@@ -3,6 +3,10 @@
 #ifndef __SOC_MEDIATEK_MT8188_MMSYS_H
 #define __SOC_MEDIATEK_MT8188_MMSYS_H

+#include <dt-bindings/reset/mt8188-resets.h>
+
+#define MT8188_VDO0_SW0_RST_B				0x190
+
 #define MT8188_VDO0_OVL_MOUT_EN				0xf14
 #define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0		BIT(0)
 #define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0		BIT(1)
@@ -118,6 +122,28 @@
 #define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER		0
 #define MT8188_VDO1_MIXER_VSYNC_LEN				0xd5c

+static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
+	[MT8188_VDO0_RST_DISP_OVL0]	= 0,
+	[MT8188_VDO0_RST_FAKE_ENG0]	= 2,
+	[MT8188_VDO0_RST_DISP_CCORR0]	= 4,
+	[MT8188_VDO0_RST_DISP_MUTEX0]	= 6,
+	[MT8188_VDO0_RST_DISP_GAMMA0]	= 8,
+	[MT8188_VDO0_RST_DISP_DITHER0]	= 10,
+	[MT8188_VDO0_RST_DISP_WDMA0]	= 17,
+	[MT8188_VDO0_RST_DISP_RDMA0]	= 19,
+	[MT8188_VDO0_RST_DSI0]		= 21,
+	[MT8188_VDO0_RST_DSI1]		= 22,
+	[MT8188_VDO0_RST_DSC_WRAP0]	= 23,
+	[MT8188_VDO0_RST_VPP_MERGE0]	= 24,
+	[MT8188_VDO0_RST_DP_INTF0]	= 25,
+	[MT8188_VDO0_RST_DISP_AAL0]	= 26,
+	[MT8188_VDO0_RST_INLINEROT0]	= 27,
+	[MT8188_VDO0_RST_APB_BUS]	= 28,
+	[MT8188_VDO0_RST_DISP_COLOR0]	= 29,
+	[MT8188_VDO0_RST_MDP_WROT0]	= 30,
+	[MT8188_VDO0_RST_DISP_RSZ0]	= 31,
+};
+
 static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
 	{
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 13249658721f..88029500ed4d 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -87,6 +87,9 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
 	.clk_driver = "clk-mt8188-vdo0",
 	.routes = mmsys_mt8188_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
+	.sw0_rst_offset = MT8188_VDO0_SW0_RST_B,
+	.rst_tb = mmsys_mt8188_vdo0_rst_tb,
+	.num_resets = ARRAY_SIZE(mmsys_mt8188_vdo0_rst_tb),
 };

 static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
--
2.18.0

Re: [PATCH v2 11/15] soc: mediatek: Add MT8188 VDO0 reset bit map

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> Add MT8188 VDO0 reset bit map.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>



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Re: [PATCH v2 11/15] soc: mediatek: Add MT8188 VDO0 reset bit map

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> Add MT8188 VDO0 reset bit map.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

[PATCH v2 12/15] soc: mediatek: Add MT8188 VDO1 reset bit map

[Hsiao Chien Sung]

Add MT8188 VDO1 reset bit map.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/soc/mediatek/mt8188-mmsys.h | 57 +++++++++++++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c    |  3 +-
 2 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
index c3e3c5cfe931..208d4dfedc1a 100644
--- a/drivers/soc/mediatek/mt8188-mmsys.h
+++ b/drivers/soc/mediatek/mt8188-mmsys.h
@@ -144,6 +144,63 @@ static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
 	[MT8188_VDO0_RST_DISP_RSZ0]	= 31,
 };

+static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
+	[MT8188_VDO1_RST_SMI_LARB2]			= 0,
+	[MT8188_VDO1_RST_SMI_LARB3]			= 1,
+	[MT8188_VDO1_RST_GALS]				= 2,
+	[MT8188_VDO1_RST_FAKE_ENG0]			= 3,
+	[MT8188_VDO1_RST_FAKE_ENG1]			= 4,
+	[MT8188_VDO1_RST_MDP_RDMA0]			= 5,
+	[MT8188_VDO1_RST_MDP_RDMA1]			= 6,
+	[MT8188_VDO1_RST_MDP_RDMA2]			= 7,
+	[MT8188_VDO1_RST_MDP_RDMA3]			= 8,
+	[MT8188_VDO1_RST_VPP_MERGE0]			= 9,
+	[MT8188_VDO1_RST_VPP_MERGE1]			= 10,
+	[MT8188_VDO1_RST_VPP_MERGE2]			= 11,
+	[MT8188_VDO1_RST_VPP_MERGE3]			= 32 + 0,
+	[MT8188_VDO1_RST_VPP_MERGE4]			= 32 + 1,
+	[MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC]		= 32 + 2,
+	[MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC]		= 32 + 3,
+	[MT8188_VDO1_RST_DISP_MUTEX]			= 32 + 4,
+	[MT8188_VDO1_RST_MDP_RDMA4]			= 32 + 5,
+	[MT8188_VDO1_RST_MDP_RDMA5]			= 32 + 6,
+	[MT8188_VDO1_RST_MDP_RDMA6]			= 32 + 7,
+	[MT8188_VDO1_RST_MDP_RDMA7]			= 32 + 8,
+	[MT8188_VDO1_RST_DP_INTF1_MMCK]			= 32 + 9,
+	[MT8188_VDO1_RST_DPI0_MM_CK]			= 32 + 10,
+	[MT8188_VDO1_RST_DPI1_MM_CK]			= 32 + 11,
+	[MT8188_VDO1_RST_MERGE0_DL_ASYNC]		= 32 + 13,
+	[MT8188_VDO1_RST_MERGE1_DL_ASYNC]		= 32 + 14,
+	[MT8188_VDO1_RST_MERGE2_DL_ASYNC]		= 32 + 15,
+	[MT8188_VDO1_RST_MERGE3_DL_ASYNC]		= 32 + 16,
+	[MT8188_VDO1_RST_MERGE4_DL_ASYNC]		= 32 + 17,
+	[MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC]	= 32 + 18,
+	[MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC]	= 32 + 19,
+	[MT8188_VDO1_RST_PADDING0]			= 32 + 20,
+	[MT8188_VDO1_RST_PADDING1]			= 32 + 21,
+	[MT8188_VDO1_RST_PADDING2]			= 32 + 22,
+	[MT8188_VDO1_RST_PADDING3]			= 32 + 23,
+	[MT8188_VDO1_RST_PADDING4]			= 32 + 24,
+	[MT8188_VDO1_RST_PADDING5]			= 32 + 25,
+	[MT8188_VDO1_RST_PADDING6]			= 32 + 26,
+	[MT8188_VDO1_RST_PADDING7]			= 32 + 27,
+	[MT8188_VDO1_RST_DISP_RSZ0]			= 32 + 28,
+	[MT8188_VDO1_RST_DISP_RSZ1]			= 32 + 29,
+	[MT8188_VDO1_RST_DISP_RSZ2]			= 32 + 30,
+	[MT8188_VDO1_RST_DISP_RSZ3]			= 32 + 31,
+	[MT8188_VDO1_RST_HDR_VDO_FE0]			= 64 + 0,
+	[MT8188_VDO1_RST_HDR_GFX_FE0]			= 64 + 1,
+	[MT8188_VDO1_RST_HDR_VDO_BE]			= 64 + 2,
+	[MT8188_VDO1_RST_HDR_VDO_FE1]			= 64 + 16,
+	[MT8188_VDO1_RST_HDR_GFX_FE1]			= 64 + 17,
+	[MT8188_VDO1_RST_DISP_MIXER]			= 64 + 18,
+	[MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC]		= 64 + 19,
+	[MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC]		= 64 + 20,
+	[MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC]		= 64 + 21,
+	[MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC]		= 64 + 22,
+	[MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC]		= 64 + 23,
+};
+
 static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
 	{
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 88029500ed4d..7a6221f87669 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -97,7 +97,8 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
 	.routes = mmsys_mt8188_vdo1_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table),
 	.sw0_rst_offset = MT8188_VDO1_SW0_RST_B,
-	.num_resets = 96,
+	.rst_tb = mmsys_mt8188_vdo1_rst_tb,
+	.num_resets = ARRAY_SIZE(mmsys_mt8188_vdo1_rst_tb),
 	.vsync_len = 1,
 };

--
2.18.0


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[PATCH v2 12/15] soc: mediatek: Add MT8188 VDO1 reset bit map

[Hsiao Chien Sung]

Add MT8188 VDO1 reset bit map.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/soc/mediatek/mt8188-mmsys.h | 57 +++++++++++++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c    |  3 +-
 2 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
index c3e3c5cfe931..208d4dfedc1a 100644
--- a/drivers/soc/mediatek/mt8188-mmsys.h
+++ b/drivers/soc/mediatek/mt8188-mmsys.h
@@ -144,6 +144,63 @@ static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
 	[MT8188_VDO0_RST_DISP_RSZ0]	= 31,
 };

+static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
+	[MT8188_VDO1_RST_SMI_LARB2]			= 0,
+	[MT8188_VDO1_RST_SMI_LARB3]			= 1,
+	[MT8188_VDO1_RST_GALS]				= 2,
+	[MT8188_VDO1_RST_FAKE_ENG0]			= 3,
+	[MT8188_VDO1_RST_FAKE_ENG1]			= 4,
+	[MT8188_VDO1_RST_MDP_RDMA0]			= 5,
+	[MT8188_VDO1_RST_MDP_RDMA1]			= 6,
+	[MT8188_VDO1_RST_MDP_RDMA2]			= 7,
+	[MT8188_VDO1_RST_MDP_RDMA3]			= 8,
+	[MT8188_VDO1_RST_VPP_MERGE0]			= 9,
+	[MT8188_VDO1_RST_VPP_MERGE1]			= 10,
+	[MT8188_VDO1_RST_VPP_MERGE2]			= 11,
+	[MT8188_VDO1_RST_VPP_MERGE3]			= 32 + 0,
+	[MT8188_VDO1_RST_VPP_MERGE4]			= 32 + 1,
+	[MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC]		= 32 + 2,
+	[MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC]		= 32 + 3,
+	[MT8188_VDO1_RST_DISP_MUTEX]			= 32 + 4,
+	[MT8188_VDO1_RST_MDP_RDMA4]			= 32 + 5,
+	[MT8188_VDO1_RST_MDP_RDMA5]			= 32 + 6,
+	[MT8188_VDO1_RST_MDP_RDMA6]			= 32 + 7,
+	[MT8188_VDO1_RST_MDP_RDMA7]			= 32 + 8,
+	[MT8188_VDO1_RST_DP_INTF1_MMCK]			= 32 + 9,
+	[MT8188_VDO1_RST_DPI0_MM_CK]			= 32 + 10,
+	[MT8188_VDO1_RST_DPI1_MM_CK]			= 32 + 11,
+	[MT8188_VDO1_RST_MERGE0_DL_ASYNC]		= 32 + 13,
+	[MT8188_VDO1_RST_MERGE1_DL_ASYNC]		= 32 + 14,
+	[MT8188_VDO1_RST_MERGE2_DL_ASYNC]		= 32 + 15,
+	[MT8188_VDO1_RST_MERGE3_DL_ASYNC]		= 32 + 16,
+	[MT8188_VDO1_RST_MERGE4_DL_ASYNC]		= 32 + 17,
+	[MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC]	= 32 + 18,
+	[MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC]	= 32 + 19,
+	[MT8188_VDO1_RST_PADDING0]			= 32 + 20,
+	[MT8188_VDO1_RST_PADDING1]			= 32 + 21,
+	[MT8188_VDO1_RST_PADDING2]			= 32 + 22,
+	[MT8188_VDO1_RST_PADDING3]			= 32 + 23,
+	[MT8188_VDO1_RST_PADDING4]			= 32 + 24,
+	[MT8188_VDO1_RST_PADDING5]			= 32 + 25,
+	[MT8188_VDO1_RST_PADDING6]			= 32 + 26,
+	[MT8188_VDO1_RST_PADDING7]			= 32 + 27,
+	[MT8188_VDO1_RST_DISP_RSZ0]			= 32 + 28,
+	[MT8188_VDO1_RST_DISP_RSZ1]			= 32 + 29,
+	[MT8188_VDO1_RST_DISP_RSZ2]			= 32 + 30,
+	[MT8188_VDO1_RST_DISP_RSZ3]			= 32 + 31,
+	[MT8188_VDO1_RST_HDR_VDO_FE0]			= 64 + 0,
+	[MT8188_VDO1_RST_HDR_GFX_FE0]			= 64 + 1,
+	[MT8188_VDO1_RST_HDR_VDO_BE]			= 64 + 2,
+	[MT8188_VDO1_RST_HDR_VDO_FE1]			= 64 + 16,
+	[MT8188_VDO1_RST_HDR_GFX_FE1]			= 64 + 17,
+	[MT8188_VDO1_RST_DISP_MIXER]			= 64 + 18,
+	[MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC]		= 64 + 19,
+	[MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC]		= 64 + 20,
+	[MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC]		= 64 + 21,
+	[MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC]		= 64 + 22,
+	[MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC]		= 64 + 23,
+};
+
 static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
 	{
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 88029500ed4d..7a6221f87669 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -97,7 +97,8 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
 	.routes = mmsys_mt8188_vdo1_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table),
 	.sw0_rst_offset = MT8188_VDO1_SW0_RST_B,
-	.num_resets = 96,
+	.rst_tb = mmsys_mt8188_vdo1_rst_tb,
+	.num_resets = ARRAY_SIZE(mmsys_mt8188_vdo1_rst_tb),
 	.vsync_len = 1,
 };

--
2.18.0

Re: [PATCH v2 12/15] soc: mediatek: Add MT8188 VDO1 reset bit map

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> Add MT8188 VDO1 reset bit map.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>   drivers/soc/mediatek/mt8188-mmsys.h | 57 +++++++++++++++++++++++++++++
>   drivers/soc/mediatek/mtk-mmsys.c    |  3 +-
>   2 files changed, 59 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
> index c3e3c5cfe931..208d4dfedc1a 100644
> --- a/drivers/soc/mediatek/mt8188-mmsys.h
> +++ b/drivers/soc/mediatek/mt8188-mmsys.h
> @@ -144,6 +144,63 @@ static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
>   	[MT8188_VDO0_RST_DISP_RSZ0]	= 31,
>   };
> 
> +static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
> +	[MT8188_VDO1_RST_SMI_LARB2]			= 0,
> +	[MT8188_VDO1_RST_SMI_LARB3]			= 1,
> +	[MT8188_VDO1_RST_GALS]				= 2,
> +	[MT8188_VDO1_RST_FAKE_ENG0]			= 3,
> +	[MT8188_VDO1_RST_FAKE_ENG1]			= 4,
> +	[MT8188_VDO1_RST_MDP_RDMA0]			= 5,
> +	[MT8188_VDO1_RST_MDP_RDMA1]			= 6,
> +	[MT8188_VDO1_RST_MDP_RDMA2]			= 7,
> +	[MT8188_VDO1_RST_MDP_RDMA3]			= 8,
> +	[MT8188_VDO1_RST_VPP_MERGE0]			= 9,
> +	[MT8188_VDO1_RST_VPP_MERGE1]			= 10,
> +	[MT8188_VDO1_RST_VPP_MERGE2]			= 11,
> +	[MT8188_VDO1_RST_VPP_MERGE3]			= 32 + 0,

Works, but there's a better way.

32 + 0 means that you're using reset SW1 register, so you can do

#define MT8188_MMSYS_RST_NR_PER_BANK	32
#define MT8188_RST_SW1_OFFSET		MT8188_MMSYS_RST_NR_PER_BANK
#define MT8188_RST_SW2_OFFSET		MT8188_MMSYS_RST_NR_PER_BANK * 2

[MT8188_VDO1_RST_VPP_MERGE3] = MT8188_RST_SW1_OFFSET + 0
[MT8188_VDO1_RST_VPP_MERGE4] = MT8188_RST_SW1_OFFSET + 0
.......
[MT8188_VDO1_RST_HDR_VDO_FE0] = MT8188_RST_SW2_OFFSET + 0
...etc

Reading this will make it clear that a certain reset bit is in a different
(sequential or not) register.

P.S.: If the RST_NR_PER_BANK is *not* MT8188 specific (as in, all reset registers
for all SoCs are always 32 bits, which I believe is true), you could move that
definition to mtk-mmsys.h as
       #define MMSYS_RST_NR_PER_BANK	32
and then define the offsets in mt8188-mmsys.h as
       #define MT8188_RST_SW1_OFFSET MMSYS_RST_NR_PER_BANK
       .... etc

Thanks,
Angelo



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Re: [PATCH v2 12/15] soc: mediatek: Add MT8188 VDO1 reset bit map

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> Add MT8188 VDO1 reset bit map.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>   drivers/soc/mediatek/mt8188-mmsys.h | 57 +++++++++++++++++++++++++++++
>   drivers/soc/mediatek/mtk-mmsys.c    |  3 +-
>   2 files changed, 59 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
> index c3e3c5cfe931..208d4dfedc1a 100644
> --- a/drivers/soc/mediatek/mt8188-mmsys.h
> +++ b/drivers/soc/mediatek/mt8188-mmsys.h
> @@ -144,6 +144,63 @@ static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
>   	[MT8188_VDO0_RST_DISP_RSZ0]	= 31,
>   };
> 
> +static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
> +	[MT8188_VDO1_RST_SMI_LARB2]			= 0,
> +	[MT8188_VDO1_RST_SMI_LARB3]			= 1,
> +	[MT8188_VDO1_RST_GALS]				= 2,
> +	[MT8188_VDO1_RST_FAKE_ENG0]			= 3,
> +	[MT8188_VDO1_RST_FAKE_ENG1]			= 4,
> +	[MT8188_VDO1_RST_MDP_RDMA0]			= 5,
> +	[MT8188_VDO1_RST_MDP_RDMA1]			= 6,
> +	[MT8188_VDO1_RST_MDP_RDMA2]			= 7,
> +	[MT8188_VDO1_RST_MDP_RDMA3]			= 8,
> +	[MT8188_VDO1_RST_VPP_MERGE0]			= 9,
> +	[MT8188_VDO1_RST_VPP_MERGE1]			= 10,
> +	[MT8188_VDO1_RST_VPP_MERGE2]			= 11,
> +	[MT8188_VDO1_RST_VPP_MERGE3]			= 32 + 0,

Works, but there's a better way.

32 + 0 means that you're using reset SW1 register, so you can do

#define MT8188_MMSYS_RST_NR_PER_BANK	32
#define MT8188_RST_SW1_OFFSET		MT8188_MMSYS_RST_NR_PER_BANK
#define MT8188_RST_SW2_OFFSET		MT8188_MMSYS_RST_NR_PER_BANK * 2

[MT8188_VDO1_RST_VPP_MERGE3] = MT8188_RST_SW1_OFFSET + 0
[MT8188_VDO1_RST_VPP_MERGE4] = MT8188_RST_SW1_OFFSET + 0
.......
[MT8188_VDO1_RST_HDR_VDO_FE0] = MT8188_RST_SW2_OFFSET + 0
...etc

Reading this will make it clear that a certain reset bit is in a different
(sequential or not) register.

P.S.: If the RST_NR_PER_BANK is *not* MT8188 specific (as in, all reset registers
for all SoCs are always 32 bits, which I believe is true), you could move that
definition to mtk-mmsys.h as
       #define MMSYS_RST_NR_PER_BANK	32
and then define the offsets in mt8188-mmsys.h as
       #define MT8188_RST_SW1_OFFSET MMSYS_RST_NR_PER_BANK
       .... etc

Thanks,
Angelo

Re: [PATCH v2 12/15] soc: mediatek: Add MT8188 VDO1 reset bit map

[Shawn Sung (宋孝謙)]

Hi Angelo,

Got it. Will fix this in the next version.

Added a new define in mtk-mmsys.h:
#define MMSYS_RST_NR(bank, bit) ((bank * 32) + bit)

And define the reset table as:
static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
        [MT8188_VDO1_RST_SMI_LARB2]           = MMSYS_RST_NR(0, 0),
        ...
        [MT8188_VDO1_RST_VPP_MERGE2]          = MMSYS_RST_NR(0, 11),
        [MT8188_VDO1_RST_VPP_MERGE3]          = MMSYS_RST_NR(1, 0),
        ...
        [MT8188_VDO1_RST_DISP_RSZ3]           = MMSYS_RST_NR(1, 31),
        [MT8188_VDO1_RST_HDR_VDO_FE0]         = MMSYS_RST_NR(2, 0),
    
...
        [MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC] = MMSYS_RST_NR(2, 23),
};

Thanks,
Hsiao Chien Sung

On Wed, 2023-06-14 at 13:35 +0200, AngeloGioacchino Del Regno wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> > Add MT8188 VDO1 reset bit map.
> > 
> > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > ---
> >   drivers/soc/mediatek/mt8188-mmsys.h | 57
> +++++++++++++++++++++++++++++
> >   drivers/soc/mediatek/mtk-mmsys.c    |  3 +-
> >   2 files changed, 59 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/soc/mediatek/mt8188-mmsys.h
> b/drivers/soc/mediatek/mt8188-mmsys.h
> > index c3e3c5cfe931..208d4dfedc1a 100644
> > --- a/drivers/soc/mediatek/mt8188-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8188-mmsys.h
> > @@ -144,6 +144,63 @@ static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
> >   [MT8188_VDO0_RST_DISP_RSZ0]= 31,
> >   };
> > 
> > +static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
> > +[MT8188_VDO1_RST_SMI_LARB2]= 0,
> > +[MT8188_VDO1_RST_SMI_LARB3]= 1,
> > +[MT8188_VDO1_RST_GALS]= 2,
> > +[MT8188_VDO1_RST_FAKE_ENG0]= 3,
> > +[MT8188_VDO1_RST_FAKE_ENG1]= 4,
> > +[MT8188_VDO1_RST_MDP_RDMA0]= 5,
> > +[MT8188_VDO1_RST_MDP_RDMA1]= 6,
> > +[MT8188_VDO1_RST_MDP_RDMA2]= 7,
> > +[MT8188_VDO1_RST_MDP_RDMA3]= 8,
> > +[MT8188_VDO1_RST_VPP_MERGE0]= 9,
> > +[MT8188_VDO1_RST_VPP_MERGE1]= 10,
> > +[MT8188_VDO1_RST_VPP_MERGE2]= 11,
> > +[MT8188_VDO1_RST_VPP_MERGE3]= 32 + 0,
> 
> Works, but there's a better way.
> 
> 32 + 0 means that you're using reset SW1 register, so you can do
> 
> #define MT8188_MMSYS_RST_NR_PER_BANK32
> #define MT8188_RST_SW1_OFFSETMT8188_MMSYS_RST_NR_PER_BANK
> #define MT8188_RST_SW2_OFFSETMT8188_MMSYS_RST_NR_PER_BANK * 2
> 
> [MT8188_VDO1_RST_VPP_MERGE3] = MT8188_RST_SW1_OFFSET + 0
> [MT8188_VDO1_RST_VPP_MERGE4] = MT8188_RST_SW1_OFFSET + 0
> .......
> [MT8188_VDO1_RST_HDR_VDO_FE0] = MT8188_RST_SW2_OFFSET + 0
> ...etc
> 
> Reading this will make it clear that a certain reset bit is in a
> different
> (sequential or not) register.
> 
> P.S.: If the RST_NR_PER_BANK is *not* MT8188 specific (as in, all
> reset registers
> for all SoCs are always 32 bits, which I believe is true), you could
> move that
> definition to mtk-mmsys.h as
>        #define MMSYS_RST_NR_PER_BANK32
> and then define the offsets in mt8188-mmsys.h as
>        #define MT8188_RST_SW1_OFFSET MMSYS_RST_NR_PER_BANK
>        .... etc
> 
> Thanks,
> Angelo
> 
> 
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Re: [PATCH v2 12/15] soc: mediatek: Add MT8188 VDO1 reset bit map

[Shawn Sung (宋孝謙)]

Hi Angelo,

Got it. Will fix this in the next version.

Added a new define in mtk-mmsys.h:
#define MMSYS_RST_NR(bank, bit) ((bank * 32) + bit)

And define the reset table as:
static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
        [MT8188_VDO1_RST_SMI_LARB2]           = MMSYS_RST_NR(0, 0),
        ...
        [MT8188_VDO1_RST_VPP_MERGE2]          = MMSYS_RST_NR(0, 11),
        [MT8188_VDO1_RST_VPP_MERGE3]          = MMSYS_RST_NR(1, 0),
        ...
        [MT8188_VDO1_RST_DISP_RSZ3]           = MMSYS_RST_NR(1, 31),
        [MT8188_VDO1_RST_HDR_VDO_FE0]         = MMSYS_RST_NR(2, 0),
    
...
        [MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC] = MMSYS_RST_NR(2, 23),
};

Thanks,
Hsiao Chien Sung

On Wed, 2023-06-14 at 13:35 +0200, AngeloGioacchino Del Regno wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> > Add MT8188 VDO1 reset bit map.
> > 
> > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > ---
> >   drivers/soc/mediatek/mt8188-mmsys.h | 57
> +++++++++++++++++++++++++++++
> >   drivers/soc/mediatek/mtk-mmsys.c    |  3 +-
> >   2 files changed, 59 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/soc/mediatek/mt8188-mmsys.h
> b/drivers/soc/mediatek/mt8188-mmsys.h
> > index c3e3c5cfe931..208d4dfedc1a 100644
> > --- a/drivers/soc/mediatek/mt8188-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8188-mmsys.h
> > @@ -144,6 +144,63 @@ static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
> >   [MT8188_VDO0_RST_DISP_RSZ0]= 31,
> >   };
> > 
> > +static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
> > +[MT8188_VDO1_RST_SMI_LARB2]= 0,
> > +[MT8188_VDO1_RST_SMI_LARB3]= 1,
> > +[MT8188_VDO1_RST_GALS]= 2,
> > +[MT8188_VDO1_RST_FAKE_ENG0]= 3,
> > +[MT8188_VDO1_RST_FAKE_ENG1]= 4,
> > +[MT8188_VDO1_RST_MDP_RDMA0]= 5,
> > +[MT8188_VDO1_RST_MDP_RDMA1]= 6,
> > +[MT8188_VDO1_RST_MDP_RDMA2]= 7,
> > +[MT8188_VDO1_RST_MDP_RDMA3]= 8,
> > +[MT8188_VDO1_RST_VPP_MERGE0]= 9,
> > +[MT8188_VDO1_RST_VPP_MERGE1]= 10,
> > +[MT8188_VDO1_RST_VPP_MERGE2]= 11,
> > +[MT8188_VDO1_RST_VPP_MERGE3]= 32 + 0,
> 
> Works, but there's a better way.
> 
> 32 + 0 means that you're using reset SW1 register, so you can do
> 
> #define MT8188_MMSYS_RST_NR_PER_BANK32
> #define MT8188_RST_SW1_OFFSETMT8188_MMSYS_RST_NR_PER_BANK
> #define MT8188_RST_SW2_OFFSETMT8188_MMSYS_RST_NR_PER_BANK * 2
> 
> [MT8188_VDO1_RST_VPP_MERGE3] = MT8188_RST_SW1_OFFSET + 0
> [MT8188_VDO1_RST_VPP_MERGE4] = MT8188_RST_SW1_OFFSET + 0
> .......
> [MT8188_VDO1_RST_HDR_VDO_FE0] = MT8188_RST_SW2_OFFSET + 0
> ...etc
> 
> Reading this will make it clear that a certain reset bit is in a
> different
> (sequential or not) register.
> 
> P.S.: If the RST_NR_PER_BANK is *not* MT8188 specific (as in, all
> reset registers
> for all SoCs are always 32 bits, which I believe is true), you could
> move that
> definition to mtk-mmsys.h as
>        #define MMSYS_RST_NR_PER_BANK32
> and then define the offsets in mt8188-mmsys.h as
>        #define MT8188_RST_SW1_OFFSET MMSYS_RST_NR_PER_BANK
>        .... etc
> 
> Thanks,
> Angelo
> 
> 

Re: [PATCH v2 12/15] soc: mediatek: Add MT8188 VDO1 reset bit map

[AngeloGioacchino Del Regno]

Il 15/06/23 08:01, Shawn Sung (宋孝謙) ha scritto:
> Hi Angelo,
> 
> Got it. Will fix this in the next version.
> 
> Added a new define in mtk-mmsys.h:
> #define MMSYS_RST_NR(bank, bit) ((bank * 32) + bit)
> 
> And define the reset table as:
> static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
>          [MT8188_VDO1_RST_SMI_LARB2]           = MMSYS_RST_NR(0, 0),
>          ...
>          [MT8188_VDO1_RST_VPP_MERGE2]          = MMSYS_RST_NR(0, 11),
>          [MT8188_VDO1_RST_VPP_MERGE3]          = MMSYS_RST_NR(1, 0),
>          ...
>          [MT8188_VDO1_RST_DISP_RSZ3]           = MMSYS_RST_NR(1, 31),
>          [MT8188_VDO1_RST_HDR_VDO_FE0]         = MMSYS_RST_NR(2, 0),
>      
> ...
>          [MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC] = MMSYS_RST_NR(2, 23),
> };
> 

Okay, that's also good. Go on!

Regards,
Angelo

> Thanks,
> Hsiao Chien Sung
> 
> On Wed, 2023-06-14 at 13:35 +0200, AngeloGioacchino Del Regno wrote:
>>   	
>> External email : Please do not click links or open attachments until
>> you have verified the sender or the content.
>>   Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
>>> Add MT8188 VDO1 reset bit map.
>>>
>>> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
>>> ---
>>>    drivers/soc/mediatek/mt8188-mmsys.h | 57
>> +++++++++++++++++++++++++++++
>>>    drivers/soc/mediatek/mtk-mmsys.c    |  3 +-
>>>    2 files changed, 59 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mt8188-mmsys.h
>> b/drivers/soc/mediatek/mt8188-mmsys.h
>>> index c3e3c5cfe931..208d4dfedc1a 100644
>>> --- a/drivers/soc/mediatek/mt8188-mmsys.h
>>> +++ b/drivers/soc/mediatek/mt8188-mmsys.h
>>> @@ -144,6 +144,63 @@ static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
>>>    [MT8188_VDO0_RST_DISP_RSZ0]= 31,
>>>    };
>>>
>>> +static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
>>> +[MT8188_VDO1_RST_SMI_LARB2]= 0,
>>> +[MT8188_VDO1_RST_SMI_LARB3]= 1,
>>> +[MT8188_VDO1_RST_GALS]= 2,
>>> +[MT8188_VDO1_RST_FAKE_ENG0]= 3,
>>> +[MT8188_VDO1_RST_FAKE_ENG1]= 4,
>>> +[MT8188_VDO1_RST_MDP_RDMA0]= 5,
>>> +[MT8188_VDO1_RST_MDP_RDMA1]= 6,
>>> +[MT8188_VDO1_RST_MDP_RDMA2]= 7,
>>> +[MT8188_VDO1_RST_MDP_RDMA3]= 8,
>>> +[MT8188_VDO1_RST_VPP_MERGE0]= 9,
>>> +[MT8188_VDO1_RST_VPP_MERGE1]= 10,
>>> +[MT8188_VDO1_RST_VPP_MERGE2]= 11,
>>> +[MT8188_VDO1_RST_VPP_MERGE3]= 32 + 0,
>>
>> Works, but there's a better way.
>>
>> 32 + 0 means that you're using reset SW1 register, so you can do
>>
>> #define MT8188_MMSYS_RST_NR_PER_BANK32
>> #define MT8188_RST_SW1_OFFSETMT8188_MMSYS_RST_NR_PER_BANK
>> #define MT8188_RST_SW2_OFFSETMT8188_MMSYS_RST_NR_PER_BANK * 2
>>
>> [MT8188_VDO1_RST_VPP_MERGE3] = MT8188_RST_SW1_OFFSET + 0
>> [MT8188_VDO1_RST_VPP_MERGE4] = MT8188_RST_SW1_OFFSET + 0
>> .......
>> [MT8188_VDO1_RST_HDR_VDO_FE0] = MT8188_RST_SW2_OFFSET + 0
>> ...etc
>>
>> Reading this will make it clear that a certain reset bit is in a
>> different
>> (sequential or not) register.
>>
>> P.S.: If the RST_NR_PER_BANK is *not* MT8188 specific (as in, all
>> reset registers
>> for all SoCs are always 32 bits, which I believe is true), you could
>> move that
>> definition to mtk-mmsys.h as
>>         #define MMSYS_RST_NR_PER_BANK32
>> and then define the offsets in mt8188-mmsys.h as
>>         #define MT8188_RST_SW1_OFFSET MMSYS_RST_NR_PER_BANK
>>         .... etc
>>
>> Thanks,
>> Angelo
>>
>>


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Re: [PATCH v2 12/15] soc: mediatek: Add MT8188 VDO1 reset bit map

[AngeloGioacchino Del Regno]

Il 15/06/23 08:01, Shawn Sung (宋孝謙) ha scritto:
> Hi Angelo,
> 
> Got it. Will fix this in the next version.
> 
> Added a new define in mtk-mmsys.h:
> #define MMSYS_RST_NR(bank, bit) ((bank * 32) + bit)
> 
> And define the reset table as:
> static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
>          [MT8188_VDO1_RST_SMI_LARB2]           = MMSYS_RST_NR(0, 0),
>          ...
>          [MT8188_VDO1_RST_VPP_MERGE2]          = MMSYS_RST_NR(0, 11),
>          [MT8188_VDO1_RST_VPP_MERGE3]          = MMSYS_RST_NR(1, 0),
>          ...
>          [MT8188_VDO1_RST_DISP_RSZ3]           = MMSYS_RST_NR(1, 31),
>          [MT8188_VDO1_RST_HDR_VDO_FE0]         = MMSYS_RST_NR(2, 0),
>      
> ...
>          [MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC] = MMSYS_RST_NR(2, 23),
> };
> 

Okay, that's also good. Go on!

Regards,
Angelo

> Thanks,
> Hsiao Chien Sung
> 
> On Wed, 2023-06-14 at 13:35 +0200, AngeloGioacchino Del Regno wrote:
>>   	
>> External email : Please do not click links or open attachments until
>> you have verified the sender or the content.
>>   Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
>>> Add MT8188 VDO1 reset bit map.
>>>
>>> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
>>> ---
>>>    drivers/soc/mediatek/mt8188-mmsys.h | 57
>> +++++++++++++++++++++++++++++
>>>    drivers/soc/mediatek/mtk-mmsys.c    |  3 +-
>>>    2 files changed, 59 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mt8188-mmsys.h
>> b/drivers/soc/mediatek/mt8188-mmsys.h
>>> index c3e3c5cfe931..208d4dfedc1a 100644
>>> --- a/drivers/soc/mediatek/mt8188-mmsys.h
>>> +++ b/drivers/soc/mediatek/mt8188-mmsys.h
>>> @@ -144,6 +144,63 @@ static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
>>>    [MT8188_VDO0_RST_DISP_RSZ0]= 31,
>>>    };
>>>
>>> +static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
>>> +[MT8188_VDO1_RST_SMI_LARB2]= 0,
>>> +[MT8188_VDO1_RST_SMI_LARB3]= 1,
>>> +[MT8188_VDO1_RST_GALS]= 2,
>>> +[MT8188_VDO1_RST_FAKE_ENG0]= 3,
>>> +[MT8188_VDO1_RST_FAKE_ENG1]= 4,
>>> +[MT8188_VDO1_RST_MDP_RDMA0]= 5,
>>> +[MT8188_VDO1_RST_MDP_RDMA1]= 6,
>>> +[MT8188_VDO1_RST_MDP_RDMA2]= 7,
>>> +[MT8188_VDO1_RST_MDP_RDMA3]= 8,
>>> +[MT8188_VDO1_RST_VPP_MERGE0]= 9,
>>> +[MT8188_VDO1_RST_VPP_MERGE1]= 10,
>>> +[MT8188_VDO1_RST_VPP_MERGE2]= 11,
>>> +[MT8188_VDO1_RST_VPP_MERGE3]= 32 + 0,
>>
>> Works, but there's a better way.
>>
>> 32 + 0 means that you're using reset SW1 register, so you can do
>>
>> #define MT8188_MMSYS_RST_NR_PER_BANK32
>> #define MT8188_RST_SW1_OFFSETMT8188_MMSYS_RST_NR_PER_BANK
>> #define MT8188_RST_SW2_OFFSETMT8188_MMSYS_RST_NR_PER_BANK * 2
>>
>> [MT8188_VDO1_RST_VPP_MERGE3] = MT8188_RST_SW1_OFFSET + 0
>> [MT8188_VDO1_RST_VPP_MERGE4] = MT8188_RST_SW1_OFFSET + 0
>> .......
>> [MT8188_VDO1_RST_HDR_VDO_FE0] = MT8188_RST_SW2_OFFSET + 0
>> ...etc
>>
>> Reading this will make it clear that a certain reset bit is in a
>> different
>> (sequential or not) register.
>>
>> P.S.: If the RST_NR_PER_BANK is *not* MT8188 specific (as in, all
>> reset registers
>> for all SoCs are always 32 bits, which I believe is true), you could
>> move that
>> definition to mtk-mmsys.h as
>>         #define MMSYS_RST_NR_PER_BANK32
>> and then define the offsets in mt8188-mmsys.h as
>>         #define MT8188_RST_SW1_OFFSET MMSYS_RST_NR_PER_BANK
>>         .... etc
>>
>> Thanks,
>> Angelo
>>
>>

[PATCH v2 13/15] drm/mediatek: Support MT8188 VDOSYS1 in display driver

[Hsiao Chien Sung]

- The mmsys_dev_num in MT8188 VDOSYS0 was set to 1 since
  VDOSYS1 was not available before. Increase it to support
  VDOSYS1 in display driver.
- Add compatible name for MT8188 VDOSYS1
  (shares the same driver data with MT8195 VDOSYS1)

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 6dcb4ba2466c..613093068bb4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -287,6 +287,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
 	.main_path = mt8188_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8188_mtk_ddp_main),
+	.mmsys_dev_num = 2,
 };

 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
@@ -327,6 +328,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
 	  .data = &mt8186_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8188-vdosys0",
 	  .data = &mt8188_vdosys0_driver_data},
+	{ .compatible = "mediatek,mt8188-vdosys1",
+	  .data = &mt8195_vdosys1_driver_data},
 	{ .compatible = "mediatek,mt8192-mmsys",
 	  .data = &mt8192_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8195-mmsys",
--
2.18.0


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[PATCH v2 13/15] drm/mediatek: Support MT8188 VDOSYS1 in display driver

[Hsiao Chien Sung]

- The mmsys_dev_num in MT8188 VDOSYS0 was set to 1 since
  VDOSYS1 was not available before. Increase it to support
  VDOSYS1 in display driver.
- Add compatible name for MT8188 VDOSYS1
  (shares the same driver data with MT8195 VDOSYS1)

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 6dcb4ba2466c..613093068bb4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -287,6 +287,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
 	.main_path = mt8188_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8188_mtk_ddp_main),
+	.mmsys_dev_num = 2,
 };

 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
@@ -327,6 +328,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
 	  .data = &mt8186_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8188-vdosys0",
 	  .data = &mt8188_vdosys0_driver_data},
+	{ .compatible = "mediatek,mt8188-vdosys1",
+	  .data = &mt8195_vdosys1_driver_data},
 	{ .compatible = "mediatek,mt8192-mmsys",
 	  .data = &mt8192_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8195-mmsys",
--
2.18.0

Re: [PATCH v2 13/15] drm/mediatek: Support MT8188 VDOSYS1 in display driver

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> - The mmsys_dev_num in MT8188 VDOSYS0 was set to 1 since
>    VDOSYS1 was not available before. Increase it to support
>    VDOSYS1 in display driver.
> - Add compatible name for MT8188 VDOSYS1
>    (shares the same driver data with MT8195 VDOSYS1)
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

Reusing data/code. Just great.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>



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Re: [PATCH v2 13/15] drm/mediatek: Support MT8188 VDOSYS1 in display driver

[AngeloGioacchino Del Regno]

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> - The mmsys_dev_num in MT8188 VDOSYS0 was set to 1 since
>    VDOSYS1 was not available before. Increase it to support
>    VDOSYS1 in display driver.
> - Add compatible name for MT8188 VDOSYS1
>    (shares the same driver data with MT8195 VDOSYS1)
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

Reusing data/code. Just great.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

[PATCH v2 14/15] drm/mediatek: Improve compatibility of display driver

[Hsiao Chien Sung]

- Check if the component is defined before using it since
  some modules are MT8188 only (ex. PADDING)
- Use a for-loop to add/remove components in an arrays,
  so we can only maintain this array to make sure every
  component will be initialized properly

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c   | 128 +++++++++++-------
 1 file changed, 78 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index c0a38f5217ee..a5f5a0f8ea85 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -51,6 +51,7 @@ enum mtk_ovl_adaptor_comp_id {

 struct ovl_adaptor_comp_match {
 	enum mtk_ovl_adaptor_comp_type type;
+	enum mtk_ddp_comp_id comp_id;
 	int alias_id;
 };

@@ -67,19 +68,19 @@ static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
 };

 static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
-	[OVL_ADAPTOR_MDP_RDMA0]	= { OVL_ADAPTOR_TYPE_RDMA, 0 },
-	[OVL_ADAPTOR_MDP_RDMA1]	= { OVL_ADAPTOR_TYPE_RDMA, 1 },
-	[OVL_ADAPTOR_MDP_RDMA2]	= { OVL_ADAPTOR_TYPE_RDMA, 2 },
-	[OVL_ADAPTOR_MDP_RDMA3]	= { OVL_ADAPTOR_TYPE_RDMA, 3 },
-	[OVL_ADAPTOR_MDP_RDMA4]	= { OVL_ADAPTOR_TYPE_RDMA, 4 },
-	[OVL_ADAPTOR_MDP_RDMA5]	= { OVL_ADAPTOR_TYPE_RDMA, 5 },
-	[OVL_ADAPTOR_MDP_RDMA6]	= { OVL_ADAPTOR_TYPE_RDMA, 6 },
-	[OVL_ADAPTOR_MDP_RDMA7]	= { OVL_ADAPTOR_TYPE_RDMA, 7 },
-	[OVL_ADAPTOR_MERGE0]	= { OVL_ADAPTOR_TYPE_MERGE, 1 },
-	[OVL_ADAPTOR_MERGE1]	= { OVL_ADAPTOR_TYPE_MERGE, 2 },
-	[OVL_ADAPTOR_MERGE2]	= { OVL_ADAPTOR_TYPE_MERGE, 3 },
-	[OVL_ADAPTOR_MERGE3]	= { OVL_ADAPTOR_TYPE_MERGE, 4 },
-	[OVL_ADAPTOR_ETHDR0]	= { OVL_ADAPTOR_TYPE_ETHDR, 0 },
+	[OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA0, 0 },
+	[OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA1, 1 },
+	[OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA2, 2 },
+	[OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA3, 3 },
+	[OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA4, 4 },
+	[OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA5, 5 },
+	[OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA6, 6 },
+	[OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA7, 7 },
+	[OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1 },
+	[OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2 },
+	[OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3 },
+	[OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4 },
+	[OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0 },
 };

 void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
@@ -192,6 +193,8 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)

 	for (i = 0; i < OVL_ADAPTOR_MERGE0; i++) {
 		comp = ovl_adaptor->ovl_adaptor_comp[i];
+		if (!comp)
+			continue;
 		ret = pm_runtime_get_sync(comp);
 		if (ret < 0) {
 			dev_err(dev, "Failed to enable power domain %d, err %d\n", i, ret);
@@ -202,12 +205,23 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
 	for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
 		comp = ovl_adaptor->ovl_adaptor_comp[i];

-		if (i < OVL_ADAPTOR_MERGE0)
+		if (!comp)
+			continue;
+
+		switch (comp_matches[i].type) {
+		case OVL_ADAPTOR_TYPE_RDMA:
 			ret = mtk_mdp_rdma_clk_enable(comp);
-		else if (i < OVL_ADAPTOR_ETHDR0)
+			break;
+		case OVL_ADAPTOR_TYPE_MERGE:
 			ret = mtk_merge_clk_enable(comp);
-		else
+			break;
+		case OVL_ADAPTOR_TYPE_ETHDR:
 			ret = mtk_ethdr_clk_enable(comp);
+			break;
+		default:
+			dev_err(dev, "Unknown type: %d\n", comp_matches[i].type);
+		}
+
 		if (ret) {
 			dev_err(dev, "Failed to enable clock %d, err %d\n", i, ret);
 			goto clk_err;
@@ -219,18 +233,33 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
 clk_err:
 	while (--i >= 0) {
 		comp = ovl_adaptor->ovl_adaptor_comp[i];
-		if (i < OVL_ADAPTOR_MERGE0)
+
+		if (!comp)
+			continue;
+
+		switch (comp_matches[i].type) {
+		case OVL_ADAPTOR_TYPE_RDMA:
 			mtk_mdp_rdma_clk_disable(comp);
-		else if (i < OVL_ADAPTOR_ETHDR0)
+			break;
+		case OVL_ADAPTOR_TYPE_MERGE:
 			mtk_merge_clk_disable(comp);
-		else
+			break;
+		case OVL_ADAPTOR_TYPE_ETHDR:
 			mtk_ethdr_clk_disable(comp);
+			break;
+		default:
+			dev_err(dev, "Unknown type: %d\n", comp_matches[i].type);
+		}
 	}
 	i = OVL_ADAPTOR_MERGE0;

 pwr_err:
-	while (--i >= 0)
-		pm_runtime_put(ovl_adaptor->ovl_adaptor_comp[i]);
+	while (--i >= 0) {
+		comp = ovl_adaptor->ovl_adaptor_comp[i];
+		if (!comp)
+			continue;
+		pm_runtime_put(comp);
+	}

 	return ret;
 }
@@ -244,13 +273,22 @@ void mtk_ovl_adaptor_clk_disable(struct device *dev)
 	for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
 		comp = ovl_adaptor->ovl_adaptor_comp[i];

-		if (i < OVL_ADAPTOR_MERGE0) {
+		if (!comp)
+			continue;
+
+		switch (comp_matches[i].type) {
+		case OVL_ADAPTOR_TYPE_RDMA:
 			mtk_mdp_rdma_clk_disable(comp);
 			pm_runtime_put(comp);
-		} else if (i < OVL_ADAPTOR_ETHDR0) {
+			break;
+		case OVL_ADAPTOR_TYPE_MERGE:
 			mtk_merge_clk_disable(comp);
-		} else {
+			break;
+		case OVL_ADAPTOR_TYPE_ETHDR:
 			mtk_ethdr_clk_disable(comp);
+			break;
+		default:
+			dev_err(dev, "Unknown type: %d\n", comp_matches[i].type);
 		}
 	}
 }
@@ -313,36 +351,26 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device *dev)

 void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex)
 {
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA3);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA4);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA5);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA6);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA7);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE1);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
+	struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+	int i;
+
+	for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
+		if (!ovl_adaptor->ovl_adaptor_comp[i])
+			continue;
+		mtk_mutex_add_comp(mutex, comp_matches[i].comp_id);
+	}
 }

 void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex)
 {
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA3);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA4);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA5);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA6);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA7);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE1);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
+	struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+	int i;
+
+	for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
+		if (!ovl_adaptor->ovl_adaptor_comp[i])
+			continue;
+		mtk_mutex_remove_comp(mutex, comp_matches[i].comp_id);
+	}
 }

 void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsigned int next)
--
2.18.0


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[PATCH v2 14/15] drm/mediatek: Improve compatibility of display driver

[Hsiao Chien Sung]

- Check if the component is defined before using it since
  some modules are MT8188 only (ex. PADDING)
- Use a for-loop to add/remove components in an arrays,
  so we can only maintain this array to make sure every
  component will be initialized properly

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c   | 128 +++++++++++-------
 1 file changed, 78 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index c0a38f5217ee..a5f5a0f8ea85 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -51,6 +51,7 @@ enum mtk_ovl_adaptor_comp_id {

 struct ovl_adaptor_comp_match {
 	enum mtk_ovl_adaptor_comp_type type;
+	enum mtk_ddp_comp_id comp_id;
 	int alias_id;
 };

@@ -67,19 +68,19 @@ static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
 };

 static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
-	[OVL_ADAPTOR_MDP_RDMA0]	= { OVL_ADAPTOR_TYPE_RDMA, 0 },
-	[OVL_ADAPTOR_MDP_RDMA1]	= { OVL_ADAPTOR_TYPE_RDMA, 1 },
-	[OVL_ADAPTOR_MDP_RDMA2]	= { OVL_ADAPTOR_TYPE_RDMA, 2 },
-	[OVL_ADAPTOR_MDP_RDMA3]	= { OVL_ADAPTOR_TYPE_RDMA, 3 },
-	[OVL_ADAPTOR_MDP_RDMA4]	= { OVL_ADAPTOR_TYPE_RDMA, 4 },
-	[OVL_ADAPTOR_MDP_RDMA5]	= { OVL_ADAPTOR_TYPE_RDMA, 5 },
-	[OVL_ADAPTOR_MDP_RDMA6]	= { OVL_ADAPTOR_TYPE_RDMA, 6 },
-	[OVL_ADAPTOR_MDP_RDMA7]	= { OVL_ADAPTOR_TYPE_RDMA, 7 },
-	[OVL_ADAPTOR_MERGE0]	= { OVL_ADAPTOR_TYPE_MERGE, 1 },
-	[OVL_ADAPTOR_MERGE1]	= { OVL_ADAPTOR_TYPE_MERGE, 2 },
-	[OVL_ADAPTOR_MERGE2]	= { OVL_ADAPTOR_TYPE_MERGE, 3 },
-	[OVL_ADAPTOR_MERGE3]	= { OVL_ADAPTOR_TYPE_MERGE, 4 },
-	[OVL_ADAPTOR_ETHDR0]	= { OVL_ADAPTOR_TYPE_ETHDR, 0 },
+	[OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA0, 0 },
+	[OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA1, 1 },
+	[OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA2, 2 },
+	[OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA3, 3 },
+	[OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA4, 4 },
+	[OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA5, 5 },
+	[OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA6, 6 },
+	[OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA7, 7 },
+	[OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1 },
+	[OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2 },
+	[OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3 },
+	[OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4 },
+	[OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0 },
 };

 void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
@@ -192,6 +193,8 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)

 	for (i = 0; i < OVL_ADAPTOR_MERGE0; i++) {
 		comp = ovl_adaptor->ovl_adaptor_comp[i];
+		if (!comp)
+			continue;
 		ret = pm_runtime_get_sync(comp);
 		if (ret < 0) {
 			dev_err(dev, "Failed to enable power domain %d, err %d\n", i, ret);
@@ -202,12 +205,23 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
 	for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
 		comp = ovl_adaptor->ovl_adaptor_comp[i];

-		if (i < OVL_ADAPTOR_MERGE0)
+		if (!comp)
+			continue;
+
+		switch (comp_matches[i].type) {
+		case OVL_ADAPTOR_TYPE_RDMA:
 			ret = mtk_mdp_rdma_clk_enable(comp);
-		else if (i < OVL_ADAPTOR_ETHDR0)
+			break;
+		case OVL_ADAPTOR_TYPE_MERGE:
 			ret = mtk_merge_clk_enable(comp);
-		else
+			break;
+		case OVL_ADAPTOR_TYPE_ETHDR:
 			ret = mtk_ethdr_clk_enable(comp);
+			break;
+		default:
+			dev_err(dev, "Unknown type: %d\n", comp_matches[i].type);
+		}
+
 		if (ret) {
 			dev_err(dev, "Failed to enable clock %d, err %d\n", i, ret);
 			goto clk_err;
@@ -219,18 +233,33 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
 clk_err:
 	while (--i >= 0) {
 		comp = ovl_adaptor->ovl_adaptor_comp[i];
-		if (i < OVL_ADAPTOR_MERGE0)
+
+		if (!comp)
+			continue;
+
+		switch (comp_matches[i].type) {
+		case OVL_ADAPTOR_TYPE_RDMA:
 			mtk_mdp_rdma_clk_disable(comp);
-		else if (i < OVL_ADAPTOR_ETHDR0)
+			break;
+		case OVL_ADAPTOR_TYPE_MERGE:
 			mtk_merge_clk_disable(comp);
-		else
+			break;
+		case OVL_ADAPTOR_TYPE_ETHDR:
 			mtk_ethdr_clk_disable(comp);
+			break;
+		default:
+			dev_err(dev, "Unknown type: %d\n", comp_matches[i].type);
+		}
 	}
 	i = OVL_ADAPTOR_MERGE0;

 pwr_err:
-	while (--i >= 0)
-		pm_runtime_put(ovl_adaptor->ovl_adaptor_comp[i]);
+	while (--i >= 0) {
+		comp = ovl_adaptor->ovl_adaptor_comp[i];
+		if (!comp)
+			continue;
+		pm_runtime_put(comp);
+	}

 	return ret;
 }
@@ -244,13 +273,22 @@ void mtk_ovl_adaptor_clk_disable(struct device *dev)
 	for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
 		comp = ovl_adaptor->ovl_adaptor_comp[i];

-		if (i < OVL_ADAPTOR_MERGE0) {
+		if (!comp)
+			continue;
+
+		switch (comp_matches[i].type) {
+		case OVL_ADAPTOR_TYPE_RDMA:
 			mtk_mdp_rdma_clk_disable(comp);
 			pm_runtime_put(comp);
-		} else if (i < OVL_ADAPTOR_ETHDR0) {
+			break;
+		case OVL_ADAPTOR_TYPE_MERGE:
 			mtk_merge_clk_disable(comp);
-		} else {
+			break;
+		case OVL_ADAPTOR_TYPE_ETHDR:
 			mtk_ethdr_clk_disable(comp);
+			break;
+		default:
+			dev_err(dev, "Unknown type: %d\n", comp_matches[i].type);
 		}
 	}
 }
@@ -313,36 +351,26 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device *dev)

 void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex)
 {
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA3);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA4);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA5);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA6);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA7);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE1);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
+	struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+	int i;
+
+	for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
+		if (!ovl_adaptor->ovl_adaptor_comp[i])
+			continue;
+		mtk_mutex_add_comp(mutex, comp_matches[i].comp_id);
+	}
 }

 void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex)
 {
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA3);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA4);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA5);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA6);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA7);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE1);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
+	struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+	int i;
+
+	for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
+		if (!ovl_adaptor->ovl_adaptor_comp[i])
+			continue;
+		mtk_mutex_remove_comp(mutex, comp_matches[i].comp_id);
+	}
 }

 void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsigned int next)
--
2.18.0

[PATCH v2 15/15] drm/mediatek: Support MT8188 VDOSYS1 PADDING in display driver

[Hsiao Chien Sung]

PADDING is a new module on MT8188, it provides ability to VDOSYS1 to
add pixels to width and height of a layer with a specified color.

Since MIXER in VDOSYS1 requires the width of a layer to be
2-pixel-align, or 4-pixel-align when ETHDR is enabled,
we need PADDING to deal with odd width.

Please notice that even if the PADDING is in bypass mode,
settings in the registers must be cleared to 0,
or undefined behaviors could happen.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/Makefile             |   3 +-
 drivers/gpu/drm/mediatek/mtk_disp_drv.h       |   3 +
 .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c   |  42 +++++-
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   2 +-
 drivers/gpu/drm/mediatek/mtk_padding.c        | 127 ++++++++++++++++++
 6 files changed, 175 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_padding.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index d4d193f60271..5e4436403b8d 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -16,7 +16,8 @@ mediatek-drm-y := mtk_disp_aal.o \
 		  mtk_dsi.o \
 		  mtk_dpi.o \
 		  mtk_ethdr.o \
-		  mtk_mdp_rdma.o
+		  mtk_mdp_rdma.o \
+		  mtk_padding.o

 obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 2254038519e1..f9fdb1268aa5 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -157,4 +157,7 @@ void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
 const u32 *mtk_mdp_rdma_get_formats(struct device *dev);
 size_t mtk_mdp_rdma_get_num_formats(struct device *dev);

+int mtk_padding_clk_enable(struct device *dev);
+void mtk_padding_clk_disable(struct device *dev);
+void mtk_padding_config(struct device *dev, struct cmdq_pkt *cmdq_pkt);
 #endif
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index a5f5a0f8ea85..58db0d4cb5b7 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -26,13 +26,22 @@
 #define MTK_OVL_ADAPTOR_LAYER_NUM 4

 enum mtk_ovl_adaptor_comp_type {
-	OVL_ADAPTOR_TYPE_RDMA = 0,
+	OVL_ADAPTOR_TYPE_PADDING,
+	OVL_ADAPTOR_TYPE_RDMA,
 	OVL_ADAPTOR_TYPE_MERGE,
 	OVL_ADAPTOR_TYPE_ETHDR,
 	OVL_ADAPTOR_TYPE_NUM,
 };

 enum mtk_ovl_adaptor_comp_id {
+	OVL_ADAPTOR_PADDING0,
+	OVL_ADAPTOR_PADDING1,
+	OVL_ADAPTOR_PADDING2,
+	OVL_ADAPTOR_PADDING3,
+	OVL_ADAPTOR_PADDING4,
+	OVL_ADAPTOR_PADDING5,
+	OVL_ADAPTOR_PADDING6,
+	OVL_ADAPTOR_PADDING7,
 	OVL_ADAPTOR_MDP_RDMA0,
 	OVL_ADAPTOR_MDP_RDMA1,
 	OVL_ADAPTOR_MDP_RDMA2,
@@ -62,6 +71,7 @@ struct mtk_disp_ovl_adaptor {
 };

 static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
+	[OVL_ADAPTOR_TYPE_PADDING]	= "padding",
 	[OVL_ADAPTOR_TYPE_RDMA]		= "vdo1-rdma",
 	[OVL_ADAPTOR_TYPE_MERGE]	= "merge",
 	[OVL_ADAPTOR_TYPE_ETHDR]	= "ethdr",
@@ -76,6 +86,14 @@ static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
 	[OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA5, 5 },
 	[OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA6, 6 },
 	[OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA7, 7 },
+	[OVL_ADAPTOR_PADDING0] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING0, 0 },
+	[OVL_ADAPTOR_PADDING1] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING1, 1 },
+	[OVL_ADAPTOR_PADDING2] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING2, 2 },
+	[OVL_ADAPTOR_PADDING3] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING3, 3 },
+	[OVL_ADAPTOR_PADDING4] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING4, 4 },
+	[OVL_ADAPTOR_PADDING5] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING5, 5 },
+	[OVL_ADAPTOR_PADDING6] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING6, 6 },
+	[OVL_ADAPTOR_PADDING7] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING7, 7 },
 	[OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1 },
 	[OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2 },
 	[OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3 },
@@ -90,6 +108,8 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
 	struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
 	struct mtk_plane_pending_state *pending = &state->pending;
 	struct mtk_mdp_rdma_cfg rdma_config = {0};
+	struct device *padding_l;
+	struct device *padding_r;
 	struct device *rdma_l;
 	struct device *rdma_r;
 	struct device *merge;
@@ -106,6 +126,8 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
 		&pending->addr, (pending->pitch / fmt_info->cpp[0]),
 		pending->x, pending->y, pending->width, pending->height);

+	padding_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_PADDING0 + 2 * idx];
+	padding_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_PADDING0 + 2 * idx + 1];
 	rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
 	rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
 	merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
@@ -143,10 +165,15 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
 	rdma_config.color_encoding = pending->color_encoding;
 	mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);

+	if (padding_l)
+		mtk_padding_config(padding_l, cmdq_pkt);
+
 	if (use_dual_pipe) {
 		rdma_config.x_left = l_w;
 		rdma_config.width = r_w;
 		mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
+		if (padding_r)
+			mtk_padding_config(padding_r, cmdq_pkt);
 	}

 	mtk_merge_start_cmdq(merge, cmdq_pkt);
@@ -209,6 +236,9 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
 			continue;

 		switch (comp_matches[i].type) {
+		case OVL_ADAPTOR_TYPE_PADDING:
+			ret = mtk_padding_clk_enable(comp);
+			break;
 		case OVL_ADAPTOR_TYPE_RDMA:
 			ret = mtk_mdp_rdma_clk_enable(comp);
 			break;
@@ -238,6 +268,9 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
 			continue;

 		switch (comp_matches[i].type) {
+		case OVL_ADAPTOR_TYPE_PADDING:
+			mtk_padding_clk_disable(comp);
+			break;
 		case OVL_ADAPTOR_TYPE_RDMA:
 			mtk_mdp_rdma_clk_disable(comp);
 			break;
@@ -277,6 +310,10 @@ void mtk_ovl_adaptor_clk_disable(struct device *dev)
 			continue;

 		switch (comp_matches[i].type) {
+		case OVL_ADAPTOR_TYPE_PADDING:
+			mtk_padding_clk_disable(comp);
+			pm_runtime_put(comp);
+			break;
 		case OVL_ADAPTOR_TYPE_RDMA:
 			mtk_mdp_rdma_clk_disable(comp);
 			pm_runtime_put(comp);
@@ -414,6 +451,9 @@ static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,

 static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
 	{
+		.compatible = "mediatek,mt8188-padding",
+		.data = (void *)OVL_ADAPTOR_TYPE_PADDING,
+	}, {
 		.compatible = "mediatek,mt8195-vdo1-rdma",
 		.data = (void *)OVL_ADAPTOR_TYPE_RDMA,
 	}, {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 613093068bb4..ed5b5b8d6c2e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -977,6 +977,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_dsi_driver,
 	&mtk_ethdr_driver,
 	&mtk_mdp_rdma_driver,
+	&mtk_padding_driver,
 };

 static int __init mtk_drm_init(void)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index eb2fd45941f0..562f2db47add 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -64,5 +64,5 @@ extern struct platform_driver mtk_dpi_driver;
 extern struct platform_driver mtk_dsi_driver;
 extern struct platform_driver mtk_ethdr_driver;
 extern struct platform_driver mtk_mdp_rdma_driver;
-
+extern struct platform_driver mtk_padding_driver;
 #endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_padding.c b/drivers/gpu/drm/mediatek/mtk_padding.c
new file mode 100644
index 000000000000..bb32325287f6
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_padding.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2023 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_disp_drv.h"
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+
+struct mtk_padding {
+	struct clk		*clk;
+	void __iomem		*regs;
+	struct cmdq_client_reg	cmdq_reg;
+};
+
+int mtk_padding_clk_enable(struct device *dev)
+{
+	struct mtk_padding *padding = dev_get_drvdata(dev);
+
+	return clk_prepare_enable(padding->clk);
+}
+
+void mtk_padding_clk_disable(struct device *dev)
+{
+	struct mtk_padding *padding = dev_get_drvdata(dev);
+
+	clk_disable_unprepare(padding->clk);
+}
+
+void mtk_padding_config(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_padding *padding = dev_get_drvdata(dev);
+
+	/* bypass padding */
+	mtk_ddp_write_mask(cmdq_pkt, GENMASK(1, 0), &padding->cmdq_reg, padding->regs, 0,
+			   GENMASK(1, 0));
+}
+
+static int mtk_padding_bind(struct device *dev, struct device *master, void *data)
+{
+	return 0;
+}
+
+static void mtk_padding_unbind(struct device *dev, struct device *master, void *data)
+{
+}
+
+static const struct component_ops mtk_padding_component_ops = {
+	.bind	= mtk_padding_bind,
+	.unbind = mtk_padding_unbind,
+};
+
+static int mtk_padding_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct mtk_padding *priv;
+	struct resource *res;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "failed to get clk\n");
+		return PTR_ERR(priv->clk);
+	}
+
+	priv->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+	if (IS_ERR(priv->regs)) {
+		dev_err(dev, "failed to do ioremap\n");
+		return PTR_ERR(priv->regs);
+	}
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+	if (ret) {
+		dev_err(dev, "failed to get gce client reg\n");
+		return ret;
+	}
+#endif
+
+	platform_set_drvdata(pdev, priv);
+
+	ret = devm_pm_runtime_enable(dev);
+	if (ret)
+		return ret;
+
+	ret = component_add(dev, &mtk_padding_component_ops);
+	if (ret) {
+		pm_runtime_disable(dev);
+		return dev_err_probe(dev, ret, "failed to add component\n");
+	}
+
+	return 0;
+}
+
+static int mtk_padding_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &mtk_padding_component_ops);
+	return 0;
+}
+
+static const struct of_device_id mtk_padding_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8188-padding" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mtk_padding_driver_dt_match);
+
+struct platform_driver mtk_padding_driver = {
+	.probe		= mtk_padding_probe,
+	.remove		= mtk_padding_remove,
+	.driver		= {
+		.name	= "mediatek-disp-padding",
+		.owner	= THIS_MODULE,
+		.of_match_table = mtk_padding_driver_dt_match,
+	},
+};
--
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 15/15] drm/mediatek: Support MT8188 VDOSYS1 PADDING in display driver

[Hsiao Chien Sung]

PADDING is a new module on MT8188, it provides ability to VDOSYS1 to
add pixels to width and height of a layer with a specified color.

Since MIXER in VDOSYS1 requires the width of a layer to be
2-pixel-align, or 4-pixel-align when ETHDR is enabled,
we need PADDING to deal with odd width.

Please notice that even if the PADDING is in bypass mode,
settings in the registers must be cleared to 0,
or undefined behaviors could happen.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/Makefile             |   3 +-
 drivers/gpu/drm/mediatek/mtk_disp_drv.h       |   3 +
 .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c   |  42 +++++-
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   2 +-
 drivers/gpu/drm/mediatek/mtk_padding.c        | 127 ++++++++++++++++++
 6 files changed, 175 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_padding.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index d4d193f60271..5e4436403b8d 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -16,7 +16,8 @@ mediatek-drm-y := mtk_disp_aal.o \
 		  mtk_dsi.o \
 		  mtk_dpi.o \
 		  mtk_ethdr.o \
-		  mtk_mdp_rdma.o
+		  mtk_mdp_rdma.o \
+		  mtk_padding.o

 obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 2254038519e1..f9fdb1268aa5 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -157,4 +157,7 @@ void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
 const u32 *mtk_mdp_rdma_get_formats(struct device *dev);
 size_t mtk_mdp_rdma_get_num_formats(struct device *dev);

+int mtk_padding_clk_enable(struct device *dev);
+void mtk_padding_clk_disable(struct device *dev);
+void mtk_padding_config(struct device *dev, struct cmdq_pkt *cmdq_pkt);
 #endif
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index a5f5a0f8ea85..58db0d4cb5b7 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -26,13 +26,22 @@
 #define MTK_OVL_ADAPTOR_LAYER_NUM 4

 enum mtk_ovl_adaptor_comp_type {
-	OVL_ADAPTOR_TYPE_RDMA = 0,
+	OVL_ADAPTOR_TYPE_PADDING,
+	OVL_ADAPTOR_TYPE_RDMA,
 	OVL_ADAPTOR_TYPE_MERGE,
 	OVL_ADAPTOR_TYPE_ETHDR,
 	OVL_ADAPTOR_TYPE_NUM,
 };

 enum mtk_ovl_adaptor_comp_id {
+	OVL_ADAPTOR_PADDING0,
+	OVL_ADAPTOR_PADDING1,
+	OVL_ADAPTOR_PADDING2,
+	OVL_ADAPTOR_PADDING3,
+	OVL_ADAPTOR_PADDING4,
+	OVL_ADAPTOR_PADDING5,
+	OVL_ADAPTOR_PADDING6,
+	OVL_ADAPTOR_PADDING7,
 	OVL_ADAPTOR_MDP_RDMA0,
 	OVL_ADAPTOR_MDP_RDMA1,
 	OVL_ADAPTOR_MDP_RDMA2,
@@ -62,6 +71,7 @@ struct mtk_disp_ovl_adaptor {
 };

 static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
+	[OVL_ADAPTOR_TYPE_PADDING]	= "padding",
 	[OVL_ADAPTOR_TYPE_RDMA]		= "vdo1-rdma",
 	[OVL_ADAPTOR_TYPE_MERGE]	= "merge",
 	[OVL_ADAPTOR_TYPE_ETHDR]	= "ethdr",
@@ -76,6 +86,14 @@ static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
 	[OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA5, 5 },
 	[OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA6, 6 },
 	[OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA7, 7 },
+	[OVL_ADAPTOR_PADDING0] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING0, 0 },
+	[OVL_ADAPTOR_PADDING1] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING1, 1 },
+	[OVL_ADAPTOR_PADDING2] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING2, 2 },
+	[OVL_ADAPTOR_PADDING3] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING3, 3 },
+	[OVL_ADAPTOR_PADDING4] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING4, 4 },
+	[OVL_ADAPTOR_PADDING5] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING5, 5 },
+	[OVL_ADAPTOR_PADDING6] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING6, 6 },
+	[OVL_ADAPTOR_PADDING7] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING7, 7 },
 	[OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1 },
 	[OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2 },
 	[OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3 },
@@ -90,6 +108,8 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
 	struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
 	struct mtk_plane_pending_state *pending = &state->pending;
 	struct mtk_mdp_rdma_cfg rdma_config = {0};
+	struct device *padding_l;
+	struct device *padding_r;
 	struct device *rdma_l;
 	struct device *rdma_r;
 	struct device *merge;
@@ -106,6 +126,8 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
 		&pending->addr, (pending->pitch / fmt_info->cpp[0]),
 		pending->x, pending->y, pending->width, pending->height);

+	padding_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_PADDING0 + 2 * idx];
+	padding_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_PADDING0 + 2 * idx + 1];
 	rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
 	rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
 	merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
@@ -143,10 +165,15 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
 	rdma_config.color_encoding = pending->color_encoding;
 	mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);

+	if (padding_l)
+		mtk_padding_config(padding_l, cmdq_pkt);
+
 	if (use_dual_pipe) {
 		rdma_config.x_left = l_w;
 		rdma_config.width = r_w;
 		mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
+		if (padding_r)
+			mtk_padding_config(padding_r, cmdq_pkt);
 	}

 	mtk_merge_start_cmdq(merge, cmdq_pkt);
@@ -209,6 +236,9 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
 			continue;

 		switch (comp_matches[i].type) {
+		case OVL_ADAPTOR_TYPE_PADDING:
+			ret = mtk_padding_clk_enable(comp);
+			break;
 		case OVL_ADAPTOR_TYPE_RDMA:
 			ret = mtk_mdp_rdma_clk_enable(comp);
 			break;
@@ -238,6 +268,9 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
 			continue;

 		switch (comp_matches[i].type) {
+		case OVL_ADAPTOR_TYPE_PADDING:
+			mtk_padding_clk_disable(comp);
+			break;
 		case OVL_ADAPTOR_TYPE_RDMA:
 			mtk_mdp_rdma_clk_disable(comp);
 			break;
@@ -277,6 +310,10 @@ void mtk_ovl_adaptor_clk_disable(struct device *dev)
 			continue;

 		switch (comp_matches[i].type) {
+		case OVL_ADAPTOR_TYPE_PADDING:
+			mtk_padding_clk_disable(comp);
+			pm_runtime_put(comp);
+			break;
 		case OVL_ADAPTOR_TYPE_RDMA:
 			mtk_mdp_rdma_clk_disable(comp);
 			pm_runtime_put(comp);
@@ -414,6 +451,9 @@ static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,

 static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
 	{
+		.compatible = "mediatek,mt8188-padding",
+		.data = (void *)OVL_ADAPTOR_TYPE_PADDING,
+	}, {
 		.compatible = "mediatek,mt8195-vdo1-rdma",
 		.data = (void *)OVL_ADAPTOR_TYPE_RDMA,
 	}, {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 613093068bb4..ed5b5b8d6c2e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -977,6 +977,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_dsi_driver,
 	&mtk_ethdr_driver,
 	&mtk_mdp_rdma_driver,
+	&mtk_padding_driver,
 };

 static int __init mtk_drm_init(void)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index eb2fd45941f0..562f2db47add 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -64,5 +64,5 @@ extern struct platform_driver mtk_dpi_driver;
 extern struct platform_driver mtk_dsi_driver;
 extern struct platform_driver mtk_ethdr_driver;
 extern struct platform_driver mtk_mdp_rdma_driver;
-
+extern struct platform_driver mtk_padding_driver;
 #endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_padding.c b/drivers/gpu/drm/mediatek/mtk_padding.c
new file mode 100644
index 000000000000..bb32325287f6
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_padding.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2023 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_disp_drv.h"
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+
+struct mtk_padding {
+	struct clk		*clk;
+	void __iomem		*regs;
+	struct cmdq_client_reg	cmdq_reg;
+};
+
+int mtk_padding_clk_enable(struct device *dev)
+{
+	struct mtk_padding *padding = dev_get_drvdata(dev);
+
+	return clk_prepare_enable(padding->clk);
+}
+
+void mtk_padding_clk_disable(struct device *dev)
+{
+	struct mtk_padding *padding = dev_get_drvdata(dev);
+
+	clk_disable_unprepare(padding->clk);
+}
+
+void mtk_padding_config(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_padding *padding = dev_get_drvdata(dev);
+
+	/* bypass padding */
+	mtk_ddp_write_mask(cmdq_pkt, GENMASK(1, 0), &padding->cmdq_reg, padding->regs, 0,
+			   GENMASK(1, 0));
+}
+
+static int mtk_padding_bind(struct device *dev, struct device *master, void *data)
+{
+	return 0;
+}
+
+static void mtk_padding_unbind(struct device *dev, struct device *master, void *data)
+{
+}
+
+static const struct component_ops mtk_padding_component_ops = {
+	.bind	= mtk_padding_bind,
+	.unbind = mtk_padding_unbind,
+};
+
+static int mtk_padding_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct mtk_padding *priv;
+	struct resource *res;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "failed to get clk\n");
+		return PTR_ERR(priv->clk);
+	}
+
+	priv->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+	if (IS_ERR(priv->regs)) {
+		dev_err(dev, "failed to do ioremap\n");
+		return PTR_ERR(priv->regs);
+	}
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+	if (ret) {
+		dev_err(dev, "failed to get gce client reg\n");
+		return ret;
+	}
+#endif
+
+	platform_set_drvdata(pdev, priv);
+
+	ret = devm_pm_runtime_enable(dev);
+	if (ret)
+		return ret;
+
+	ret = component_add(dev, &mtk_padding_component_ops);
+	if (ret) {
+		pm_runtime_disable(dev);
+		return dev_err_probe(dev, ret, "failed to add component\n");
+	}
+
+	return 0;
+}
+
+static int mtk_padding_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &mtk_padding_component_ops);
+	return 0;
+}
+
+static const struct of_device_id mtk_padding_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8188-padding" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mtk_padding_driver_dt_match);
+
+struct platform_driver mtk_padding_driver = {
+	.probe		= mtk_padding_probe,
+	.remove		= mtk_padding_remove,
+	.driver		= {
+		.name	= "mediatek-disp-padding",
+		.owner	= THIS_MODULE,
+		.of_match_table = mtk_padding_driver_dt_match,
+	},
+};
--
2.18.0