Re: [PATCH v3 1/3] arm: handle demuxed ID registers

[Eric Auger <eauger@redhat.com>]

On 6/22/26 3:56 PM, Sebastian Ott wrote:
> From: Cornelia Huck <cohuck@redhat.com>
> 
> For some registers, we do not have a single ID register, but actually
> an array of values (e.g. CCSIDR_EL1, where the actual value is
> determined by whatever CSSELR_EL1 points to.) If we want to avoid
> using a different way to handle registers like that for every
> instance, we should provide some kind of infrastructure. Therefore,
> add accessors {GET,SET}_IDREG_DEMUX that are similar to the accessors
> we already use for regular ID registers.
> 
> Tested-by: Alireza Sanaee <alireza.sanaee@huawei.com>
> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
> Signed-off-by: Sebastian Ott <sebott@redhat.com>

With actual implementation
Suggested-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Eric Auger <eric.auger@redhat.com>

Eric

> ---
>  target/arm/cpu-sysregs.h |  9 +++++++++
>  target/arm/cpu.h         | 12 ++++++++++++
>  target/arm/cpu64.c       |  8 ++++++++
>  3 files changed, 29 insertions(+)
> 
> diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h
> index 7877a3b06a..a4b9621a7e 100644
> --- a/target/arm/cpu-sysregs.h
> +++ b/target/arm/cpu-sysregs.h
> @@ -20,20 +20,29 @@
>  
>  #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) NAME##_IDX,
>  
> +#define DEF_MUX(NAME, OP0, OP1, CRN, CRM, OP2, NUM)     \
> +    NAME##_IDX,                                         \
> +    NAME##_IDX_LAST = NAME##_IDX + NUM - 1,
> +
>  typedef enum ARMIDRegisterIdx {
>  #include "cpu-sysregs.h.inc"
>      NUM_ID_IDX,
>  } ARMIDRegisterIdx;
>  
>  #undef DEF
> +#undef DEF_MUX
>  #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \
>      SYS_##NAME = ENCODE_ID_REG(OP0, OP1, CRN, CRM, OP2),
>  
> +#define DEF_MUX(NAME, OP0, OP1, CRN, CRM, OP2, NUM)     \
> +    DEF(NAME, OP0, OP1, CRN, CRM, OP2)
> +
>  typedef enum ARMSysRegs {
>  #include "cpu-sysregs.h.inc"
>  } ARMSysRegs;
>  
>  #undef DEF
> +#undef DEF_MUX
>  
>  extern const uint32_t id_register_sysreg[NUM_ID_IDX];
>  
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 31a5567c95..fe0046b02e 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -919,6 +919,18 @@ typedef struct {
>          i_->idregs[REG ## _EL1_IDX];                                    \
>      })
>  
> +#define SET_IDREG_DEMUX(ISAR, REG, INDEX, VALUE)                        \
> +    ({                                                                  \
> +        ARMISARegisters *i_ = (ISAR);                                   \
> +        i_->idregs[REG ## _IDX + INDEX] = VALUE;                        \
> +    })
> +
> +#define GET_IDREG_DEMUX(ISAR, REG, INDEX)                               \
> +    ({                                                                  \
> +        ARMISARegisters *i_ = (ISAR);                                   \
> +        i_->idregs[REG ## _IDX + INDEX];                                \
> +    })
> +
>  /**
>   * ARMCPU:
>   * @env: #CPUARMState
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 2816735577..48a0421674 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -42,14 +42,21 @@
>  #define DEF(NAME, OP0, OP1, CRN, CRM, OP2)      \
>      [NAME##_IDX] = SYS_##NAME,
>  
> +#define DEF_MUX(NAME, OP0, OP1, CRN, CRM, OP2, NUM)     \
> +    DEF(NAME, OP0, OP1, CRN, CRM, OP2)
> +
>  const uint32_t id_register_sysreg[NUM_ID_IDX] = {
>  #include "cpu-sysregs.h.inc"
>  };
>  
>  #undef DEF
> +#undef DEF_MUX
>  #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \
>      case SYS_##NAME: return NAME##_IDX;
>  
> +#define DEF_MUX(NAME, OP0, OP1, CRN, CRM, OP2, NUM)     \
> +    DEF(NAME, OP0, OP1, CRN, CRM, OP2)
> +
>  int get_sysreg_idx(ARMSysRegs sysreg)
>  {
>      switch (sysreg) {
> @@ -59,6 +66,7 @@ int get_sysreg_idx(ARMSysRegs sysreg)
>  }
>  
>  #undef DEF
> +#undef DEF_MUX
>  
>  void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
>  {