[Intel-gfx] [PATCH 0/6] drm/dsc, drm/dp, and /drm/i915: rc model size updates

[Intel-gfx] [PATCH 0/6] drm/dsc, drm/dp, and /drm/i915: rc model size updates

[Jani Nikula]

For whatever reason this old series was never merged. Please let's get
this done.

For i915 DP this still needs a patch to start using the model size from
DPCD.

BR,
Jani.

Jani Nikula (6):
  drm/dsc: use rc_model_size from DSC config for PPS
  drm/i915/dsc: configure hardware using specified rc_model_size
  drm/i915/dsc: make rc_model_size an encoder defined value
  drm/dsc: add helper for calculating rc buffer size from DPCD
  drm/i915/bios: fill in DSC rc_model_size from VBT
  drm/i915/dsi: use VBT data for rc_model_size

 drivers/gpu/drm/drm_dsc.c                 | 30 +++++++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_bios.c | 11 +++------
 drivers/gpu/drm/i915/display/intel_dp.c   |  8 ++++++
 drivers/gpu/drm/i915/display/intel_vdsc.c |  4 +--
 include/drm/drm_dsc.h                     |  1 +
 5 files changed, 41 insertions(+), 13 deletions(-)

-- 
2.20.1

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[PATCH 0/6] drm/dsc, drm/dp, and /drm/i915: rc model size updates

[Jani Nikula]

For whatever reason this old series was never merged. Please let's get
this done.

For i915 DP this still needs a patch to start using the model size from
DPCD.

BR,
Jani.

Jani Nikula (6):
  drm/dsc: use rc_model_size from DSC config for PPS
  drm/i915/dsc: configure hardware using specified rc_model_size
  drm/i915/dsc: make rc_model_size an encoder defined value
  drm/dsc: add helper for calculating rc buffer size from DPCD
  drm/i915/bios: fill in DSC rc_model_size from VBT
  drm/i915/dsi: use VBT data for rc_model_size

 drivers/gpu/drm/drm_dsc.c                 | 30 +++++++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_bios.c | 11 +++------
 drivers/gpu/drm/i915/display/intel_dp.c   |  8 ++++++
 drivers/gpu/drm/i915/display/intel_vdsc.c |  4 +--
 include/drm/drm_dsc.h                     |  1 +
 5 files changed, 41 insertions(+), 13 deletions(-)

-- 
2.20.1

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[Intel-gfx] [PATCH 1/6] drm/dsc: use rc_model_size from DSC config for PPS

[Jani Nikula]

The PPS is supposed to reflect the DSC config instead of hard coding the
rc_model_size. Make it so.

Currently all users of drm_dsc_pps_payload_pack() hard code the size to
8192 also in the DSC config, so this change should have no impact, other
than allowing the drivers to use other sizes as needed.

Cc: Alex Deucher <alexdeucher@gmail.com>
Cc: Harry Wentland <hwentlan@amd.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/drm_dsc.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
index 4a475d9696ff..09afbc01ea94 100644
--- a/drivers/gpu/drm/drm_dsc.c
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -186,8 +186,7 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
 	pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp;
 
 	/* PPS 38, 39 */
-	pps_payload->rc_model_size =
-		cpu_to_be16(DSC_RC_MODEL_SIZE_CONST);
+	pps_payload->rc_model_size = cpu_to_be16(dsc_cfg->rc_model_size);
 
 	/* PPS 40 */
 	pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
-- 
2.20.1

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[PATCH 1/6] drm/dsc: use rc_model_size from DSC config for PPS

[Jani Nikula]

The PPS is supposed to reflect the DSC config instead of hard coding the
rc_model_size. Make it so.

Currently all users of drm_dsc_pps_payload_pack() hard code the size to
8192 also in the DSC config, so this change should have no impact, other
than allowing the drivers to use other sizes as needed.

Cc: Alex Deucher <alexdeucher@gmail.com>
Cc: Harry Wentland <hwentlan@amd.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/drm_dsc.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
index 4a475d9696ff..09afbc01ea94 100644
--- a/drivers/gpu/drm/drm_dsc.c
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -186,8 +186,7 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
 	pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp;
 
 	/* PPS 38, 39 */
-	pps_payload->rc_model_size =
-		cpu_to_be16(DSC_RC_MODEL_SIZE_CONST);
+	pps_payload->rc_model_size = cpu_to_be16(dsc_cfg->rc_model_size);
 
 	/* PPS 40 */
 	pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
-- 
2.20.1

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[Intel-gfx] [PATCH 2/6] drm/i915/dsc: configure hardware using specified rc_model_size

[Jani Nikula]

The rc_model_size is specified in the DSC config, and the hardware
programming should respect that instead of hard coding a value of 8192.

Regardless, the rc_model_size in DSC config is currently hard coded to
the same value, so this should have no impact, other than allowing the
use of other sizes as needed.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index e2716a67b281..22d08679844f 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -741,7 +741,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 
 	/* Populate PICTURE_PARAMETER_SET_9 registers */
 	pps_val = 0;
-	pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) |
+	pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
 		DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
 	drm_info(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
 	if (!is_pipe_dsc(crtc_state)) {
-- 
2.20.1

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[PATCH 2/6] drm/i915/dsc: configure hardware using specified rc_model_size

[Jani Nikula]

The rc_model_size is specified in the DSC config, and the hardware
programming should respect that instead of hard coding a value of 8192.

Regardless, the rc_model_size in DSC config is currently hard coded to
the same value, so this should have no impact, other than allowing the
use of other sizes as needed.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index e2716a67b281..22d08679844f 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -741,7 +741,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 
 	/* Populate PICTURE_PARAMETER_SET_9 registers */
 	pps_val = 0;
-	pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) |
+	pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
 		DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
 	drm_info(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
 	if (!is_pipe_dsc(crtc_state)) {
-- 
2.20.1

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[Intel-gfx] [PATCH 3/6] drm/i915/dsc: make rc_model_size an encoder defined value

[Jani Nikula]

Move the intialization of the rc_model_size from the common code into
encoder code, allowing different encoders to specify the size according
to their needs. Keep using the hard coded value in the encoders for now
to make this a non-functional change.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c    | 3 +++
 drivers/gpu/drm/i915/display/intel_dp.c   | 8 ++++++++
 drivers/gpu/drm/i915/display/intel_vdsc.c | 2 --
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index a9439b415603..676e40172fe9 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1535,6 +1535,9 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
 
 	vdsc_cfg->convert_rgb = true;
 
+	/* FIXME: initialize from VBT */
+	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
+
 	ret = intel_dsc_compute_params(encoder, crtc_state);
 	if (ret)
 		return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index cb5e42c3ecd5..b2bc0c8c39c7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2289,6 +2289,14 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
 	u8 line_buf_depth;
 	int ret;
 
+	/*
+	 * RC_MODEL_SIZE is currently a constant across all configurations.
+	 *
+	 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
+	 * DP_DSC_RC_BUF_SIZE for this.
+	 */
+	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
+
 	ret = intel_dsc_compute_params(encoder, crtc_state);
 	if (ret)
 		return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 22d08679844f..f58cc5700784 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -454,8 +454,6 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
 	else if (vdsc_cfg->bits_per_component == 12)
 		vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
 
-	/* RC_MODEL_SIZE is a constant across all configurations */
-	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
 	/* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
 	vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
 		(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
-- 
2.20.1

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[PATCH 3/6] drm/i915/dsc: make rc_model_size an encoder defined value

[Jani Nikula]

Move the intialization of the rc_model_size from the common code into
encoder code, allowing different encoders to specify the size according
to their needs. Keep using the hard coded value in the encoders for now
to make this a non-functional change.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c    | 3 +++
 drivers/gpu/drm/i915/display/intel_dp.c   | 8 ++++++++
 drivers/gpu/drm/i915/display/intel_vdsc.c | 2 --
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index a9439b415603..676e40172fe9 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1535,6 +1535,9 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
 
 	vdsc_cfg->convert_rgb = true;
 
+	/* FIXME: initialize from VBT */
+	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
+
 	ret = intel_dsc_compute_params(encoder, crtc_state);
 	if (ret)
 		return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index cb5e42c3ecd5..b2bc0c8c39c7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2289,6 +2289,14 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
 	u8 line_buf_depth;
 	int ret;
 
+	/*
+	 * RC_MODEL_SIZE is currently a constant across all configurations.
+	 *
+	 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
+	 * DP_DSC_RC_BUF_SIZE for this.
+	 */
+	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
+
 	ret = intel_dsc_compute_params(encoder, crtc_state);
 	if (ret)
 		return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 22d08679844f..f58cc5700784 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -454,8 +454,6 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
 	else if (vdsc_cfg->bits_per_component == 12)
 		vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
 
-	/* RC_MODEL_SIZE is a constant across all configurations */
-	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
 	/* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
 	vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
 		(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
-- 
2.20.1

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Re: [Intel-gfx] [PATCH 3/6] drm/i915/dsc: make rc_model_size an encoder defined value

[Navare, Manasi]

On Tue, Dec 08, 2020 at 02:33:52PM +0200, Jani Nikula wrote:
> Move the intialization of the rc_model_size from the common code into
> encoder code, allowing different encoders to specify the size according
> to their needs. Keep using the hard coded value in the encoders for now
> to make this a non-functional change.
> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

So still using the hardcoded value since thats in the DSC C model, Looks good to me

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c    | 3 +++
>  drivers/gpu/drm/i915/display/intel_dp.c   | 8 ++++++++
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 2 --
>  3 files changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index a9439b415603..676e40172fe9 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1535,6 +1535,9 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
>  
>  	vdsc_cfg->convert_rgb = true;
>  
> +	/* FIXME: initialize from VBT */
> +	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
> +
>  	ret = intel_dsc_compute_params(encoder, crtc_state);
>  	if (ret)
>  		return ret;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index cb5e42c3ecd5..b2bc0c8c39c7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2289,6 +2289,14 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
>  	u8 line_buf_depth;
>  	int ret;
>  
> +	/*
> +	 * RC_MODEL_SIZE is currently a constant across all configurations.
> +	 *
> +	 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
> +	 * DP_DSC_RC_BUF_SIZE for this.
> +	 */
> +	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
> +
>  	ret = intel_dsc_compute_params(encoder, crtc_state);
>  	if (ret)
>  		return ret;
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 22d08679844f..f58cc5700784 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -454,8 +454,6 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
>  	else if (vdsc_cfg->bits_per_component == 12)
>  		vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
>  
> -	/* RC_MODEL_SIZE is a constant across all configurations */
> -	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
>  	/* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
>  	vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
>  		(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
> -- 
> 2.20.1
> 
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Re: [PATCH 3/6] drm/i915/dsc: make rc_model_size an encoder defined value

[Navare, Manasi]

On Tue, Dec 08, 2020 at 02:33:52PM +0200, Jani Nikula wrote:
> Move the intialization of the rc_model_size from the common code into
> encoder code, allowing different encoders to specify the size according
> to their needs. Keep using the hard coded value in the encoders for now
> to make this a non-functional change.
> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

So still using the hardcoded value since thats in the DSC C model, Looks good to me

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c    | 3 +++
>  drivers/gpu/drm/i915/display/intel_dp.c   | 8 ++++++++
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 2 --
>  3 files changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index a9439b415603..676e40172fe9 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1535,6 +1535,9 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
>  
>  	vdsc_cfg->convert_rgb = true;
>  
> +	/* FIXME: initialize from VBT */
> +	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
> +
>  	ret = intel_dsc_compute_params(encoder, crtc_state);
>  	if (ret)
>  		return ret;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index cb5e42c3ecd5..b2bc0c8c39c7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2289,6 +2289,14 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
>  	u8 line_buf_depth;
>  	int ret;
>  
> +	/*
> +	 * RC_MODEL_SIZE is currently a constant across all configurations.
> +	 *
> +	 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
> +	 * DP_DSC_RC_BUF_SIZE for this.
> +	 */
> +	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
> +
>  	ret = intel_dsc_compute_params(encoder, crtc_state);
>  	if (ret)
>  		return ret;
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 22d08679844f..f58cc5700784 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -454,8 +454,6 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
>  	else if (vdsc_cfg->bits_per_component == 12)
>  		vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
>  
> -	/* RC_MODEL_SIZE is a constant across all configurations */
> -	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
>  	/* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
>  	vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
>  		(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
> -- 
> 2.20.1
> 
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[Intel-gfx] [PATCH 4/6] drm/dsc: add helper for calculating rc buffer size from DPCD

[Jani Nikula]

Add a helper for calculating the rc buffer size from the DCPD offsets
DP_DSC_RC_BUF_BLK_SIZE and DP_DSC_RC_BUF_SIZE.

Cc: Alex Deucher <alexdeucher@gmail.com>
Cc: Harry Wentland <hwentlan@amd.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/drm_dsc.c | 27 +++++++++++++++++++++++++++
 include/drm/drm_dsc.h     |  1 +
 2 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
index 09afbc01ea94..ff602f7ec65b 100644
--- a/drivers/gpu/drm/drm_dsc.c
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -49,6 +49,33 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header)
 }
 EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
 
+/**
+ * drm_dsc_dp_rc_buffer_size - get rc buffer size in bytes
+ * @rc_buffer_block_size: block size code, according to DPCD offset 62h
+ * @rc_buffer_size: number of blocks - 1, according to DPCD offset 63h
+ *
+ * return:
+ * buffer size in bytes, or 0 on invalid input
+ */
+int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size)
+{
+	int size = 1024 * (rc_buffer_size + 1);
+
+	switch (rc_buffer_block_size) {
+	case DP_DSC_RC_BUF_BLK_SIZE_1:
+		return 1 * size;
+	case DP_DSC_RC_BUF_BLK_SIZE_4:
+		return 4 * size;
+	case DP_DSC_RC_BUF_BLK_SIZE_16:
+		return 16 * size;
+	case DP_DSC_RC_BUF_BLK_SIZE_64:
+		return 64 * size;
+	default:
+		return 0;
+	}
+}
+EXPORT_SYMBOL(drm_dsc_dp_rc_buffer_size);
+
 /**
  * drm_dsc_pps_payload_pack() - Populates the DSC PPS
  *
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 53c51231b31c..cf43561e60fa 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -603,6 +603,7 @@ struct drm_dsc_pps_infoframe {
 } __packed;
 
 void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
+int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
 void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
 				const struct drm_dsc_config *dsc_cfg);
 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
-- 
2.20.1

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[PATCH 4/6] drm/dsc: add helper for calculating rc buffer size from DPCD

[Jani Nikula]

Add a helper for calculating the rc buffer size from the DCPD offsets
DP_DSC_RC_BUF_BLK_SIZE and DP_DSC_RC_BUF_SIZE.

Cc: Alex Deucher <alexdeucher@gmail.com>
Cc: Harry Wentland <hwentlan@amd.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/drm_dsc.c | 27 +++++++++++++++++++++++++++
 include/drm/drm_dsc.h     |  1 +
 2 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
index 09afbc01ea94..ff602f7ec65b 100644
--- a/drivers/gpu/drm/drm_dsc.c
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -49,6 +49,33 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header)
 }
 EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
 
+/**
+ * drm_dsc_dp_rc_buffer_size - get rc buffer size in bytes
+ * @rc_buffer_block_size: block size code, according to DPCD offset 62h
+ * @rc_buffer_size: number of blocks - 1, according to DPCD offset 63h
+ *
+ * return:
+ * buffer size in bytes, or 0 on invalid input
+ */
+int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size)
+{
+	int size = 1024 * (rc_buffer_size + 1);
+
+	switch (rc_buffer_block_size) {
+	case DP_DSC_RC_BUF_BLK_SIZE_1:
+		return 1 * size;
+	case DP_DSC_RC_BUF_BLK_SIZE_4:
+		return 4 * size;
+	case DP_DSC_RC_BUF_BLK_SIZE_16:
+		return 16 * size;
+	case DP_DSC_RC_BUF_BLK_SIZE_64:
+		return 64 * size;
+	default:
+		return 0;
+	}
+}
+EXPORT_SYMBOL(drm_dsc_dp_rc_buffer_size);
+
 /**
  * drm_dsc_pps_payload_pack() - Populates the DSC PPS
  *
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 53c51231b31c..cf43561e60fa 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -603,6 +603,7 @@ struct drm_dsc_pps_infoframe {
 } __packed;
 
 void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
+int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
 void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
 				const struct drm_dsc_config *dsc_cfg);
 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
-- 
2.20.1

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[Intel-gfx] [PATCH 5/6] drm/i915/bios: fill in DSC rc_model_size from VBT

[Jani Nikula]

The VBT fields match the DPCD data, so use the same helper.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 4cc949b228f2..06c3310446a2 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2555,16 +2555,11 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
 			      crtc_state->dsc.slice_count);
 
 	/*
-	 * FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the
-	 * implementation specific physical rate buffer size. Currently we use
-	 * the required rate buffer model size calculated in
-	 * drm_dsc_compute_rc_parameters() according to VESA DSC Annex E.
-	 *
 	 * The VBT rc_buffer_block_size and rc_buffer_size definitions
-	 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC
-	 * implementation should also use the DPCD (or perhaps VBT for eDP)
-	 * provided value for the buffer size.
+	 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63.
 	 */
+	vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size,
+							    dsc->rc_buffer_size);
 
 	/* FIXME: DSI spec says bpc + 1 for this one */
 	vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);
-- 
2.20.1

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[PATCH 5/6] drm/i915/bios: fill in DSC rc_model_size from VBT

[Jani Nikula]

The VBT fields match the DPCD data, so use the same helper.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 4cc949b228f2..06c3310446a2 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2555,16 +2555,11 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
 			      crtc_state->dsc.slice_count);
 
 	/*
-	 * FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the
-	 * implementation specific physical rate buffer size. Currently we use
-	 * the required rate buffer model size calculated in
-	 * drm_dsc_compute_rc_parameters() according to VESA DSC Annex E.
-	 *
 	 * The VBT rc_buffer_block_size and rc_buffer_size definitions
-	 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC
-	 * implementation should also use the DPCD (or perhaps VBT for eDP)
-	 * provided value for the buffer size.
+	 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63.
 	 */
+	vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size,
+							    dsc->rc_buffer_size);
 
 	/* FIXME: DSI spec says bpc + 1 for this one */
 	vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);
-- 
2.20.1

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Re: [Intel-gfx] [PATCH 5/6] drm/i915/bios: fill in DSC rc_model_size from VBT

[Navare, Manasi]

On Tue, Dec 08, 2020 at 02:33:54PM +0200, Jani Nikula wrote:
> The VBT fields match the DPCD data, so use the same helper.
> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Only for DSI so far right?

In that case looks good

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_bios.c | 11 +++--------
>  1 file changed, 3 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 4cc949b228f2..06c3310446a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2555,16 +2555,11 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
>  			      crtc_state->dsc.slice_count);
>  
>  	/*
> -	 * FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the
> -	 * implementation specific physical rate buffer size. Currently we use
> -	 * the required rate buffer model size calculated in
> -	 * drm_dsc_compute_rc_parameters() according to VESA DSC Annex E.
> -	 *
>  	 * The VBT rc_buffer_block_size and rc_buffer_size definitions
> -	 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC
> -	 * implementation should also use the DPCD (or perhaps VBT for eDP)
> -	 * provided value for the buffer size.
> +	 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63.
>  	 */
> +	vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size,
> +							    dsc->rc_buffer_size);
>  
>  	/* FIXME: DSI spec says bpc + 1 for this one */
>  	vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);
> -- 
> 2.20.1
> 
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Re: [PATCH 5/6] drm/i915/bios: fill in DSC rc_model_size from VBT

[Navare, Manasi]

On Tue, Dec 08, 2020 at 02:33:54PM +0200, Jani Nikula wrote:
> The VBT fields match the DPCD data, so use the same helper.
> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Only for DSI so far right?

In that case looks good

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_bios.c | 11 +++--------
>  1 file changed, 3 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 4cc949b228f2..06c3310446a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2555,16 +2555,11 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
>  			      crtc_state->dsc.slice_count);
>  
>  	/*
> -	 * FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the
> -	 * implementation specific physical rate buffer size. Currently we use
> -	 * the required rate buffer model size calculated in
> -	 * drm_dsc_compute_rc_parameters() according to VESA DSC Annex E.
> -	 *
>  	 * The VBT rc_buffer_block_size and rc_buffer_size definitions
> -	 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC
> -	 * implementation should also use the DPCD (or perhaps VBT for eDP)
> -	 * provided value for the buffer size.
> +	 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63.
>  	 */
> +	vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size,
> +							    dsc->rc_buffer_size);
>  
>  	/* FIXME: DSI spec says bpc + 1 for this one */
>  	vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);
> -- 
> 2.20.1
> 
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Re: [Intel-gfx] [PATCH 5/6] drm/i915/bios: fill in DSC rc_model_size from VBT

[Jani Nikula]

On Tue, 08 Dec 2020, "Navare, Manasi" <manasi.d.navare@intel.com> wrote:
> On Tue, Dec 08, 2020 at 02:33:54PM +0200, Jani Nikula wrote:
>> The VBT fields match the DPCD data, so use the same helper.
>> 
>> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Only for DSI so far right?

Yes. We'll still need a patch to start using the rc_model_size from DPCD
for DP.

> In that case looks good
>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Thanks for the reviews. Pushed up to and including this one to
drm-intel-next. The last patch in the series still to be reviewed.

BR,
Jani.


>
> Manasi
>
>> ---
>>  drivers/gpu/drm/i915/display/intel_bios.c | 11 +++--------
>>  1 file changed, 3 insertions(+), 8 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
>> index 4cc949b228f2..06c3310446a2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
>> @@ -2555,16 +2555,11 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
>>  			      crtc_state->dsc.slice_count);
>>  
>>  	/*
>> -	 * FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the
>> -	 * implementation specific physical rate buffer size. Currently we use
>> -	 * the required rate buffer model size calculated in
>> -	 * drm_dsc_compute_rc_parameters() according to VESA DSC Annex E.
>> -	 *
>>  	 * The VBT rc_buffer_block_size and rc_buffer_size definitions
>> -	 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC
>> -	 * implementation should also use the DPCD (or perhaps VBT for eDP)
>> -	 * provided value for the buffer size.
>> +	 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63.
>>  	 */
>> +	vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size,
>> +							    dsc->rc_buffer_size);
>>  
>>  	/* FIXME: DSI spec says bpc + 1 for this one */
>>  	vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);
>> -- 
>> 2.20.1
>> 

-- 
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Re: [PATCH 5/6] drm/i915/bios: fill in DSC rc_model_size from VBT

[Jani Nikula]

On Tue, 08 Dec 2020, "Navare, Manasi" <manasi.d.navare@intel.com> wrote:
> On Tue, Dec 08, 2020 at 02:33:54PM +0200, Jani Nikula wrote:
>> The VBT fields match the DPCD data, so use the same helper.
>> 
>> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Only for DSI so far right?

Yes. We'll still need a patch to start using the rc_model_size from DPCD
for DP.

> In that case looks good
>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Thanks for the reviews. Pushed up to and including this one to
drm-intel-next. The last patch in the series still to be reviewed.

BR,
Jani.


>
> Manasi
>
>> ---
>>  drivers/gpu/drm/i915/display/intel_bios.c | 11 +++--------
>>  1 file changed, 3 insertions(+), 8 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
>> index 4cc949b228f2..06c3310446a2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
>> @@ -2555,16 +2555,11 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
>>  			      crtc_state->dsc.slice_count);
>>  
>>  	/*
>> -	 * FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the
>> -	 * implementation specific physical rate buffer size. Currently we use
>> -	 * the required rate buffer model size calculated in
>> -	 * drm_dsc_compute_rc_parameters() according to VESA DSC Annex E.
>> -	 *
>>  	 * The VBT rc_buffer_block_size and rc_buffer_size definitions
>> -	 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC
>> -	 * implementation should also use the DPCD (or perhaps VBT for eDP)
>> -	 * provided value for the buffer size.
>> +	 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63.
>>  	 */
>> +	vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size,
>> +							    dsc->rc_buffer_size);
>>  
>>  	/* FIXME: DSI spec says bpc + 1 for this one */
>>  	vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);
>> -- 
>> 2.20.1
>> 

-- 
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[Intel-gfx] [PATCH 6/6] drm/i915/dsi: use VBT data for rc_model_size

[Jani Nikula]

Stop overriding the VBT defined value for rc_model_size.

Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 676e40172fe9..a9439b415603 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1535,9 +1535,6 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
 
 	vdsc_cfg->convert_rgb = true;
 
-	/* FIXME: initialize from VBT */
-	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
-
 	ret = intel_dsc_compute_params(encoder, crtc_state);
 	if (ret)
 		return ret;
-- 
2.20.1

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[PATCH 6/6] drm/i915/dsi: use VBT data for rc_model_size

[Jani Nikula]

Stop overriding the VBT defined value for rc_model_size.

Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 676e40172fe9..a9439b415603 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1535,9 +1535,6 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
 
 	vdsc_cfg->convert_rgb = true;
 
-	/* FIXME: initialize from VBT */
-	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
-
 	ret = intel_dsc_compute_params(encoder, crtc_state);
 	if (ret)
 		return ret;
-- 
2.20.1

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/dsc, drm/dp, and /drm/i915: rc model size updates

[Patchwork]

== Series Details ==

Series: drm/dsc, drm/dp, and /drm/i915: rc model size updates
URL   : https://patchwork.freedesktop.org/series/84685/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
e40fcc2fb88c drm/dsc: use rc_model_size from DSC config for PPS
d3786025b31c drm/i915/dsc: configure hardware using specified rc_model_size
aecdbfc662d5 drm/i915/dsc: make rc_model_size an encoder defined value
-:6: WARNING:TYPO_SPELLING: 'intialization' may be misspelled - perhaps 'initialization'?
#6: 
Move the intialization of the rc_model_size from the common code into

total: 0 errors, 1 warnings, 0 checks, 31 lines checked
925c8324ea3e drm/dsc: add helper for calculating rc buffer size from DPCD
d997af2e7914 drm/i915/bios: fill in DSC rc_model_size from VBT
52414a882a77 drm/i915/dsi: use VBT data for rc_model_size


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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/dsc, drm/dp, and /drm/i915: rc model size updates

[Patchwork]

== Series Details ==

Series: drm/dsc, drm/dp, and /drm/i915: rc model size updates
URL   : https://patchwork.freedesktop.org/series/84685/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dsc.c:49:24: warning: symbol 'dcn20_dsc_funcs' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:1074:6: warning: symbol 'dcn20_enable_plane' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:2236:6: warning: symbol 'dcn20_get_mpctree_visual_confirm_color' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:2572:1: warning: no newline at end of file
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:1389:17:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:1389:17: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3620:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3622:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3624:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3626:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3628:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3630:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3632:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3634:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3636:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3638:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3640:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3642:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3644:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3646:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3648:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3650:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3652:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3654:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3656:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3658:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3660:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3662:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3664:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3666:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3668:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3670:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3672:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3674:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3676:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3678:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3680:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3684:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3686:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3688:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3690:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3692:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3694:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3696:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3700:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3702:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3704:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3706:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3708:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3710:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3712:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3714:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3716:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:676:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:676:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:677:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:677:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:678:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:678:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:679:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:679:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:680:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:680:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:681:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:681:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:685:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:685:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:690:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:690:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:774:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:774:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:775:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:775:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:776:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:776:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:777:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:777:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:778:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:778:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:779:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:779:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:783:17:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:783:17: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:788:17:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:788:17: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:857:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:857:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:858:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:858:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:859:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:859:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:860:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:860:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:861:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:861:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:862:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:862:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:866:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:866:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:870:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:870:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:888:17:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:888:17: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:892:17:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:892:17: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:92:30: warning: symbol 'dcn2_0_ip' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:940:17:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:940:17: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:944:17:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:944:17: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:990:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:990:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:994:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:994:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1091:6: warning: symbol 'dcn21_calculate_wm' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1308:6: warning: symbol 'dcn21_validate_bandwidth' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1442:31: warning: symbol 'dcn21_opp_create' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1458:25: warning: symbol 'dcn21_timing_generator_create' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1480:12: warning: symbol 'dcn21_mpc_create' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1507:34: warning: symbol 'dcn21_dsc_create' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1640:23: warning: symbol 'dcn21_stream_encoder_create' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:164:37: warning: symbol 'dcn2_1_soc' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1658:17:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1658:17: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1721:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1721:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1722:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1722:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1723:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1723:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1724:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1724:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1725:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1725:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1767:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1767:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1772:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1772:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1871:16: warning: symbol 'dcn21_patch_unknown_plane_state' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:487:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:487:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:488:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:488:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:489:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:489:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:490:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:490:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:494:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:494:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:498:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:498:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:538:17:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:538:17: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:542:17:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:542:17: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:605:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:605:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:609:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:609:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:661:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:661:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:662:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:662:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:663:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:663:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:664:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:664:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:668:17:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:668:17: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:673:17:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:673:17: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:691:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:691:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:695:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:695:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:784:19: warning: symbol 'dcn21_i2c_hw_create' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:94:30: warning: symbol 'dcn2_1_ip' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1030:21: warning: symbol 'dcn301_link_encoder_create' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1051:19: warning: symbol 'dcn301_panel_cntl_create' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1133:23: warning: symbol 'dcn301_stream_encoder_create' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1165:18: warning: symbol 'dcn301_hwseq_create' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1319:13: warning: symbol 'dcn301_hubp_create' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1338:6: warning: symbol 'dcn301_dwbc_create' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1363:6: warning: symbol 'dcn301_mmhubbub_create' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1471:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1473:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1475:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1477:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1479:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1481:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1483:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1485:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1487:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1489:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1491:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1493:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1495:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1497:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1499:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1501:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1503:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1505:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1507:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1509:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1511:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1513:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1515:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1517:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1519:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1521:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1523:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1525:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1527:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1529:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1531:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1533:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1535:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1537:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1539:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1541:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1543:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1545:33: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1549:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1551:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1553:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1555:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1557:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1559:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1561:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1563:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1565:41: warning: cast to restricted __le32
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:165:37: warning: symbol 'dcn3_01_soc' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:447:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:447:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:448:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:448:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:449:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:449:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:450:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:450:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:493:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:493:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:497:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:497:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:508:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:508:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:512:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:512:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:539:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:539:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:540:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:540:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:541:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:541:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:542:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:542:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:546:17:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:546:17: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:550:17:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:550:17: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:634:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:634:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:638:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:638:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:646:17: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:647:17:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:669:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:669:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:670:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:670:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:671:9:   also defined here
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:671:9: warning: Initializer entry defined twice
+drivers/gpu/drm/amd/amdgpu/../display


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/dsc, drm/dp, and /drm/i915: rc model size updates

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 3569 bytes --]

== Series Details ==

Series: drm/dsc, drm/dp, and /drm/i915: rc model size updates
URL   : https://patchwork.freedesktop.org/series/84685/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9461 -> Patchwork_19081
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_19081:

### CI changes ###

#### Possible regressions ####

  * boot (NEW):
    - {fi-tgl-dsi}:       [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/fi-tgl-dsi/boot.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/fi-tgl-dsi/boot.html

  
New tests
---------

  New tests have been introduced between CI_DRM_9461 and Patchwork_19081:

### New CI tests (1) ###

  * boot:
    - Statuses : 2 fail(s) 38 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_19081 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@vgem_basic@setversion:
    - fi-tgl-y:           [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/fi-tgl-y/igt@vgem_basic@setversion.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/fi-tgl-y/igt@vgem_basic@setversion.html

  
#### Possible fixes ####

  * igt@debugfs_test@read_all_entries:
    - fi-tgl-y:           [DMESG-WARN][5] ([i915#402]) -> [PASS][6] +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [DMESG-FAIL][7] ([i915#165]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (43 -> 40)
------------------------------

  Missing    (3): fi-ilk-m540 fi-bdw-samus fi-hsw-4200u 


Build changes
-------------

  * Linux: CI_DRM_9461 -> Patchwork_19081

  CI-20190529: 20190529
  CI_DRM_9461: cac67f316baee6c9d82e94e881a9a397c5dce95a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5885: d99f644b1868b9c92435b05ebfafa230721cd677 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19081: 52414a882a7728b1ba4855481fb198dbf3d7531f @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

52414a882a77 drm/i915/dsi: use VBT data for rc_model_size
d997af2e7914 drm/i915/bios: fill in DSC rc_model_size from VBT
925c8324ea3e drm/dsc: add helper for calculating rc buffer size from DPCD
aecdbfc662d5 drm/i915/dsc: make rc_model_size an encoder defined value
d3786025b31c drm/i915/dsc: configure hardware using specified rc_model_size
e40fcc2fb88c drm/dsc: use rc_model_size from DSC config for PPS

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/index.html

[-- Attachment #1.2: Type: text/html, Size: 4385 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/dsc, drm/dp, and /drm/i915: rc model size updates

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 15696 bytes --]

== Series Details ==

Series: drm/dsc, drm/dp, and /drm/i915: rc model size updates
URL   : https://patchwork.freedesktop.org/series/84685/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9461_full -> Patchwork_19081_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

New tests
---------

  New tests have been introduced between CI_DRM_9461_full and Patchwork_19081_full:

### New CI tests (1) ###

  * boot:
    - Statuses : 175 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_19081_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@preservation-s3@vcs1:
    - shard-kbl:          [PASS][1] -> [DMESG-WARN][2] ([i915#180])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@vcs1.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-kbl2/igt@gem_ctx_isolation@preservation-s3@vcs1.html

  * igt@gem_pread@exhaustion:
    - shard-skl:          NOTRUN -> [WARN][3] ([i915#2658])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-skl2/igt@gem_pread@exhaustion.html

  * igt@i915_pm_rpm@cursor:
    - shard-glk:          [PASS][4] -> [DMESG-WARN][5] ([i915#118] / [i915#95])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-glk2/igt@i915_pm_rpm@cursor.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-glk8/igt@i915_pm_rpm@cursor.html

  * igt@kms_async_flips@test-time-stamp:
    - shard-tglb:         [PASS][6] -> [FAIL][7] ([i915#2597])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-tglb1/igt@kms_async_flips@test-time-stamp.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-tglb1/igt@kms_async_flips@test-time-stamp.html

  * igt@kms_big_fb@linear-64bpp-rotate-90:
    - shard-skl:          NOTRUN -> [SKIP][8] ([fdo#109271]) +40 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-skl2/igt@kms_big_fb@linear-64bpp-rotate-90.html

  * igt@kms_chamelium@dp-edid-change-during-suspend:
    - shard-apl:          NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +5 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-apl6/igt@kms_chamelium@dp-edid-change-during-suspend.html

  * igt@kms_color_chamelium@pipe-c-ctm-0-5:
    - shard-skl:          NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +4 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-skl4/igt@kms_color_chamelium@pipe-c-ctm-0-5.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x128-random:
    - shard-skl:          [PASS][11] -> [FAIL][12] ([i915#54]) +2 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html

  * igt@kms_draw_crc@draw-method-xrgb8888-pwrite-ytiled:
    - shard-glk:          [PASS][13] -> [FAIL][14] ([i915#52] / [i915#54])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-glk2/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-ytiled.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-glk8/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-ytiled.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][15] -> [FAIL][16] ([i915#79])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([i915#79])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
    - shard-skl:          [PASS][19] -> [FAIL][20] ([i915#2122]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
    - shard-skl:          NOTRUN -> [FAIL][21] ([i915#2628])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-skl2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [PASS][22] -> [FAIL][23] ([i915#1188]) +1 similar issue
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-skl5/igt@kms_hdr@bpc-switch-dpms.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-skl3/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c:
    - shard-apl:          NOTRUN -> [SKIP][24] ([fdo#109271]) +38 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-apl6/igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
    - shard-skl:          NOTRUN -> [FAIL][25] ([fdo#108145] / [i915#265])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
    - shard-skl:          NOTRUN -> [FAIL][26] ([i915#265])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
    - shard-apl:          NOTRUN -> [FAIL][27] ([fdo#108145] / [i915#265])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-apl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][28] -> [FAIL][29] ([fdo#108145] / [i915#265])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [PASS][30] -> [SKIP][31] ([fdo#109642] / [fdo#111068])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-iclb2/igt@kms_psr2_su@page_flip.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-iclb8/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@psr2_dpms:
    - shard-iclb:         [PASS][32] -> [SKIP][33] ([fdo#109441]) +1 similar issue
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-iclb2/igt@kms_psr@psr2_dpms.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-iclb3/igt@kms_psr@psr2_dpms.html

  * igt@kms_vblank@pipe-d-wait-idle:
    - shard-apl:          NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#533])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-apl6/igt@kms_vblank@pipe-d-wait-idle.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-skl:          NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#2437])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-skl2/igt@kms_writeback@writeback-fb-id.html

  
#### Possible fixes ####

  * igt@gem_exec_whisper@basic-fds-forked-all:
    - shard-glk:          [DMESG-WARN][36] ([i915#118] / [i915#95]) -> [PASS][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-glk1/igt@gem_exec_whisper@basic-fds-forked-all.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-glk8/igt@gem_exec_whisper@basic-fds-forked-all.html

  * igt@gem_softpin@noreloc-s3:
    - shard-skl:          [INCOMPLETE][38] ([i915#198] / [i915#2405]) -> [PASS][39]
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-skl3/igt@gem_softpin@noreloc-s3.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-skl2/igt@gem_softpin@noreloc-s3.html

  * igt@gem_workarounds@suspend-resume:
    - shard-skl:          [INCOMPLETE][40] ([i915#198]) -> [PASS][41]
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-skl3/igt@gem_workarounds@suspend-resume.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-skl6/igt@gem_workarounds@suspend-resume.html

  * igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen:
    - shard-skl:          [FAIL][42] ([i915#54]) -> [PASS][43] +2 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
    - shard-skl:          [FAIL][44] ([i915#2122]) -> [PASS][45] +1 similar issue
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [FAIL][46] ([fdo#108145] / [i915#265]) -> [PASS][47] +1 similar issue
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [SKIP][48] ([fdo#109441]) -> [PASS][49] +2 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-iclb8/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html

  
#### Warnings ####

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         [WARN][50] ([i915#2681] / [i915#2684]) -> [WARN][51] ([i915#2684])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-iclb5/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
    - shard-kbl:          [DMESG-WARN][52] -> [INCOMPLETE][53] ([i915#155] / [i915#2405])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-kbl7/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-kbl4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][54], [FAIL][55]) ([i915#1814] / [i915#2295] / [i915#2722] / [i915#483] / [i915#602]) -> ([FAIL][56], [FAIL][57]) ([i915#1436] / [i915#2295] / [i915#2722] / [i915#483])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-kbl1/igt@runner@aborted.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-kbl7/igt@runner@aborted.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-kbl2/igt@runner@aborted.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-kbl3/igt@runner@aborted.html
    - shard-glk:          ([FAIL][58], [FAIL][59]) ([i915#1814] / [i915#2295] / [i915#2722] / [i915#483] / [k.org#202321]) -> ([FAIL][60], [FAIL][61]) ([i915#1814] / [i915#2295] / [i915#2722] / [k.org#202321])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-glk6/igt@runner@aborted.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-glk7/igt@runner@aborted.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-glk5/igt@runner@aborted.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-glk1/igt@runner@aborted.html
    - shard-skl:          [FAIL][62] ([i915#2295] / [i915#2722]) -> [FAIL][63] ([i915#2295] / [i915#2722] / [i915#483])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9461/shard-skl8/igt@runner@aborted.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/shard-skl7/igt@runner@aborted.html

  
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
  [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2597]: https://gitlab.freedesktop.org/drm/intel/issues/2597
  [i915#2628]: https://gitlab.freedesktop.org/drm/intel/issues/2628
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
  [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
  [i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
  [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#602]: https://gitlab.freedesktop.org/drm/intel/issues/602
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
  [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_9461 -> Patchwork_19081

  CI-20190529: 20190529
  CI_DRM_9461: cac67f316baee6c9d82e94e881a9a397c5dce95a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5885: d99f644b1868b9c92435b05ebfafa230721cd677 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19081: 52414a882a7728b1ba4855481fb198dbf3d7531f @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19081/index.html

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_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 0/6] drm/dsc, drm/dp, and /drm/i915: rc model size updates

[Jani Nikula]

On Tue, 08 Dec 2020, Jani Nikula <jani.nikula@intel.com> wrote:
> For whatever reason this old series was never merged. Please let's get
> this done.

Daniel, Maarten, may I have an ack to merge patches 1 and 4 via
drm-intel?

BR,
Jani.


>
> For i915 DP this still needs a patch to start using the model size from
> DPCD.
>
> BR,
> Jani.
>
> Jani Nikula (6):
>   drm/dsc: use rc_model_size from DSC config for PPS
>   drm/i915/dsc: configure hardware using specified rc_model_size
>   drm/i915/dsc: make rc_model_size an encoder defined value
>   drm/dsc: add helper for calculating rc buffer size from DPCD
>   drm/i915/bios: fill in DSC rc_model_size from VBT
>   drm/i915/dsi: use VBT data for rc_model_size
>
>  drivers/gpu/drm/drm_dsc.c                 | 30 +++++++++++++++++++++--
>  drivers/gpu/drm/i915/display/intel_bios.c | 11 +++------
>  drivers/gpu/drm/i915/display/intel_dp.c   |  8 ++++++
>  drivers/gpu/drm/i915/display/intel_vdsc.c |  4 +--
>  include/drm/drm_dsc.h                     |  1 +
>  5 files changed, 41 insertions(+), 13 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 0/6] drm/dsc, drm/dp, and /drm/i915: rc model size updates

[Jani Nikula]

On Tue, 08 Dec 2020, Jani Nikula <jani.nikula@intel.com> wrote:
> For whatever reason this old series was never merged. Please let's get
> this done.

Daniel, Maarten, may I have an ack to merge patches 1 and 4 via
drm-intel?

BR,
Jani.


>
> For i915 DP this still needs a patch to start using the model size from
> DPCD.
>
> BR,
> Jani.
>
> Jani Nikula (6):
>   drm/dsc: use rc_model_size from DSC config for PPS
>   drm/i915/dsc: configure hardware using specified rc_model_size
>   drm/i915/dsc: make rc_model_size an encoder defined value
>   drm/dsc: add helper for calculating rc buffer size from DPCD
>   drm/i915/bios: fill in DSC rc_model_size from VBT
>   drm/i915/dsi: use VBT data for rc_model_size
>
>  drivers/gpu/drm/drm_dsc.c                 | 30 +++++++++++++++++++++--
>  drivers/gpu/drm/i915/display/intel_bios.c | 11 +++------
>  drivers/gpu/drm/i915/display/intel_dp.c   |  8 ++++++
>  drivers/gpu/drm/i915/display/intel_vdsc.c |  4 +--
>  include/drm/drm_dsc.h                     |  1 +
>  5 files changed, 41 insertions(+), 13 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH 0/6] drm/dsc, drm/dp, and /drm/i915: rc model size updates

[Daniel Vetter]

On Wed, Dec 09, 2020 at 11:34:44AM +0200, Jani Nikula wrote:
> On Tue, 08 Dec 2020, Jani Nikula <jani.nikula@intel.com> wrote:
> > For whatever reason this old series was never merged. Please let's get
> > this done.
> 
> Daniel, Maarten, may I have an ack to merge patches 1 and 4 via
> drm-intel?

Ack.
-Daniel

> 
> BR,
> Jani.
> 
> 
> >
> > For i915 DP this still needs a patch to start using the model size from
> > DPCD.
> >
> > BR,
> > Jani.
> >
> > Jani Nikula (6):
> >   drm/dsc: use rc_model_size from DSC config for PPS
> >   drm/i915/dsc: configure hardware using specified rc_model_size
> >   drm/i915/dsc: make rc_model_size an encoder defined value
> >   drm/dsc: add helper for calculating rc buffer size from DPCD
> >   drm/i915/bios: fill in DSC rc_model_size from VBT
> >   drm/i915/dsi: use VBT data for rc_model_size
> >
> >  drivers/gpu/drm/drm_dsc.c                 | 30 +++++++++++++++++++++--
> >  drivers/gpu/drm/i915/display/intel_bios.c | 11 +++------
> >  drivers/gpu/drm/i915/display/intel_dp.c   |  8 ++++++
> >  drivers/gpu/drm/i915/display/intel_vdsc.c |  4 +--
> >  include/drm/drm_dsc.h                     |  1 +
> >  5 files changed, 41 insertions(+), 13 deletions(-)
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
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Re: [PATCH 0/6] drm/dsc, drm/dp, and /drm/i915: rc model size updates

[Daniel Vetter]

On Wed, Dec 09, 2020 at 11:34:44AM +0200, Jani Nikula wrote:
> On Tue, 08 Dec 2020, Jani Nikula <jani.nikula@intel.com> wrote:
> > For whatever reason this old series was never merged. Please let's get
> > this done.
> 
> Daniel, Maarten, may I have an ack to merge patches 1 and 4 via
> drm-intel?

Ack.
-Daniel

> 
> BR,
> Jani.
> 
> 
> >
> > For i915 DP this still needs a patch to start using the model size from
> > DPCD.
> >
> > BR,
> > Jani.
> >
> > Jani Nikula (6):
> >   drm/dsc: use rc_model_size from DSC config for PPS
> >   drm/i915/dsc: configure hardware using specified rc_model_size
> >   drm/i915/dsc: make rc_model_size an encoder defined value
> >   drm/dsc: add helper for calculating rc buffer size from DPCD
> >   drm/i915/bios: fill in DSC rc_model_size from VBT
> >   drm/i915/dsi: use VBT data for rc_model_size
> >
> >  drivers/gpu/drm/drm_dsc.c                 | 30 +++++++++++++++++++++--
> >  drivers/gpu/drm/i915/display/intel_bios.c | 11 +++------
> >  drivers/gpu/drm/i915/display/intel_dp.c   |  8 ++++++
> >  drivers/gpu/drm/i915/display/intel_vdsc.c |  4 +--
> >  include/drm/drm_dsc.h                     |  1 +
> >  5 files changed, 41 insertions(+), 13 deletions(-)
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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