* [PATCH v7 0/7] Add PCIe support for Qualcomm IPQ5332
@ 2025-01-22 6:34 ` Varadarajan Narayanan
0 siblings, 0 replies; 37+ messages in thread
From: Varadarajan Narayanan @ 2025-01-22 6:34 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, quic_varada, linux-arm-msm,
linux-pci, devicetree, linux-kernel, linux-phy
Patch series adds support for enabling the PCIe controller and
UNIPHY found on Qualcomm IPQ5332 platform. PCIe0 is Gen3 X1 and
PCIe1 is Gen3 X2 are added.
This series combines [1] and [2]. [1] introduces IPQ5018 PCIe
support and [2] depends on [1] to introduce IPQ5332 PCIe support.
Since the community was interested in [2] (please see [3]), tried
to revive IPQ5332's PCIe support with v2 of this patch series.
v2 of this series pulled in the phy driver from [1] tried to
address comments/feedback given in both [1] and [2].
1. Enable IPQ5018 PCI support (Nitheesh Sekar) - https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/
2. Add PCIe support for Qualcomm IPQ5332 (Praveenkumar I) - https://lore.kernel.org/linux-arm-msm/20231214062847.2215542-1-quic_ipkumar@quicinc.com/
3. Community interest - https://lore.kernel.org/linux-arm-msm/20240310132915.GE3390@thinkpad/
v7: phy bindings:
* Include data type definition to 'num-lanes'
controller bindings:
* Split the ipq9574 and ipq5332 changes into separate patches
dtsi:
* Add root port definitions
v6: phy bindings:
* Fix num-lanes definition
phy driver:
* Fix num-lanes handling in probe to use generally followed pattern
controller bindings:
* Give more info in commit log
dtsi:
* Add assigned-clocks & assigned-clock-rates to controller nodes
* Add num-lanes to pcie0_phy
v5: phy bindings:
* Drop '3x1' & '3x2' from compatible string
* Use 'num-lanes' to differentiate instead of '3x1' or '3x2'
in compatible string
* Describe clocks and resets instead of just maxItems
phy driver:
* Get num-lanes from DTS
* Drop compatible specific init data as there is only one
compatible string
controller bindings:
* Re-arrange 5332 and 9574 compatibles to handle fallback usage in dts
dtsi:
* Add 'num-lanes' to "pcie1_phy: phy@4b1000"
* Make ipq5332 as main and ipq9574 as fallback compatible
* Sort controller nodes per address
misc:
Add R-B tag from Konrad to dts and dtsi patches
v4: * phy bindings - Create ipq5332 compatible instead of reusing ipq9574 for bindings
* phy bindings - Remove reset-names as the resets are handled with bulk APIs
* phy bindings - Fix order in the 'required' section
* phy bindings - Remove clock-output-names
* dtsi - Add missing reset for pcie1_phy
* dtsi - Convert 'reg-names' to a vertical list
* dts - Fix nodes sort order
* dts - Use property-n followed by property-names
v3: * Update the cover letter with the sources of the patches
* Rename the dt-bindings yaml file similar to other phys
* Drop ipq5332 specific pcie controllor bindings and reuse
ipq9574 pcie controller bindings for ipq5332
* Please see patches for specific changes
* Set GPL license for phy-qcom-uniphy-pcie-28lp.c
v2: Address review comments from V1
Drop the 'required clocks' change that would break ABI (in dt-binding, dts, gcc-ipq5332.c)
Include phy driver from the dependent series
v1: https://lore.kernel.org/linux-arm-msm/20231214062847.2215542-1-quic_ipkumar@quicinc.com/
Nitheesh Sekar (2):
dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy
phy: qcom: Introduce PCIe UNIPHY 28LP driver
Praveenkumar I (2):
arm64: dts: qcom: ipq5332: Add PCIe related nodes
arm64: dts: qcom: ipq5332-rdp441: Enable PCIe phys and controllers
Varadarajan Narayanan (3):
dt-bindings: PCI: qcom: Use sdx55 reg description for ipq9574
arm64: dts: qcom: ipq9574: Reorder reg and reg-names
dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller
.../devicetree/bindings/pci/qcom,pcie.yaml | 15 +-
.../phy/qcom,ipq5332-uniphy-pcie-phy.yaml | 76 +++++
arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 76 +++++
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 268 +++++++++++++++-
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 52 ++--
drivers/phy/qualcomm/Kconfig | 12 +
drivers/phy/qualcomm/Makefile | 1 +
.../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 286 ++++++++++++++++++
8 files changed, 763 insertions(+), 23 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
create mode 100644 drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
base-commit: 37136bf5c3a6f6b686d74f41837a6406bec6b7bc
--
2.34.1
^ permalink raw reply [flat|nested] 37+ messages in thread* [PATCH v7 0/7] Add PCIe support for Qualcomm IPQ5332
@ 2025-01-22 6:34 ` Varadarajan Narayanan
0 siblings, 0 replies; 37+ messages in thread
From: Varadarajan Narayanan @ 2025-01-22 6:34 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, quic_varada, linux-arm-msm,
linux-pci, devicetree, linux-kernel, linux-phy
Patch series adds support for enabling the PCIe controller and
UNIPHY found on Qualcomm IPQ5332 platform. PCIe0 is Gen3 X1 and
PCIe1 is Gen3 X2 are added.
This series combines [1] and [2]. [1] introduces IPQ5018 PCIe
support and [2] depends on [1] to introduce IPQ5332 PCIe support.
Since the community was interested in [2] (please see [3]), tried
to revive IPQ5332's PCIe support with v2 of this patch series.
v2 of this series pulled in the phy driver from [1] tried to
address comments/feedback given in both [1] and [2].
1. Enable IPQ5018 PCI support (Nitheesh Sekar) - https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/
2. Add PCIe support for Qualcomm IPQ5332 (Praveenkumar I) - https://lore.kernel.org/linux-arm-msm/20231214062847.2215542-1-quic_ipkumar@quicinc.com/
3. Community interest - https://lore.kernel.org/linux-arm-msm/20240310132915.GE3390@thinkpad/
v7: phy bindings:
* Include data type definition to 'num-lanes'
controller bindings:
* Split the ipq9574 and ipq5332 changes into separate patches
dtsi:
* Add root port definitions
v6: phy bindings:
* Fix num-lanes definition
phy driver:
* Fix num-lanes handling in probe to use generally followed pattern
controller bindings:
* Give more info in commit log
dtsi:
* Add assigned-clocks & assigned-clock-rates to controller nodes
* Add num-lanes to pcie0_phy
v5: phy bindings:
* Drop '3x1' & '3x2' from compatible string
* Use 'num-lanes' to differentiate instead of '3x1' or '3x2'
in compatible string
* Describe clocks and resets instead of just maxItems
phy driver:
* Get num-lanes from DTS
* Drop compatible specific init data as there is only one
compatible string
controller bindings:
* Re-arrange 5332 and 9574 compatibles to handle fallback usage in dts
dtsi:
* Add 'num-lanes' to "pcie1_phy: phy@4b1000"
* Make ipq5332 as main and ipq9574 as fallback compatible
* Sort controller nodes per address
misc:
Add R-B tag from Konrad to dts and dtsi patches
v4: * phy bindings - Create ipq5332 compatible instead of reusing ipq9574 for bindings
* phy bindings - Remove reset-names as the resets are handled with bulk APIs
* phy bindings - Fix order in the 'required' section
* phy bindings - Remove clock-output-names
* dtsi - Add missing reset for pcie1_phy
* dtsi - Convert 'reg-names' to a vertical list
* dts - Fix nodes sort order
* dts - Use property-n followed by property-names
v3: * Update the cover letter with the sources of the patches
* Rename the dt-bindings yaml file similar to other phys
* Drop ipq5332 specific pcie controllor bindings and reuse
ipq9574 pcie controller bindings for ipq5332
* Please see patches for specific changes
* Set GPL license for phy-qcom-uniphy-pcie-28lp.c
v2: Address review comments from V1
Drop the 'required clocks' change that would break ABI (in dt-binding, dts, gcc-ipq5332.c)
Include phy driver from the dependent series
v1: https://lore.kernel.org/linux-arm-msm/20231214062847.2215542-1-quic_ipkumar@quicinc.com/
Nitheesh Sekar (2):
dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy
phy: qcom: Introduce PCIe UNIPHY 28LP driver
Praveenkumar I (2):
arm64: dts: qcom: ipq5332: Add PCIe related nodes
arm64: dts: qcom: ipq5332-rdp441: Enable PCIe phys and controllers
Varadarajan Narayanan (3):
dt-bindings: PCI: qcom: Use sdx55 reg description for ipq9574
arm64: dts: qcom: ipq9574: Reorder reg and reg-names
dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller
.../devicetree/bindings/pci/qcom,pcie.yaml | 15 +-
.../phy/qcom,ipq5332-uniphy-pcie-phy.yaml | 76 +++++
arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 76 +++++
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 268 +++++++++++++++-
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 52 ++--
drivers/phy/qualcomm/Kconfig | 12 +
drivers/phy/qualcomm/Makefile | 1 +
.../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 286 ++++++++++++++++++
8 files changed, 763 insertions(+), 23 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
create mode 100644 drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
base-commit: 37136bf5c3a6f6b686d74f41837a6406bec6b7bc
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 37+ messages in thread* [PATCH v7 1/7] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy
2025-01-22 6:34 ` Varadarajan Narayanan
@ 2025-01-22 6:34 ` Varadarajan Narayanan
-1 siblings, 0 replies; 37+ messages in thread
From: Varadarajan Narayanan @ 2025-01-22 6:34 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, quic_varada, linux-arm-msm,
linux-pci, devicetree, linux-kernel, linux-phy
From: Nitheesh Sekar <quic_nsekar@quicinc.com>
Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5332.
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v7: * Add data type definition to 'num-lanes'
v6: * Fix num-lanes definition
* Make it mandatory
v5: * Drop '3x1' & '3x2' from compatible string
* Use 'num-lanes' to differentiate instead of '3x1' or '3x2'
in compatible string
* Describe clocks and resets instead of just maxItems
v4: Remove reset-names as the resets are not used individually
Remove clock-output-names as its usage is removed from driver
Fix order in the 'required' section
v3: Fix compatible string to be similar to other phys and rename file accordingly
Fix clocks minItems -> maxItems
Change one of the maintainer from Sricharan to Varadarajan
v2: Rename the file to match the compatible
Drop 'driver' from title
Dropped 'clock-names'
Fixed 'reset-names'
---
.../phy/qcom,ipq5332-uniphy-pcie-phy.yaml | 76 +++++++++++++++++++
1 file changed, 76 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
new file mode 100644
index 000000000000..e39168d55d23
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm UNIPHY PCIe 28LP PHY
+
+maintainers:
+ - Nitheesh Sekar <quic_nsekar@quicinc.com>
+ - Varadarajan Narayanan <quic_varada@quicinc.com>
+
+description:
+ PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq5332-uniphy-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: pcie pipe clock
+ - description: pcie ahb clock
+
+ resets:
+ items:
+ - description: phy reset
+ - description: ahb reset
+ - description: cfg reset
+
+ "#phy-cells":
+ const: 0
+
+ "#clock-cells":
+ const: 0
+
+ num-lanes:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2]
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+ - "#phy-cells"
+ - "#clock-cells"
+ - num-lanes
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
+
+ pcie0_phy: phy@4b0000 {
+ compatible = "qcom,ipq5332-uniphy-pcie-phy";
+ reg = <0x004b0000 0x800>;
+
+ clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
+
+ resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>;
+
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
+
+ num-lanes = <1>;
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH v7 1/7] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy
@ 2025-01-22 6:34 ` Varadarajan Narayanan
0 siblings, 0 replies; 37+ messages in thread
From: Varadarajan Narayanan @ 2025-01-22 6:34 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, quic_varada, linux-arm-msm,
linux-pci, devicetree, linux-kernel, linux-phy
From: Nitheesh Sekar <quic_nsekar@quicinc.com>
Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5332.
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v7: * Add data type definition to 'num-lanes'
v6: * Fix num-lanes definition
* Make it mandatory
v5: * Drop '3x1' & '3x2' from compatible string
* Use 'num-lanes' to differentiate instead of '3x1' or '3x2'
in compatible string
* Describe clocks and resets instead of just maxItems
v4: Remove reset-names as the resets are not used individually
Remove clock-output-names as its usage is removed from driver
Fix order in the 'required' section
v3: Fix compatible string to be similar to other phys and rename file accordingly
Fix clocks minItems -> maxItems
Change one of the maintainer from Sricharan to Varadarajan
v2: Rename the file to match the compatible
Drop 'driver' from title
Dropped 'clock-names'
Fixed 'reset-names'
---
.../phy/qcom,ipq5332-uniphy-pcie-phy.yaml | 76 +++++++++++++++++++
1 file changed, 76 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
new file mode 100644
index 000000000000..e39168d55d23
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm UNIPHY PCIe 28LP PHY
+
+maintainers:
+ - Nitheesh Sekar <quic_nsekar@quicinc.com>
+ - Varadarajan Narayanan <quic_varada@quicinc.com>
+
+description:
+ PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq5332-uniphy-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: pcie pipe clock
+ - description: pcie ahb clock
+
+ resets:
+ items:
+ - description: phy reset
+ - description: ahb reset
+ - description: cfg reset
+
+ "#phy-cells":
+ const: 0
+
+ "#clock-cells":
+ const: 0
+
+ num-lanes:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2]
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+ - "#phy-cells"
+ - "#clock-cells"
+ - num-lanes
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
+
+ pcie0_phy: phy@4b0000 {
+ compatible = "qcom,ipq5332-uniphy-pcie-phy";
+ reg = <0x004b0000 0x800>;
+
+ clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
+
+ resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>;
+
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
+
+ num-lanes = <1>;
+ };
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v7 1/7] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy
2025-01-22 6:34 ` Varadarajan Narayanan
@ 2025-01-23 7:54 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 37+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-23 7:54 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, linux-arm-msm, linux-pci,
devicetree, linux-kernel, linux-phy
On Wed, Jan 22, 2025 at 12:04:05PM +0530, Varadarajan Narayanan wrote:
> From: Nitheesh Sekar <quic_nsekar@quicinc.com>
>
> Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5332.
>
> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> v7: * Add data type definition to 'num-lanes'
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v7 1/7] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy
@ 2025-01-23 7:54 ` Krzysztof Kozlowski
0 siblings, 0 replies; 37+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-23 7:54 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, linux-arm-msm, linux-pci,
devicetree, linux-kernel, linux-phy
On Wed, Jan 22, 2025 at 12:04:05PM +0530, Varadarajan Narayanan wrote:
> From: Nitheesh Sekar <quic_nsekar@quicinc.com>
>
> Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5332.
>
> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> v7: * Add data type definition to 'num-lanes'
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v7 2/7] phy: qcom: Introduce PCIe UNIPHY 28LP driver
2025-01-22 6:34 ` Varadarajan Narayanan
@ 2025-01-22 6:34 ` Varadarajan Narayanan
-1 siblings, 0 replies; 37+ messages in thread
From: Varadarajan Narayanan @ 2025-01-22 6:34 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, quic_varada, linux-arm-msm,
linux-pci, devicetree, linux-kernel, linux-phy
From: Nitheesh Sekar <quic_nsekar@quicinc.com>
Add Qualcomm PCIe UNIPHY 28LP driver support present
in Qualcomm IPQ5332 SoC and the phy init sequence.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v6: Use generally followed pattern for getting num-lanes from DT
v5: * Use 'num-lanes' to differentiate instead of '3x1' or '3x2'
in compatible string
* Drop compatible specific init data as there is only one
compatible string
* Fix header file order
v4: Fix uppercase hex digit
Use phy->id for pipe clock source
v3: Added 'Reviewed-by: Dmitry Baryshkov' and made following updates
s/unsigned int/u32/g
Fix 'lane_offset' comments
Fix #define tab -> space
Fix mixed case hex numbers
Fix licensing & owner
Change for-loop pointer to use [] instead of ->
Use 'less than max' instead of 'not equal to max' in termination condition
Smatch and Coccinelle passed
v2: Drop IPQ5018 related code and data
Use uniform prefix for struct names
Place "}, {", on the same line
In qcom_uniphy_pcie_init(), use for-loop instead of while
Swap reset and clock disable order in qcom_uniphy_pcie_power_off
Add reset assert to qcom_uniphy_pcie_power_on's error path
Use macros for usleep duration
Inlined qcom_uniphy_pcie_get_resources & use devm_platform_get_and_ioremap_resource
Drop 'clock-output-names' from phy_pipe_clk_register
---
drivers/phy/qualcomm/Kconfig | 12 +
drivers/phy/qualcomm/Makefile | 1 +
.../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 286 ++++++++++++++++++
3 files changed, 299 insertions(+)
create mode 100644 drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
index 846f8c99547f..a6b71fda1b9c 100644
--- a/drivers/phy/qualcomm/Kconfig
+++ b/drivers/phy/qualcomm/Kconfig
@@ -154,6 +154,18 @@ config PHY_QCOM_M31_USB
management. This driver is required even for peripheral only or
host only mode configurations.
+config PHY_QCOM_UNIPHY_PCIE_28LP
+ bool "PCIE UNIPHY 28LP PHY driver"
+ depends on ARCH_QCOM
+ depends on HAS_IOMEM
+ depends on OF
+ select GENERIC_PHY
+ help
+ Enable this to support the PCIe UNIPHY 28LP phy transceiver that
+ is used with PCIe controllers on Qualcomm IPQ5332 chips. It
+ handles PHY initialization, clock management required after
+ resetting the hardware and power management.
+
config PHY_QCOM_USB_HS
tristate "Qualcomm USB HS PHY module"
depends on USB_ULPI_BUS
diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile
index eb60e950ad53..42038bc30974 100644
--- a/drivers/phy/qualcomm/Makefile
+++ b/drivers/phy/qualcomm/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_PHY_QCOM_QMP_USB_LEGACY) += phy-qcom-qmp-usb-legacy.o
obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2) += phy-qcom-snps-eusb2.o
obj-$(CONFIG_PHY_QCOM_EUSB2_REPEATER) += phy-qcom-eusb2-repeater.o
+obj-$(CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP) += phy-qcom-uniphy-pcie-28lp.o
obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
new file mode 100644
index 000000000000..d44dc769af6f
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#define RST_ASSERT_DELAY_MIN_US 100
+#define RST_ASSERT_DELAY_MAX_US 150
+#define PIPE_CLK_DELAY_MIN_US 5000
+#define PIPE_CLK_DELAY_MAX_US 5100
+#define CLK_EN_DELAY_MIN_US 30
+#define CLK_EN_DELAY_MAX_US 50
+#define CDR_CTRL_REG_1 0x80
+#define CDR_CTRL_REG_2 0x84
+#define CDR_CTRL_REG_3 0x88
+#define CDR_CTRL_REG_4 0x8c
+#define CDR_CTRL_REG_5 0x90
+#define CDR_CTRL_REG_6 0x94
+#define CDR_CTRL_REG_7 0x98
+#define SSCG_CTRL_REG_1 0x9c
+#define SSCG_CTRL_REG_2 0xa0
+#define SSCG_CTRL_REG_3 0xa4
+#define SSCG_CTRL_REG_4 0xa8
+#define SSCG_CTRL_REG_5 0xac
+#define SSCG_CTRL_REG_6 0xb0
+#define PCS_INTERNAL_CONTROL_2 0x2d8
+
+#define PHY_CFG_PLLCFG 0x220
+#define PHY_CFG_EIOS_DTCT_REG 0x3e4
+#define PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME 0x3e8
+
+#define PHY_MODE_FIXED 0x1
+
+enum qcom_uniphy_pcie_type {
+ PHY_TYPE_PCIE = 1,
+ PHY_TYPE_PCIE_GEN2,
+ PHY_TYPE_PCIE_GEN3,
+};
+
+struct qcom_uniphy_pcie_regs {
+ u32 offset;
+ u32 val;
+};
+
+struct qcom_uniphy_pcie_data {
+ int lane_offset; /* offset between the lane register bases */
+ u32 phy_type;
+ const struct qcom_uniphy_pcie_regs *init_seq;
+ u32 init_seq_num;
+ u32 pipe_clk_rate;
+};
+
+struct qcom_uniphy_pcie {
+ struct phy phy;
+ struct device *dev;
+ const struct qcom_uniphy_pcie_data *data;
+ struct clk_bulk_data *clks;
+ int num_clks;
+ struct reset_control *resets;
+ void __iomem *base;
+ int lanes;
+};
+
+#define phy_to_dw_phy(x) container_of((x), struct qca_uni_pcie_phy, phy)
+
+static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = {
+ {
+ .offset = PHY_CFG_PLLCFG,
+ .val = 0x30,
+ }, {
+ .offset = PHY_CFG_EIOS_DTCT_REG,
+ .val = 0x53ef,
+ }, {
+ .offset = PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME,
+ .val = 0xcf,
+ },
+};
+
+static const struct qcom_uniphy_pcie_data ipq5332_data = {
+ .lane_offset = 0x800,
+ .phy_type = PHY_TYPE_PCIE_GEN3,
+ .init_seq = ipq5332_regs,
+ .init_seq_num = ARRAY_SIZE(ipq5332_regs),
+ .pipe_clk_rate = 250000000,
+};
+
+static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy)
+{
+ const struct qcom_uniphy_pcie_data *data = phy->data;
+ const struct qcom_uniphy_pcie_regs *init_seq;
+ void __iomem *base = phy->base;
+ int lane, i;
+
+ for (lane = 0; lane < phy->lanes; lane++) {
+ init_seq = data->init_seq;
+
+ for (i = 0; i < data->init_seq_num; i++)
+ writel(init_seq[i].val, base + init_seq[i].offset);
+
+ base += data->lane_offset;
+ }
+}
+
+static int qcom_uniphy_pcie_power_off(struct phy *x)
+{
+ struct qcom_uniphy_pcie *phy = phy_get_drvdata(x);
+
+ clk_bulk_disable_unprepare(phy->num_clks, phy->clks);
+
+ return reset_control_assert(phy->resets);
+}
+
+static int qcom_uniphy_pcie_power_on(struct phy *x)
+{
+ struct qcom_uniphy_pcie *phy = phy_get_drvdata(x);
+ int ret;
+
+ ret = reset_control_assert(phy->resets);
+ if (ret) {
+ dev_err(phy->dev, "reset assert failed (%d)\n", ret);
+ return ret;
+ }
+
+ usleep_range(RST_ASSERT_DELAY_MIN_US, RST_ASSERT_DELAY_MAX_US);
+
+ ret = reset_control_deassert(phy->resets);
+ if (ret) {
+ dev_err(phy->dev, "reset deassert failed (%d)\n", ret);
+ return ret;
+ }
+
+ usleep_range(PIPE_CLK_DELAY_MIN_US, PIPE_CLK_DELAY_MAX_US);
+
+ ret = clk_bulk_prepare_enable(phy->num_clks, phy->clks);
+ if (ret) {
+ dev_err(phy->dev, "clk prepare and enable failed %d\n", ret);
+ return ret;
+ }
+
+ usleep_range(CLK_EN_DELAY_MIN_US, CLK_EN_DELAY_MAX_US);
+
+ qcom_uniphy_pcie_init(phy);
+ return 0;
+}
+
+static inline int qcom_uniphy_pcie_get_resources(struct platform_device *pdev,
+ struct qcom_uniphy_pcie *phy)
+{
+ struct resource *res;
+
+ phy->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(phy->base))
+ return PTR_ERR(phy->base);
+
+ phy->num_clks = devm_clk_bulk_get_all(phy->dev, &phy->clks);
+ if (phy->num_clks < 0)
+ return phy->num_clks;
+
+ phy->resets = devm_reset_control_array_get_exclusive(phy->dev);
+ if (IS_ERR(phy->resets))
+ return PTR_ERR(phy->resets);
+
+ return 0;
+}
+
+/*
+ * Register a fixed rate pipe clock.
+ *
+ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
+ * controls it. The <s>_pipe_clk coming out of the GCC is requested
+ * by the PHY driver for its operations.
+ * We register the <s>_pipe_clksrc here. The gcc driver takes care
+ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
+ * Below picture shows this relationship.
+ *
+ * +---------------+
+ * | PHY block |<<---------------------------------------+
+ * | | |
+ * | +-------+ | +-----+ |
+ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
+ * clk | +-------+ | +-----+
+ * +---------------+
+ */
+static inline int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy, int id)
+{
+ const struct qcom_uniphy_pcie_data *data = phy->data;
+ struct clk_hw *hw;
+ char name[64];
+
+ snprintf(name, sizeof(name), "phy%d_pipe_clk_src", id);
+ hw = devm_clk_hw_register_fixed_rate(phy->dev, name, NULL, 0,
+ data->pipe_clk_rate);
+ if (IS_ERR(hw))
+ return dev_err_probe(phy->dev, PTR_ERR(hw),
+ "Unable to register %s\n", name);
+
+ return devm_of_clk_add_hw_provider(phy->dev, of_clk_hw_simple_get, hw);
+}
+
+static const struct of_device_id qcom_uniphy_pcie_id_table[] = {
+ {
+ .compatible = "qcom,ipq5332-uniphy-pcie-phy",
+ .data = &ipq5332_data,
+ }, {
+ /* Sentinel */
+ },
+};
+MODULE_DEVICE_TABLE(of, qcom_uniphy_pcie_id_table);
+
+static const struct phy_ops pcie_ops = {
+ .power_on = qcom_uniphy_pcie_power_on,
+ .power_off = qcom_uniphy_pcie_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int qcom_uniphy_pcie_probe(struct platform_device *pdev)
+{
+ struct phy_provider *phy_provider;
+ struct device *dev = &pdev->dev;
+ struct qcom_uniphy_pcie *phy;
+ struct phy *generic_phy;
+ int ret;
+
+ phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, phy);
+ phy->dev = &pdev->dev;
+
+ phy->data = of_device_get_match_data(dev);
+ if (!phy->data)
+ return -EINVAL;
+
+ phy->lanes = 1;
+ if (of_property_read_u32(dev_of_node(dev), "num-lanes", &phy->lanes))
+ dev_info(dev, "Not able to get num-lanes. Assuming 1\n");
+
+ ret = qcom_uniphy_pcie_get_resources(pdev, phy);
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to get resources: %d\n", ret);
+
+ generic_phy = devm_phy_create(phy->dev, NULL, &pcie_ops);
+ if (IS_ERR(generic_phy))
+ return PTR_ERR(generic_phy);
+
+ phy_set_drvdata(generic_phy, phy);
+
+ ret = phy_pipe_clk_register(phy, generic_phy->id);
+ if (ret)
+ dev_err(&pdev->dev, "failed to register phy pipe clk\n");
+
+ phy_provider = devm_of_phy_provider_register(phy->dev,
+ of_phy_simple_xlate);
+ if (IS_ERR(phy_provider))
+ return PTR_ERR(phy_provider);
+
+ return 0;
+}
+
+static struct platform_driver qcom_uniphy_pcie_driver = {
+ .probe = qcom_uniphy_pcie_probe,
+ .driver = {
+ .name = "qcom-uniphy-pcie",
+ .of_match_table = qcom_uniphy_pcie_id_table,
+ },
+};
+
+module_platform_driver(qcom_uniphy_pcie_driver);
+
+MODULE_DESCRIPTION("PCIE QCOM UNIPHY driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH v7 2/7] phy: qcom: Introduce PCIe UNIPHY 28LP driver
@ 2025-01-22 6:34 ` Varadarajan Narayanan
0 siblings, 0 replies; 37+ messages in thread
From: Varadarajan Narayanan @ 2025-01-22 6:34 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, quic_varada, linux-arm-msm,
linux-pci, devicetree, linux-kernel, linux-phy
From: Nitheesh Sekar <quic_nsekar@quicinc.com>
Add Qualcomm PCIe UNIPHY 28LP driver support present
in Qualcomm IPQ5332 SoC and the phy init sequence.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v6: Use generally followed pattern for getting num-lanes from DT
v5: * Use 'num-lanes' to differentiate instead of '3x1' or '3x2'
in compatible string
* Drop compatible specific init data as there is only one
compatible string
* Fix header file order
v4: Fix uppercase hex digit
Use phy->id for pipe clock source
v3: Added 'Reviewed-by: Dmitry Baryshkov' and made following updates
s/unsigned int/u32/g
Fix 'lane_offset' comments
Fix #define tab -> space
Fix mixed case hex numbers
Fix licensing & owner
Change for-loop pointer to use [] instead of ->
Use 'less than max' instead of 'not equal to max' in termination condition
Smatch and Coccinelle passed
v2: Drop IPQ5018 related code and data
Use uniform prefix for struct names
Place "}, {", on the same line
In qcom_uniphy_pcie_init(), use for-loop instead of while
Swap reset and clock disable order in qcom_uniphy_pcie_power_off
Add reset assert to qcom_uniphy_pcie_power_on's error path
Use macros for usleep duration
Inlined qcom_uniphy_pcie_get_resources & use devm_platform_get_and_ioremap_resource
Drop 'clock-output-names' from phy_pipe_clk_register
---
drivers/phy/qualcomm/Kconfig | 12 +
drivers/phy/qualcomm/Makefile | 1 +
.../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 286 ++++++++++++++++++
3 files changed, 299 insertions(+)
create mode 100644 drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
index 846f8c99547f..a6b71fda1b9c 100644
--- a/drivers/phy/qualcomm/Kconfig
+++ b/drivers/phy/qualcomm/Kconfig
@@ -154,6 +154,18 @@ config PHY_QCOM_M31_USB
management. This driver is required even for peripheral only or
host only mode configurations.
+config PHY_QCOM_UNIPHY_PCIE_28LP
+ bool "PCIE UNIPHY 28LP PHY driver"
+ depends on ARCH_QCOM
+ depends on HAS_IOMEM
+ depends on OF
+ select GENERIC_PHY
+ help
+ Enable this to support the PCIe UNIPHY 28LP phy transceiver that
+ is used with PCIe controllers on Qualcomm IPQ5332 chips. It
+ handles PHY initialization, clock management required after
+ resetting the hardware and power management.
+
config PHY_QCOM_USB_HS
tristate "Qualcomm USB HS PHY module"
depends on USB_ULPI_BUS
diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile
index eb60e950ad53..42038bc30974 100644
--- a/drivers/phy/qualcomm/Makefile
+++ b/drivers/phy/qualcomm/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_PHY_QCOM_QMP_USB_LEGACY) += phy-qcom-qmp-usb-legacy.o
obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2) += phy-qcom-snps-eusb2.o
obj-$(CONFIG_PHY_QCOM_EUSB2_REPEATER) += phy-qcom-eusb2-repeater.o
+obj-$(CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP) += phy-qcom-uniphy-pcie-28lp.o
obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
new file mode 100644
index 000000000000..d44dc769af6f
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#define RST_ASSERT_DELAY_MIN_US 100
+#define RST_ASSERT_DELAY_MAX_US 150
+#define PIPE_CLK_DELAY_MIN_US 5000
+#define PIPE_CLK_DELAY_MAX_US 5100
+#define CLK_EN_DELAY_MIN_US 30
+#define CLK_EN_DELAY_MAX_US 50
+#define CDR_CTRL_REG_1 0x80
+#define CDR_CTRL_REG_2 0x84
+#define CDR_CTRL_REG_3 0x88
+#define CDR_CTRL_REG_4 0x8c
+#define CDR_CTRL_REG_5 0x90
+#define CDR_CTRL_REG_6 0x94
+#define CDR_CTRL_REG_7 0x98
+#define SSCG_CTRL_REG_1 0x9c
+#define SSCG_CTRL_REG_2 0xa0
+#define SSCG_CTRL_REG_3 0xa4
+#define SSCG_CTRL_REG_4 0xa8
+#define SSCG_CTRL_REG_5 0xac
+#define SSCG_CTRL_REG_6 0xb0
+#define PCS_INTERNAL_CONTROL_2 0x2d8
+
+#define PHY_CFG_PLLCFG 0x220
+#define PHY_CFG_EIOS_DTCT_REG 0x3e4
+#define PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME 0x3e8
+
+#define PHY_MODE_FIXED 0x1
+
+enum qcom_uniphy_pcie_type {
+ PHY_TYPE_PCIE = 1,
+ PHY_TYPE_PCIE_GEN2,
+ PHY_TYPE_PCIE_GEN3,
+};
+
+struct qcom_uniphy_pcie_regs {
+ u32 offset;
+ u32 val;
+};
+
+struct qcom_uniphy_pcie_data {
+ int lane_offset; /* offset between the lane register bases */
+ u32 phy_type;
+ const struct qcom_uniphy_pcie_regs *init_seq;
+ u32 init_seq_num;
+ u32 pipe_clk_rate;
+};
+
+struct qcom_uniphy_pcie {
+ struct phy phy;
+ struct device *dev;
+ const struct qcom_uniphy_pcie_data *data;
+ struct clk_bulk_data *clks;
+ int num_clks;
+ struct reset_control *resets;
+ void __iomem *base;
+ int lanes;
+};
+
+#define phy_to_dw_phy(x) container_of((x), struct qca_uni_pcie_phy, phy)
+
+static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = {
+ {
+ .offset = PHY_CFG_PLLCFG,
+ .val = 0x30,
+ }, {
+ .offset = PHY_CFG_EIOS_DTCT_REG,
+ .val = 0x53ef,
+ }, {
+ .offset = PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME,
+ .val = 0xcf,
+ },
+};
+
+static const struct qcom_uniphy_pcie_data ipq5332_data = {
+ .lane_offset = 0x800,
+ .phy_type = PHY_TYPE_PCIE_GEN3,
+ .init_seq = ipq5332_regs,
+ .init_seq_num = ARRAY_SIZE(ipq5332_regs),
+ .pipe_clk_rate = 250000000,
+};
+
+static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy)
+{
+ const struct qcom_uniphy_pcie_data *data = phy->data;
+ const struct qcom_uniphy_pcie_regs *init_seq;
+ void __iomem *base = phy->base;
+ int lane, i;
+
+ for (lane = 0; lane < phy->lanes; lane++) {
+ init_seq = data->init_seq;
+
+ for (i = 0; i < data->init_seq_num; i++)
+ writel(init_seq[i].val, base + init_seq[i].offset);
+
+ base += data->lane_offset;
+ }
+}
+
+static int qcom_uniphy_pcie_power_off(struct phy *x)
+{
+ struct qcom_uniphy_pcie *phy = phy_get_drvdata(x);
+
+ clk_bulk_disable_unprepare(phy->num_clks, phy->clks);
+
+ return reset_control_assert(phy->resets);
+}
+
+static int qcom_uniphy_pcie_power_on(struct phy *x)
+{
+ struct qcom_uniphy_pcie *phy = phy_get_drvdata(x);
+ int ret;
+
+ ret = reset_control_assert(phy->resets);
+ if (ret) {
+ dev_err(phy->dev, "reset assert failed (%d)\n", ret);
+ return ret;
+ }
+
+ usleep_range(RST_ASSERT_DELAY_MIN_US, RST_ASSERT_DELAY_MAX_US);
+
+ ret = reset_control_deassert(phy->resets);
+ if (ret) {
+ dev_err(phy->dev, "reset deassert failed (%d)\n", ret);
+ return ret;
+ }
+
+ usleep_range(PIPE_CLK_DELAY_MIN_US, PIPE_CLK_DELAY_MAX_US);
+
+ ret = clk_bulk_prepare_enable(phy->num_clks, phy->clks);
+ if (ret) {
+ dev_err(phy->dev, "clk prepare and enable failed %d\n", ret);
+ return ret;
+ }
+
+ usleep_range(CLK_EN_DELAY_MIN_US, CLK_EN_DELAY_MAX_US);
+
+ qcom_uniphy_pcie_init(phy);
+ return 0;
+}
+
+static inline int qcom_uniphy_pcie_get_resources(struct platform_device *pdev,
+ struct qcom_uniphy_pcie *phy)
+{
+ struct resource *res;
+
+ phy->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(phy->base))
+ return PTR_ERR(phy->base);
+
+ phy->num_clks = devm_clk_bulk_get_all(phy->dev, &phy->clks);
+ if (phy->num_clks < 0)
+ return phy->num_clks;
+
+ phy->resets = devm_reset_control_array_get_exclusive(phy->dev);
+ if (IS_ERR(phy->resets))
+ return PTR_ERR(phy->resets);
+
+ return 0;
+}
+
+/*
+ * Register a fixed rate pipe clock.
+ *
+ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
+ * controls it. The <s>_pipe_clk coming out of the GCC is requested
+ * by the PHY driver for its operations.
+ * We register the <s>_pipe_clksrc here. The gcc driver takes care
+ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
+ * Below picture shows this relationship.
+ *
+ * +---------------+
+ * | PHY block |<<---------------------------------------+
+ * | | |
+ * | +-------+ | +-----+ |
+ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
+ * clk | +-------+ | +-----+
+ * +---------------+
+ */
+static inline int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy, int id)
+{
+ const struct qcom_uniphy_pcie_data *data = phy->data;
+ struct clk_hw *hw;
+ char name[64];
+
+ snprintf(name, sizeof(name), "phy%d_pipe_clk_src", id);
+ hw = devm_clk_hw_register_fixed_rate(phy->dev, name, NULL, 0,
+ data->pipe_clk_rate);
+ if (IS_ERR(hw))
+ return dev_err_probe(phy->dev, PTR_ERR(hw),
+ "Unable to register %s\n", name);
+
+ return devm_of_clk_add_hw_provider(phy->dev, of_clk_hw_simple_get, hw);
+}
+
+static const struct of_device_id qcom_uniphy_pcie_id_table[] = {
+ {
+ .compatible = "qcom,ipq5332-uniphy-pcie-phy",
+ .data = &ipq5332_data,
+ }, {
+ /* Sentinel */
+ },
+};
+MODULE_DEVICE_TABLE(of, qcom_uniphy_pcie_id_table);
+
+static const struct phy_ops pcie_ops = {
+ .power_on = qcom_uniphy_pcie_power_on,
+ .power_off = qcom_uniphy_pcie_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int qcom_uniphy_pcie_probe(struct platform_device *pdev)
+{
+ struct phy_provider *phy_provider;
+ struct device *dev = &pdev->dev;
+ struct qcom_uniphy_pcie *phy;
+ struct phy *generic_phy;
+ int ret;
+
+ phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, phy);
+ phy->dev = &pdev->dev;
+
+ phy->data = of_device_get_match_data(dev);
+ if (!phy->data)
+ return -EINVAL;
+
+ phy->lanes = 1;
+ if (of_property_read_u32(dev_of_node(dev), "num-lanes", &phy->lanes))
+ dev_info(dev, "Not able to get num-lanes. Assuming 1\n");
+
+ ret = qcom_uniphy_pcie_get_resources(pdev, phy);
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to get resources: %d\n", ret);
+
+ generic_phy = devm_phy_create(phy->dev, NULL, &pcie_ops);
+ if (IS_ERR(generic_phy))
+ return PTR_ERR(generic_phy);
+
+ phy_set_drvdata(generic_phy, phy);
+
+ ret = phy_pipe_clk_register(phy, generic_phy->id);
+ if (ret)
+ dev_err(&pdev->dev, "failed to register phy pipe clk\n");
+
+ phy_provider = devm_of_phy_provider_register(phy->dev,
+ of_phy_simple_xlate);
+ if (IS_ERR(phy_provider))
+ return PTR_ERR(phy_provider);
+
+ return 0;
+}
+
+static struct platform_driver qcom_uniphy_pcie_driver = {
+ .probe = qcom_uniphy_pcie_probe,
+ .driver = {
+ .name = "qcom-uniphy-pcie",
+ .of_match_table = qcom_uniphy_pcie_id_table,
+ },
+};
+
+module_platform_driver(qcom_uniphy_pcie_driver);
+
+MODULE_DESCRIPTION("PCIE QCOM UNIPHY driver");
+MODULE_LICENSE("GPL");
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v7 3/7] dt-bindings: PCI: qcom: Use sdx55 reg description for ipq9574
2025-01-22 6:34 ` Varadarajan Narayanan
@ 2025-01-22 6:34 ` Varadarajan Narayanan
-1 siblings, 0 replies; 37+ messages in thread
From: Varadarajan Narayanan @ 2025-01-22 6:34 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, quic_varada, linux-arm-msm,
linux-pci, devicetree, linux-kernel, linux-phy
All DT entries except "reg" is similar between ipq5332 and
ipq9574. ipq9574 has 5 registers while ipq5332 has 6. MHI is the
additional (i.e. sixth entry). Since this matches with the
sdx55's "reg" definition which allows for 5 or 6 registers,
combine ipq9574 with sdx55.
This change is to prepare ipq9574 to be used as ipq5332's
fallback compatible.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index bd87f6b49d68..413c6b76c26c 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -165,7 +165,6 @@ allOf:
enum:
- qcom,pcie-ipq6018
- qcom,pcie-ipq8074-gen3
- - qcom,pcie-ipq9574
then:
properties:
reg:
@@ -206,6 +205,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,pcie-ipq9574
- qcom,pcie-sdx55
then:
properties:
--
2.34.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH v7 3/7] dt-bindings: PCI: qcom: Use sdx55 reg description for ipq9574
@ 2025-01-22 6:34 ` Varadarajan Narayanan
0 siblings, 0 replies; 37+ messages in thread
From: Varadarajan Narayanan @ 2025-01-22 6:34 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, quic_varada, linux-arm-msm,
linux-pci, devicetree, linux-kernel, linux-phy
All DT entries except "reg" is similar between ipq5332 and
ipq9574. ipq9574 has 5 registers while ipq5332 has 6. MHI is the
additional (i.e. sixth entry). Since this matches with the
sdx55's "reg" definition which allows for 5 or 6 registers,
combine ipq9574 with sdx55.
This change is to prepare ipq9574 to be used as ipq5332's
fallback compatible.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index bd87f6b49d68..413c6b76c26c 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -165,7 +165,6 @@ allOf:
enum:
- qcom,pcie-ipq6018
- qcom,pcie-ipq8074-gen3
- - qcom,pcie-ipq9574
then:
properties:
reg:
@@ -206,6 +205,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,pcie-ipq9574
- qcom,pcie-sdx55
then:
properties:
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v7 3/7] dt-bindings: PCI: qcom: Use sdx55 reg description for ipq9574
2025-01-22 6:34 ` Varadarajan Narayanan
@ 2025-01-23 7:55 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 37+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-23 7:55 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, linux-arm-msm, linux-pci,
devicetree, linux-kernel, linux-phy
On Wed, Jan 22, 2025 at 12:04:07PM +0530, Varadarajan Narayanan wrote:
> All DT entries except "reg" is similar between ipq5332 and
> ipq9574. ipq9574 has 5 registers while ipq5332 has 6. MHI is the
> additional (i.e. sixth entry). Since this matches with the
> sdx55's "reg" definition which allows for 5 or 6 registers,
> combine ipq9574 with sdx55.
>
> This change is to prepare ipq9574 to be used as ipq5332's
> fallback compatible.
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v7 3/7] dt-bindings: PCI: qcom: Use sdx55 reg description for ipq9574
@ 2025-01-23 7:55 ` Krzysztof Kozlowski
0 siblings, 0 replies; 37+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-23 7:55 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, linux-arm-msm, linux-pci,
devicetree, linux-kernel, linux-phy
On Wed, Jan 22, 2025 at 12:04:07PM +0530, Varadarajan Narayanan wrote:
> All DT entries except "reg" is similar between ipq5332 and
> ipq9574. ipq9574 has 5 registers while ipq5332 has 6. MHI is the
> additional (i.e. sixth entry). Since this matches with the
> sdx55's "reg" definition which allows for 5 or 6 registers,
> combine ipq9574 with sdx55.
>
> This change is to prepare ipq9574 to be used as ipq5332's
> fallback compatible.
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v7 3/7] dt-bindings: PCI: qcom: Use sdx55 reg description for ipq9574
2025-01-22 6:34 ` Varadarajan Narayanan
@ 2025-02-03 16:16 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 37+ messages in thread
From: Manivannan Sadhasivam @ 2025-02-03 16:16 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: bhelgaas, lpieralisi, kw, robh, krzk+dt, conor+dt, vkoul, kishon,
andersson, konradybcio, p.zabel, dmitry.baryshkov, quic_nsekar,
linux-arm-msm, linux-pci, devicetree, linux-kernel, linux-phy
On Wed, Jan 22, 2025 at 12:04:07PM +0530, Varadarajan Narayanan wrote:
> All DT entries except "reg" is similar between ipq5332 and
> ipq9574. ipq9574 has 5 registers while ipq5332 has 6. MHI is the
> additional (i.e. sixth entry). Since this matches with the
> sdx55's "reg" definition which allows for 5 or 6 registers,
> combine ipq9574 with sdx55.
>
> This change is to prepare ipq9574 to be used as ipq5332's
> fallback compatible.
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Mani
> ---
> Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index bd87f6b49d68..413c6b76c26c 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -165,7 +165,6 @@ allOf:
> enum:
> - qcom,pcie-ipq6018
> - qcom,pcie-ipq8074-gen3
> - - qcom,pcie-ipq9574
> then:
> properties:
> reg:
> @@ -206,6 +205,7 @@ allOf:
> compatible:
> contains:
> enum:
> + - qcom,pcie-ipq9574
> - qcom,pcie-sdx55
> then:
> properties:
> --
> 2.34.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v7 3/7] dt-bindings: PCI: qcom: Use sdx55 reg description for ipq9574
@ 2025-02-03 16:16 ` Manivannan Sadhasivam
0 siblings, 0 replies; 37+ messages in thread
From: Manivannan Sadhasivam @ 2025-02-03 16:16 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: bhelgaas, lpieralisi, kw, robh, krzk+dt, conor+dt, vkoul, kishon,
andersson, konradybcio, p.zabel, dmitry.baryshkov, quic_nsekar,
linux-arm-msm, linux-pci, devicetree, linux-kernel, linux-phy
On Wed, Jan 22, 2025 at 12:04:07PM +0530, Varadarajan Narayanan wrote:
> All DT entries except "reg" is similar between ipq5332 and
> ipq9574. ipq9574 has 5 registers while ipq5332 has 6. MHI is the
> additional (i.e. sixth entry). Since this matches with the
> sdx55's "reg" definition which allows for 5 or 6 registers,
> combine ipq9574 with sdx55.
>
> This change is to prepare ipq9574 to be used as ipq5332's
> fallback compatible.
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Mani
> ---
> Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index bd87f6b49d68..413c6b76c26c 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -165,7 +165,6 @@ allOf:
> enum:
> - qcom,pcie-ipq6018
> - qcom,pcie-ipq8074-gen3
> - - qcom,pcie-ipq9574
> then:
> properties:
> reg:
> @@ -206,6 +205,7 @@ allOf:
> compatible:
> contains:
> enum:
> + - qcom,pcie-ipq9574
> - qcom,pcie-sdx55
> then:
> properties:
> --
> 2.34.1
>
--
மணிவண்ணன் சதாசிவம்
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v7 4/7] arm64: dts: qcom: ipq9574: Reorder reg and reg-names
2025-01-22 6:34 ` Varadarajan Narayanan
@ 2025-01-22 6:34 ` Varadarajan Narayanan
-1 siblings, 0 replies; 37+ messages in thread
From: Varadarajan Narayanan @ 2025-01-22 6:34 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, quic_varada, linux-arm-msm,
linux-pci, devicetree, linux-kernel, linux-phy
The 'reg' & 'reg-names' constraints used in the bindings and dtsi
are different resulting in dt_bindings_check errors. Re-order
them to address following errors.
arch/arm64/boot/dts/qcom/ipq9574-rdp449.dtb: pcie@20000000: reg-names:0: 'parf' was expected
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 52 +++++++++++++++++----------
1 file changed, 34 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 942290028972..d27c55c7f6e4 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -876,12 +876,16 @@ frame@b128000 {
pcie1: pcie@10000000 {
compatible = "qcom,pcie-ipq9574";
- reg = <0x10000000 0xf1d>,
- <0x10000f20 0xa8>,
- <0x10001000 0x1000>,
- <0x000f8000 0x4000>,
- <0x10100000 0x1000>;
- reg-names = "dbi", "elbi", "atu", "parf", "config";
+ reg = <0x000f8000 0x4000>,
+ <0x10000000 0xf1d>,
+ <0x10000f20 0xa8>,
+ <0x10001000 0x1000>,
+ <0x10100000 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config";
device_type = "pci";
linux,pci-domain = <1>;
bus-range = <0x00 0xff>;
@@ -956,12 +960,16 @@ pcie1: pcie@10000000 {
pcie3: pcie@18000000 {
compatible = "qcom,pcie-ipq9574";
- reg = <0x18000000 0xf1d>,
- <0x18000f20 0xa8>,
- <0x18001000 0x1000>,
- <0x000f0000 0x4000>,
- <0x18100000 0x1000>;
- reg-names = "dbi", "elbi", "atu", "parf", "config";
+ reg = <0x000f0000 0x4000>,
+ <0x18000000 0xf1d>,
+ <0x18000f20 0xa8>,
+ <0x18001000 0x1000>,
+ <0x18100000 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config";
device_type = "pci";
linux,pci-domain = <3>;
bus-range = <0x00 0xff>;
@@ -1036,12 +1044,16 @@ pcie3: pcie@18000000 {
pcie2: pcie@20000000 {
compatible = "qcom,pcie-ipq9574";
- reg = <0x20000000 0xf1d>,
+ reg = <0x00088000 0x4000>,
+ <0x20000000 0xf1d>,
<0x20000f20 0xa8>,
<0x20001000 0x1000>,
- <0x00088000 0x4000>,
<0x20100000 0x1000>;
- reg-names = "dbi", "elbi", "atu", "parf", "config";
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config";
device_type = "pci";
linux,pci-domain = <2>;
bus-range = <0x00 0xff>;
@@ -1116,12 +1128,16 @@ pcie2: pcie@20000000 {
pcie0: pci@28000000 {
compatible = "qcom,pcie-ipq9574";
- reg = <0x28000000 0xf1d>,
+ reg = <0x00080000 0x4000>,
+ <0x28000000 0xf1d>,
<0x28000f20 0xa8>,
<0x28001000 0x1000>,
- <0x00080000 0x4000>,
<0x28100000 0x1000>;
- reg-names = "dbi", "elbi", "atu", "parf", "config";
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
--
2.34.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH v7 4/7] arm64: dts: qcom: ipq9574: Reorder reg and reg-names
@ 2025-01-22 6:34 ` Varadarajan Narayanan
0 siblings, 0 replies; 37+ messages in thread
From: Varadarajan Narayanan @ 2025-01-22 6:34 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, quic_varada, linux-arm-msm,
linux-pci, devicetree, linux-kernel, linux-phy
The 'reg' & 'reg-names' constraints used in the bindings and dtsi
are different resulting in dt_bindings_check errors. Re-order
them to address following errors.
arch/arm64/boot/dts/qcom/ipq9574-rdp449.dtb: pcie@20000000: reg-names:0: 'parf' was expected
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 52 +++++++++++++++++----------
1 file changed, 34 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 942290028972..d27c55c7f6e4 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -876,12 +876,16 @@ frame@b128000 {
pcie1: pcie@10000000 {
compatible = "qcom,pcie-ipq9574";
- reg = <0x10000000 0xf1d>,
- <0x10000f20 0xa8>,
- <0x10001000 0x1000>,
- <0x000f8000 0x4000>,
- <0x10100000 0x1000>;
- reg-names = "dbi", "elbi", "atu", "parf", "config";
+ reg = <0x000f8000 0x4000>,
+ <0x10000000 0xf1d>,
+ <0x10000f20 0xa8>,
+ <0x10001000 0x1000>,
+ <0x10100000 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config";
device_type = "pci";
linux,pci-domain = <1>;
bus-range = <0x00 0xff>;
@@ -956,12 +960,16 @@ pcie1: pcie@10000000 {
pcie3: pcie@18000000 {
compatible = "qcom,pcie-ipq9574";
- reg = <0x18000000 0xf1d>,
- <0x18000f20 0xa8>,
- <0x18001000 0x1000>,
- <0x000f0000 0x4000>,
- <0x18100000 0x1000>;
- reg-names = "dbi", "elbi", "atu", "parf", "config";
+ reg = <0x000f0000 0x4000>,
+ <0x18000000 0xf1d>,
+ <0x18000f20 0xa8>,
+ <0x18001000 0x1000>,
+ <0x18100000 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config";
device_type = "pci";
linux,pci-domain = <3>;
bus-range = <0x00 0xff>;
@@ -1036,12 +1044,16 @@ pcie3: pcie@18000000 {
pcie2: pcie@20000000 {
compatible = "qcom,pcie-ipq9574";
- reg = <0x20000000 0xf1d>,
+ reg = <0x00088000 0x4000>,
+ <0x20000000 0xf1d>,
<0x20000f20 0xa8>,
<0x20001000 0x1000>,
- <0x00088000 0x4000>,
<0x20100000 0x1000>;
- reg-names = "dbi", "elbi", "atu", "parf", "config";
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config";
device_type = "pci";
linux,pci-domain = <2>;
bus-range = <0x00 0xff>;
@@ -1116,12 +1128,16 @@ pcie2: pcie@20000000 {
pcie0: pci@28000000 {
compatible = "qcom,pcie-ipq9574";
- reg = <0x28000000 0xf1d>,
+ reg = <0x00080000 0x4000>,
+ <0x28000000 0xf1d>,
<0x28000f20 0xa8>,
<0x28001000 0x1000>,
- <0x00080000 0x4000>,
<0x28100000 0x1000>;
- reg-names = "dbi", "elbi", "atu", "parf", "config";
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v7 4/7] arm64: dts: qcom: ipq9574: Reorder reg and reg-names
2025-01-22 6:34 ` Varadarajan Narayanan
@ 2025-01-27 10:33 ` Konrad Dybcio
-1 siblings, 0 replies; 37+ messages in thread
From: Konrad Dybcio @ 2025-01-27 10:33 UTC (permalink / raw)
To: Varadarajan Narayanan, bhelgaas, lpieralisi, kw,
manivannan.sadhasivam, robh, krzk+dt, conor+dt, vkoul, kishon,
andersson, konradybcio, p.zabel, dmitry.baryshkov, quic_nsekar,
linux-arm-msm, linux-pci, devicetree, linux-kernel, linux-phy
On 22.01.2025 7:34 AM, Varadarajan Narayanan wrote:
> The 'reg' & 'reg-names' constraints used in the bindings and dtsi
> are different resulting in dt_bindings_check errors. Re-order
> them to address following errors.
>
> arch/arm64/boot/dts/qcom/ipq9574-rdp449.dtb: pcie@20000000: reg-names:0: 'parf' was expected
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 52 +++++++++++++++++----------
> 1 file changed, 34 insertions(+), 18 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 942290028972..d27c55c7f6e4 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -876,12 +876,16 @@ frame@b128000 {
>
> pcie1: pcie@10000000 {
> compatible = "qcom,pcie-ipq9574";
> - reg = <0x10000000 0xf1d>,
> - <0x10000f20 0xa8>,
> - <0x10001000 0x1000>,
> - <0x000f8000 0x4000>,
> - <0x10100000 0x1000>;
> - reg-names = "dbi", "elbi", "atu", "parf", "config";
> + reg = <0x000f8000 0x4000>,
> + <0x10000000 0xf1d>,
> + <0x10000f20 0xa8>,
> + <0x10001000 0x1000>,
> + <0x10100000 0x1000>;
The unit address (the one after '@' in the node definition) is supposed to
match the first 'reg' entry. So you need to update that and reorder the
nodes accordingly.
Krzysztof, is this acceptable to pick up given the reg entries are being
shuffled around?
Konrad
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH v7 4/7] arm64: dts: qcom: ipq9574: Reorder reg and reg-names
@ 2025-01-27 10:33 ` Konrad Dybcio
0 siblings, 0 replies; 37+ messages in thread
From: Konrad Dybcio @ 2025-01-27 10:33 UTC (permalink / raw)
To: Varadarajan Narayanan, bhelgaas, lpieralisi, kw,
manivannan.sadhasivam, robh, krzk+dt, conor+dt, vkoul, kishon,
andersson, konradybcio, p.zabel, dmitry.baryshkov, quic_nsekar,
linux-arm-msm, linux-pci, devicetree, linux-kernel, linux-phy
On 22.01.2025 7:34 AM, Varadarajan Narayanan wrote:
> The 'reg' & 'reg-names' constraints used in the bindings and dtsi
> are different resulting in dt_bindings_check errors. Re-order
> them to address following errors.
>
> arch/arm64/boot/dts/qcom/ipq9574-rdp449.dtb: pcie@20000000: reg-names:0: 'parf' was expected
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 52 +++++++++++++++++----------
> 1 file changed, 34 insertions(+), 18 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 942290028972..d27c55c7f6e4 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -876,12 +876,16 @@ frame@b128000 {
>
> pcie1: pcie@10000000 {
> compatible = "qcom,pcie-ipq9574";
> - reg = <0x10000000 0xf1d>,
> - <0x10000f20 0xa8>,
> - <0x10001000 0x1000>,
> - <0x000f8000 0x4000>,
> - <0x10100000 0x1000>;
> - reg-names = "dbi", "elbi", "atu", "parf", "config";
> + reg = <0x000f8000 0x4000>,
> + <0x10000000 0xf1d>,
> + <0x10000f20 0xa8>,
> + <0x10001000 0x1000>,
> + <0x10100000 0x1000>;
The unit address (the one after '@' in the node definition) is supposed to
match the first 'reg' entry. So you need to update that and reorder the
nodes accordingly.
Krzysztof, is this acceptable to pick up given the reg entries are being
shuffled around?
Konrad
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH v7 4/7] arm64: dts: qcom: ipq9574: Reorder reg and reg-names
2025-01-27 10:33 ` Konrad Dybcio
@ 2025-02-03 16:27 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 37+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-03 16:27 UTC (permalink / raw)
To: Konrad Dybcio, Varadarajan Narayanan, bhelgaas, lpieralisi, kw,
manivannan.sadhasivam, robh, krzk+dt, conor+dt, vkoul, kishon,
andersson, konradybcio, p.zabel, dmitry.baryshkov, quic_nsekar,
linux-arm-msm, linux-pci, devicetree, linux-kernel, linux-phy
On 27/01/2025 11:33, Konrad Dybcio wrote:
> On 22.01.2025 7:34 AM, Varadarajan Narayanan wrote:
>> The 'reg' & 'reg-names' constraints used in the bindings and dtsi
>> are different resulting in dt_bindings_check errors. Re-order
>> them to address following errors.
>>
>> arch/arm64/boot/dts/qcom/ipq9574-rdp449.dtb: pcie@20000000: reg-names:0: 'parf' was expected
>>
>> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 52 +++++++++++++++++----------
>> 1 file changed, 34 insertions(+), 18 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index 942290028972..d27c55c7f6e4 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -876,12 +876,16 @@ frame@b128000 {
>>
>> pcie1: pcie@10000000 {
>> compatible = "qcom,pcie-ipq9574";
>> - reg = <0x10000000 0xf1d>,
>> - <0x10000f20 0xa8>,
>> - <0x10001000 0x1000>,
>> - <0x000f8000 0x4000>,
>> - <0x10100000 0x1000>;
>> - reg-names = "dbi", "elbi", "atu", "parf", "config";
>> + reg = <0x000f8000 0x4000>,
>> + <0x10000000 0xf1d>,
>> + <0x10000f20 0xa8>,
>> + <0x10001000 0x1000>,
>> + <0x10100000 0x1000>;
>
> The unit address (the one after '@' in the node definition) is supposed to
> match the first 'reg' entry. So you need to update that and reorder the
> nodes accordingly.
>
> Krzysztof, is this acceptable to pick up given the reg entries are being
> shuffled around?
Uh, no, this leads to warnings.
BTW, I really hope tools were being used to spot that, not maintainers
like you or me.
But this is anyway old patchset whose newer version was rejected. There
is just to many wrong things happening in the process - now one more:
not running standard tests on this.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH v7 4/7] arm64: dts: qcom: ipq9574: Reorder reg and reg-names
@ 2025-02-03 16:27 ` Krzysztof Kozlowski
0 siblings, 0 replies; 37+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-03 16:27 UTC (permalink / raw)
To: Konrad Dybcio, Varadarajan Narayanan, bhelgaas, lpieralisi, kw,
manivannan.sadhasivam, robh, krzk+dt, conor+dt, vkoul, kishon,
andersson, konradybcio, p.zabel, dmitry.baryshkov, quic_nsekar,
linux-arm-msm, linux-pci, devicetree, linux-kernel, linux-phy
On 27/01/2025 11:33, Konrad Dybcio wrote:
> On 22.01.2025 7:34 AM, Varadarajan Narayanan wrote:
>> The 'reg' & 'reg-names' constraints used in the bindings and dtsi
>> are different resulting in dt_bindings_check errors. Re-order
>> them to address following errors.
>>
>> arch/arm64/boot/dts/qcom/ipq9574-rdp449.dtb: pcie@20000000: reg-names:0: 'parf' was expected
>>
>> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 52 +++++++++++++++++----------
>> 1 file changed, 34 insertions(+), 18 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index 942290028972..d27c55c7f6e4 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -876,12 +876,16 @@ frame@b128000 {
>>
>> pcie1: pcie@10000000 {
>> compatible = "qcom,pcie-ipq9574";
>> - reg = <0x10000000 0xf1d>,
>> - <0x10000f20 0xa8>,
>> - <0x10001000 0x1000>,
>> - <0x000f8000 0x4000>,
>> - <0x10100000 0x1000>;
>> - reg-names = "dbi", "elbi", "atu", "parf", "config";
>> + reg = <0x000f8000 0x4000>,
>> + <0x10000000 0xf1d>,
>> + <0x10000f20 0xa8>,
>> + <0x10001000 0x1000>,
>> + <0x10100000 0x1000>;
>
> The unit address (the one after '@' in the node definition) is supposed to
> match the first 'reg' entry. So you need to update that and reorder the
> nodes accordingly.
>
> Krzysztof, is this acceptable to pick up given the reg entries are being
> shuffled around?
Uh, no, this leads to warnings.
BTW, I really hope tools were being used to spot that, not maintainers
like you or me.
But this is anyway old patchset whose newer version was rejected. There
is just to many wrong things happening in the process - now one more:
not running standard tests on this.
Best regards,
Krzysztof
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v7 5/7] dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller
2025-01-22 6:34 ` Varadarajan Narayanan
@ 2025-01-22 6:34 ` Varadarajan Narayanan
-1 siblings, 0 replies; 37+ messages in thread
From: Varadarajan Narayanan @ 2025-01-22 6:34 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, quic_varada, linux-arm-msm,
linux-pci, devicetree, linux-kernel, linux-phy
Document the PCIe controller on IPQ5332 platform. IPQ5332 will
use IPQ9574 as the fall back compatible.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v7: Moved ipq9574 related changes to a separate patch
Add 'global' interrupt
v6: Commit message update only. Add info regarding the moving of
ipq9574 from 5 "reg" definition to 5 or 6 reg definition.
v5: Re-arrange 5332 and 9574 compatibles to handle fallback usage in dts
v4: * v3 reused ipq9574 bindings for ipq5332. Instead add one for ipq5332
* DTS uses ipq9574 compatible as fallback. Hence move ipq9574 to be able
to use the 'reg' section for both ipq5332 and ipq9574. Else, dtbs_check
and dt_binding_check flag errors.
---
.../devicetree/bindings/pci/qcom,pcie.yaml | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 413c6b76c26c..ead97286fd41 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -34,6 +34,10 @@ properties:
- items:
- const: qcom,pcie-msm8998
- const: qcom,pcie-msm8996
+ - items:
+ - enum:
+ - qcom,pcie-ipq5332
+ - const: qcom,pcie-ipq9574
reg:
minItems: 4
@@ -45,11 +49,11 @@ properties:
interrupts:
minItems: 1
- maxItems: 8
+ maxItems: 9
interrupt-names:
minItems: 1
- maxItems: 8
+ maxItems: 9
iommu-map:
minItems: 1
@@ -205,6 +209,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,pcie-ipq5332
- qcom,pcie-ipq9574
- qcom,pcie-sdx55
then:
@@ -407,6 +412,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,pcie-ipq5332
- qcom,pcie-ipq9574
then:
properties:
@@ -439,6 +445,7 @@ allOf:
interrupts:
minItems: 8
interrupt-names:
+ minItems: 8
items:
- const: msi0
- const: msi1
@@ -448,6 +455,7 @@ allOf:
- const: msi5
- const: msi6
- const: msi7
+ - const: global
- if:
properties:
@@ -555,6 +563,7 @@ allOf:
enum:
- qcom,pcie-apq8064
- qcom,pcie-ipq4019
+ - qcom,pcie-ipq5332
- qcom,pcie-ipq8064
- qcom,pcie-ipq8064v2
- qcom,pcie-ipq8074
--
2.34.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH v7 5/7] dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller
@ 2025-01-22 6:34 ` Varadarajan Narayanan
0 siblings, 0 replies; 37+ messages in thread
From: Varadarajan Narayanan @ 2025-01-22 6:34 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, quic_varada, linux-arm-msm,
linux-pci, devicetree, linux-kernel, linux-phy
Document the PCIe controller on IPQ5332 platform. IPQ5332 will
use IPQ9574 as the fall back compatible.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v7: Moved ipq9574 related changes to a separate patch
Add 'global' interrupt
v6: Commit message update only. Add info regarding the moving of
ipq9574 from 5 "reg" definition to 5 or 6 reg definition.
v5: Re-arrange 5332 and 9574 compatibles to handle fallback usage in dts
v4: * v3 reused ipq9574 bindings for ipq5332. Instead add one for ipq5332
* DTS uses ipq9574 compatible as fallback. Hence move ipq9574 to be able
to use the 'reg' section for both ipq5332 and ipq9574. Else, dtbs_check
and dt_binding_check flag errors.
---
.../devicetree/bindings/pci/qcom,pcie.yaml | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 413c6b76c26c..ead97286fd41 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -34,6 +34,10 @@ properties:
- items:
- const: qcom,pcie-msm8998
- const: qcom,pcie-msm8996
+ - items:
+ - enum:
+ - qcom,pcie-ipq5332
+ - const: qcom,pcie-ipq9574
reg:
minItems: 4
@@ -45,11 +49,11 @@ properties:
interrupts:
minItems: 1
- maxItems: 8
+ maxItems: 9
interrupt-names:
minItems: 1
- maxItems: 8
+ maxItems: 9
iommu-map:
minItems: 1
@@ -205,6 +209,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,pcie-ipq5332
- qcom,pcie-ipq9574
- qcom,pcie-sdx55
then:
@@ -407,6 +412,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,pcie-ipq5332
- qcom,pcie-ipq9574
then:
properties:
@@ -439,6 +445,7 @@ allOf:
interrupts:
minItems: 8
interrupt-names:
+ minItems: 8
items:
- const: msi0
- const: msi1
@@ -448,6 +455,7 @@ allOf:
- const: msi5
- const: msi6
- const: msi7
+ - const: global
- if:
properties:
@@ -555,6 +563,7 @@ allOf:
enum:
- qcom,pcie-apq8064
- qcom,pcie-ipq4019
+ - qcom,pcie-ipq5332
- qcom,pcie-ipq8064
- qcom,pcie-ipq8064v2
- qcom,pcie-ipq8074
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v7 5/7] dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller
2025-01-22 6:34 ` Varadarajan Narayanan
@ 2025-01-23 7:58 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 37+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-23 7:58 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, linux-arm-msm, linux-pci,
devicetree, linux-kernel, linux-phy
On Wed, Jan 22, 2025 at 12:04:09PM +0530, Varadarajan Narayanan wrote:
> Document the PCIe controller on IPQ5332 platform. IPQ5332 will
> use IPQ9574 as the fall back compatible.
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> v7: Moved ipq9574 related changes to a separate patch
> Add 'global' interrupt
>
> v6: Commit message update only. Add info regarding the moving of
> ipq9574 from 5 "reg" definition to 5 or 6 reg definition.
>
> v5: Re-arrange 5332 and 9574 compatibles to handle fallback usage in dts
>
> v4: * v3 reused ipq9574 bindings for ipq5332. Instead add one for ipq5332
> * DTS uses ipq9574 compatible as fallback. Hence move ipq9574 to be able
> to use the 'reg' section for both ipq5332 and ipq9574. Else, dtbs_check
> and dt_binding_check flag errors.
> ---
> .../devicetree/bindings/pci/qcom,pcie.yaml | 13 +++++++++++--
> 1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index 413c6b76c26c..ead97286fd41 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -34,6 +34,10 @@ properties:
> - items:
> - const: qcom,pcie-msm8998
> - const: qcom,pcie-msm8996
> + - items:
> + - enum:
> + - qcom,pcie-ipq5332
> + - const: qcom,pcie-ipq9574
Repeated many times on reviews to qcom: don't add to the end of the
lists. In case of multiple items, these are ordered by fallback, so this
goes next to other ipq entry... wait, that's already qcom,pcie-ipq9574,
so why are you duplicating?
On what tree are you working?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v7 5/7] dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller
@ 2025-01-23 7:58 ` Krzysztof Kozlowski
0 siblings, 0 replies; 37+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-23 7:58 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, linux-arm-msm, linux-pci,
devicetree, linux-kernel, linux-phy
On Wed, Jan 22, 2025 at 12:04:09PM +0530, Varadarajan Narayanan wrote:
> Document the PCIe controller on IPQ5332 platform. IPQ5332 will
> use IPQ9574 as the fall back compatible.
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> v7: Moved ipq9574 related changes to a separate patch
> Add 'global' interrupt
>
> v6: Commit message update only. Add info regarding the moving of
> ipq9574 from 5 "reg" definition to 5 or 6 reg definition.
>
> v5: Re-arrange 5332 and 9574 compatibles to handle fallback usage in dts
>
> v4: * v3 reused ipq9574 bindings for ipq5332. Instead add one for ipq5332
> * DTS uses ipq9574 compatible as fallback. Hence move ipq9574 to be able
> to use the 'reg' section for both ipq5332 and ipq9574. Else, dtbs_check
> and dt_binding_check flag errors.
> ---
> .../devicetree/bindings/pci/qcom,pcie.yaml | 13 +++++++++++--
> 1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index 413c6b76c26c..ead97286fd41 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -34,6 +34,10 @@ properties:
> - items:
> - const: qcom,pcie-msm8998
> - const: qcom,pcie-msm8996
> + - items:
> + - enum:
> + - qcom,pcie-ipq5332
> + - const: qcom,pcie-ipq9574
Repeated many times on reviews to qcom: don't add to the end of the
lists. In case of multiple items, these are ordered by fallback, so this
goes next to other ipq entry... wait, that's already qcom,pcie-ipq9574,
so why are you duplicating?
On what tree are you working?
Best regards,
Krzysztof
--
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^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v7 5/7] dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller
2025-01-23 7:58 ` Krzysztof Kozlowski
@ 2025-01-23 8:05 ` Varadarajan Narayanan
-1 siblings, 0 replies; 37+ messages in thread
From: Varadarajan Narayanan @ 2025-01-23 8:05 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, linux-arm-msm, linux-pci,
devicetree, linux-kernel, linux-phy
On Thu, Jan 23, 2025 at 08:58:29AM +0100, Krzysztof Kozlowski wrote:
> On Wed, Jan 22, 2025 at 12:04:09PM +0530, Varadarajan Narayanan wrote:
> > Document the PCIe controller on IPQ5332 platform. IPQ5332 will
> > use IPQ9574 as the fall back compatible.
> >
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
> > v7: Moved ipq9574 related changes to a separate patch
> > Add 'global' interrupt
> >
> > v6: Commit message update only. Add info regarding the moving of
> > ipq9574 from 5 "reg" definition to 5 or 6 reg definition.
> >
> > v5: Re-arrange 5332 and 9574 compatibles to handle fallback usage in dts
> >
> > v4: * v3 reused ipq9574 bindings for ipq5332. Instead add one for ipq5332
> > * DTS uses ipq9574 compatible as fallback. Hence move ipq9574 to be able
> > to use the 'reg' section for both ipq5332 and ipq9574. Else, dtbs_check
> > and dt_binding_check flag errors.
> > ---
> > .../devicetree/bindings/pci/qcom,pcie.yaml | 13 +++++++++++--
> > 1 file changed, 11 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > index 413c6b76c26c..ead97286fd41 100644
> > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > @@ -34,6 +34,10 @@ properties:
> > - items:
> > - const: qcom,pcie-msm8998
> > - const: qcom,pcie-msm8996
> > + - items:
> > + - enum:
> > + - qcom,pcie-ipq5332
> > + - const: qcom,pcie-ipq9574
>
> Repeated many times on reviews to qcom: don't add to the end of the
> lists. In case of multiple items, these are ordered by fallback, so this
> goes next to other ipq entry... wait, that's already qcom,pcie-ipq9574,
> so why are you duplicating?
>
> On what tree are you working?
Looks like ipq5424 changes got merged between the time I cloned
linux-next, tested and posted the patch. Will fix this and post
a new one.
Thanks
Varada
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v7 5/7] dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller
@ 2025-01-23 8:05 ` Varadarajan Narayanan
0 siblings, 0 replies; 37+ messages in thread
From: Varadarajan Narayanan @ 2025-01-23 8:05 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, linux-arm-msm, linux-pci,
devicetree, linux-kernel, linux-phy
On Thu, Jan 23, 2025 at 08:58:29AM +0100, Krzysztof Kozlowski wrote:
> On Wed, Jan 22, 2025 at 12:04:09PM +0530, Varadarajan Narayanan wrote:
> > Document the PCIe controller on IPQ5332 platform. IPQ5332 will
> > use IPQ9574 as the fall back compatible.
> >
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
> > v7: Moved ipq9574 related changes to a separate patch
> > Add 'global' interrupt
> >
> > v6: Commit message update only. Add info regarding the moving of
> > ipq9574 from 5 "reg" definition to 5 or 6 reg definition.
> >
> > v5: Re-arrange 5332 and 9574 compatibles to handle fallback usage in dts
> >
> > v4: * v3 reused ipq9574 bindings for ipq5332. Instead add one for ipq5332
> > * DTS uses ipq9574 compatible as fallback. Hence move ipq9574 to be able
> > to use the 'reg' section for both ipq5332 and ipq9574. Else, dtbs_check
> > and dt_binding_check flag errors.
> > ---
> > .../devicetree/bindings/pci/qcom,pcie.yaml | 13 +++++++++++--
> > 1 file changed, 11 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > index 413c6b76c26c..ead97286fd41 100644
> > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > @@ -34,6 +34,10 @@ properties:
> > - items:
> > - const: qcom,pcie-msm8998
> > - const: qcom,pcie-msm8996
> > + - items:
> > + - enum:
> > + - qcom,pcie-ipq5332
> > + - const: qcom,pcie-ipq9574
>
> Repeated many times on reviews to qcom: don't add to the end of the
> lists. In case of multiple items, these are ordered by fallback, so this
> goes next to other ipq entry... wait, that's already qcom,pcie-ipq9574,
> so why are you duplicating?
>
> On what tree are you working?
Looks like ipq5424 changes got merged between the time I cloned
linux-next, tested and posted the patch. Will fix this and post
a new one.
Thanks
Varada
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v7 5/7] dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller
2025-01-23 8:05 ` Varadarajan Narayanan
@ 2025-01-23 8:27 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 37+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-23 8:27 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, linux-arm-msm, linux-pci,
devicetree, linux-kernel, linux-phy
On Thu, Jan 23, 2025 at 01:35:36PM +0530, Varadarajan Narayanan wrote:
> On Thu, Jan 23, 2025 at 08:58:29AM +0100, Krzysztof Kozlowski wrote:
> > On Wed, Jan 22, 2025 at 12:04:09PM +0530, Varadarajan Narayanan wrote:
> > > Document the PCIe controller on IPQ5332 platform. IPQ5332 will
> > > use IPQ9574 as the fall back compatible.
> > >
> > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > > ---
> > > v7: Moved ipq9574 related changes to a separate patch
> > > Add 'global' interrupt
> > >
> > > v6: Commit message update only. Add info regarding the moving of
> > > ipq9574 from 5 "reg" definition to 5 or 6 reg definition.
> > >
> > > v5: Re-arrange 5332 and 9574 compatibles to handle fallback usage in dts
> > >
> > > v4: * v3 reused ipq9574 bindings for ipq5332. Instead add one for ipq5332
> > > * DTS uses ipq9574 compatible as fallback. Hence move ipq9574 to be able
> > > to use the 'reg' section for both ipq5332 and ipq9574. Else, dtbs_check
> > > and dt_binding_check flag errors.
> > > ---
> > > .../devicetree/bindings/pci/qcom,pcie.yaml | 13 +++++++++++--
> > > 1 file changed, 11 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > > index 413c6b76c26c..ead97286fd41 100644
> > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > > @@ -34,6 +34,10 @@ properties:
> > > - items:
> > > - const: qcom,pcie-msm8998
> > > - const: qcom,pcie-msm8996
> > > + - items:
> > > + - enum:
> > > + - qcom,pcie-ipq5332
> > > + - const: qcom,pcie-ipq9574
> >
> > Repeated many times on reviews to qcom: don't add to the end of the
> > lists. In case of multiple items, these are ordered by fallback, so this
> > goes next to other ipq entry... wait, that's already qcom,pcie-ipq9574,
> > so why are you duplicating?
> >
> > On what tree are you working?
>
> Looks like ipq5424 changes got merged between the time I cloned
> linux-next, tested and posted the patch. Will fix this and post
> a new one.
Yeah, that would explain. Please grow the enum instead.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v7 5/7] dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller
@ 2025-01-23 8:27 ` Krzysztof Kozlowski
0 siblings, 0 replies; 37+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-23 8:27 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, linux-arm-msm, linux-pci,
devicetree, linux-kernel, linux-phy
On Thu, Jan 23, 2025 at 01:35:36PM +0530, Varadarajan Narayanan wrote:
> On Thu, Jan 23, 2025 at 08:58:29AM +0100, Krzysztof Kozlowski wrote:
> > On Wed, Jan 22, 2025 at 12:04:09PM +0530, Varadarajan Narayanan wrote:
> > > Document the PCIe controller on IPQ5332 platform. IPQ5332 will
> > > use IPQ9574 as the fall back compatible.
> > >
> > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > > ---
> > > v7: Moved ipq9574 related changes to a separate patch
> > > Add 'global' interrupt
> > >
> > > v6: Commit message update only. Add info regarding the moving of
> > > ipq9574 from 5 "reg" definition to 5 or 6 reg definition.
> > >
> > > v5: Re-arrange 5332 and 9574 compatibles to handle fallback usage in dts
> > >
> > > v4: * v3 reused ipq9574 bindings for ipq5332. Instead add one for ipq5332
> > > * DTS uses ipq9574 compatible as fallback. Hence move ipq9574 to be able
> > > to use the 'reg' section for both ipq5332 and ipq9574. Else, dtbs_check
> > > and dt_binding_check flag errors.
> > > ---
> > > .../devicetree/bindings/pci/qcom,pcie.yaml | 13 +++++++++++--
> > > 1 file changed, 11 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > > index 413c6b76c26c..ead97286fd41 100644
> > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > > @@ -34,6 +34,10 @@ properties:
> > > - items:
> > > - const: qcom,pcie-msm8998
> > > - const: qcom,pcie-msm8996
> > > + - items:
> > > + - enum:
> > > + - qcom,pcie-ipq5332
> > > + - const: qcom,pcie-ipq9574
> >
> > Repeated many times on reviews to qcom: don't add to the end of the
> > lists. In case of multiple items, these are ordered by fallback, so this
> > goes next to other ipq entry... wait, that's already qcom,pcie-ipq9574,
> > so why are you duplicating?
> >
> > On what tree are you working?
>
> Looks like ipq5424 changes got merged between the time I cloned
> linux-next, tested and posted the patch. Will fix this and post
> a new one.
Yeah, that would explain. Please grow the enum instead.
Best regards,
Krzysztof
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v7 6/7] arm64: dts: qcom: ipq5332: Add PCIe related nodes
2025-01-22 6:34 ` Varadarajan Narayanan
@ 2025-01-22 6:34 ` Varadarajan Narayanan
-1 siblings, 0 replies; 37+ messages in thread
From: Varadarajan Narayanan @ 2025-01-22 6:34 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, quic_varada, linux-arm-msm,
linux-pci, devicetree, linux-kernel, linux-phy
Cc: Praveenkumar I, Konrad Dybcio
From: Praveenkumar I <quic_ipkumar@quicinc.com>
Add phy and controller nodes for pcie0_x1 and pcie1_x2.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v7: * Fix IO 'ranges' entry
* Add root port definitions
* Not adding 'dma-coherent' as the controller doesn't have that support
* Remove 'bus-range' as it has default values
* Group root complex related entries and root port related entries
separately
v6: * Add 'num-lanes' to "pcie0_phy: phy@4b0000"
* Earlier, some related clock rates were set in U-Boot. In
recent versions of U-Boot this has been removed resulting
in the phy link not coming up. To remove boot loader
dependency add assigned-clocks and assigned-clock-rates to
the controller nodes.
* Not sure if 'Reviewed-by' should be dropped.
v5: Add 'num-lanes' to "pcie1_phy: phy@4b1000"
Make ipq5332 as main and ipq9574 as fallback compatible
Move controller nodes per address
Having Konrad's Reviewed-By
v4: Remove 'reset-names' as driver uses bulk APIs
Remove 'clock-output-names' as driver uses bulk APIs
Add missing reset for pcie1_phy
Convert 'reg-names' to a vertical list
Move 'msi-map' before interrupts
v3: Fix compatible string for phy nodes
Use ipq9574 as backup compatible instead of new compatible for ipq5332
Fix mixed case hex addresses
Add "mhi" space
Removed unnecessary comments and stray blank lines
v2: Fix nodes' location per address
---
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 268 +++++++++++++++++++++++++-
1 file changed, 266 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index ca3da95730bd..e5c920c21974 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -186,6 +186,46 @@ rng: rng@e3000 {
clock-names = "core";
};
+ pcie0_phy: phy@4b0000 {
+ compatible = "qcom,ipq5332-uniphy-pcie-phy";
+ reg = <0x004b0000 0x800>;
+
+ clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
+
+ resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>;
+
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
+
+ num-lanes = <1>;
+
+ status = "disabled";
+ };
+
+ pcie1_phy: phy@4b1000 {
+ compatible = "qcom,ipq5332-uniphy-pcie-phy";
+ reg = <0x004b1000 0x1000>;
+
+ clocks = <&gcc GCC_PCIE3X2_PIPE_CLK>,
+ <&gcc GCC_PCIE3X2_PHY_AHB_CLK>;
+
+ resets = <&gcc GCC_PCIE3X2_PHY_BCR>,
+ <&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>,
+ <&gcc GCC_PCIE3X2PHY_PHY_BCR>;
+
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
+
+ num-lanes = <2>;
+
+ status = "disabled";
+ };
+
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5332-tlmm";
reg = <0x01000000 0x300000>;
@@ -212,8 +252,8 @@ gcc: clock-controller@1800000 {
#interconnect-cells = <1>;
clocks = <&xo_board>,
<&sleep_clk>,
- <0>,
- <0>,
+ <&pcie1_phy>,
+ <&pcie0_phy>,
<0>;
};
@@ -479,6 +519,230 @@ frame@b128000 {
status = "disabled";
};
};
+
+ pcie1: pcie@18000000 {
+ compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
+ reg = <0x00088000 0x3000>,
+ <0x18000000 0xf1d>,
+ <0x18000f20 0xa8>,
+ <0x18001000 0x1000>,
+ <0x18100000 0x1000>,
+ <0x0008b000 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ num-lanes = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x00100000>,
+ <0x02000000 0x0 0x18300000 0x18300000 0x0 0x07d00000>;
+
+ msi-map = <0x0 &v2m0 0x0 0xffd>;
+
+ interrupts = <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 412 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 413 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 414 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 415 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE3X2_AXI_M_CLK>,
+ <&gcc GCC_PCIE3X2_AXI_S_CLK>,
+ <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE3X2_RCHG_CLK>,
+ <&gcc GCC_PCIE3X2_AHB_CLK>,
+ <&gcc GCC_PCIE3X2_AUX_CLK>;
+ clock-names = "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng",
+ "ahb",
+ "aux";
+
+ assigned-clocks = <&gcc GCC_PCIE3X2_AUX_CLK>,
+ <&gcc GCC_PCIE3X2_AXI_M_CLK>,
+ <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE3X2_AXI_S_CLK>,
+ <&gcc GCC_PCIE3X2_RCHG_CLK>;
+
+ assigned-clock-rates = <2000000>,
+ <266666666>,
+ <240000000>,
+ <240000000>,
+ <100000000>;
+
+ resets = <&gcc GCC_PCIE3X2_PIPE_ARES>,
+ <&gcc GCC_PCIE3X2_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE3X2_AXI_S_STICKY_ARES>,
+ <&gcc GCC_PCIE3X2_AXI_S_CLK_ARES>,
+ <&gcc GCC_PCIE3X2_AXI_M_STICKY_ARES>,
+ <&gcc GCC_PCIE3X2_AXI_M_CLK_ARES>,
+ <&gcc GCC_PCIE3X2_AUX_CLK_ARES>,
+ <&gcc GCC_PCIE3X2_AHB_CLK_ARES>;
+ reset-names = "pipe",
+ "sticky",
+ "axi_s_sticky",
+ "axi_s",
+ "axi_m_sticky",
+ "axi_m",
+ "aux",
+ "ahb";
+
+ phys = <&pcie1_phy>;
+ phy-names = "pciephy";
+
+ interconnects = <&gcc MASTER_SNOC_PCIE3_2_M &gcc SLAVE_SNOC_PCIE3_2_M>,
+ <&gcc MASTER_ANOC_PCIE3_2_S &gcc SLAVE_ANOC_PCIE3_2_S>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+
+ pcie0: pcie@20000000 {
+ compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
+ reg = <0x00080000 0x3000>,
+ <0x20000000 0xf1d>,
+ <0x20000f20 0xa8>,
+ <0x20001000 0x1000>,
+ <0x20100000 0x1000>,
+ <0x00083000 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x00100000>,
+ <0x02000000 0x0 0x20300000 0x20300000 0x0 0x0fd00000>;
+
+ msi-map = <0x0 &v2m0 0x0 0xffd>;
+
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 36 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 37 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 38 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE3X1_0_AXI_M_CLK>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_CLK>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE3X1_0_RCHG_CLK>,
+ <&gcc GCC_PCIE3X1_0_AHB_CLK>,
+ <&gcc GCC_PCIE3X1_0_AUX_CLK>;
+ clock-names = "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng",
+ "ahb",
+ "aux";
+
+ assigned-clocks = <&gcc GCC_PCIE3X1_0_AUX_CLK>,
+ <&gcc GCC_PCIE3X1_0_AXI_M_CLK>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_CLK>,
+ <&gcc GCC_PCIE3X1_0_RCHG_CLK>;
+
+ assigned-clock-rates = <2000000>,
+ <240000000>,
+ <240000000>,
+ <240000000>,
+ <100000000>;
+
+ resets = <&gcc GCC_PCIE3X1_0_PIPE_ARES>,
+ <&gcc GCC_PCIE3X1_0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_STICKY_ARES>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_AXI_M_STICKY_ARES>,
+ <&gcc GCC_PCIE3X1_0_AXI_M_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_AUX_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_AHB_CLK_ARES>;
+ reset-names = "pipe",
+ "sticky",
+ "axi_s_sticky",
+ "axi_s",
+ "axi_m_sticky",
+ "axi_m",
+ "aux",
+ "ahb";
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ interconnects = <&gcc MASTER_SNOC_PCIE3_1_M &gcc SLAVE_SNOC_PCIE3_1_M>,
+ <&gcc MASTER_ANOC_PCIE3_1_S &gcc SLAVE_ANOC_PCIE3_1_S>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
};
timer {
--
2.34.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH v7 6/7] arm64: dts: qcom: ipq5332: Add PCIe related nodes
@ 2025-01-22 6:34 ` Varadarajan Narayanan
0 siblings, 0 replies; 37+ messages in thread
From: Varadarajan Narayanan @ 2025-01-22 6:34 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, quic_varada, linux-arm-msm,
linux-pci, devicetree, linux-kernel, linux-phy
Cc: Praveenkumar I, Konrad Dybcio
From: Praveenkumar I <quic_ipkumar@quicinc.com>
Add phy and controller nodes for pcie0_x1 and pcie1_x2.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v7: * Fix IO 'ranges' entry
* Add root port definitions
* Not adding 'dma-coherent' as the controller doesn't have that support
* Remove 'bus-range' as it has default values
* Group root complex related entries and root port related entries
separately
v6: * Add 'num-lanes' to "pcie0_phy: phy@4b0000"
* Earlier, some related clock rates were set in U-Boot. In
recent versions of U-Boot this has been removed resulting
in the phy link not coming up. To remove boot loader
dependency add assigned-clocks and assigned-clock-rates to
the controller nodes.
* Not sure if 'Reviewed-by' should be dropped.
v5: Add 'num-lanes' to "pcie1_phy: phy@4b1000"
Make ipq5332 as main and ipq9574 as fallback compatible
Move controller nodes per address
Having Konrad's Reviewed-By
v4: Remove 'reset-names' as driver uses bulk APIs
Remove 'clock-output-names' as driver uses bulk APIs
Add missing reset for pcie1_phy
Convert 'reg-names' to a vertical list
Move 'msi-map' before interrupts
v3: Fix compatible string for phy nodes
Use ipq9574 as backup compatible instead of new compatible for ipq5332
Fix mixed case hex addresses
Add "mhi" space
Removed unnecessary comments and stray blank lines
v2: Fix nodes' location per address
---
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 268 +++++++++++++++++++++++++-
1 file changed, 266 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index ca3da95730bd..e5c920c21974 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -186,6 +186,46 @@ rng: rng@e3000 {
clock-names = "core";
};
+ pcie0_phy: phy@4b0000 {
+ compatible = "qcom,ipq5332-uniphy-pcie-phy";
+ reg = <0x004b0000 0x800>;
+
+ clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
+
+ resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>;
+
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
+
+ num-lanes = <1>;
+
+ status = "disabled";
+ };
+
+ pcie1_phy: phy@4b1000 {
+ compatible = "qcom,ipq5332-uniphy-pcie-phy";
+ reg = <0x004b1000 0x1000>;
+
+ clocks = <&gcc GCC_PCIE3X2_PIPE_CLK>,
+ <&gcc GCC_PCIE3X2_PHY_AHB_CLK>;
+
+ resets = <&gcc GCC_PCIE3X2_PHY_BCR>,
+ <&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>,
+ <&gcc GCC_PCIE3X2PHY_PHY_BCR>;
+
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
+
+ num-lanes = <2>;
+
+ status = "disabled";
+ };
+
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5332-tlmm";
reg = <0x01000000 0x300000>;
@@ -212,8 +252,8 @@ gcc: clock-controller@1800000 {
#interconnect-cells = <1>;
clocks = <&xo_board>,
<&sleep_clk>,
- <0>,
- <0>,
+ <&pcie1_phy>,
+ <&pcie0_phy>,
<0>;
};
@@ -479,6 +519,230 @@ frame@b128000 {
status = "disabled";
};
};
+
+ pcie1: pcie@18000000 {
+ compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
+ reg = <0x00088000 0x3000>,
+ <0x18000000 0xf1d>,
+ <0x18000f20 0xa8>,
+ <0x18001000 0x1000>,
+ <0x18100000 0x1000>,
+ <0x0008b000 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ num-lanes = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x00100000>,
+ <0x02000000 0x0 0x18300000 0x18300000 0x0 0x07d00000>;
+
+ msi-map = <0x0 &v2m0 0x0 0xffd>;
+
+ interrupts = <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 412 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 413 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 414 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 415 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE3X2_AXI_M_CLK>,
+ <&gcc GCC_PCIE3X2_AXI_S_CLK>,
+ <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE3X2_RCHG_CLK>,
+ <&gcc GCC_PCIE3X2_AHB_CLK>,
+ <&gcc GCC_PCIE3X2_AUX_CLK>;
+ clock-names = "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng",
+ "ahb",
+ "aux";
+
+ assigned-clocks = <&gcc GCC_PCIE3X2_AUX_CLK>,
+ <&gcc GCC_PCIE3X2_AXI_M_CLK>,
+ <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE3X2_AXI_S_CLK>,
+ <&gcc GCC_PCIE3X2_RCHG_CLK>;
+
+ assigned-clock-rates = <2000000>,
+ <266666666>,
+ <240000000>,
+ <240000000>,
+ <100000000>;
+
+ resets = <&gcc GCC_PCIE3X2_PIPE_ARES>,
+ <&gcc GCC_PCIE3X2_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE3X2_AXI_S_STICKY_ARES>,
+ <&gcc GCC_PCIE3X2_AXI_S_CLK_ARES>,
+ <&gcc GCC_PCIE3X2_AXI_M_STICKY_ARES>,
+ <&gcc GCC_PCIE3X2_AXI_M_CLK_ARES>,
+ <&gcc GCC_PCIE3X2_AUX_CLK_ARES>,
+ <&gcc GCC_PCIE3X2_AHB_CLK_ARES>;
+ reset-names = "pipe",
+ "sticky",
+ "axi_s_sticky",
+ "axi_s",
+ "axi_m_sticky",
+ "axi_m",
+ "aux",
+ "ahb";
+
+ phys = <&pcie1_phy>;
+ phy-names = "pciephy";
+
+ interconnects = <&gcc MASTER_SNOC_PCIE3_2_M &gcc SLAVE_SNOC_PCIE3_2_M>,
+ <&gcc MASTER_ANOC_PCIE3_2_S &gcc SLAVE_ANOC_PCIE3_2_S>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+
+ pcie0: pcie@20000000 {
+ compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
+ reg = <0x00080000 0x3000>,
+ <0x20000000 0xf1d>,
+ <0x20000f20 0xa8>,
+ <0x20001000 0x1000>,
+ <0x20100000 0x1000>,
+ <0x00083000 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x00100000>,
+ <0x02000000 0x0 0x20300000 0x20300000 0x0 0x0fd00000>;
+
+ msi-map = <0x0 &v2m0 0x0 0xffd>;
+
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 36 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 37 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 38 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE3X1_0_AXI_M_CLK>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_CLK>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE3X1_0_RCHG_CLK>,
+ <&gcc GCC_PCIE3X1_0_AHB_CLK>,
+ <&gcc GCC_PCIE3X1_0_AUX_CLK>;
+ clock-names = "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng",
+ "ahb",
+ "aux";
+
+ assigned-clocks = <&gcc GCC_PCIE3X1_0_AUX_CLK>,
+ <&gcc GCC_PCIE3X1_0_AXI_M_CLK>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_CLK>,
+ <&gcc GCC_PCIE3X1_0_RCHG_CLK>;
+
+ assigned-clock-rates = <2000000>,
+ <240000000>,
+ <240000000>,
+ <240000000>,
+ <100000000>;
+
+ resets = <&gcc GCC_PCIE3X1_0_PIPE_ARES>,
+ <&gcc GCC_PCIE3X1_0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_STICKY_ARES>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_AXI_M_STICKY_ARES>,
+ <&gcc GCC_PCIE3X1_0_AXI_M_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_AUX_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_AHB_CLK_ARES>;
+ reset-names = "pipe",
+ "sticky",
+ "axi_s_sticky",
+ "axi_s",
+ "axi_m_sticky",
+ "axi_m",
+ "aux",
+ "ahb";
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ interconnects = <&gcc MASTER_SNOC_PCIE3_1_M &gcc SLAVE_SNOC_PCIE3_1_M>,
+ <&gcc MASTER_ANOC_PCIE3_1_S &gcc SLAVE_ANOC_PCIE3_1_S>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
};
timer {
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v7 6/7] arm64: dts: qcom: ipq5332: Add PCIe related nodes
2025-01-22 6:34 ` Varadarajan Narayanan
@ 2025-02-03 16:26 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 37+ messages in thread
From: Manivannan Sadhasivam @ 2025-02-03 16:26 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: bhelgaas, lpieralisi, kw, robh, krzk+dt, conor+dt, vkoul, kishon,
andersson, konradybcio, p.zabel, dmitry.baryshkov, quic_nsekar,
linux-arm-msm, linux-pci, devicetree, linux-kernel, linux-phy,
Praveenkumar I, Konrad Dybcio
On Wed, Jan 22, 2025 at 12:04:10PM +0530, Varadarajan Narayanan wrote:
> From: Praveenkumar I <quic_ipkumar@quicinc.com>
>
> Add phy and controller nodes for pcie0_x1 and pcie1_x2.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
One minor comment below.
[...]
> + assigned-clocks = <&gcc GCC_PCIE3X2_AUX_CLK>,
> + <&gcc GCC_PCIE3X2_AXI_M_CLK>,
> + <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>,
> + <&gcc GCC_PCIE3X2_AXI_S_CLK>,
> + <&gcc GCC_PCIE3X2_RCHG_CLK>;
> +
> + assigned-clock-rates = <2000000>,
> + <266666666>,
> + <240000000>,
> + <240000000>,
> + <100000000>;
> +
Does the drivers really need to set clock rate for these many clocks?
No, as per the reply to my similar question to IPQ5424:
https://lore.kernel.org/linux-arm-msm/9206e44c-da4f-4bdb-850f-fac511f4ddc7@quicinc.com/
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v7 6/7] arm64: dts: qcom: ipq5332: Add PCIe related nodes
@ 2025-02-03 16:26 ` Manivannan Sadhasivam
0 siblings, 0 replies; 37+ messages in thread
From: Manivannan Sadhasivam @ 2025-02-03 16:26 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: bhelgaas, lpieralisi, kw, robh, krzk+dt, conor+dt, vkoul, kishon,
andersson, konradybcio, p.zabel, dmitry.baryshkov, quic_nsekar,
linux-arm-msm, linux-pci, devicetree, linux-kernel, linux-phy,
Praveenkumar I, Konrad Dybcio
On Wed, Jan 22, 2025 at 12:04:10PM +0530, Varadarajan Narayanan wrote:
> From: Praveenkumar I <quic_ipkumar@quicinc.com>
>
> Add phy and controller nodes for pcie0_x1 and pcie1_x2.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
One minor comment below.
[...]
> + assigned-clocks = <&gcc GCC_PCIE3X2_AUX_CLK>,
> + <&gcc GCC_PCIE3X2_AXI_M_CLK>,
> + <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>,
> + <&gcc GCC_PCIE3X2_AXI_S_CLK>,
> + <&gcc GCC_PCIE3X2_RCHG_CLK>;
> +
> + assigned-clock-rates = <2000000>,
> + <266666666>,
> + <240000000>,
> + <240000000>,
> + <100000000>;
> +
Does the drivers really need to set clock rate for these many clocks?
No, as per the reply to my similar question to IPQ5424:
https://lore.kernel.org/linux-arm-msm/9206e44c-da4f-4bdb-850f-fac511f4ddc7@quicinc.com/
- Mani
--
மணிவண்ணன் சதாசிவம்
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v7 7/7] arm64: dts: qcom: ipq5332-rdp441: Enable PCIe phys and controllers
2025-01-22 6:34 ` Varadarajan Narayanan
@ 2025-01-22 6:34 ` Varadarajan Narayanan
-1 siblings, 0 replies; 37+ messages in thread
From: Varadarajan Narayanan @ 2025-01-22 6:34 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, quic_varada, linux-arm-msm,
linux-pci, devicetree, linux-kernel, linux-phy
Cc: Praveenkumar I, Konrad Dybcio
From: Praveenkumar I <quic_ipkumar@quicinc.com>
Enable the PCIe controller and PHY nodes for RDP 441.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v5: Add 'Reviewed-by: Konrad Dybcio'
v4: Fix nodes sort order
Use property-n followed by property-names
v3: Reorder nodes alphabetically
Fix commit subject
---
arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 76 +++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
index 846413817e9a..79ec77cfe552 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
@@ -32,6 +32,34 @@ &sdhc {
status = "okay";
};
+&pcie0 {
+ pinctrl-0 = <&pcie0_default>;
+ pinctrl-names = "default";
+
+ perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ status = "okay";
+};
+
+&pcie1 {
+ pinctrl-0 = <&pcie1_default>;
+ pinctrl-names = "default";
+
+ perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ status = "okay";
+};
+
&tlmm {
i2c_1_pins: i2c-1-state {
pins = "gpio29", "gpio30";
@@ -40,6 +68,54 @@ i2c_1_pins: i2c-1-state {
bias-pull-up;
};
+ pcie0_default: pcie0-default-state {
+ clkreq-n-pins {
+ pins = "gpio37";
+ function = "pcie0_clk";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio38";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ output-low;
+ };
+
+ wake-n-pins {
+ pins = "gpio39";
+ function = "pcie0_wake";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ pcie1_default: pcie1-default-state {
+ clkreq-n-pins {
+ pins = "gpio46";
+ function = "pcie1_clk";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio47";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ output-low;
+ };
+
+ wake-n-pins {
+ pins = "gpio48";
+ function = "pcie1_wake";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio13";
--
2.34.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH v7 7/7] arm64: dts: qcom: ipq5332-rdp441: Enable PCIe phys and controllers
@ 2025-01-22 6:34 ` Varadarajan Narayanan
0 siblings, 0 replies; 37+ messages in thread
From: Varadarajan Narayanan @ 2025-01-22 6:34 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, manivannan.sadhasivam, robh, krzk+dt,
conor+dt, vkoul, kishon, andersson, konradybcio, p.zabel,
dmitry.baryshkov, quic_nsekar, quic_varada, linux-arm-msm,
linux-pci, devicetree, linux-kernel, linux-phy
Cc: Praveenkumar I, Konrad Dybcio
From: Praveenkumar I <quic_ipkumar@quicinc.com>
Enable the PCIe controller and PHY nodes for RDP 441.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v5: Add 'Reviewed-by: Konrad Dybcio'
v4: Fix nodes sort order
Use property-n followed by property-names
v3: Reorder nodes alphabetically
Fix commit subject
---
arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 76 +++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
index 846413817e9a..79ec77cfe552 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
@@ -32,6 +32,34 @@ &sdhc {
status = "okay";
};
+&pcie0 {
+ pinctrl-0 = <&pcie0_default>;
+ pinctrl-names = "default";
+
+ perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ status = "okay";
+};
+
+&pcie1 {
+ pinctrl-0 = <&pcie1_default>;
+ pinctrl-names = "default";
+
+ perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ status = "okay";
+};
+
&tlmm {
i2c_1_pins: i2c-1-state {
pins = "gpio29", "gpio30";
@@ -40,6 +68,54 @@ i2c_1_pins: i2c-1-state {
bias-pull-up;
};
+ pcie0_default: pcie0-default-state {
+ clkreq-n-pins {
+ pins = "gpio37";
+ function = "pcie0_clk";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio38";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ output-low;
+ };
+
+ wake-n-pins {
+ pins = "gpio39";
+ function = "pcie0_wake";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ pcie1_default: pcie1-default-state {
+ clkreq-n-pins {
+ pins = "gpio46";
+ function = "pcie1_clk";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio47";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ output-low;
+ };
+
+ wake-n-pins {
+ pins = "gpio48";
+ function = "pcie1_wake";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio13";
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v7 7/7] arm64: dts: qcom: ipq5332-rdp441: Enable PCIe phys and controllers
2025-01-22 6:34 ` Varadarajan Narayanan
@ 2025-02-03 16:27 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 37+ messages in thread
From: Manivannan Sadhasivam @ 2025-02-03 16:27 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: bhelgaas, lpieralisi, kw, robh, krzk+dt, conor+dt, vkoul, kishon,
andersson, konradybcio, p.zabel, dmitry.baryshkov, quic_nsekar,
linux-arm-msm, linux-pci, devicetree, linux-kernel, linux-phy,
Praveenkumar I, Konrad Dybcio
On Wed, Jan 22, 2025 at 12:04:11PM +0530, Varadarajan Narayanan wrote:
> From: Praveenkumar I <quic_ipkumar@quicinc.com>
>
> Enable the PCIe controller and PHY nodes for RDP 441.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Mani
> ---
> v5: Add 'Reviewed-by: Konrad Dybcio'
>
> v4: Fix nodes sort order
> Use property-n followed by property-names
>
> v3: Reorder nodes alphabetically
> Fix commit subject
> ---
> arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 76 +++++++++++++++++++++
> 1 file changed, 76 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
> index 846413817e9a..79ec77cfe552 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
> @@ -32,6 +32,34 @@ &sdhc {
> status = "okay";
> };
>
> +&pcie0 {
> + pinctrl-0 = <&pcie0_default>;
> + pinctrl-names = "default";
> +
> + perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
> +
> + status = "okay";
> +};
> +
> +&pcie0_phy {
> + status = "okay";
> +};
> +
> +&pcie1 {
> + pinctrl-0 = <&pcie1_default>;
> + pinctrl-names = "default";
> +
> + perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
> +
> + status = "okay";
> +};
> +
> +&pcie1_phy {
> + status = "okay";
> +};
> +
> &tlmm {
> i2c_1_pins: i2c-1-state {
> pins = "gpio29", "gpio30";
> @@ -40,6 +68,54 @@ i2c_1_pins: i2c-1-state {
> bias-pull-up;
> };
>
> + pcie0_default: pcie0-default-state {
> + clkreq-n-pins {
> + pins = "gpio37";
> + function = "pcie0_clk";
> + drive-strength = <8>;
> + bias-pull-up;
> + };
> +
> + perst-n-pins {
> + pins = "gpio38";
> + function = "gpio";
> + drive-strength = <8>;
> + bias-pull-up;
> + output-low;
> + };
> +
> + wake-n-pins {
> + pins = "gpio39";
> + function = "pcie0_wake";
> + drive-strength = <8>;
> + bias-pull-up;
> + };
> + };
> +
> + pcie1_default: pcie1-default-state {
> + clkreq-n-pins {
> + pins = "gpio46";
> + function = "pcie1_clk";
> + drive-strength = <8>;
> + bias-pull-up;
> + };
> +
> + perst-n-pins {
> + pins = "gpio47";
> + function = "gpio";
> + drive-strength = <8>;
> + bias-pull-up;
> + output-low;
> + };
> +
> + wake-n-pins {
> + pins = "gpio48";
> + function = "pcie1_wake";
> + drive-strength = <8>;
> + bias-pull-up;
> + };
> + };
> +
> sdc_default_state: sdc-default-state {
> clk-pins {
> pins = "gpio13";
> --
> 2.34.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH v7 7/7] arm64: dts: qcom: ipq5332-rdp441: Enable PCIe phys and controllers
@ 2025-02-03 16:27 ` Manivannan Sadhasivam
0 siblings, 0 replies; 37+ messages in thread
From: Manivannan Sadhasivam @ 2025-02-03 16:27 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: bhelgaas, lpieralisi, kw, robh, krzk+dt, conor+dt, vkoul, kishon,
andersson, konradybcio, p.zabel, dmitry.baryshkov, quic_nsekar,
linux-arm-msm, linux-pci, devicetree, linux-kernel, linux-phy,
Praveenkumar I, Konrad Dybcio
On Wed, Jan 22, 2025 at 12:04:11PM +0530, Varadarajan Narayanan wrote:
> From: Praveenkumar I <quic_ipkumar@quicinc.com>
>
> Enable the PCIe controller and PHY nodes for RDP 441.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Mani
> ---
> v5: Add 'Reviewed-by: Konrad Dybcio'
>
> v4: Fix nodes sort order
> Use property-n followed by property-names
>
> v3: Reorder nodes alphabetically
> Fix commit subject
> ---
> arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 76 +++++++++++++++++++++
> 1 file changed, 76 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
> index 846413817e9a..79ec77cfe552 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
> @@ -32,6 +32,34 @@ &sdhc {
> status = "okay";
> };
>
> +&pcie0 {
> + pinctrl-0 = <&pcie0_default>;
> + pinctrl-names = "default";
> +
> + perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
> +
> + status = "okay";
> +};
> +
> +&pcie0_phy {
> + status = "okay";
> +};
> +
> +&pcie1 {
> + pinctrl-0 = <&pcie1_default>;
> + pinctrl-names = "default";
> +
> + perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
> +
> + status = "okay";
> +};
> +
> +&pcie1_phy {
> + status = "okay";
> +};
> +
> &tlmm {
> i2c_1_pins: i2c-1-state {
> pins = "gpio29", "gpio30";
> @@ -40,6 +68,54 @@ i2c_1_pins: i2c-1-state {
> bias-pull-up;
> };
>
> + pcie0_default: pcie0-default-state {
> + clkreq-n-pins {
> + pins = "gpio37";
> + function = "pcie0_clk";
> + drive-strength = <8>;
> + bias-pull-up;
> + };
> +
> + perst-n-pins {
> + pins = "gpio38";
> + function = "gpio";
> + drive-strength = <8>;
> + bias-pull-up;
> + output-low;
> + };
> +
> + wake-n-pins {
> + pins = "gpio39";
> + function = "pcie0_wake";
> + drive-strength = <8>;
> + bias-pull-up;
> + };
> + };
> +
> + pcie1_default: pcie1-default-state {
> + clkreq-n-pins {
> + pins = "gpio46";
> + function = "pcie1_clk";
> + drive-strength = <8>;
> + bias-pull-up;
> + };
> +
> + perst-n-pins {
> + pins = "gpio47";
> + function = "gpio";
> + drive-strength = <8>;
> + bias-pull-up;
> + output-low;
> + };
> +
> + wake-n-pins {
> + pins = "gpio48";
> + function = "pcie1_wake";
> + drive-strength = <8>;
> + bias-pull-up;
> + };
> + };
> +
> sdc_default_state: sdc-default-state {
> clk-pins {
> pins = "gpio13";
> --
> 2.34.1
>
--
மணிவண்ணன் சதாசிவம்
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v7 4/7] arm64: dts: qcom: ipq9574: Reorder reg and reg-names
@ 2025-01-22 22:39 kernel test robot
0 siblings, 0 replies; 37+ messages in thread
From: kernel test robot @ 2025-01-22 22:39 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp
::::::
:::::: Manual check reason: "dtcheck: binding changes may go via different trees"
::::::
BCC: lkp@intel.com
CC: llvm@lists.linux.dev
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20250122063411.3503097-5-quic_varada@quicinc.com>
References: <20250122063411.3503097-5-quic_varada@quicinc.com>
TO: Varadarajan Narayanan <quic_varada@quicinc.com>
TO: bhelgaas@google.com
TO: lpieralisi@kernel.org
TO: kw@linux.com
TO: manivannan.sadhasivam@linaro.org
TO: robh@kernel.org
TO: krzk+dt@kernel.org
TO: conor+dt@kernel.org
TO: vkoul@kernel.org
TO: kishon@kernel.org
TO: andersson@kernel.org
TO: konradybcio@kernel.org
TO: p.zabel@pengutronix.de
TO: dmitry.baryshkov@linaro.org
TO: quic_nsekar@quicinc.com
TO: quic_varada@quicinc.com
TO: linux-arm-msm@vger.kernel.org
TO: linux-pci@vger.kernel.org
TO: devicetree@vger.kernel.org
TO: linux-kernel@vger.kernel.org
TO: linux-phy@lists.infradead.org
Hi Varadarajan,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 37136bf5c3a6f6b686d74f41837a6406bec6b7bc]
url: https://github.com/intel-lab-lkp/linux/commits/Varadarajan-Narayanan/dt-bindings-phy-qcom-uniphy-pcie-Document-PCIe-uniphy/20250122-143841
base: 37136bf5c3a6f6b686d74f41837a6406bec6b7bc
patch link: https://lore.kernel.org/r/20250122063411.3503097-5-quic_varada%40quicinc.com
patch subject: [PATCH v7 4/7] arm64: dts: qcom: ipq9574: Reorder reg and reg-names
:::::: branch date: 16 hours ago
:::::: commit date: 16 hours ago
config: arm64-randconfig-003-20250123 (https://download.01.org/0day-ci/archive/20250123/202501230653.Zc6gMuls-lkp@intel.com/config)
compiler: clang version 20.0.0git (https://github.com/llvm/llvm-project c23f2417dc5f6dc371afb07af5627ec2a9d373a0)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250123/202501230653.Zc6gMuls-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202501230653.Zc6gMuls-lkp@intel.com/
dtcheck warnings: (new ones prefixed by >>)
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi:877.24-959.5: Warning (simple_bus_reg): /soc@0/pcie@10000000: simple-bus unit address format error, expected "f8000"
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi:961.24-1043.5: Warning (simple_bus_reg): /soc@0/pcie@18000000: simple-bus unit address format error, expected "f0000"
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi:1045.24-1127.5: Warning (simple_bus_reg): /soc@0/pcie@20000000: simple-bus unit address format error, expected "88000"
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi:1129.23-1210.5: Warning (simple_bus_reg): /soc@0/pci@28000000: simple-bus unit address format error, expected "80000"
--
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi:877.24-959.5: Warning (simple_bus_reg): /soc@0/pcie@10000000: simple-bus unit address format error, expected "f8000"
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi:961.24-1043.5: Warning (simple_bus_reg): /soc@0/pcie@18000000: simple-bus unit address format error, expected "f0000"
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi:1045.24-1127.5: Warning (simple_bus_reg): /soc@0/pcie@20000000: simple-bus unit address format error, expected "88000"
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi:1129.23-1210.5: Warning (simple_bus_reg): /soc@0/pci@28000000: simple-bus unit address format error, expected "80000"
vim +/f8000 +877 arch/arm64/boot/dts/qcom/ipq9574.dtsi
97cb36ff52a106 Devi Priya 2023-03-16 16
97cb36ff52a106 Devi Priya 2023-03-16 17 / {
97cb36ff52a106 Devi Priya 2023-03-16 18 interrupt-parent = <&intc>;
97cb36ff52a106 Devi Priya 2023-03-16 19 #address-cells = <2>;
97cb36ff52a106 Devi Priya 2023-03-16 20 #size-cells = <2>;
97cb36ff52a106 Devi Priya 2023-03-16 21
97cb36ff52a106 Devi Priya 2023-03-16 22 clocks {
758aa2d7e3c0ac Luo Jie 2025-01-03 23 ref_48mhz_clk: ref-48mhz-clk {
758aa2d7e3c0ac Luo Jie 2025-01-03 24 compatible = "fixed-factor-clock";
758aa2d7e3c0ac Luo Jie 2025-01-03 25 clocks = <&xo_clk>;
758aa2d7e3c0ac Luo Jie 2025-01-03 26 #clock-cells = <0>;
758aa2d7e3c0ac Luo Jie 2025-01-03 27 };
758aa2d7e3c0ac Luo Jie 2025-01-03 28
97cb36ff52a106 Devi Priya 2023-03-16 29 sleep_clk: sleep-clk {
97cb36ff52a106 Devi Priya 2023-03-16 30 compatible = "fixed-clock";
97cb36ff52a106 Devi Priya 2023-03-16 31 #clock-cells = <0>;
97cb36ff52a106 Devi Priya 2023-03-16 32 };
97cb36ff52a106 Devi Priya 2023-03-16 33
97cb36ff52a106 Devi Priya 2023-03-16 34 xo_board_clk: xo-board-clk {
050b312654523a Luo Jie 2025-01-03 35 compatible = "fixed-factor-clock";
050b312654523a Luo Jie 2025-01-03 36 clocks = <&ref_48mhz_clk>;
97cb36ff52a106 Devi Priya 2023-03-16 37 #clock-cells = <0>;
97cb36ff52a106 Devi Priya 2023-03-16 38 };
758aa2d7e3c0ac Luo Jie 2025-01-03 39
758aa2d7e3c0ac Luo Jie 2025-01-03 40 xo_clk: xo-clk {
758aa2d7e3c0ac Luo Jie 2025-01-03 41 compatible = "fixed-clock";
758aa2d7e3c0ac Luo Jie 2025-01-03 42 #clock-cells = <0>;
758aa2d7e3c0ac Luo Jie 2025-01-03 43 };
97cb36ff52a106 Devi Priya 2023-03-16 44 };
97cb36ff52a106 Devi Priya 2023-03-16 45
97cb36ff52a106 Devi Priya 2023-03-16 46 cpus {
97cb36ff52a106 Devi Priya 2023-03-16 47 #address-cells = <1>;
97cb36ff52a106 Devi Priya 2023-03-16 48 #size-cells = <0>;
97cb36ff52a106 Devi Priya 2023-03-16 49
6f8c1ed2580918 Krzysztof Kozlowski 2024-10-22 50 cpu0: cpu@0 {
97cb36ff52a106 Devi Priya 2023-03-16 51 device_type = "cpu";
97cb36ff52a106 Devi Priya 2023-03-16 52 compatible = "arm,cortex-a73";
97cb36ff52a106 Devi Priya 2023-03-16 53 reg = <0x0>;
97cb36ff52a106 Devi Priya 2023-03-16 54 enable-method = "psci";
6f8c1ed2580918 Krzysztof Kozlowski 2024-10-22 55 next-level-cache = <&l2_0>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 56 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 57 clock-names = "cpu";
8f0ae6bc0098f6 Devi Priya 2023-05-17 58 operating-points-v2 = <&cpu_opp_table>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 59 cpu-supply = <&ipq9574_s1>;
752f585805c559 Praveenkumar I 2023-07-13 60 #cooling-cells = <2>;
97cb36ff52a106 Devi Priya 2023-03-16 61 };
97cb36ff52a106 Devi Priya 2023-03-16 62
6f8c1ed2580918 Krzysztof Kozlowski 2024-10-22 63 cpu1: cpu@1 {
97cb36ff52a106 Devi Priya 2023-03-16 64 device_type = "cpu";
97cb36ff52a106 Devi Priya 2023-03-16 65 compatible = "arm,cortex-a73";
97cb36ff52a106 Devi Priya 2023-03-16 66 reg = <0x1>;
97cb36ff52a106 Devi Priya 2023-03-16 67 enable-method = "psci";
6f8c1ed2580918 Krzysztof Kozlowski 2024-10-22 68 next-level-cache = <&l2_0>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 69 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 70 clock-names = "cpu";
8f0ae6bc0098f6 Devi Priya 2023-05-17 71 operating-points-v2 = <&cpu_opp_table>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 72 cpu-supply = <&ipq9574_s1>;
752f585805c559 Praveenkumar I 2023-07-13 73 #cooling-cells = <2>;
97cb36ff52a106 Devi Priya 2023-03-16 74 };
97cb36ff52a106 Devi Priya 2023-03-16 75
6f8c1ed2580918 Krzysztof Kozlowski 2024-10-22 76 cpu2: cpu@2 {
97cb36ff52a106 Devi Priya 2023-03-16 77 device_type = "cpu";
97cb36ff52a106 Devi Priya 2023-03-16 78 compatible = "arm,cortex-a73";
97cb36ff52a106 Devi Priya 2023-03-16 79 reg = <0x2>;
97cb36ff52a106 Devi Priya 2023-03-16 80 enable-method = "psci";
6f8c1ed2580918 Krzysztof Kozlowski 2024-10-22 81 next-level-cache = <&l2_0>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 82 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 83 clock-names = "cpu";
8f0ae6bc0098f6 Devi Priya 2023-05-17 84 operating-points-v2 = <&cpu_opp_table>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 85 cpu-supply = <&ipq9574_s1>;
752f585805c559 Praveenkumar I 2023-07-13 86 #cooling-cells = <2>;
97cb36ff52a106 Devi Priya 2023-03-16 87 };
97cb36ff52a106 Devi Priya 2023-03-16 88
6f8c1ed2580918 Krzysztof Kozlowski 2024-10-22 89 cpu3: cpu@3 {
97cb36ff52a106 Devi Priya 2023-03-16 90 device_type = "cpu";
97cb36ff52a106 Devi Priya 2023-03-16 91 compatible = "arm,cortex-a73";
97cb36ff52a106 Devi Priya 2023-03-16 92 reg = <0x3>;
97cb36ff52a106 Devi Priya 2023-03-16 93 enable-method = "psci";
6f8c1ed2580918 Krzysztof Kozlowski 2024-10-22 94 next-level-cache = <&l2_0>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 95 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 96 clock-names = "cpu";
8f0ae6bc0098f6 Devi Priya 2023-05-17 97 operating-points-v2 = <&cpu_opp_table>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 98 cpu-supply = <&ipq9574_s1>;
752f585805c559 Praveenkumar I 2023-07-13 99 #cooling-cells = <2>;
97cb36ff52a106 Devi Priya 2023-03-16 100 };
97cb36ff52a106 Devi Priya 2023-03-16 101
6f8c1ed2580918 Krzysztof Kozlowski 2024-10-22 102 l2_0: l2-cache {
97cb36ff52a106 Devi Priya 2023-03-16 103 compatible = "cache";
97cb36ff52a106 Devi Priya 2023-03-16 104 cache-level = <2>;
9c6e72fb2058dc Krzysztof Kozlowski 2023-04-16 105 cache-unified;
97cb36ff52a106 Devi Priya 2023-03-16 106 };
97cb36ff52a106 Devi Priya 2023-03-16 107 };
97cb36ff52a106 Devi Priya 2023-03-16 108
590db411752dd8 Poovendhan Selvaraj 2023-05-11 109 firmware {
590db411752dd8 Poovendhan Selvaraj 2023-05-11 110 scm {
590db411752dd8 Poovendhan Selvaraj 2023-05-11 111 compatible = "qcom,scm-ipq9574", "qcom,scm";
590db411752dd8 Poovendhan Selvaraj 2023-05-11 112 qcom,dload-mode = <&tcsr 0x6100>;
590db411752dd8 Poovendhan Selvaraj 2023-05-11 113 };
590db411752dd8 Poovendhan Selvaraj 2023-05-11 114 };
590db411752dd8 Poovendhan Selvaraj 2023-05-11 115
97cb36ff52a106 Devi Priya 2023-03-16 116 memory@40000000 {
97cb36ff52a106 Devi Priya 2023-03-16 117 device_type = "memory";
97cb36ff52a106 Devi Priya 2023-03-16 118 /* We expect the bootloader to fill in the size */
97cb36ff52a106 Devi Priya 2023-03-16 119 reg = <0x0 0x40000000 0x0 0x0>;
97cb36ff52a106 Devi Priya 2023-03-16 120 };
97cb36ff52a106 Devi Priya 2023-03-16 121
8f0ae6bc0098f6 Devi Priya 2023-05-17 122 cpu_opp_table: opp-table-cpu {
b36074357baf27 Varadarajan Narayanan 2023-10-20 123 compatible = "operating-points-v2-kryo-cpu";
8f0ae6bc0098f6 Devi Priya 2023-05-17 124 opp-shared;
b36074357baf27 Varadarajan Narayanan 2023-10-20 125 nvmem-cells = <&cpu_speed_bin>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 126
8f0ae6bc0098f6 Devi Priya 2023-05-17 127 opp-936000000 {
8f0ae6bc0098f6 Devi Priya 2023-05-17 128 opp-hz = /bits/ 64 <936000000>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 129 opp-microvolt = <725000>;
b36074357baf27 Varadarajan Narayanan 2023-10-20 130 opp-supported-hw = <0xf>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 131 clock-latency-ns = <200000>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 132 };
8f0ae6bc0098f6 Devi Priya 2023-05-17 133
8f0ae6bc0098f6 Devi Priya 2023-05-17 134 opp-1104000000 {
8f0ae6bc0098f6 Devi Priya 2023-05-17 135 opp-hz = /bits/ 64 <1104000000>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 136 opp-microvolt = <787500>;
b36074357baf27 Varadarajan Narayanan 2023-10-20 137 opp-supported-hw = <0xf>;
b36074357baf27 Varadarajan Narayanan 2023-10-20 138 clock-latency-ns = <200000>;
b36074357baf27 Varadarajan Narayanan 2023-10-20 139 };
b36074357baf27 Varadarajan Narayanan 2023-10-20 140
b36074357baf27 Varadarajan Narayanan 2023-10-20 141 opp-1200000000 {
b36074357baf27 Varadarajan Narayanan 2023-10-20 142 opp-hz = /bits/ 64 <1200000000>;
b36074357baf27 Varadarajan Narayanan 2023-10-20 143 opp-microvolt = <862500>;
b36074357baf27 Varadarajan Narayanan 2023-10-20 144 opp-supported-hw = <0xf>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 145 clock-latency-ns = <200000>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 146 };
8f0ae6bc0098f6 Devi Priya 2023-05-17 147
8f0ae6bc0098f6 Devi Priya 2023-05-17 148 opp-1416000000 {
8f0ae6bc0098f6 Devi Priya 2023-05-17 149 opp-hz = /bits/ 64 <1416000000>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 150 opp-microvolt = <862500>;
b36074357baf27 Varadarajan Narayanan 2023-10-20 151 opp-supported-hw = <0x7>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 152 clock-latency-ns = <200000>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 153 };
8f0ae6bc0098f6 Devi Priya 2023-05-17 154
8f0ae6bc0098f6 Devi Priya 2023-05-17 155 opp-1488000000 {
8f0ae6bc0098f6 Devi Priya 2023-05-17 156 opp-hz = /bits/ 64 <1488000000>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 157 opp-microvolt = <925000>;
b36074357baf27 Varadarajan Narayanan 2023-10-20 158 opp-supported-hw = <0x7>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 159 clock-latency-ns = <200000>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 160 };
8f0ae6bc0098f6 Devi Priya 2023-05-17 161
8f0ae6bc0098f6 Devi Priya 2023-05-17 162 opp-1800000000 {
8f0ae6bc0098f6 Devi Priya 2023-05-17 163 opp-hz = /bits/ 64 <1800000000>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 164 opp-microvolt = <987500>;
b36074357baf27 Varadarajan Narayanan 2023-10-20 165 opp-supported-hw = <0x5>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 166 clock-latency-ns = <200000>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 167 };
8f0ae6bc0098f6 Devi Priya 2023-05-17 168
8f0ae6bc0098f6 Devi Priya 2023-05-17 169 opp-2208000000 {
8f0ae6bc0098f6 Devi Priya 2023-05-17 170 opp-hz = /bits/ 64 <2208000000>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 171 opp-microvolt = <1062500>;
b36074357baf27 Varadarajan Narayanan 2023-10-20 172 opp-supported-hw = <0x1>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 173 clock-latency-ns = <200000>;
8f0ae6bc0098f6 Devi Priya 2023-05-17 174 };
8f0ae6bc0098f6 Devi Priya 2023-05-17 175 };
8f0ae6bc0098f6 Devi Priya 2023-05-17 176
97cb36ff52a106 Devi Priya 2023-03-16 177 pmu {
97cb36ff52a106 Devi Priya 2023-03-16 178 compatible = "arm,cortex-a73-pmu";
97cb36ff52a106 Devi Priya 2023-03-16 179 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
97cb36ff52a106 Devi Priya 2023-03-16 180 };
97cb36ff52a106 Devi Priya 2023-03-16 181
97cb36ff52a106 Devi Priya 2023-03-16 182 psci {
97cb36ff52a106 Devi Priya 2023-03-16 183 compatible = "arm,psci-1.0";
97cb36ff52a106 Devi Priya 2023-03-16 184 method = "smc";
97cb36ff52a106 Devi Priya 2023-03-16 185 };
97cb36ff52a106 Devi Priya 2023-03-16 186
7e1acc8b92a3b6 Stephan Gerhold 2023-06-15 187 rpm: remoteproc {
7e1acc8b92a3b6 Stephan Gerhold 2023-06-15 188 compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc";
7e1acc8b92a3b6 Stephan Gerhold 2023-06-15 189
7e1acc8b92a3b6 Stephan Gerhold 2023-06-15 190 glink-edge {
7e1acc8b92a3b6 Stephan Gerhold 2023-06-15 191 compatible = "qcom,glink-rpm";
7e1acc8b92a3b6 Stephan Gerhold 2023-06-15 192 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
7e1acc8b92a3b6 Stephan Gerhold 2023-06-15 193 qcom,rpm-msg-ram = <&rpm_msg_ram>;
7e1acc8b92a3b6 Stephan Gerhold 2023-06-15 194 mboxes = <&apcs_glb 0>;
7e1acc8b92a3b6 Stephan Gerhold 2023-06-15 195
7e1acc8b92a3b6 Stephan Gerhold 2023-06-15 196 rpm_requests: rpm-requests {
0b7d94e9d15d90 Dmitry Baryshkov 2024-07-29 197 compatible = "qcom,rpm-ipq9574", "qcom,glink-smd-rpm";
7e1acc8b92a3b6 Stephan Gerhold 2023-06-15 198 qcom,glink-channels = "rpm_requests";
7e1acc8b92a3b6 Stephan Gerhold 2023-06-15 199 };
7e1acc8b92a3b6 Stephan Gerhold 2023-06-15 200 };
7e1acc8b92a3b6 Stephan Gerhold 2023-06-15 201 };
7e1acc8b92a3b6 Stephan Gerhold 2023-06-15 202
97cb36ff52a106 Devi Priya 2023-03-16 203 reserved-memory {
97cb36ff52a106 Devi Priya 2023-03-16 204 #address-cells = <2>;
97cb36ff52a106 Devi Priya 2023-03-16 205 #size-cells = <2>;
97cb36ff52a106 Devi Priya 2023-03-16 206 ranges;
97cb36ff52a106 Devi Priya 2023-03-16 207
f684391e3d323b Anusha Rao 2023-06-02 208 bootloader@4a100000 {
f684391e3d323b Anusha Rao 2023-06-02 209 reg = <0x0 0x4a100000 0x0 0x400000>;
f684391e3d323b Anusha Rao 2023-06-02 210 no-map;
f684391e3d323b Anusha Rao 2023-06-02 211 };
f684391e3d323b Anusha Rao 2023-06-02 212
f684391e3d323b Anusha Rao 2023-06-02 213 sbl@4a500000 {
f684391e3d323b Anusha Rao 2023-06-02 214 reg = <0x0 0x4a500000 0x0 0x100000>;
f684391e3d323b Anusha Rao 2023-06-02 215 no-map;
f684391e3d323b Anusha Rao 2023-06-02 216 };
f684391e3d323b Anusha Rao 2023-06-02 217
97cb36ff52a106 Devi Priya 2023-03-16 218 tz_region: tz@4a600000 {
97cb36ff52a106 Devi Priya 2023-03-16 219 reg = <0x0 0x4a600000 0x0 0x400000>;
97cb36ff52a106 Devi Priya 2023-03-16 220 no-map;
97cb36ff52a106 Devi Priya 2023-03-16 221 };
46384ac7a61885 Poovendhan Selvaraj 2023-05-11 222
46384ac7a61885 Poovendhan Selvaraj 2023-05-11 223 smem@4aa00000 {
46384ac7a61885 Poovendhan Selvaraj 2023-05-11 224 compatible = "qcom,smem";
f684391e3d323b Anusha Rao 2023-06-02 225 reg = <0x0 0x4aa00000 0x0 0x100000>;
5fe8508e2bc8eb Vignesh Viswanathan 2023-09-04 226 hwlocks = <&tcsr_mutex 3>;
46384ac7a61885 Poovendhan Selvaraj 2023-05-11 227 no-map;
46384ac7a61885 Poovendhan Selvaraj 2023-05-11 228 };
97cb36ff52a106 Devi Priya 2023-03-16 229 };
97cb36ff52a106 Devi Priya 2023-03-16 230
97cb36ff52a106 Devi Priya 2023-03-16 231 soc: soc@0 {
97cb36ff52a106 Devi Priya 2023-03-16 232 compatible = "simple-bus";
97cb36ff52a106 Devi Priya 2023-03-16 233 #address-cells = <1>;
97cb36ff52a106 Devi Priya 2023-03-16 234 #size-cells = <1>;
97cb36ff52a106 Devi Priya 2023-03-16 235 ranges = <0 0 0 0xffffffff>;
97cb36ff52a106 Devi Priya 2023-03-16 236
8cc864a4375dd6 Devi Priya 2023-05-17 237 rpm_msg_ram: sram@60000 {
8cc864a4375dd6 Devi Priya 2023-05-17 238 compatible = "qcom,rpm-msg-ram";
8cc864a4375dd6 Devi Priya 2023-05-17 239 reg = <0x00060000 0x6000>;
8cc864a4375dd6 Devi Priya 2023-05-17 240 };
8cc864a4375dd6 Devi Priya 2023-05-17 241
d80c7fbfa908e3 devi priya 2024-08-01 242 pcie0_phy: phy@84000 {
d80c7fbfa908e3 devi priya 2024-08-01 243 compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
d80c7fbfa908e3 devi priya 2024-08-01 244 reg = <0x00084000 0x1000>;
d80c7fbfa908e3 devi priya 2024-08-01 245
d80c7fbfa908e3 devi priya 2024-08-01 246 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
d80c7fbfa908e3 devi priya 2024-08-01 247 <&gcc GCC_PCIE0_AHB_CLK>,
d80c7fbfa908e3 devi priya 2024-08-01 248 <&gcc GCC_PCIE0_PIPE_CLK>;
d80c7fbfa908e3 devi priya 2024-08-01 249 clock-names = "aux", "cfg_ahb", "pipe";
d80c7fbfa908e3 devi priya 2024-08-01 250
d80c7fbfa908e3 devi priya 2024-08-01 251 assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
d80c7fbfa908e3 devi priya 2024-08-01 252 assigned-clock-rates = <20000000>;
d80c7fbfa908e3 devi priya 2024-08-01 253
d80c7fbfa908e3 devi priya 2024-08-01 254 resets = <&gcc GCC_PCIE0_PHY_BCR>,
d80c7fbfa908e3 devi priya 2024-08-01 255 <&gcc GCC_PCIE0PHY_PHY_BCR>;
d80c7fbfa908e3 devi priya 2024-08-01 256 reset-names = "phy", "common";
d80c7fbfa908e3 devi priya 2024-08-01 257
d80c7fbfa908e3 devi priya 2024-08-01 258 #clock-cells = <0>;
d80c7fbfa908e3 devi priya 2024-08-01 259 clock-output-names = "gcc_pcie0_pipe_clk_src";
d80c7fbfa908e3 devi priya 2024-08-01 260
d80c7fbfa908e3 devi priya 2024-08-01 261 #phy-cells = <0>;
d80c7fbfa908e3 devi priya 2024-08-01 262 status = "disabled";
d80c7fbfa908e3 devi priya 2024-08-01 263 };
d80c7fbfa908e3 devi priya 2024-08-01 264
d80c7fbfa908e3 devi priya 2024-08-01 265 pcie2_phy: phy@8c000 {
d80c7fbfa908e3 devi priya 2024-08-01 266 compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
d80c7fbfa908e3 devi priya 2024-08-01 267 reg = <0x0008c000 0x2000>;
d80c7fbfa908e3 devi priya 2024-08-01 268
d80c7fbfa908e3 devi priya 2024-08-01 269 clocks = <&gcc GCC_PCIE2_AUX_CLK>,
d80c7fbfa908e3 devi priya 2024-08-01 270 <&gcc GCC_PCIE2_AHB_CLK>,
d80c7fbfa908e3 devi priya 2024-08-01 271 <&gcc GCC_PCIE2_PIPE_CLK>;
d80c7fbfa908e3 devi priya 2024-08-01 272 clock-names = "aux", "cfg_ahb", "pipe";
d80c7fbfa908e3 devi priya 2024-08-01 273
d80c7fbfa908e3 devi priya 2024-08-01 274 assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
d80c7fbfa908e3 devi priya 2024-08-01 275 assigned-clock-rates = <20000000>;
d80c7fbfa908e3 devi priya 2024-08-01 276
d80c7fbfa908e3 devi priya 2024-08-01 277 resets = <&gcc GCC_PCIE2_PHY_BCR>,
d80c7fbfa908e3 devi priya 2024-08-01 278 <&gcc GCC_PCIE2PHY_PHY_BCR>;
d80c7fbfa908e3 devi priya 2024-08-01 279 reset-names = "phy", "common";
d80c7fbfa908e3 devi priya 2024-08-01 280
d80c7fbfa908e3 devi priya 2024-08-01 281 #clock-cells = <0>;
d80c7fbfa908e3 devi priya 2024-08-01 282 clock-output-names = "gcc_pcie2_pipe_clk_src";
d80c7fbfa908e3 devi priya 2024-08-01 283
d80c7fbfa908e3 devi priya 2024-08-01 284 #phy-cells = <0>;
d80c7fbfa908e3 devi priya 2024-08-01 285 status = "disabled";
d80c7fbfa908e3 devi priya 2024-08-01 286 };
d80c7fbfa908e3 devi priya 2024-08-01 287
9ef42640504e09 Kathiravan T 2023-05-17 288 rng: rng@e3000 {
b3d6e8c68c3a69 Md Sadre Alam 2024-12-26 289 compatible = "qcom,ipq9574-trng", "qcom,trng";
9ef42640504e09 Kathiravan T 2023-05-17 290 reg = <0x000e3000 0x1000>;
9ef42640504e09 Kathiravan T 2023-05-17 291 clocks = <&gcc GCC_PRNG_AHB_CLK>;
9ef42640504e09 Kathiravan T 2023-05-17 292 clock-names = "core";
9ef42640504e09 Kathiravan T 2023-05-17 293 };
9ef42640504e09 Kathiravan T 2023-05-17 294
e60ac570137b42 Alexandru Gagniuc 2024-05-06 295 mdio: mdio@90000 {
e60ac570137b42 Alexandru Gagniuc 2024-05-06 296 compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio";
e60ac570137b42 Alexandru Gagniuc 2024-05-06 297 reg = <0x00090000 0x64>;
e60ac570137b42 Alexandru Gagniuc 2024-05-06 298 #address-cells = <1>;
e60ac570137b42 Alexandru Gagniuc 2024-05-06 299 #size-cells = <0>;
e60ac570137b42 Alexandru Gagniuc 2024-05-06 300 clocks = <&gcc GCC_MDIO_AHB_CLK>;
e60ac570137b42 Alexandru Gagniuc 2024-05-06 301 clock-names = "gcc_mdio_ahb_clk";
e60ac570137b42 Alexandru Gagniuc 2024-05-06 302 status = "disabled";
e60ac570137b42 Alexandru Gagniuc 2024-05-06 303 };
e60ac570137b42 Alexandru Gagniuc 2024-05-06 304
d80c7fbfa908e3 devi priya 2024-08-01 305 pcie3_phy: phy@f4000 {
d80c7fbfa908e3 devi priya 2024-08-01 306 compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
d80c7fbfa908e3 devi priya 2024-08-01 307 reg = <0x000f4000 0x2000>;
d80c7fbfa908e3 devi priya 2024-08-01 308
d80c7fbfa908e3 devi priya 2024-08-01 309 clocks = <&gcc GCC_PCIE3_AUX_CLK>,
d80c7fbfa908e3 devi priya 2024-08-01 310 <&gcc GCC_PCIE3_AHB_CLK>,
d80c7fbfa908e3 devi priya 2024-08-01 311 <&gcc GCC_PCIE3_PIPE_CLK>;
d80c7fbfa908e3 devi priya 2024-08-01 312 clock-names = "aux", "cfg_ahb", "pipe";
d80c7fbfa908e3 devi priya 2024-08-01 313
d80c7fbfa908e3 devi priya 2024-08-01 314 assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
d80c7fbfa908e3 devi priya 2024-08-01 315 assigned-clock-rates = <20000000>;
d80c7fbfa908e3 devi priya 2024-08-01 316
d80c7fbfa908e3 devi priya 2024-08-01 317 resets = <&gcc GCC_PCIE3_PHY_BCR>,
d80c7fbfa908e3 devi priya 2024-08-01 318 <&gcc GCC_PCIE3PHY_PHY_BCR>;
d80c7fbfa908e3 devi priya 2024-08-01 319 reset-names = "phy", "common";
d80c7fbfa908e3 devi priya 2024-08-01 320
d80c7fbfa908e3 devi priya 2024-08-01 321 #clock-cells = <0>;
d80c7fbfa908e3 devi priya 2024-08-01 322 clock-output-names = "gcc_pcie3_pipe_clk_src";
d80c7fbfa908e3 devi priya 2024-08-01 323
d80c7fbfa908e3 devi priya 2024-08-01 324 #phy-cells = <0>;
d80c7fbfa908e3 devi priya 2024-08-01 325 status = "disabled";
d80c7fbfa908e3 devi priya 2024-08-01 326 };
d80c7fbfa908e3 devi priya 2024-08-01 327
d80c7fbfa908e3 devi priya 2024-08-01 328 pcie1_phy: phy@fc000 {
d80c7fbfa908e3 devi priya 2024-08-01 329 compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
d80c7fbfa908e3 devi priya 2024-08-01 330 reg = <0x000fc000 0x1000>;
d80c7fbfa908e3 devi priya 2024-08-01 331
d80c7fbfa908e3 devi priya 2024-08-01 332 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
d80c7fbfa908e3 devi priya 2024-08-01 333 <&gcc GCC_PCIE1_AHB_CLK>,
d80c7fbfa908e3 devi priya 2024-08-01 334 <&gcc GCC_PCIE1_PIPE_CLK>;
d80c7fbfa908e3 devi priya 2024-08-01 335 clock-names = "aux", "cfg_ahb", "pipe";
d80c7fbfa908e3 devi priya 2024-08-01 336
d80c7fbfa908e3 devi priya 2024-08-01 337 assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
d80c7fbfa908e3 devi priya 2024-08-01 338 assigned-clock-rates = <20000000>;
d80c7fbfa908e3 devi priya 2024-08-01 339
d80c7fbfa908e3 devi priya 2024-08-01 340 resets = <&gcc GCC_PCIE1_PHY_BCR>,
d80c7fbfa908e3 devi priya 2024-08-01 341 <&gcc GCC_PCIE1PHY_PHY_BCR>;
d80c7fbfa908e3 devi priya 2024-08-01 342 reset-names = "phy", "common";
d80c7fbfa908e3 devi priya 2024-08-01 343
d80c7fbfa908e3 devi priya 2024-08-01 344 #clock-cells = <0>;
d80c7fbfa908e3 devi priya 2024-08-01 345 clock-output-names = "gcc_pcie1_pipe_clk_src";
d80c7fbfa908e3 devi priya 2024-08-01 346
d80c7fbfa908e3 devi priya 2024-08-01 347 #phy-cells = <0>;
d80c7fbfa908e3 devi priya 2024-08-01 348 status = "disabled";
d80c7fbfa908e3 devi priya 2024-08-01 349 };
d80c7fbfa908e3 devi priya 2024-08-01 350
758aa2d7e3c0ac Luo Jie 2025-01-03 351 cmn_pll: clock-controller@9b000 {
758aa2d7e3c0ac Luo Jie 2025-01-03 352 compatible = "qcom,ipq9574-cmn-pll";
758aa2d7e3c0ac Luo Jie 2025-01-03 353 reg = <0x0009b000 0x800>;
758aa2d7e3c0ac Luo Jie 2025-01-03 354 clocks = <&ref_48mhz_clk>,
758aa2d7e3c0ac Luo Jie 2025-01-03 355 <&gcc GCC_CMN_12GPLL_AHB_CLK>,
758aa2d7e3c0ac Luo Jie 2025-01-03 356 <&gcc GCC_CMN_12GPLL_SYS_CLK>;
758aa2d7e3c0ac Luo Jie 2025-01-03 357 clock-names = "ref", "ahb", "sys";
758aa2d7e3c0ac Luo Jie 2025-01-03 358 #clock-cells = <1>;
758aa2d7e3c0ac Luo Jie 2025-01-03 359 assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
758aa2d7e3c0ac Luo Jie 2025-01-03 360 assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
758aa2d7e3c0ac Luo Jie 2025-01-03 361 };
758aa2d7e3c0ac Luo Jie 2025-01-03 362
05e6b82f395c40 Kathiravan T 2023-05-26 363 qfprom: efuse@a4000 {
05e6b82f395c40 Kathiravan T 2023-05-26 364 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
05e6b82f395c40 Kathiravan T 2023-05-26 365 reg = <0x000a4000 0x5a1>;
05e6b82f395c40 Kathiravan T 2023-05-26 366 #address-cells = <1>;
05e6b82f395c40 Kathiravan T 2023-05-26 367 #size-cells = <1>;
b36074357baf27 Varadarajan Narayanan 2023-10-20 368
b36074357baf27 Varadarajan Narayanan 2023-10-20 369 cpu_speed_bin: cpu-speed-bin@15 {
b36074357baf27 Varadarajan Narayanan 2023-10-20 370 reg = <0x15 0x2>;
b36074357baf27 Varadarajan Narayanan 2023-10-20 371 bits = <7 2>;
b36074357baf27 Varadarajan Narayanan 2023-10-20 372 };
05e6b82f395c40 Kathiravan T 2023-05-26 373 };
05e6b82f395c40 Kathiravan T 2023-05-26 374
ffadc79ed99f0f Anusha Rao 2023-05-26 375 cryptobam: dma-controller@704000 {
ffadc79ed99f0f Anusha Rao 2023-05-26 376 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
ffadc79ed99f0f Anusha Rao 2023-05-26 377 reg = <0x00704000 0x20000>;
ffadc79ed99f0f Anusha Rao 2023-05-26 378 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
ffadc79ed99f0f Anusha Rao 2023-05-26 379 #dma-cells = <1>;
ffadc79ed99f0f Anusha Rao 2023-05-26 380 qcom,ee = <1>;
ffadc79ed99f0f Anusha Rao 2023-05-26 381 qcom,controlled-remotely;
ffadc79ed99f0f Anusha Rao 2023-05-26 382 };
ffadc79ed99f0f Anusha Rao 2023-05-26 383
ffadc79ed99f0f Anusha Rao 2023-05-26 384 crypto: crypto@73a000 {
ffadc79ed99f0f Anusha Rao 2023-05-26 385 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";
ffadc79ed99f0f Anusha Rao 2023-05-26 386 reg = <0x0073a000 0x6000>;
ffadc79ed99f0f Anusha Rao 2023-05-26 387 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
ffadc79ed99f0f Anusha Rao 2023-05-26 388 <&gcc GCC_CRYPTO_AXI_CLK>,
ffadc79ed99f0f Anusha Rao 2023-05-26 389 <&gcc GCC_CRYPTO_CLK>;
ffadc79ed99f0f Anusha Rao 2023-05-26 390 clock-names = "iface", "bus", "core";
ffadc79ed99f0f Anusha Rao 2023-05-26 391 dmas = <&cryptobam 2>, <&cryptobam 3>;
ffadc79ed99f0f Anusha Rao 2023-05-26 392 dma-names = "rx", "tx";
ffadc79ed99f0f Anusha Rao 2023-05-26 393 };
ffadc79ed99f0f Anusha Rao 2023-05-26 394
2e0580e10e919b Varadarajan Narayanan 2023-06-07 395 tsens: thermal-sensor@4a9000 {
2e0580e10e919b Varadarajan Narayanan 2023-06-07 396 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens";
2e0580e10e919b Varadarajan Narayanan 2023-06-07 397 reg = <0x004a9000 0x1000>,
2e0580e10e919b Varadarajan Narayanan 2023-06-07 398 <0x004a8000 0x1000>;
2e0580e10e919b Varadarajan Narayanan 2023-06-07 399 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2e0580e10e919b Varadarajan Narayanan 2023-06-07 400 interrupt-names = "combined";
2e0580e10e919b Varadarajan Narayanan 2023-06-07 401 #qcom,sensors = <16>;
2e0580e10e919b Varadarajan Narayanan 2023-06-07 402 #thermal-sensor-cells = <1>;
2e0580e10e919b Varadarajan Narayanan 2023-06-07 403 };
2e0580e10e919b Varadarajan Narayanan 2023-06-07 404
97cb36ff52a106 Devi Priya 2023-03-16 405 tlmm: pinctrl@1000000 {
97cb36ff52a106 Devi Priya 2023-03-16 406 compatible = "qcom,ipq9574-tlmm";
97cb36ff52a106 Devi Priya 2023-03-16 407 reg = <0x01000000 0x300000>;
97cb36ff52a106 Devi Priya 2023-03-16 408 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
97cb36ff52a106 Devi Priya 2023-03-16 409 gpio-controller;
97cb36ff52a106 Devi Priya 2023-03-16 410 #gpio-cells = <2>;
97cb36ff52a106 Devi Priya 2023-03-16 411 gpio-ranges = <&tlmm 0 0 65>;
97cb36ff52a106 Devi Priya 2023-03-16 412 interrupt-controller;
97cb36ff52a106 Devi Priya 2023-03-16 413 #interrupt-cells = <2>;
97cb36ff52a106 Devi Priya 2023-03-16 414
97cb36ff52a106 Devi Priya 2023-03-16 415 uart2_pins: uart2-state {
97cb36ff52a106 Devi Priya 2023-03-16 416 pins = "gpio34", "gpio35";
97cb36ff52a106 Devi Priya 2023-03-16 417 function = "blsp2_uart";
97cb36ff52a106 Devi Priya 2023-03-16 418 drive-strength = <8>;
97cb36ff52a106 Devi Priya 2023-03-16 419 bias-disable;
97cb36ff52a106 Devi Priya 2023-03-16 420 };
97cb36ff52a106 Devi Priya 2023-03-16 421 };
97cb36ff52a106 Devi Priya 2023-03-16 422
97cb36ff52a106 Devi Priya 2023-03-16 423 gcc: clock-controller@1800000 {
97cb36ff52a106 Devi Priya 2023-03-16 424 compatible = "qcom,ipq9574-gcc";
97cb36ff52a106 Devi Priya 2023-03-16 425 reg = <0x01800000 0x80000>;
97cb36ff52a106 Devi Priya 2023-03-16 426 clocks = <&xo_board_clk>,
97cb36ff52a106 Devi Priya 2023-03-16 427 <&sleep_clk>,
4fc6a939aba4c0 Devi Priya 2023-04-25 428 <0>,
d80c7fbfa908e3 devi priya 2024-08-01 429 <&pcie0_phy>,
d80c7fbfa908e3 devi priya 2024-08-01 430 <&pcie1_phy>,
d80c7fbfa908e3 devi priya 2024-08-01 431 <&pcie2_phy>,
d80c7fbfa908e3 devi priya 2024-08-01 432 <&pcie3_phy>,
97cb36ff52a106 Devi Priya 2023-03-16 433 <0>;
97cb36ff52a106 Devi Priya 2023-03-16 434 #clock-cells = <1>;
97cb36ff52a106 Devi Priya 2023-03-16 435 #reset-cells = <1>;
5d0ab61a700214 Varadarajan Narayanan 2024-04-30 436 #interconnect-cells = <1>;
97cb36ff52a106 Devi Priya 2023-03-16 437 };
97cb36ff52a106 Devi Priya 2023-03-16 438
46384ac7a61885 Poovendhan Selvaraj 2023-05-11 439 tcsr_mutex: hwlock@1905000 {
46384ac7a61885 Poovendhan Selvaraj 2023-05-11 440 compatible = "qcom,tcsr-mutex";
46384ac7a61885 Poovendhan Selvaraj 2023-05-11 441 reg = <0x01905000 0x20000>;
46384ac7a61885 Poovendhan Selvaraj 2023-05-11 442 #hwlock-cells = <1>;
46384ac7a61885 Poovendhan Selvaraj 2023-05-11 443 };
46384ac7a61885 Poovendhan Selvaraj 2023-05-11 444
590db411752dd8 Poovendhan Selvaraj 2023-05-11 445 tcsr: syscon@1937000 {
590db411752dd8 Poovendhan Selvaraj 2023-05-11 446 compatible = "qcom,tcsr-ipq9574", "syscon";
590db411752dd8 Poovendhan Selvaraj 2023-05-11 447 reg = <0x01937000 0x21000>;
590db411752dd8 Poovendhan Selvaraj 2023-05-11 448 };
590db411752dd8 Poovendhan Selvaraj 2023-05-11 449
97cb36ff52a106 Devi Priya 2023-03-16 450 sdhc_1: mmc@7804000 {
97cb36ff52a106 Devi Priya 2023-03-16 451 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
2ae5e34d93cfe5 Vignesh Viswanathan 2023-12-15 452 reg = <0x07804000 0x1000>,
2ae5e34d93cfe5 Vignesh Viswanathan 2023-12-15 453 <0x07805000 0x1000>,
2ae5e34d93cfe5 Vignesh Viswanathan 2023-12-15 454 <0x07808000 0x2000>;
2ae5e34d93cfe5 Vignesh Viswanathan 2023-12-15 455 reg-names = "hc", "cqhci", "ice";
97cb36ff52a106 Devi Priya 2023-03-16 456
97cb36ff52a106 Devi Priya 2023-03-16 457 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
97cb36ff52a106 Devi Priya 2023-03-16 458 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
97cb36ff52a106 Devi Priya 2023-03-16 459 interrupt-names = "hc_irq", "pwr_irq";
97cb36ff52a106 Devi Priya 2023-03-16 460
97cb36ff52a106 Devi Priya 2023-03-16 461 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
97cb36ff52a106 Devi Priya 2023-03-16 462 <&gcc GCC_SDCC1_APPS_CLK>,
2ae5e34d93cfe5 Vignesh Viswanathan 2023-12-15 463 <&xo_board_clk>,
2ae5e34d93cfe5 Vignesh Viswanathan 2023-12-15 464 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
2ae5e34d93cfe5 Vignesh Viswanathan 2023-12-15 465 clock-names = "iface", "core", "xo", "ice";
97cb36ff52a106 Devi Priya 2023-03-16 466 non-removable;
2ae5e34d93cfe5 Vignesh Viswanathan 2023-12-15 467 supports-cqe;
97cb36ff52a106 Devi Priya 2023-03-16 468 status = "disabled";
97cb36ff52a106 Devi Priya 2023-03-16 469 };
97cb36ff52a106 Devi Priya 2023-03-16 470
9ef42640504e09 Kathiravan T 2023-05-17 471 blsp_dma: dma-controller@7884000 {
9ef42640504e09 Kathiravan T 2023-05-17 472 compatible = "qcom,bam-v1.7.0";
9ef42640504e09 Kathiravan T 2023-05-17 473 reg = <0x07884000 0x2b000>;
9ef42640504e09 Kathiravan T 2023-05-17 474 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
9ef42640504e09 Kathiravan T 2023-05-17 475 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
9ef42640504e09 Kathiravan T 2023-05-17 476 clock-names = "bam_clk";
9ef42640504e09 Kathiravan T 2023-05-17 477 #dma-cells = <1>;
9ef42640504e09 Kathiravan T 2023-05-17 478 qcom,ee = <0>;
9ef42640504e09 Kathiravan T 2023-05-17 479 };
9ef42640504e09 Kathiravan T 2023-05-17 480
9ef42640504e09 Kathiravan T 2023-05-17 481 blsp1_uart0: serial@78af000 {
9ef42640504e09 Kathiravan T 2023-05-17 482 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
9ef42640504e09 Kathiravan T 2023-05-17 483 reg = <0x078af000 0x200>;
9ef42640504e09 Kathiravan T 2023-05-17 484 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
9ef42640504e09 Kathiravan T 2023-05-17 485 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
9ef42640504e09 Kathiravan T 2023-05-17 486 <&gcc GCC_BLSP1_AHB_CLK>;
9ef42640504e09 Kathiravan T 2023-05-17 487 clock-names = "core", "iface";
9ef42640504e09 Kathiravan T 2023-05-17 488 status = "disabled";
9ef42640504e09 Kathiravan T 2023-05-17 489 };
9ef42640504e09 Kathiravan T 2023-05-17 490
9ef42640504e09 Kathiravan T 2023-05-17 491 blsp1_uart1: serial@78b0000 {
9ef42640504e09 Kathiravan T 2023-05-17 492 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
9ef42640504e09 Kathiravan T 2023-05-17 493 reg = <0x078b0000 0x200>;
9ef42640504e09 Kathiravan T 2023-05-17 494 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
9ef42640504e09 Kathiravan T 2023-05-17 495 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
9ef42640504e09 Kathiravan T 2023-05-17 496 <&gcc GCC_BLSP1_AHB_CLK>;
9ef42640504e09 Kathiravan T 2023-05-17 497 clock-names = "core", "iface";
9ef42640504e09 Kathiravan T 2023-05-17 498 status = "disabled";
9ef42640504e09 Kathiravan T 2023-05-17 499 };
9ef42640504e09 Kathiravan T 2023-05-17 500
97cb36ff52a106 Devi Priya 2023-03-16 501 blsp1_uart2: serial@78b1000 {
97cb36ff52a106 Devi Priya 2023-03-16 502 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
97cb36ff52a106 Devi Priya 2023-03-16 503 reg = <0x078b1000 0x200>;
97cb36ff52a106 Devi Priya 2023-03-16 504 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
97cb36ff52a106 Devi Priya 2023-03-16 505 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
97cb36ff52a106 Devi Priya 2023-03-16 506 <&gcc GCC_BLSP1_AHB_CLK>;
97cb36ff52a106 Devi Priya 2023-03-16 507 clock-names = "core", "iface";
97cb36ff52a106 Devi Priya 2023-03-16 508 status = "disabled";
97cb36ff52a106 Devi Priya 2023-03-16 509 };
97cb36ff52a106 Devi Priya 2023-03-16 510
9ef42640504e09 Kathiravan T 2023-05-17 511 blsp1_uart3: serial@78b2000 {
9ef42640504e09 Kathiravan T 2023-05-17 512 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
9ef42640504e09 Kathiravan T 2023-05-17 513 reg = <0x078b2000 0x200>;
9ef42640504e09 Kathiravan T 2023-05-17 514 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
9ef42640504e09 Kathiravan T 2023-05-17 515 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
9ef42640504e09 Kathiravan T 2023-05-17 516 <&gcc GCC_BLSP1_AHB_CLK>;
9ef42640504e09 Kathiravan T 2023-05-17 517 clock-names = "core", "iface";
9ef42640504e09 Kathiravan T 2023-05-17 518 status = "disabled";
9ef42640504e09 Kathiravan T 2023-05-17 519 };
9ef42640504e09 Kathiravan T 2023-05-17 520
9ef42640504e09 Kathiravan T 2023-05-17 521 blsp1_uart4: serial@78b3000 {
9ef42640504e09 Kathiravan T 2023-05-17 522 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
9ef42640504e09 Kathiravan T 2023-05-17 523 reg = <0x078b3000 0x200>;
9ef42640504e09 Kathiravan T 2023-05-17 524 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
9ef42640504e09 Kathiravan T 2023-05-17 525 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
9ef42640504e09 Kathiravan T 2023-05-17 526 <&gcc GCC_BLSP1_AHB_CLK>;
9ef42640504e09 Kathiravan T 2023-05-17 527 clock-names = "core", "iface";
9ef42640504e09 Kathiravan T 2023-05-17 528 status = "disabled";
9ef42640504e09 Kathiravan T 2023-05-17 529 };
9ef42640504e09 Kathiravan T 2023-05-17 530
9ef42640504e09 Kathiravan T 2023-05-17 531 blsp1_uart5: serial@78b4000 {
9ef42640504e09 Kathiravan T 2023-05-17 532 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
9ef42640504e09 Kathiravan T 2023-05-17 533 reg = <0x078b4000 0x200>;
9ef42640504e09 Kathiravan T 2023-05-17 534 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
9ef42640504e09 Kathiravan T 2023-05-17 535 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
9ef42640504e09 Kathiravan T 2023-05-17 536 <&gcc GCC_BLSP1_AHB_CLK>;
9ef42640504e09 Kathiravan T 2023-05-17 537 clock-names = "core", "iface";
9ef42640504e09 Kathiravan T 2023-05-17 538 status = "disabled";
9ef42640504e09 Kathiravan T 2023-05-17 539 };
9ef42640504e09 Kathiravan T 2023-05-17 540
9ef42640504e09 Kathiravan T 2023-05-17 541 blsp1_spi0: spi@78b5000 {
9ef42640504e09 Kathiravan T 2023-05-17 542 compatible = "qcom,spi-qup-v2.2.1";
9ef42640504e09 Kathiravan T 2023-05-17 543 reg = <0x078b5000 0x600>;
9ef42640504e09 Kathiravan T 2023-05-17 544 #address-cells = <1>;
9ef42640504e09 Kathiravan T 2023-05-17 545 #size-cells = <0>;
9ef42640504e09 Kathiravan T 2023-05-17 546 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
9ef42640504e09 Kathiravan T 2023-05-17 547 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
9ef42640504e09 Kathiravan T 2023-05-17 548 <&gcc GCC_BLSP1_AHB_CLK>;
9ef42640504e09 Kathiravan T 2023-05-17 549 clock-names = "core", "iface";
9ef42640504e09 Kathiravan T 2023-05-17 550 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
9ef42640504e09 Kathiravan T 2023-05-17 551 dma-names = "tx", "rx";
9ef42640504e09 Kathiravan T 2023-05-17 552 status = "disabled";
9ef42640504e09 Kathiravan T 2023-05-17 553 };
9ef42640504e09 Kathiravan T 2023-05-17 554
9ef42640504e09 Kathiravan T 2023-05-17 555 blsp1_i2c1: i2c@78b6000 {
9ef42640504e09 Kathiravan T 2023-05-17 556 compatible = "qcom,i2c-qup-v2.2.1";
9ef42640504e09 Kathiravan T 2023-05-17 557 reg = <0x078b6000 0x600>;
9ef42640504e09 Kathiravan T 2023-05-17 558 #address-cells = <1>;
9ef42640504e09 Kathiravan T 2023-05-17 559 #size-cells = <0>;
9ef42640504e09 Kathiravan T 2023-05-17 560 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
9ef42640504e09 Kathiravan T 2023-05-17 561 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
9ef42640504e09 Kathiravan T 2023-05-17 562 <&gcc GCC_BLSP1_AHB_CLK>;
9ef42640504e09 Kathiravan T 2023-05-17 563 clock-names = "core", "iface";
5229c1d6a0c7d7 Devi Priya 2023-06-15 564 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
5229c1d6a0c7d7 Devi Priya 2023-06-15 565 assigned-clock-rates = <50000000>;
9ef42640504e09 Kathiravan T 2023-05-17 566 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
9ef42640504e09 Kathiravan T 2023-05-17 567 dma-names = "tx", "rx";
9ef42640504e09 Kathiravan T 2023-05-17 568 status = "disabled";
9ef42640504e09 Kathiravan T 2023-05-17 569 };
9ef42640504e09 Kathiravan T 2023-05-17 570
9ef42640504e09 Kathiravan T 2023-05-17 571 blsp1_spi1: spi@78b6000 {
9ef42640504e09 Kathiravan T 2023-05-17 572 compatible = "qcom,spi-qup-v2.2.1";
9ef42640504e09 Kathiravan T 2023-05-17 573 reg = <0x078b6000 0x600>;
9ef42640504e09 Kathiravan T 2023-05-17 574 #address-cells = <1>;
9ef42640504e09 Kathiravan T 2023-05-17 575 #size-cells = <0>;
9ef42640504e09 Kathiravan T 2023-05-17 576 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
9ef42640504e09 Kathiravan T 2023-05-17 577 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
9ef42640504e09 Kathiravan T 2023-05-17 578 <&gcc GCC_BLSP1_AHB_CLK>;
9ef42640504e09 Kathiravan T 2023-05-17 579 clock-names = "core", "iface";
9ef42640504e09 Kathiravan T 2023-05-17 580 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
9ef42640504e09 Kathiravan T 2023-05-17 581 dma-names = "tx", "rx";
9ef42640504e09 Kathiravan T 2023-05-17 582 status = "disabled";
9ef42640504e09 Kathiravan T 2023-05-17 583 };
9ef42640504e09 Kathiravan T 2023-05-17 584
9ef42640504e09 Kathiravan T 2023-05-17 585 blsp1_i2c2: i2c@78b7000 {
9ef42640504e09 Kathiravan T 2023-05-17 586 compatible = "qcom,i2c-qup-v2.2.1";
9ef42640504e09 Kathiravan T 2023-05-17 587 reg = <0x078b7000 0x600>;
9ef42640504e09 Kathiravan T 2023-05-17 588 #address-cells = <1>;
9ef42640504e09 Kathiravan T 2023-05-17 589 #size-cells = <0>;
9ef42640504e09 Kathiravan T 2023-05-17 590 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
9ef42640504e09 Kathiravan T 2023-05-17 591 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
9ef42640504e09 Kathiravan T 2023-05-17 592 <&gcc GCC_BLSP1_AHB_CLK>;
9ef42640504e09 Kathiravan T 2023-05-17 593 clock-names = "core", "iface";
5229c1d6a0c7d7 Devi Priya 2023-06-15 594 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
5229c1d6a0c7d7 Devi Priya 2023-06-15 595 assigned-clock-rates = <50000000>;
9ef42640504e09 Kathiravan T 2023-05-17 596 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
9ef42640504e09 Kathiravan T 2023-05-17 597 dma-names = "tx", "rx";
9ef42640504e09 Kathiravan T 2023-05-17 598 status = "disabled";
9ef42640504e09 Kathiravan T 2023-05-17 599 };
9ef42640504e09 Kathiravan T 2023-05-17 600
9ef42640504e09 Kathiravan T 2023-05-17 601 blsp1_spi2: spi@78b7000 {
9ef42640504e09 Kathiravan T 2023-05-17 602 compatible = "qcom,spi-qup-v2.2.1";
9ef42640504e09 Kathiravan T 2023-05-17 603 reg = <0x078b7000 0x600>;
9ef42640504e09 Kathiravan T 2023-05-17 604 #address-cells = <1>;
9ef42640504e09 Kathiravan T 2023-05-17 605 #size-cells = <0>;
9ef42640504e09 Kathiravan T 2023-05-17 606 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
9ef42640504e09 Kathiravan T 2023-05-17 607 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
9ef42640504e09 Kathiravan T 2023-05-17 608 <&gcc GCC_BLSP1_AHB_CLK>;
9ef42640504e09 Kathiravan T 2023-05-17 609 clock-names = "core", "iface";
9ef42640504e09 Kathiravan T 2023-05-17 610 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
9ef42640504e09 Kathiravan T 2023-05-17 611 dma-names = "tx", "rx";
9ef42640504e09 Kathiravan T 2023-05-17 612 status = "disabled";
9ef42640504e09 Kathiravan T 2023-05-17 613 };
9ef42640504e09 Kathiravan T 2023-05-17 614
9ef42640504e09 Kathiravan T 2023-05-17 615 blsp1_i2c3: i2c@78b8000 {
9ef42640504e09 Kathiravan T 2023-05-17 616 compatible = "qcom,i2c-qup-v2.2.1";
9ef42640504e09 Kathiravan T 2023-05-17 617 reg = <0x078b8000 0x600>;
9ef42640504e09 Kathiravan T 2023-05-17 618 #address-cells = <1>;
9ef42640504e09 Kathiravan T 2023-05-17 619 #size-cells = <0>;
9ef42640504e09 Kathiravan T 2023-05-17 620 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
9ef42640504e09 Kathiravan T 2023-05-17 621 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
9ef42640504e09 Kathiravan T 2023-05-17 622 <&gcc GCC_BLSP1_AHB_CLK>;
9ef42640504e09 Kathiravan T 2023-05-17 623 clock-names = "core", "iface";
5229c1d6a0c7d7 Devi Priya 2023-06-15 624 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
5229c1d6a0c7d7 Devi Priya 2023-06-15 625 assigned-clock-rates = <50000000>;
9ef42640504e09 Kathiravan T 2023-05-17 626 dmas = <&blsp_dma 18>, <&blsp_dma 19>;
9ef42640504e09 Kathiravan T 2023-05-17 627 dma-names = "tx", "rx";
9ef42640504e09 Kathiravan T 2023-05-17 628 status = "disabled";
9ef42640504e09 Kathiravan T 2023-05-17 629 };
9ef42640504e09 Kathiravan T 2023-05-17 630
9ef42640504e09 Kathiravan T 2023-05-17 631 blsp1_spi3: spi@78b8000 {
9ef42640504e09 Kathiravan T 2023-05-17 632 compatible = "qcom,spi-qup-v2.2.1";
9ef42640504e09 Kathiravan T 2023-05-17 633 reg = <0x078b8000 0x600>;
9ef42640504e09 Kathiravan T 2023-05-17 634 #address-cells = <1>;
9ef42640504e09 Kathiravan T 2023-05-17 635 #size-cells = <0>;
9ef42640504e09 Kathiravan T 2023-05-17 636 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
9ef42640504e09 Kathiravan T 2023-05-17 637 spi-max-frequency = <50000000>;
9ef42640504e09 Kathiravan T 2023-05-17 638 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
9ef42640504e09 Kathiravan T 2023-05-17 639 <&gcc GCC_BLSP1_AHB_CLK>;
9ef42640504e09 Kathiravan T 2023-05-17 640 clock-names = "core", "iface";
9ef42640504e09 Kathiravan T 2023-05-17 641 dmas = <&blsp_dma 18>, <&blsp_dma 19>;
9ef42640504e09 Kathiravan T 2023-05-17 642 dma-names = "tx", "rx";
9ef42640504e09 Kathiravan T 2023-05-17 643 status = "disabled";
9ef42640504e09 Kathiravan T 2023-05-17 644 };
9ef42640504e09 Kathiravan T 2023-05-17 645
9ef42640504e09 Kathiravan T 2023-05-17 646 blsp1_i2c4: i2c@78b9000 {
9ef42640504e09 Kathiravan T 2023-05-17 647 compatible = "qcom,i2c-qup-v2.2.1";
9ef42640504e09 Kathiravan T 2023-05-17 648 reg = <0x078b9000 0x600>;
9ef42640504e09 Kathiravan T 2023-05-17 649 #address-cells = <1>;
9ef42640504e09 Kathiravan T 2023-05-17 650 #size-cells = <0>;
9ef42640504e09 Kathiravan T 2023-05-17 651 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
9ef42640504e09 Kathiravan T 2023-05-17 652 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
9ef42640504e09 Kathiravan T 2023-05-17 653 <&gcc GCC_BLSP1_AHB_CLK>;
9ef42640504e09 Kathiravan T 2023-05-17 654 clock-names = "core", "iface";
5229c1d6a0c7d7 Devi Priya 2023-06-15 655 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
5229c1d6a0c7d7 Devi Priya 2023-06-15 656 assigned-clock-rates = <50000000>;
9ef42640504e09 Kathiravan T 2023-05-17 657 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
9ef42640504e09 Kathiravan T 2023-05-17 658 dma-names = "tx", "rx";
9ef42640504e09 Kathiravan T 2023-05-17 659 status = "disabled";
9ef42640504e09 Kathiravan T 2023-05-17 660 };
9ef42640504e09 Kathiravan T 2023-05-17 661
9ef42640504e09 Kathiravan T 2023-05-17 662 blsp1_spi4: spi@78b9000 {
9ef42640504e09 Kathiravan T 2023-05-17 663 compatible = "qcom,spi-qup-v2.2.1";
9ef42640504e09 Kathiravan T 2023-05-17 664 reg = <0x078b9000 0x600>;
9ef42640504e09 Kathiravan T 2023-05-17 665 #address-cells = <1>;
9ef42640504e09 Kathiravan T 2023-05-17 666 #size-cells = <0>;
9ef42640504e09 Kathiravan T 2023-05-17 667 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
9ef42640504e09 Kathiravan T 2023-05-17 668 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
9ef42640504e09 Kathiravan T 2023-05-17 669 <&gcc GCC_BLSP1_AHB_CLK>;
9ef42640504e09 Kathiravan T 2023-05-17 670 clock-names = "core", "iface";
9ef42640504e09 Kathiravan T 2023-05-17 671 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
9ef42640504e09 Kathiravan T 2023-05-17 672 dma-names = "tx", "rx";
9ef42640504e09 Kathiravan T 2023-05-17 673 status = "disabled";
9ef42640504e09 Kathiravan T 2023-05-17 674 };
9ef42640504e09 Kathiravan T 2023-05-17 675
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 676 usb_0_qusbphy: phy@7b000 {
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 677 compatible = "qcom,ipq9574-qusb2-phy";
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 678 reg = <0x0007b000 0x180>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 679 #phy-cells = <0>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 680
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 681 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 682 <&xo_board_clk>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 683 clock-names = "cfg_ahb",
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 684 "ref";
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 685
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 686 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 687 status = "disabled";
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 688 };
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 689
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 690 usb_0_qmpphy: phy@7d000 {
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 691 compatible = "qcom,ipq9574-qmp-usb3-phy";
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 692 reg = <0x0007d000 0xa00>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 693 #phy-cells = <0>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 694
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 695 clocks = <&gcc GCC_USB0_AUX_CLK>,
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 696 <&xo_board_clk>,
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 697 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 698 <&gcc GCC_USB0_PIPE_CLK>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 699 clock-names = "aux",
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 700 "ref",
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 701 "cfg_ahb",
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 702 "pipe";
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 703
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 704 resets = <&gcc GCC_USB0_PHY_BCR>,
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 705 <&gcc GCC_USB3PHY_0_PHY_BCR>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 706 reset-names = "phy",
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 707 "phy_phy";
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 708
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 709 #clock-cells = <0>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 710 clock-output-names = "usb0_pipe_clk";
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 711
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 712 status = "disabled";
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 713 };
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 714
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 715 usb3: usb@8af8800 {
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 716 compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 717 reg = <0x08af8800 0x400>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 718 #address-cells = <1>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 719 #size-cells = <1>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 720 ranges;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 721
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 722 clocks = <&gcc GCC_SNOC_USB_CLK>,
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 723 <&gcc GCC_USB0_MASTER_CLK>,
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 724 <&gcc GCC_ANOC_USB_AXI_CLK>,
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 725 <&gcc GCC_USB0_SLEEP_CLK>,
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 726 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 727
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 728 clock-names = "cfg_noc",
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 729 "core",
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 730 "iface",
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 731 "sleep",
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 732 "mock_utmi";
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 733
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 734 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 735 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 736 assigned-clock-rates = <200000000>,
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 737 <24000000>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 738
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 739 interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 740 interrupt-names = "pwr_event";
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 741
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 742 resets = <&gcc GCC_USB_BCR>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 743 status = "disabled";
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 744
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 745 usb_0_dwc3: usb@8a00000 {
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 746 compatible = "snps,dwc3";
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 747 reg = <0x8a00000 0xcd00>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 748 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 749 clock-names = "ref";
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 750 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 751 phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 752 phy-names = "usb2-phy", "usb3-phy";
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 753 tx-fifo-resize;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 754 snps,is-utmi-l1-suspend;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 755 snps,hird-threshold = /bits/ 8 <0x0>;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 756 snps,dis_u2_susphy_quirk;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 757 snps,dis_u3_susphy_quirk;
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 758 };
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 759 };
a98bfb31f6766d Varadarajan Narayanan 2023-06-09 760
97cb36ff52a106 Devi Priya 2023-03-16 761 intc: interrupt-controller@b000000 {
97cb36ff52a106 Devi Priya 2023-03-16 762 compatible = "qcom,msm-qgic2";
97cb36ff52a106 Devi Priya 2023-03-16 763 reg = <0x0b000000 0x1000>, /* GICD */
6fb45762691d12 Devi Priya 2023-04-25 764 <0x0b002000 0x2000>, /* GICC */
97cb36ff52a106 Devi Priya 2023-03-16 765 <0x0b001000 0x1000>, /* GICH */
6fb45762691d12 Devi Priya 2023-04-25 766 <0x0b004000 0x2000>; /* GICV */
97cb36ff52a106 Devi Priya 2023-03-16 767 #address-cells = <1>;
97cb36ff52a106 Devi Priya 2023-03-16 768 #size-cells = <1>;
97cb36ff52a106 Devi Priya 2023-03-16 769 interrupt-controller;
97cb36ff52a106 Devi Priya 2023-03-16 770 #interrupt-cells = <3>;
6fb45762691d12 Devi Priya 2023-04-25 771 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
97cb36ff52a106 Devi Priya 2023-03-16 772 ranges = <0 0x0b00c000 0x3000>;
97cb36ff52a106 Devi Priya 2023-03-16 773
97cb36ff52a106 Devi Priya 2023-03-16 774 v2m0: v2m@0 {
97cb36ff52a106 Devi Priya 2023-03-16 775 compatible = "arm,gic-v2m-frame";
97cb36ff52a106 Devi Priya 2023-03-16 776 reg = <0x00000000 0xffd>;
97cb36ff52a106 Devi Priya 2023-03-16 777 msi-controller;
97cb36ff52a106 Devi Priya 2023-03-16 778 };
97cb36ff52a106 Devi Priya 2023-03-16 779
97cb36ff52a106 Devi Priya 2023-03-16 780 v2m1: v2m@1000 {
97cb36ff52a106 Devi Priya 2023-03-16 781 compatible = "arm,gic-v2m-frame";
97cb36ff52a106 Devi Priya 2023-03-16 782 reg = <0x00001000 0xffd>;
97cb36ff52a106 Devi Priya 2023-03-16 783 msi-controller;
97cb36ff52a106 Devi Priya 2023-03-16 784 };
97cb36ff52a106 Devi Priya 2023-03-16 785
97cb36ff52a106 Devi Priya 2023-03-16 786 v2m2: v2m@2000 {
97cb36ff52a106 Devi Priya 2023-03-16 787 compatible = "arm,gic-v2m-frame";
97cb36ff52a106 Devi Priya 2023-03-16 788 reg = <0x00002000 0xffd>;
97cb36ff52a106 Devi Priya 2023-03-16 789 msi-controller;
97cb36ff52a106 Devi Priya 2023-03-16 790 };
97cb36ff52a106 Devi Priya 2023-03-16 791 };
97cb36ff52a106 Devi Priya 2023-03-16 792
9ef42640504e09 Kathiravan T 2023-05-17 793 watchdog: watchdog@b017000 {
9ef42640504e09 Kathiravan T 2023-05-17 794 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt";
9ef42640504e09 Kathiravan T 2023-05-17 795 reg = <0x0b017000 0x1000>;
9ef42640504e09 Kathiravan T 2023-05-17 796 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
9ef42640504e09 Kathiravan T 2023-05-17 797 clocks = <&sleep_clk>;
9ef42640504e09 Kathiravan T 2023-05-17 798 timeout-sec = <30>;
9ef42640504e09 Kathiravan T 2023-05-17 799 };
9ef42640504e09 Kathiravan T 2023-05-17 800
84c4a652db1cf7 Devi Priya 2023-04-06 801 apcs_glb: mailbox@b111000 {
84c4a652db1cf7 Devi Priya 2023-04-06 802 compatible = "qcom,ipq9574-apcs-apps-global",
84c4a652db1cf7 Devi Priya 2023-04-06 803 "qcom,ipq6018-apcs-apps-global";
84c4a652db1cf7 Devi Priya 2023-04-06 804 reg = <0x0b111000 0x1000>;
84c4a652db1cf7 Devi Priya 2023-04-06 805 #clock-cells = <1>;
77c726a4f3b124 Kathiravan Thirumoorthy 2023-09-14 806 clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>;
77c726a4f3b124 Kathiravan Thirumoorthy 2023-09-14 807 clock-names = "pll", "xo", "gpll0";
84c4a652db1cf7 Devi Priya 2023-04-06 808 #mbox-cells = <1>;
84c4a652db1cf7 Devi Priya 2023-04-06 809 };
84c4a652db1cf7 Devi Priya 2023-04-06 810
84c4a652db1cf7 Devi Priya 2023-04-06 811 a73pll: clock@b116000 {
84c4a652db1cf7 Devi Priya 2023-04-06 812 compatible = "qcom,ipq9574-a73pll";
84c4a652db1cf7 Devi Priya 2023-04-06 813 reg = <0x0b116000 0x40>;
84c4a652db1cf7 Devi Priya 2023-04-06 814 #clock-cells = <0>;
84c4a652db1cf7 Devi Priya 2023-04-06 815 clocks = <&xo_board_clk>;
84c4a652db1cf7 Devi Priya 2023-04-06 816 clock-names = "xo";
84c4a652db1cf7 Devi Priya 2023-04-06 817 };
84c4a652db1cf7 Devi Priya 2023-04-06 818
97cb36ff52a106 Devi Priya 2023-03-16 819 timer@b120000 {
97cb36ff52a106 Devi Priya 2023-03-16 820 compatible = "arm,armv7-timer-mem";
97cb36ff52a106 Devi Priya 2023-03-16 821 reg = <0x0b120000 0x1000>;
97cb36ff52a106 Devi Priya 2023-03-16 822 #address-cells = <1>;
97cb36ff52a106 Devi Priya 2023-03-16 823 #size-cells = <1>;
97cb36ff52a106 Devi Priya 2023-03-16 824 ranges;
97cb36ff52a106 Devi Priya 2023-03-16 825
97cb36ff52a106 Devi Priya 2023-03-16 826 frame@b120000 {
97cb36ff52a106 Devi Priya 2023-03-16 827 reg = <0x0b121000 0x1000>,
97cb36ff52a106 Devi Priya 2023-03-16 828 <0x0b122000 0x1000>;
97cb36ff52a106 Devi Priya 2023-03-16 829 frame-number = <0>;
97cb36ff52a106 Devi Priya 2023-03-16 830 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
97cb36ff52a106 Devi Priya 2023-03-16 831 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
97cb36ff52a106 Devi Priya 2023-03-16 832 };
97cb36ff52a106 Devi Priya 2023-03-16 833
97cb36ff52a106 Devi Priya 2023-03-16 834 frame@b123000 {
97cb36ff52a106 Devi Priya 2023-03-16 835 reg = <0x0b123000 0x1000>;
97cb36ff52a106 Devi Priya 2023-03-16 836 frame-number = <1>;
97cb36ff52a106 Devi Priya 2023-03-16 837 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
97cb36ff52a106 Devi Priya 2023-03-16 838 status = "disabled";
97cb36ff52a106 Devi Priya 2023-03-16 839 };
97cb36ff52a106 Devi Priya 2023-03-16 840
97cb36ff52a106 Devi Priya 2023-03-16 841 frame@b124000 {
97cb36ff52a106 Devi Priya 2023-03-16 842 reg = <0x0b124000 0x1000>;
97cb36ff52a106 Devi Priya 2023-03-16 843 frame-number = <2>;
97cb36ff52a106 Devi Priya 2023-03-16 844 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
97cb36ff52a106 Devi Priya 2023-03-16 845 status = "disabled";
97cb36ff52a106 Devi Priya 2023-03-16 846 };
97cb36ff52a106 Devi Priya 2023-03-16 847
97cb36ff52a106 Devi Priya 2023-03-16 848 frame@b125000 {
97cb36ff52a106 Devi Priya 2023-03-16 849 reg = <0x0b125000 0x1000>;
97cb36ff52a106 Devi Priya 2023-03-16 850 frame-number = <3>;
97cb36ff52a106 Devi Priya 2023-03-16 851 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
97cb36ff52a106 Devi Priya 2023-03-16 852 status = "disabled";
97cb36ff52a106 Devi Priya 2023-03-16 853 };
97cb36ff52a106 Devi Priya 2023-03-16 854
97cb36ff52a106 Devi Priya 2023-03-16 855 frame@b126000 {
97cb36ff52a106 Devi Priya 2023-03-16 856 reg = <0x0b126000 0x1000>;
97cb36ff52a106 Devi Priya 2023-03-16 857 frame-number = <4>;
97cb36ff52a106 Devi Priya 2023-03-16 858 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
97cb36ff52a106 Devi Priya 2023-03-16 859 status = "disabled";
97cb36ff52a106 Devi Priya 2023-03-16 860 };
97cb36ff52a106 Devi Priya 2023-03-16 861
97cb36ff52a106 Devi Priya 2023-03-16 862 frame@b127000 {
97cb36ff52a106 Devi Priya 2023-03-16 863 reg = <0x0b127000 0x1000>;
97cb36ff52a106 Devi Priya 2023-03-16 864 frame-number = <5>;
97cb36ff52a106 Devi Priya 2023-03-16 865 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
97cb36ff52a106 Devi Priya 2023-03-16 866 status = "disabled";
97cb36ff52a106 Devi Priya 2023-03-16 867 };
97cb36ff52a106 Devi Priya 2023-03-16 868
97cb36ff52a106 Devi Priya 2023-03-16 869 frame@b128000 {
97cb36ff52a106 Devi Priya 2023-03-16 870 reg = <0x0b128000 0x1000>;
97cb36ff52a106 Devi Priya 2023-03-16 871 frame-number = <6>;
97cb36ff52a106 Devi Priya 2023-03-16 872 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
97cb36ff52a106 Devi Priya 2023-03-16 873 status = "disabled";
97cb36ff52a106 Devi Priya 2023-03-16 874 };
97cb36ff52a106 Devi Priya 2023-03-16 875 };
d80c7fbfa908e3 devi priya 2024-08-01 876
d80c7fbfa908e3 devi priya 2024-08-01 @877 pcie1: pcie@10000000 {
d80c7fbfa908e3 devi priya 2024-08-01 878 compatible = "qcom,pcie-ipq9574";
e124af76347ee3 Varadarajan Narayanan 2025-01-22 879 reg = <0x000f8000 0x4000>,
e124af76347ee3 Varadarajan Narayanan 2025-01-22 880 <0x10000000 0xf1d>,
d80c7fbfa908e3 devi priya 2024-08-01 881 <0x10000f20 0xa8>,
d80c7fbfa908e3 devi priya 2024-08-01 882 <0x10001000 0x1000>,
d80c7fbfa908e3 devi priya 2024-08-01 883 <0x10100000 0x1000>;
e124af76347ee3 Varadarajan Narayanan 2025-01-22 884 reg-names = "parf",
e124af76347ee3 Varadarajan Narayanan 2025-01-22 885 "dbi",
e124af76347ee3 Varadarajan Narayanan 2025-01-22 886 "elbi",
e124af76347ee3 Varadarajan Narayanan 2025-01-22 887 "atu",
e124af76347ee3 Varadarajan Narayanan 2025-01-22 888 "config";
d80c7fbfa908e3 devi priya 2024-08-01 889 device_type = "pci";
d80c7fbfa908e3 devi priya 2024-08-01 890 linux,pci-domain = <1>;
d80c7fbfa908e3 devi priya 2024-08-01 891 bus-range = <0x00 0xff>;
d80c7fbfa908e3 devi priya 2024-08-01 892 num-lanes = <1>;
d80c7fbfa908e3 devi priya 2024-08-01 893 #address-cells = <3>;
d80c7fbfa908e3 devi priya 2024-08-01 894 #size-cells = <2>;
d80c7fbfa908e3 devi priya 2024-08-01 895
d80c7fbfa908e3 devi priya 2024-08-01 896 ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>,
d80c7fbfa908e3 devi priya 2024-08-01 897 <0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>;
d80c7fbfa908e3 devi priya 2024-08-01 898
d80c7fbfa908e3 devi priya 2024-08-01 899 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
d80c7fbfa908e3 devi priya 2024-08-01 900 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
d80c7fbfa908e3 devi priya 2024-08-01 901 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
d80c7fbfa908e3 devi priya 2024-08-01 902 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
d80c7fbfa908e3 devi priya 2024-08-01 903 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
d80c7fbfa908e3 devi priya 2024-08-01 904 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
d80c7fbfa908e3 devi priya 2024-08-01 905 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
d80c7fbfa908e3 devi priya 2024-08-01 906 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
d80c7fbfa908e3 devi priya 2024-08-01 907 interrupt-names = "msi0",
d80c7fbfa908e3 devi priya 2024-08-01 908 "msi1",
d80c7fbfa908e3 devi priya 2024-08-01 909 "msi2",
d80c7fbfa908e3 devi priya 2024-08-01 910 "msi3",
d80c7fbfa908e3 devi priya 2024-08-01 911 "msi4",
d80c7fbfa908e3 devi priya 2024-08-01 912 "msi5",
d80c7fbfa908e3 devi priya 2024-08-01 913 "msi6",
d80c7fbfa908e3 devi priya 2024-08-01 914 "msi7";
d80c7fbfa908e3 devi priya 2024-08-01 915
d80c7fbfa908e3 devi priya 2024-08-01 916 #interrupt-cells = <1>;
d80c7fbfa908e3 devi priya 2024-08-01 917 interrupt-map-mask = <0 0 0 0x7>;
d80c7fbfa908e3 devi priya 2024-08-01 918 interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
d80c7fbfa908e3 devi priya 2024-08-01 919 <0 0 0 2 &intc 0 0 49 IRQ_TYPE_LEVEL_HIGH>,
d80c7fbfa908e3 devi priya 2024-08-01 920 <0 0 0 3 &intc 0 0 84 IRQ_TYPE_LEVEL_HIGH>,
d80c7fbfa908e3 devi priya 2024-08-01 921 <0 0 0 4 &intc 0 0 85 IRQ_TYPE_LEVEL_HIGH>;
d80c7fbfa908e3 devi priya 2024-08-01 922
d80c7fbfa908e3 devi priya 2024-08-01 923 clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
d80c7fbfa908e3 devi priya 2024-08-01 924 <&gcc GCC_PCIE1_AXI_S_CLK>,
d80c7fbfa908e3 devi priya 2024-08-01 925 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
d80c7fbfa908e3 devi priya 2024-08-01 926 <&gcc GCC_PCIE1_RCHNG_CLK>,
d80c7fbfa908e3 devi priya 2024-08-01 927 <&gcc GCC_PCIE1_AHB_CLK>,
d80c7fbfa908e3 devi priya 2024-08-01 928 <&gcc GCC_PCIE1_AUX_CLK>;
d80c7fbfa908e3 devi priya 2024-08-01 929 clock-names = "axi_m",
d80c7fbfa908e3 devi priya 2024-08-01 930 "axi_s",
d80c7fbfa908e3 devi priya 2024-08-01 931 "axi_bridge",
d80c7fbfa908e3 devi priya 2024-08-01 932 "rchng",
d80c7fbfa908e3 devi priya 2024-08-01 933 "ahb",
d80c7fbfa908e3 devi priya 2024-08-01 934 "aux";
d80c7fbfa908e3 devi priya 2024-08-01 935
d80c7fbfa908e3 devi priya 2024-08-01 936 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
d80c7fbfa908e3 devi priya 2024-08-01 937 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
d80c7fbfa908e3 devi priya 2024-08-01 938 <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>,
d80c7fbfa908e3 devi priya 2024-08-01 939 <&gcc GCC_PCIE1_AXI_S_ARES>,
d80c7fbfa908e3 devi priya 2024-08-01 940 <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>,
d80c7fbfa908e3 devi priya 2024-08-01 941 <&gcc GCC_PCIE1_AXI_M_ARES>,
d80c7fbfa908e3 devi priya 2024-08-01 942 <&gcc GCC_PCIE1_AUX_ARES>,
d80c7fbfa908e3 devi priya 2024-08-01 943 <&gcc GCC_PCIE1_AHB_ARES>;
d80c7fbfa908e3 devi priya 2024-08-01 944 reset-names = "pipe",
d80c7fbfa908e3 devi priya 2024-08-01 945 "sticky",
d80c7fbfa908e3 devi priya 2024-08-01 946 "axi_s_sticky",
d80c7fbfa908e3 devi priya 2024-08-01 947 "axi_s",
d80c7fbfa908e3 devi priya 2024-08-01 948 "axi_m_sticky",
d80c7fbfa908e3 devi priya 2024-08-01 949 "axi_m",
d80c7fbfa908e3 devi priya 2024-08-01 950 "aux",
d80c7fbfa908e3 devi priya 2024-08-01 951 "ahb";
d80c7fbfa908e3 devi priya 2024-08-01 952
d80c7fbfa908e3 devi priya 2024-08-01 953 phys = <&pcie1_phy>;
d80c7fbfa908e3 devi priya 2024-08-01 954 phy-names = "pciephy";
d80c7fbfa908e3 devi priya 2024-08-01 955 interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
d80c7fbfa908e3 devi priya 2024-08-01 956 <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>;
d80c7fbfa908e3 devi priya 2024-08-01 957 interconnect-names = "pcie-mem", "cpu-pcie";
d80c7fbfa908e3 devi priya 2024-08-01 958 status = "disabled";
d80c7fbfa908e3 devi priya 2024-08-01 959 };
d80c7fbfa908e3 devi priya 2024-08-01 960
d80c7fbfa908e3 devi priya 2024-08-01 @961 pcie3: pcie@18000000 {
d80c7fbfa908e3 devi priya 2024-08-01 962 compatible = "qcom,pcie-ipq9574";
e124af76347ee3 Varadarajan Narayanan 2025-01-22 963 reg = <0x000f0000 0x4000>,
e124af76347ee3 Varadarajan Narayanan 2025-01-22 964 <0x18000000 0xf1d>,
d80c7fbfa908e3 devi priya 2024-08-01 965 <0x18000f20 0xa8>,
d80c7fbfa908e3 devi priya 2024-08-01 966 <0x18001000 0x1000>,
d80c7fbfa908e3 devi priya 2024-08-01 967 <0x18100000 0x1000>;
e124af76347ee3 Varadarajan Narayanan 2025-01-22 968 reg-names = "parf",
e124af76347ee3 Varadarajan Narayanan 2025-01-22 969 "dbi",
e124af76347ee3 Varadarajan Narayanan 2025-01-22 970 "elbi",
e124af76347ee3 Varadarajan Narayanan 2025-01-22 971 "atu",
e124af76347ee3 Varadarajan Narayanan 2025-01-22 972 "config";
d80c7fbfa908e3 devi priya 2024-08-01 973 device_type = "pci";
d80c7fbfa908e3 devi priya 2024-08-01 974 linux,pci-domain = <3>;
d80c7fbfa908e3 devi priya 2024-08-01 975 bus-range = <0x00 0xff>;
d80c7fbfa908e3 devi priya 2024-08-01 976 num-lanes = <2>;
d80c7fbfa908e3 devi priya 2024-08-01 977 #address-cells = <3>;
d80c7fbfa908e3 devi priya 2024-08-01 978 #size-cells = <2>;
d80c7fbfa908e3 devi priya 2024-08-01 979
d80c7fbfa908e3 devi priya 2024-08-01 980 ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>,
d80c7fbfa908e3 devi priya 2024-08-01 981 <0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>;
d80c7fbfa908e3 devi priya 2024-08-01 982
d80c7fbfa908e3 devi priya 2024-08-01 983 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
d80c7fbfa908e3 devi priya 2024-08-01 984 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
d80c7fbfa908e3 devi priya 2024-08-01 985 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
d80c7fbfa908e3 devi priya 2024-08-01 986 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
d80c7fbfa908e3 devi priya 2024-08-01 987 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
d80c7fbfa908e3 devi priya 2024-08-01 988 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
d80c7fbfa908e3 devi priya 2024-08-01 989 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
d80c7fbfa908e3 devi priya 2024-08-01 990 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
d80c7fbfa908e3 devi priya 2024-08-01 991 interrupt-names = "msi0",
d80c7fbfa908e3 devi priya 2024-08-01 992 "msi1",
d80c7fbfa908e3 devi priya 2024-08-01 993 "msi2",
d80c7fbfa908e3 devi priya 2024-08-01 994 "msi3",
d80c7fbfa908e3 devi priya 2024-08-01 995 "msi4",
d80c7fbfa908e3 devi priya 2024-08-01 996 "msi5",
d80c7fbfa908e3 devi priya 2024-08-01 997 "msi6",
d80c7fbfa908e3 devi priya 2024-08-01 998 "msi7";
d80c7fbfa908e3 devi priya 2024-08-01 999
d80c7fbfa908e3 devi priya 2024-08-01 1000 #interrupt-cells = <1>;
d80c7fbfa908e3 devi priya 2024-08-01 1001 interrupt-map-mask = <0 0 0 0x7>;
d80c7fbfa908e3 devi priya 2024-08-01 1002 interrupt-map = <0 0 0 1 &intc 0 0 189 IRQ_TYPE_LEVEL_HIGH>,
d80c7fbfa908e3 devi priya 2024-08-01 1003 <0 0 0 2 &intc 0 0 190 IRQ_TYPE_LEVEL_HIGH>,
d80c7fbfa908e3 devi priya 2024-08-01 1004 <0 0 0 3 &intc 0 0 191 IRQ_TYPE_LEVEL_HIGH>,
d80c7fbfa908e3 devi priya 2024-08-01 1005 <0 0 0 4 &intc 0 0 192 IRQ_TYPE_LEVEL_HIGH>;
d80c7fbfa908e3 devi priya 2024-08-01 1006
d80c7fbfa908e3 devi priya 2024-08-01 1007 clocks = <&gcc GCC_PCIE3_AXI_M_CLK>,
d80c7fbfa908e3 devi priya 2024-08-01 1008 <&gcc GCC_PCIE3_AXI_S_CLK>,
d80c7fbfa908e3 devi priya 2024-08-01 1009 <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>,
d80c7fbfa908e3 devi priya 2024-08-01 1010 <&gcc GCC_PCIE3_RCHNG_CLK>,
d80c7fbfa908e3 devi priya 2024-08-01 1011 <&gcc GCC_PCIE3_AHB_CLK>,
d80c7fbfa908e3 devi priya 2024-08-01 1012 <&gcc GCC_PCIE3_AUX_CLK>;
d80c7fbfa908e3 devi priya 2024-08-01 1013 clock-names = "axi_m",
d80c7fbfa908e3 devi priya 2024-08-01 1014 "axi_s",
d80c7fbfa908e3 devi priya 2024-08-01 1015 "axi_bridge",
d80c7fbfa908e3 devi priya 2024-08-01 1016 "rchng",
d80c7fbfa908e3 devi priya 2024-08-01 1017 "ahb",
d80c7fbfa908e3 devi priya 2024-08-01 1018 "aux";
d80c7fbfa908e3 devi priya 2024-08-01 1019
d80c7fbfa908e3 devi priya 2024-08-01 1020 resets = <&gcc GCC_PCIE3_PIPE_ARES>,
d80c7fbfa908e3 devi priya 2024-08-01 1021 <&gcc GCC_PCIE3_CORE_STICKY_ARES>,
d80c7fbfa908e3 devi priya 2024-08-01 1022 <&gcc GCC_PCIE3_AXI_S_STICKY_ARES>,
d80c7fbfa908e3 devi priya 2024-08-01 1023 <&gcc GCC_PCIE3_AXI_S_ARES>,
d80c7fbfa908e3 devi priya 2024-08-01 1024 <&gcc GCC_PCIE3_AXI_M_STICKY_ARES>,
d80c7fbfa908e3 devi priya 2024-08-01 1025 <&gcc GCC_PCIE3_AXI_M_ARES>,
d80c7fbfa908e3 devi priya 2024-08-01 1026 <&gcc GCC_PCIE3_AUX_ARES>,
d80c7fbfa908e3 devi priya 2024-08-01 1027 <&gcc GCC_PCIE3_AHB_ARES>;
d80c7fbfa908e3 devi priya 2024-08-01 1028 reset-names = "pipe",
d80c7fbfa908e3 devi priya 2024-08-01 1029 "sticky",
d80c7fbfa908e3 devi priya 2024-08-01 1030 "axi_s_sticky",
d80c7fbfa908e3 devi priya 2024-08-01 1031 "axi_s",
d80c7fbfa908e3 devi priya 2024-08-01 1032 "axi_m_sticky",
d80c7fbfa908e3 devi priya 2024-08-01 1033 "axi_m",
d80c7fbfa908e3 devi priya 2024-08-01 1034 "aux",
d80c7fbfa908e3 devi priya 2024-08-01 1035 "ahb";
d80c7fbfa908e3 devi priya 2024-08-01 1036
d80c7fbfa908e3 devi priya 2024-08-01 1037 phys = <&pcie3_phy>;
d80c7fbfa908e3 devi priya 2024-08-01 1038 phy-names = "pciephy";
d80c7fbfa908e3 devi priya 2024-08-01 1039 interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>,
d80c7fbfa908e3 devi priya 2024-08-01 1040 <&gcc MASTER_SNOC_PCIE3 &gcc SLAVE_SNOC_PCIE3>;
d80c7fbfa908e3 devi priya 2024-08-01 1041 interconnect-names = "pcie-mem", "cpu-pcie";
d80c7fbfa908e3 devi priya 2024-08-01 1042 status = "disabled";
d80c7fbfa908e3 devi priya 2024-08-01 1043 };
d80c7fbfa908e3 devi priya 2024-08-01 1044
d80c7fbfa908e3 devi priya 2024-08-01 @1045 pcie2: pcie@20000000 {
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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2025-01-22 6:34 [PATCH v7 0/7] Add PCIe support for Qualcomm IPQ5332 Varadarajan Narayanan
2025-01-22 6:34 ` Varadarajan Narayanan
2025-01-22 6:34 ` [PATCH v7 1/7] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy Varadarajan Narayanan
2025-01-22 6:34 ` Varadarajan Narayanan
2025-01-23 7:54 ` Krzysztof Kozlowski
2025-01-23 7:54 ` Krzysztof Kozlowski
2025-01-22 6:34 ` [PATCH v7 2/7] phy: qcom: Introduce PCIe UNIPHY 28LP driver Varadarajan Narayanan
2025-01-22 6:34 ` Varadarajan Narayanan
2025-01-22 6:34 ` [PATCH v7 3/7] dt-bindings: PCI: qcom: Use sdx55 reg description for ipq9574 Varadarajan Narayanan
2025-01-22 6:34 ` Varadarajan Narayanan
2025-01-23 7:55 ` Krzysztof Kozlowski
2025-01-23 7:55 ` Krzysztof Kozlowski
2025-02-03 16:16 ` Manivannan Sadhasivam
2025-02-03 16:16 ` Manivannan Sadhasivam
2025-01-22 6:34 ` [PATCH v7 4/7] arm64: dts: qcom: ipq9574: Reorder reg and reg-names Varadarajan Narayanan
2025-01-22 6:34 ` Varadarajan Narayanan
2025-01-27 10:33 ` Konrad Dybcio
2025-01-27 10:33 ` Konrad Dybcio
2025-02-03 16:27 ` Krzysztof Kozlowski
2025-02-03 16:27 ` Krzysztof Kozlowski
2025-01-22 6:34 ` [PATCH v7 5/7] dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller Varadarajan Narayanan
2025-01-22 6:34 ` Varadarajan Narayanan
2025-01-23 7:58 ` Krzysztof Kozlowski
2025-01-23 7:58 ` Krzysztof Kozlowski
2025-01-23 8:05 ` Varadarajan Narayanan
2025-01-23 8:05 ` Varadarajan Narayanan
2025-01-23 8:27 ` Krzysztof Kozlowski
2025-01-23 8:27 ` Krzysztof Kozlowski
2025-01-22 6:34 ` [PATCH v7 6/7] arm64: dts: qcom: ipq5332: Add PCIe related nodes Varadarajan Narayanan
2025-01-22 6:34 ` Varadarajan Narayanan
2025-02-03 16:26 ` Manivannan Sadhasivam
2025-02-03 16:26 ` Manivannan Sadhasivam
2025-01-22 6:34 ` [PATCH v7 7/7] arm64: dts: qcom: ipq5332-rdp441: Enable PCIe phys and controllers Varadarajan Narayanan
2025-01-22 6:34 ` Varadarajan Narayanan
2025-02-03 16:27 ` Manivannan Sadhasivam
2025-02-03 16:27 ` Manivannan Sadhasivam
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2025-01-22 22:39 [PATCH v7 4/7] arm64: dts: qcom: ipq9574: Reorder reg and reg-names kernel test robot
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