From: "Hailong Fan (范海龙)" <Hailong.Fan@mediatek.com>
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Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: Re: [PATCH v2 1/2] dt-bindings: dsp: mediatek: add mt8196 dsp document
Date: Tue, 26 Aug 2025 07:16:15 +0000 [thread overview]
Message-ID: <f8b2a2bf59eb8f6cdbc7fd80e5c2c5df7df9271e.camel@mediatek.com> (raw)
In-Reply-To: <738c1951-afbc-4cda-a16e-54a5055ca7c8@kernel.org>
On Wed, 2025-07-09 at 08:57 +0200, Krzysztof Kozlowski wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>
>
> On 09/07/2025 08:05, Hailong Fan (范海龙) wrote:
> > >
> > > OK, this is a valid argument, however we still try to unify the
> > > inputs
> > > so bindings can share such pieces. It is discouraged to have
> > > similar
> > > devices with different bindings in only one place: clk26m ->
> > > clk27m
> > > or
> > > whatever other number.
> > >
> > > Common is also to name the clock input based on the purpose (like
> > > bus, ref).
> > >
> > >
> > > Best regards,
> > > Krzysztof
> >
> > On the MediaTek platform, the main SoC clock sources are typically
> > 32K,
> > 13M, and 26M. This is why the terms clk32k, clk13m, and clk26m are
> > used.
> > Specifically, clk26m refers to the system’s 26 MHz clock source.
> > The clkxxx naming convention is intended to indicate that these are
> > SoC
>
> But it should nnot.
>
> > clock sources, while also distinguishing between different clock
> > frequencies.
> >
> > Therefore, using other terms could potentially cause confusion.
>
> No, you don't understand. This device receives some main PLL or ref
> clock. That's the only important information in the name, not its
> frequency..
>
> >
> > For example, the ADSP clock sources are ADSPPLL(800MHz) and
> > clk26m(26MHz).
> > On other platforms, the definition of clk26m in the Device Tree
> > Source
> > (DTS) is as follows:
> >
> >
https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt8188.dtsi*n328__;Iw!!CTRNKA9wMg0ARbw!ibScPB89tyVolnUhBscm6gkEwMebDiD8FozTY1H_-cMZ5_klBxmJxgWlOTOhboITEls4ef4w-Tce2qs$
> > The mt8196 platform uses the same design.
>
> So you add poor code, because previously Mediatek added more poor
> code?
> What sort of argument is that?
Thank you for your suggestion. We are planning to update it to sys_clk
in the next version. What do you think?
>
>
> Best regards,
> Krzysztof
next prev parent reply other threads:[~2025-08-26 7:16 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-03 7:56 [PATCH v2 0/2] ASoC: mediatek: Add support of SOF on Mediatek mt8196 SoC hailong.fan
2025-07-03 7:56 ` [PATCH v2 1/2] dt-bindings: dsp: mediatek: add mt8196 dsp document hailong.fan
2025-07-03 8:08 ` Krzysztof Kozlowski
2025-07-03 9:05 ` AngeloGioacchino Del Regno
2025-07-03 10:24 ` Krzysztof Kozlowski
2025-07-09 6:05 ` Hailong Fan (范海龙)
2025-07-09 6:57 ` Krzysztof Kozlowski
2025-08-26 7:16 ` Hailong Fan (范海龙) [this message]
2025-07-09 6:34 ` Hailong Fan (范海龙)
2025-07-09 6:59 ` Krzysztof Kozlowski
2025-08-26 7:21 ` Hailong Fan (范海龙)
2025-07-09 2:52 ` Hailong Fan (范海龙)
2025-07-09 6:55 ` Krzysztof Kozlowski
2025-08-26 7:23 ` Hailong Fan (范海龙)
2025-07-03 10:19 ` Rob Herring (Arm)
2025-07-03 7:56 ` [PATCH v2 2/2] ASoC: SOF: MediaTek: Add mt8196 hardware support hailong.fan
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