From: schwab@suse.de (Andreas Schwab)
To: linux-riscv@lists.infradead.org
Subject: [PATCH 5/5] RISC-V: Use fixed width integer types for 32-bit compatible
Date: Thu, 21 Jun 2018 12:21:19 +0200 [thread overview]
Message-ID: <mvmwousjv8g.fsf@suse.de> (raw)
In-Reply-To: <20180621064322.GE19319@infradead.org> (Christoph Hellwig's message of "Wed, 20 Jun 2018 23:43:22 -0700")
On Jun 20 2018, Christoph Hellwig <hch@infradead.org> wrote:
>> static int apply_r_riscv_32_rela(struct module *me, u32 *location, Elf_Addr v)
>> {
>> if (v != (u32)v) {
>> - pr_err("%s: value %016llx out of range for 32-bit field\n",
>> + pr_err("%s: value %016" PRIxX "out of range for 32-bit field\n",
>> me->name, v);
>> return -EINVAL;
>
> But in general Linux uXX and sXX values are always the same underlying
> fundamental C type. What is the mismatch here?
The mismatch is that v is Elf_Addr, not u32.
Andreas.
--
Andreas Schwab, SUSE Labs, schwab at suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."
WARNING: multiple messages have this Message-ID (diff)
From: Andreas Schwab <schwab@suse.de>
To: Christoph Hellwig <hch@infradead.org>
Cc: Zong Li <zong@andestech.com>,
palmer@sifive.com, aou@eecs.berkeley.edu,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
greentime@adnestech.com
Subject: Re: [PATCH 5/5] RISC-V: Use fixed width integer types for 32-bit compatible
Date: Thu, 21 Jun 2018 12:21:19 +0200 [thread overview]
Message-ID: <mvmwousjv8g.fsf@suse.de> (raw)
In-Reply-To: <20180621064322.GE19319@infradead.org> (Christoph Hellwig's message of "Wed, 20 Jun 2018 23:43:22 -0700")
On Jun 20 2018, Christoph Hellwig <hch@infradead.org> wrote:
>> static int apply_r_riscv_32_rela(struct module *me, u32 *location, Elf_Addr v)
>> {
>> if (v != (u32)v) {
>> - pr_err("%s: value %016llx out of range for 32-bit field\n",
>> + pr_err("%s: value %016" PRIxX "out of range for 32-bit field\n",
>> me->name, v);
>> return -EINVAL;
>
> But in general Linux uXX and sXX values are always the same underlying
> fundamental C type. What is the mismatch here?
The mismatch is that v is Elf_Addr, not u32.
Andreas.
--
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."
next prev parent reply other threads:[~2018-06-21 10:21 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-21 1:41 [PATCH 0/5] Building for 32-bit RISC-V kernel Zong Li
2018-06-21 1:41 ` Zong Li
2018-06-21 1:41 ` [PATCH 1/5] RISC-V: Add conditional macro for zone of DMA32 Zong Li
2018-06-21 1:41 ` Zong Li
2018-06-21 6:40 ` Christoph Hellwig
2018-06-21 6:40 ` Christoph Hellwig
2018-06-21 7:06 ` Zong Li
2018-06-21 7:06 ` Zong Li
2018-06-21 1:41 ` [PATCH] RISC-V: Add conditional marco for boot_sec_cpu Zong Li
2018-06-21 1:41 ` Zong Li
2018-06-21 1:41 ` [PATCH 2/5] RISC-V: Select GENERIC_UCMPDI2 on RV32I Zong Li
2018-06-21 1:41 ` Zong Li
2018-06-21 1:41 ` [PATCH 3/5] RISC-V: Add definiion of extract symbol's index and type for 32-bit Zong Li
2018-06-21 1:41 ` Zong Li
2018-06-21 1:41 ` [PATCH 4/5] RISC-V: Change variable type for 32-bit compatible Zong Li
2018-06-21 1:41 ` Zong Li
2018-06-21 6:41 ` Christoph Hellwig
2018-06-21 6:41 ` Christoph Hellwig
2018-06-21 7:12 ` Zong Li
2018-06-21 7:12 ` Zong Li
2018-06-21 15:19 ` Zong Li
2018-06-21 15:19 ` Zong Li
2018-06-21 1:41 ` [PATCH 5/5] RISC-V: Use fixed width integer types " Zong Li
2018-06-21 1:41 ` Zong Li
2018-06-21 6:43 ` Christoph Hellwig
2018-06-21 6:43 ` Christoph Hellwig
2018-06-21 10:13 ` Zong Li
2018-06-21 10:13 ` Zong Li
2018-06-21 10:21 ` Andreas Schwab [this message]
2018-06-21 10:21 ` Andreas Schwab
2018-06-21 14:53 ` Christoph Hellwig
2018-06-21 14:53 ` Christoph Hellwig
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