* Re: [PATCH v6 2/2] media: Add a driver for the ov5645 camera sensor.
From: Mark Brown @ 2016-11-14 13:46 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Todor Tomov, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
galak, mchehab, hverkuil, geert, matrandg, sakari.ailus,
linux-media
In-Reply-To: <7012441.uVkdQjEznh@avalon>
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On Mon, Nov 14, 2016 at 02:18:49PM +0200, Laurent Pinchart wrote:
> On Wednesday 26 Oct 2016 12:51:49 Mark Brown wrote:
> > Why would this be guaranteed by the API given that it's not documented
> > and why would many drivers break? It's fairly rare for devices other
> > than SoCs to have strict power on sequencing requirements as it is hard
> > to achieve in practical systems.
> Is there a reason why the API shouldn't guarantee that regulators are powered
> on in the order listed, and powered off in the reverse order ? Looking at the
If it ever even did that through implementation it's not been true for a
very long time - it does the regulator enables in parallel in order to
reduce the overall time to power things up. I keep wanting to come up
with code to figure out if we're using multiple enable bits in a single
register and hit them all at once though it's likely to be more trouble
than it's worth.
> implementation that's already the case for regulator_bulk_disable(), but
> regulator_bulk_enable() uses async scheduling so doesn't guarantee ordering. I
> wonder whether a synchronous version of regulator_bulk_enable() would be
> useful.
*Possibly* but I'd be surprised to learn that there's a substantial
amount of hardware out there that cares given that a power on reset
circuit isn't exactly complex to implement. You do sometimes see a
global rail that should come up first (especially if there is an
integrated regulator) but I've not seen many cases where the hardware
cared outside of SoCs.
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^ permalink raw reply
* [PATCH v4 2/2] Add support for OV5647 sensor
From: Ramiro Oliveira @ 2016-11-14 13:46 UTC (permalink / raw)
To: mchehab, linux-kernel, linux-media, robh+dt, devicetree
Cc: davem, gregkh, geert+renesas, akpm, linux, hverkuil, dheitmueller,
slongerbeam, lars, robert.jarzmik, pavel, pali.rohar,
sakari.ailus, mark.rutland, Ramiro.Oliveira, CARLOS.PALMINHA
In-Reply-To: <cover.1479129004.git.roliveir@synopsys.com>
Add support for OV5647 sensor.
Modes supported:
- 640x480 RAW 8
Signed-off-by: Ramiro Oliveira <roliveir@synopsys.com>
---
MAINTAINERS | 7 +
drivers/media/i2c/Kconfig | 12 +
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/ov5647.c | 861 +++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 881 insertions(+)
create mode 100644 drivers/media/i2c/ov5647.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 93e9f42..6a71422 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8895,6 +8895,13 @@ M: Harald Welte <laforge@gnumonks.org>
S: Maintained
F: drivers/char/pcmcia/cm4040_cs.*
+OMNIVISION OV5647 SENSOR DRIVER
+M: Ramiro Oliveira <roliveir@synopsys.com>
+L: linux-media@vger.kernel.org
+T: git git://linuxtv.org/media_tree.git
+S: Maintained
+F: drivers/media/i2c/ov5647.c
+
OMNIVISION OV7670 SENSOR DRIVER
M: Jonathan Corbet <corbet@lwn.net>
L: linux-media@vger.kernel.org
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index 2669b4b..4237165 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -531,6 +531,18 @@ config VIDEO_OV2659
To compile this driver as a module, choose M here: the
module will be called ov2659.
+config VIDEO_OV5647
+ tristate "OmniVision OV5647 sensor support"
+ depends on OF
+ depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
+ depends on MEDIA_CAMERA_SUPPORT
+ ---help---
+ This is a Video4Linux2 sensor-level driver for the OmniVision
+ OV5647 camera.
+
+ To compile this driver as a module, choose M here: the
+ module will be called ov5647.
+
config VIDEO_OV7640
tristate "OmniVision OV7640 sensor support"
depends on I2C && VIDEO_V4L2
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index 92773b2..0d9014c 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -82,3 +82,4 @@ obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o
obj-$(CONFIG_VIDEO_ML86V7667) += ml86v7667.o
obj-$(CONFIG_VIDEO_OV2659) += ov2659.o
obj-$(CONFIG_VIDEO_TC358743) += tc358743.o
+obj-$(CONFIG_VIDEO_OV5647) += ov5647.o
diff --git a/drivers/media/i2c/ov5647.c b/drivers/media/i2c/ov5647.c
new file mode 100644
index 0000000..0b3b4f2
--- /dev/null
+++ b/drivers/media/i2c/ov5647.c
@@ -0,0 +1,861 @@
+/*
+ * A V4L2 driver for OmniVision OV5647 cameras.
+ *
+ * Based on Samsung S5K6AAFX SXGA 1/6" 1.3M CMOS Image Sensor driver
+ * Copyright (C) 2011 Sylwester Nawrocki <s.nawrocki@samsung.com>
+ *
+ * Based on Omnivision OV7670 Camera Driver
+ * Copyright (C) 2006-7 Jonathan Corbet <corbet@lwn.net>
+ *
+ * Copyright (C) 2016, Synopsys, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed .as is. WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/videodev2.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-mediabus.h>
+#include <media/v4l2-image-sizes.h>
+#include <media/v4l2-of.h>
+#include <linux/io.h>
+
+#define SENSOR_NAME "ov5647"
+
+#define OV5647_SW_RESET 0x1003
+#define OV5647_REG_CHIPID_H 0x300A
+#define OV5647_REG_CHIPID_L 0x300B
+
+#define REG_TERM 0xfffe
+#define VAL_TERM 0xfe
+#define REG_DLY 0xffff
+
+#define OV5647_ROW_START 0x01
+#define OV5647_ROW_START_MIN 0
+#define OV5647_ROW_START_MAX 2004
+#define OV5647_ROW_START_DEF 54
+
+#define OV5647_COLUMN_START 0x02
+#define OV5647_COLUMN_START_MIN 0
+#define OV5647_COLUMN_START_MAX 2750
+#define OV5647_COLUMN_START_DEF 16
+
+#define OV5647_WINDOW_HEIGHT 0x03
+#define OV5647_WINDOW_HEIGHT_MIN 2
+#define OV5647_WINDOW_HEIGHT_MAX 2006
+#define OV5647_WINDOW_HEIGHT_DEF 1944
+
+#define OV5647_WINDOW_WIDTH 0x04
+#define OV5647_WINDOW_WIDTH_MIN 2
+#define OV5647_WINDOW_WIDTH_MAX 2752
+#define OV5647_WINDOW_WIDTH_DEF 2592
+
+struct regval_list {
+ u16 addr;
+ u8 data;
+};
+
+struct cfg_array {
+ struct regval_list *regs;
+ int size;
+};
+
+struct sensor_win_size {
+ int width;
+ int height;
+ unsigned int hoffset;
+ unsigned int voffset;
+ unsigned int hts;
+ unsigned int vts;
+ unsigned int pclk;
+ unsigned int mipi_bps;
+ unsigned int fps_fixed;
+ unsigned int bin_factor;
+ unsigned int intg_min;
+ unsigned int intg_max;
+ void *regs;
+ int regs_size;
+ int (*set_size)(struct v4l2_subdev *sd);
+};
+
+
+struct ov5647 {
+ struct device *dev;
+ struct v4l2_subdev sd;
+ struct media_pad pad;
+ struct mutex lock;
+ struct v4l2_mbus_framefmt format;
+ struct sensor_format_struct *fmt;
+ unsigned int width;
+ unsigned int height;
+ unsigned int capture_mode;
+ int hue;
+ struct v4l2_fract tpf;
+ struct sensor_win_size *current_wins;
+};
+
+static inline struct ov5647 *to_state(struct v4l2_subdev *sd)
+{
+ return container_of(sd, struct ov5647, sd);
+}
+
+static struct regval_list sensor_oe_disable_regs[] = {
+ {0x3000, 0x00},
+ {0x3001, 0x00},
+ {0x3002, 0x00},
+};
+
+static struct regval_list sensor_oe_enable_regs[] = {
+ {0x3000, 0x0f},
+ {0x3001, 0xff},
+ {0x3002, 0xe4},
+};
+
+static struct regval_list ov5647_640x480[] = {
+ {0x0100, 0x00},
+ {0x0103, 0x01},
+ {0x3034, 0x08},
+ {0x3035, 0x21},
+ {0x3036, 0x46},
+ {0x303c, 0x11},
+ {0x3106, 0xf5},
+ {0x3821, 0x07},
+ {0x3820, 0x41},
+ {0x3827, 0xec},
+ {0x370c, 0x0f},
+ {0x3612, 0x59},
+ {0x3618, 0x00},
+ {0x5000, 0x06},
+ {0x5001, 0x01},
+ {0x5002, 0x41},
+ {0x5003, 0x08},
+ {0x5a00, 0x08},
+ {0x3000, 0x00},
+ {0x3001, 0x00},
+ {0x3002, 0x00},
+ {0x3016, 0x08},
+ {0x3017, 0xe0},
+ {0x3018, 0x44},
+ {0x301c, 0xf8},
+ {0x301d, 0xf0},
+ {0x3a18, 0x00},
+ {0x3a19, 0xf8},
+ {0x3c01, 0x80},
+ {0x3b07, 0x0c},
+ {0x380c, 0x07},
+ {0x380d, 0x68},
+ {0x380e, 0x03},
+ {0x380f, 0xd8},
+ {0x3814, 0x31},
+ {0x3815, 0x31},
+ {0x3708, 0x64},
+ {0x3709, 0x52},
+ {0x3808, 0x02},
+ {0x3809, 0x80},
+ {0x380a, 0x01},
+ {0x380b, 0xE0},
+ {0x3801, 0x00},
+ {0x3802, 0x00},
+ {0x3803, 0x00},
+ {0x3804, 0x0a},
+ {0x3805, 0x3f},
+ {0x3806, 0x07},
+ {0x3807, 0xa1},
+ {0x3811, 0x08},
+ {0x3813, 0x02},
+ {0x3630, 0x2e},
+ {0x3632, 0xe2},
+ {0x3633, 0x23},
+ {0x3634, 0x44},
+ {0x3636, 0x06},
+ {0x3620, 0x64},
+ {0x3621, 0xe0},
+ {0x3600, 0x37},
+ {0x3704, 0xa0},
+ {0x3703, 0x5a},
+ {0x3715, 0x78},
+ {0x3717, 0x01},
+ {0x3731, 0x02},
+ {0x370b, 0x60},
+ {0x3705, 0x1a},
+ {0x3f05, 0x02},
+ {0x3f06, 0x10},
+ {0x3f01, 0x0a},
+ {0x3a08, 0x01},
+ {0x3a09, 0x27},
+ {0x3a0a, 0x00},
+ {0x3a0b, 0xf6},
+ {0x3a0d, 0x04},
+ {0x3a0e, 0x03},
+ {0x3a0f, 0x58},
+ {0x3a10, 0x50},
+ {0x3a1b, 0x58},
+ {0x3a1e, 0x50},
+ {0x3a11, 0x60},
+ {0x3a1f, 0x28},
+ {0x4001, 0x02},
+ {0x4004, 0x02},
+ {0x4000, 0x09},
+ {0x4837, 0x24},
+ {0x4050, 0x6e},
+ {0x4051, 0x8f},
+ {0x0100, 0x01},
+};
+
+struct sensor_format_struct;
+
+/**
+ * @short I2C Write operation
+ * @param[in] i2c_client I2C client
+ * @param[in] reg register address
+ * @param[in] val value to write
+ * @return Error code
+ */
+static int ov5647_write(struct v4l2_subdev *sd, u16 reg, u8 val)
+{
+ int ret;
+ unsigned char data[3] = { reg >> 8, reg & 0xff, val};
+ struct i2c_client *client = v4l2_get_subdevdata(sd);
+
+ ret = i2c_master_send(client, data, 3);
+ if (ret != 3) {
+ dev_dbg(&client->dev, "%s: i2c write error, reg: %x\n",
+ __func__, reg);
+ return ret < 0 ? ret : -EIO;
+ }
+ return 0;
+}
+
+/**
+ * @short I2C Read operation
+ * @param[in] i2c_client I2C client
+ * @param[in] reg register address
+ * @param[out] val value read
+ * @return Error code
+ */
+static int ov5647_read(struct v4l2_subdev *sd, u16 reg, u8 *val)
+{
+ int ret;
+ unsigned char data_w[2] = { reg >> 8, reg & 0xff };
+ struct i2c_client *client = v4l2_get_subdevdata(sd);
+
+
+ ret = i2c_master_send(client, data_w, 2);
+
+ if (ret < 2) {
+ dev_dbg(&client->dev, "%s: i2c read error, reg: %x\n",
+ __func__, reg);
+ return ret < 0 ? ret : -EIO;
+ }
+
+
+ ret = i2c_master_recv(client, val, 1);
+
+ if (ret < 1) {
+ dev_dbg(&client->dev, "%s: i2c read error, reg: %x\n",
+ __func__, reg);
+ return ret < 0 ? ret : -EIO;
+ }
+ return 0;
+}
+
+static int ov5647_write_array(struct v4l2_subdev *sd,
+ struct regval_list *regs, int array_size)
+{
+ int i = 0;
+ int ret = 0;
+
+ if (!regs)
+ return -EINVAL;
+
+ while (i < array_size) {
+ ret = ov5647_write(sd, regs->addr, regs->data);
+ if (ret < 0)
+ return ret;
+ i++;
+ regs++;
+ }
+ return 0;
+}
+
+static void ov5647_set_virtual_channel(struct v4l2_subdev *sd, int channel)
+{
+ u8 channel_id;
+
+ ov5647_read(sd, 0x4814, &channel_id);
+ channel_id &= ~(3 << 6);
+ ov5647_write(sd, 0x4814, channel_id | (channel << 6));
+}
+
+void ov5647_stream_on(struct v4l2_subdev *sd)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(sd);
+
+ ov5647_write(sd, 0x4202, 0x00);
+ dev_dbg(&client->dev, "Stream on");
+ ov5647_write(sd, 0x300D, 0x00);
+}
+
+void ov5647_stream_off(struct v4l2_subdev *sd)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(sd);
+
+ ov5647_write(sd, 0x4202, 0x0f);
+ dev_dbg(&client->dev, "Stream off");
+ ov5647_write(sd, 0x300D, 0x01);
+}
+
+/****************************************************************************/
+
+/**
+ * @short Set SW standby
+ * @param[in] sd v4l2 sd
+ * @param[in] stanby standby mode status (on or off)
+ * @return Error code
+ */
+static int set_sw_standby(struct v4l2_subdev *sd, bool standby)
+{
+ int ret;
+ unsigned char rdval;
+
+ ret = ov5647_read(sd, 0x0100, &rdval);
+ if (ret != 0)
+ return ret;
+
+ if (standby)
+ ret = ov5647_write(sd, 0x0100, rdval&0xfe);
+ else
+ ret = ov5647_write(sd, 0x0100, rdval|0x01);
+
+ return ret;
+}
+
+/**
+ * @short Store information about the video data format.
+ */
+static struct sensor_format_struct {
+ __u8 *desc;
+ u32 mbus_code;
+ struct regval_list *regs;
+ int regs_size;
+ int bpp;
+} sensor_formats[] = {
+ {
+ .desc = "Raw RGB Bayer",
+ .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
+ .regs = ov5647_640x480,
+ .regs_size = ARRAY_SIZE(ov5647_640x480),
+ .bpp = 1
+ },
+};
+#define N_FMTS ARRAY_SIZE(sensor_formats)
+
+/* ----------------------------------------------------------------------- */
+
+/**
+ * @short Initialize sensor
+ * @param[in] sd v4l2 subdev
+ * @param[in] val not used
+ * @return Error code
+ */
+static int __sensor_init(struct v4l2_subdev *sd)
+{
+ int ret;
+ u8 resetval;
+ u8 rdval;
+ struct i2c_client *client = v4l2_get_subdevdata(sd);
+
+ dev_dbg(&client->dev, "sensor init\n");
+
+ ret = ov5647_read(sd, 0x0100, &rdval);
+ if (ret != 0)
+ return ret;
+
+ ov5647_write(sd, 0x4800, 0x25);
+ ov5647_stream_off(sd);
+
+ ret = ov5647_write_array(sd, ov5647_640x480,
+ ARRAY_SIZE(ov5647_640x480));
+ if (ret < 0) {
+ dev_err(&client->dev, "write sensor_default_regs error\n");
+ return ret;
+ }
+
+ ov5647_set_virtual_channel(sd, 0);
+
+ ov5647_read(sd, 0x0100, &resetval);
+ if (!resetval&0x01) {
+ dev_err(&client->dev, "Device was in SW standby");
+ ov5647_write(sd, 0x0100, 0x01);
+ }
+
+ ov5647_write(sd, 0x4800, 0x04);
+ ov5647_stream_on(sd);
+
+ return 0;
+}
+
+/**
+ * @short Control sensor power state
+ * @param[in] sd v4l2 subdev
+ * @param[in] on Sensor power
+ * @return Error code
+ */
+static int sensor_power(struct v4l2_subdev *sd, int on)
+{
+ int ret;
+ struct ov5647 *ov5647 = to_state(sd);
+ struct i2c_client *client = v4l2_get_subdevdata(sd);
+
+ ret = 0;
+ mutex_lock(&ov5647->lock);
+
+ if (on) {
+ dev_dbg(&client->dev, "OV5647 power on!\n");
+
+ ret = ov5647_write_array(sd, sensor_oe_enable_regs,
+ ARRAY_SIZE(sensor_oe_enable_regs));
+
+ ret = __sensor_init(sd);
+
+ if (ret < 0)
+ dev_err(&client->dev,
+ "Camera not available! Check Power!\n");
+ } else {
+ dev_dbg(&client->dev, "OV5647 power off!\n");
+
+ dev_dbg(&client->dev, "disable oe\n");
+ ret = ov5647_write_array(sd, sensor_oe_disable_regs,
+ ARRAY_SIZE(sensor_oe_disable_regs));
+
+ if (ret < 0)
+ dev_dbg(&client->dev, "disable oe failed!\n");
+
+ ret = set_sw_standby(sd, true);
+
+ if (ret < 0)
+ dev_dbg(&client->dev, "soft stby failed!\n");
+
+ }
+
+ mutex_unlock(&ov5647->lock);
+
+ return ret;
+}
+
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+/**
+ * @short Get register value
+ * @param[in] sd v4l2 subdev
+ * @param[in] reg register struct
+ * @return Error code
+ */
+static int sensor_get_register(struct v4l2_subdev *sd,
+ struct v4l2_dbg_register *reg)
+{
+ unsigned char val = 0;
+ int ret;
+
+ ret = ov5647_read(sd, reg->reg & 0xff, &val);
+ reg->val = val;
+ reg->size = 1;
+ return ret;
+}
+
+/**
+ * @short Set register value
+ * @param[in] sd v4l2 subdev
+ * @param[in] reg register struct
+ * @return Error code
+ */
+static int sensor_set_register(struct v4l2_subdev *sd,
+ const struct v4l2_dbg_register *reg)
+{
+ ov5647_write(sd, reg->reg & 0xff, reg->val & 0xff);
+ return 0;
+}
+#endif
+
+/* ----------------------------------------------------------------------- */
+
+/**
+ * @short Subdev core operations registration
+ */
+static const struct v4l2_subdev_core_ops sensor_core_ops = {
+ .s_power = sensor_power,
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+ .g_register = sensor_get_register,
+ .s_register = sensor_set_register,
+#endif
+};
+
+/* ----------------------------------------------------------------------- */
+
+
+
+/**
+ * @short Enumerate available image formats
+ * @param[in] sd v4l2 subdev
+ * @param[in] index index
+ * @param[in] code MBUS Pixel code
+ * @return Error code
+ */
+static int sensor_enum_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ if (code->pad || code->index >= N_FMTS)
+ return -EINVAL;
+
+ code->code = sensor_formats[code->index].mbus_code;
+ return 0;
+}
+
+/**
+ * @short Try frame format internal function
+ * @param[in] sd v4l2 subdev
+ * @param[in] fmt frame format
+ * @return Error code
+ */
+static int sensor_try_fmt_internal(struct v4l2_subdev *sd,
+ struct v4l2_mbus_framefmt *fmt, struct sensor_format_struct **ret_fmt,
+ struct sensor_win_size **ret_wsize)
+{
+ int index;
+
+ for (index = 0; index < N_FMTS; index++)
+ if (sensor_formats[index].mbus_code == fmt->code)
+ break;
+
+ if (index >= N_FMTS)
+ return -EINVAL;
+
+ if (ret_fmt != NULL)
+ *ret_fmt = sensor_formats + index;
+
+ fmt->field = V4L2_FIELD_NONE;
+
+ return 0;
+}
+
+/**
+ * @short Set frame format
+ * @param[in] sd v4l2 subdev
+ * @param[in] fmt frame format
+ * @return Error code
+ */
+static int sensor_s_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ int ret;
+ struct sensor_format_struct *sensor_fmt;
+ struct sensor_win_size *wsize;
+ struct ov5647 *info = to_state(sd);
+
+ ov5647_write_array(sd, sensor_oe_disable_regs,
+ ARRAY_SIZE(sensor_oe_disable_regs));
+
+ ret = sensor_try_fmt_internal(sd, &fmt->format,
+ &sensor_fmt, &wsize);
+ if (ret)
+ return ret;
+
+ ov5647_write_array(sd, sensor_fmt->regs, sensor_fmt->regs_size);
+
+ ret = 0;
+
+ if (wsize->regs)
+ ov5647_write_array(sd, wsize->regs, wsize->regs_size);
+
+ if (wsize->set_size)
+ wsize->set_size(sd);
+
+ info->fmt = sensor_fmt;
+ info->width = wsize->width;
+ info->height = wsize->height;
+
+ ov5647_write_array(sd, sensor_oe_enable_regs,
+ ARRAY_SIZE(sensor_oe_enable_regs));
+
+ return 0;
+}
+
+/**
+ * @short Set stream parameters
+ * @param[in] sd v4l2 subdev
+ * @param[in] parms stream parameters
+ * @return Error code
+ */
+static int sensor_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
+{
+ struct v4l2_captureparm *cp = &parms->parm.capture;
+ struct ov5647 *info = to_state(sd);
+
+ if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ return -EINVAL;
+
+ if (info->tpf.numerator == 0)
+ return -EINVAL;
+
+ info->capture_mode = cp->capturemode;
+
+ return 0;
+}
+
+/**
+ * @short Get stream parameters
+ * @param[in] sd v4l2 subdev
+ * @param[in] parms stream parameters
+ * @return Error code
+ */
+static int sensor_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
+{
+ struct v4l2_captureparm *cp = &parms->parm.capture;
+ struct ov5647 *info = to_state(sd);
+
+ if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ return -EINVAL;
+
+ memset(cp, 0, sizeof(struct v4l2_captureparm));
+ cp->capability = V4L2_CAP_TIMEPERFRAME;
+ cp->capturemode = info->capture_mode;
+
+ return 0;
+}
+
+/**
+ * @short Subdev video operations registration
+ *
+ */
+static const struct v4l2_subdev_video_ops sensor_video_ops = {
+ .s_parm = sensor_s_parm,
+ .g_parm = sensor_g_parm,
+};
+
+/* ----------------------------------------------------------------------- */
+
+/**
+ * @short Subdev operations registration
+ *
+ */
+static const struct v4l2_subdev_ops subdev_ops = {
+ .core = &sensor_core_ops,
+ .video = &sensor_video_ops,
+};
+
+/* -----------------------------------------------------------------------------
+ * V4L2 subdev internal operations
+ */
+
+/**
+ * @short Detect camera version and model
+ * @param[in] sd v4l2 subdev
+ * @return Error code
+ */
+int ov5647_detect(struct v4l2_subdev *sd)
+{
+ unsigned char v;
+ int ret;
+ struct i2c_client *client = v4l2_get_subdevdata(sd);
+
+ ret = ov5647_write(sd, OV5647_SW_RESET, 0x01);
+ if (ret < 0)
+ return ret;
+ ret = ov5647_read(sd, OV5647_REG_CHIPID_H, &v);
+ if (ret < 0)
+ return ret;
+ if (v != 0x56) {
+ dev_err(&client->dev, "Wrong model version detected");
+ return -ENODEV;
+ }
+ ret = ov5647_read(sd, OV5647_REG_CHIPID_L, &v);
+ if (ret < 0)
+ return ret;
+ if (v != 0x47) {
+ dev_err(&client->dev, "Wrong model version detected");
+ return -ENODEV;
+ }
+
+ ret = ov5647_write(sd, OV5647_SW_RESET, 0x00);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/**
+ * @short Detect if camera is registered
+ * @param[in] sd v4l2 subdev
+ * @return Error code
+ */
+static int ov5647_registered(struct v4l2_subdev *sd)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(sd);
+
+ dev_info(&client->dev, "OV5647 detected at address 0x%02x\n",
+ client->addr);
+
+ return 0;
+}
+
+/**
+ * @short Open device
+ * @param[in] sd v4l2 subdev
+ * @param[in] fh v4l2 file handler
+ * @return Error code
+ */
+static int ov5647_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
+{
+ struct v4l2_mbus_framefmt *format =
+ v4l2_subdev_get_try_format(sd, fh->pad, 0);
+ struct v4l2_rect *crop =
+ v4l2_subdev_get_try_crop(sd, fh->pad, 0);
+
+ crop->left = OV5647_COLUMN_START_DEF;
+ crop->top = OV5647_ROW_START_DEF;
+ crop->width = OV5647_WINDOW_WIDTH_DEF;
+ crop->height = OV5647_WINDOW_HEIGHT_DEF;
+
+ format->code = MEDIA_BUS_FMT_SBGGR8_1X8;
+
+ format->width = OV5647_WINDOW_WIDTH_DEF;
+ format->height = OV5647_WINDOW_HEIGHT_DEF;
+ format->field = V4L2_FIELD_NONE;
+ format->colorspace = V4L2_COLORSPACE_SRGB;
+
+ return sensor_power(sd, true);
+}
+
+/**
+ * @short Open device
+ * @param[in] sd v4l2 subdev
+ * @param[in] fh v4l2 file handler
+ * @return Error code
+ */
+static int ov5647_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
+{
+ return sensor_power(sd, false);
+}
+
+/**
+ * @short Subdev internal operations registration
+ *
+ */
+static const struct v4l2_subdev_internal_ops ov5647_subdev_internal_ops = {
+ .registered = ov5647_registered,
+ .open = ov5647_open,
+ .close = ov5647_close,
+};
+
+/**
+ * @short Initialization routine - Entry point of the driver
+ * @param[in] client pointer to the i2c client structure
+ * @param[in] id pointer to the i2c device id structure
+ * @return 0 on success and a negative number on failure
+ */
+static int ov5647_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct device *dev = &client->dev;
+ struct ov5647 *sensor;
+ int ret = 0;
+ struct v4l2_subdev *sd;
+
+ dev_info(&client->dev, "Installing OmniVision OV5647 camera driver\n");
+
+ sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
+ if (sensor == NULL)
+ return -ENOMEM;
+
+ mutex_init(&sensor->lock);
+ sensor->dev = dev;
+
+ sd = &sensor->sd;
+ v4l2_i2c_subdev_init(sd, client, &subdev_ops);
+ sensor->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+
+ sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
+ sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
+ ret = media_entity_pads_init(&sd->entity, 1, &sensor->pad);
+ if (ret < 0)
+ goto mutex_remove;
+
+ ret = ov5647_detect(sd);
+ if (ret < 0)
+ goto error;
+
+ ret = v4l2_async_register_subdev(sd);
+ if (ret < 0)
+ goto error;
+
+ return 0;
+error:
+ media_entity_cleanup(&sd->entity);
+mutex_remove:
+ mutex_destroy(&sensor->lock);
+ return ret;
+}
+
+/**
+ * @short Exit routine - Exit point of the driver
+ * @param[in] client pointer to the i2c client structure
+ * @return 0 on success and a negative number on failure
+ */
+static int ov5647_remove(struct i2c_client *client)
+{
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct ov5647 *ov5647 = to_state(sd);
+
+ v4l2_async_unregister_subdev(&ov5647->sd);
+ media_entity_cleanup(&ov5647->sd.entity);
+ v4l2_device_unregister_subdev(sd);
+ mutex_destroy(&ov5647->lock);
+
+ return 0;
+}
+
+static const struct i2c_device_id ov5647_id[] = {
+ { "ov5647", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, ov5647_id);
+
+#if IS_ENABLED(CONFIG_OF)
+static const struct of_device_id ov5647_of_match[] = {
+ { .compatible = "ovti,ov5647" },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, ov5647_of_match);
+#endif
+
+/**
+ * @short i2c driver structure
+ */
+static struct i2c_driver ov5647_driver = {
+ .driver = {
+ .of_match_table = of_match_ptr(ov5647_of_match),
+ .owner = THIS_MODULE,
+ .name = "ov5647",
+ },
+ .probe = ov5647_probe,
+ .remove = ov5647_remove,
+ .id_table = ov5647_id,
+};
+
+module_i2c_driver(ov5647_driver);
+
+MODULE_AUTHOR("Ramiro Oliveira <roliveir@synopsys.com>");
+MODULE_DESCRIPTION("A low-level driver for OmniVision ov5647 sensors");
+MODULE_LICENSE("GPL v2");
--
2.10.2
^ permalink raw reply related
* [PATCH v4 1/2] Add OV5647 device tree documentation
From: Ramiro Oliveira @ 2016-11-14 13:46 UTC (permalink / raw)
To: mchehab, linux-kernel, linux-media, robh+dt, devicetree
Cc: davem, gregkh, geert+renesas, akpm, linux, hverkuil, dheitmueller,
slongerbeam, lars, robert.jarzmik, pavel, pali.rohar,
sakari.ailus, mark.rutland, Ramiro.Oliveira, CARLOS.PALMINHA
In-Reply-To: <cover.1479129004.git.roliveir@synopsys.com>
Add device tree documentation.
Signed-off-by: Ramiro Oliveira <roliveir@synopsys.com>
---
.../devicetree/bindings/media/i2c/ov5647.txt | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/i2c/ov5647.txt
diff --git a/Documentation/devicetree/bindings/media/i2c/ov5647.txt b/Documentation/devicetree/bindings/media/i2c/ov5647.txt
new file mode 100644
index 0000000..4c91b3b
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/ov5647.txt
@@ -0,0 +1,19 @@
+Omnivision OV5647 raw image sensor
+---------------------------------
+
+OV5647 is a raw image sensor with MIPI CSI-2 and CCP2 image data interfaces
+and CCI (I2C compatible) control bus.
+
+Required properties:
+
+- compatible : "ovti,ov5647";
+- reg : I2C slave address of the sensor;
+
+The common video interfaces bindings (see video-interfaces.txt) should be
+used to specify link to the image data receiver. The OV5647 device
+node should contain one 'port' child node with an 'endpoint' subnode.
+
+Following properties are valid for the endpoint node:
+
+- data-lanes : (optional) specifies MIPI CSI-2 data lanes as covered in
+ video-interfaces.txt. The sensor supports only two data lanes.
--
2.10.2
^ permalink raw reply related
* [PATCH v4 0/2] Add support for Omnivision OV5647
From: Ramiro Oliveira @ 2016-11-14 13:46 UTC (permalink / raw)
To: mchehab, linux-kernel, linux-media, robh+dt, devicetree
Cc: davem, gregkh, geert+renesas, akpm, linux, hverkuil, dheitmueller,
slongerbeam, lars, robert.jarzmik, pavel, pali.rohar,
sakari.ailus, mark.rutland, Ramiro.Oliveira, CARLOS.PALMINHA
Hello,
This patch adds support for the Omnivision OV5647 sensor.
At the moment it only supports 640x480 in Raw 8.
This is the fourth version of the OV5647 camera driver patchset.
v4:
- Add correct license
- Revert debugging info to generic infrastructure
- Turn defines into enums
- Correct code style issues
- Remove unused defines
- Make sure all errors where being handled
- Rename some functions to make code more readable
- Add some debugging info
v3:
- No changes. Re-submitted due to lack of responses
v2:
- Corrections in DT documentation
Ramiro Oliveira (2):
Add OV5647 device tree documentation
Add support for OV5647 sensor
.../devicetree/bindings/media/i2c/ov5647.txt | 19 +
MAINTAINERS | 7 +
drivers/media/i2c/Kconfig | 12 +
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/ov5647.c | 861 +++++++++++++++++++++
5 files changed, 900 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/i2c/ov5647.txt
create mode 100644 drivers/media/i2c/ov5647.c
--
2.10.2
^ permalink raw reply
* Re: [PATCH] x86: re-add stack alignment check
From: Andrew Cooper @ 2016-11-14 13:45 UTC (permalink / raw)
To: Jan Beulich, xen-devel; +Cc: Wei Liu
In-Reply-To: <5829C95A020000780011E6EA@prv-mh.provo.novell.com>
On 14/11/16 13:25, Jan Beulich wrote:
> Commit 279840d5ea ("x86/boot: install trap handlers much earlier on
> boot"), perhaps not really intentionally, removed this check. Add it
No - that was deliberate. The check isn't useful (see below).
> back,
> - preventing it to trigger before any output is set up,
"preventing it from triggering ..."
> - accompanying it with a (weaker, due to its open coding of what
> get_stack_bottom() does) build time check.
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
> ---
> While not strictly needed for 4.8, I thought I'd still submit it as a
> possible candidate.
>
> --- a/xen/arch/x86/cpu/common.c
> +++ b/xen/arch/x86/cpu/common.c
> @@ -643,6 +643,11 @@ void load_system_tables(void)
> .limit = (IDT_ENTRIES * sizeof(idt_entry_t)) - 1,
> };
>
> + /* Bottom-of-stack must be 16-byte aligned! */
> + BUILD_BUG_ON((sizeof(struct cpu_info) -
> + offsetof(struct cpu_info, guest_cpu_user_regs.es)) & 0xf);
> + BUG_ON(system_state != SYS_STATE_early_boot && (stack_bottom & 0xf));
This will still triple fault the system if it triggers on an AP.
Exceptions aren't hooked up yet.
The reason I dropped the check was that there was no way it was going to
fail on the BSP (because of the alignment of cpu0_stack) or APs (because
of the alloc_xenheap_pages(STACK_ORDER, memflags) allocation).
The BUILD_BUG_ON() is useful to retain, but I would suggest making
get_stack_bottom() a static inline and putting the BUILD_BUG_ON() there.
~Andrew
> +
> /* Main stack for interrupts/exceptions. */
> tss->rsp0 = stack_bottom;
> tss->bitmap = IOBMP_INVALID_OFFSET;
>
>
>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply
* [U-Boot] [PATCH] MAINTAINERS: mark sunxi status as Orphan
From: Ian Campbell @ 2016-11-14 13:45 UTC (permalink / raw)
To: u-boot
In-Reply-To: <20161114115325.1601-1-hdegoede@redhat.com>
On Mon, 2016-11-14 at 12:53 +0100, Hans de Goede wrote:
> Ian has not had any time for sunxi for some time now and I'm
> in the same situation now, so I'm stepping down as sunxi
> custodian and marking the sunxi support as Orphan.
>
> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
> Cc: Chen-Yu Tsai <wens@csie.org>
> Cc: Ian Campbell <ijc@hellion.org.uk>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
:-(
^ permalink raw reply
* Re: [glibc PATCH] fcntl: put F_OFD_* constants under #ifdef __USE_FILE_OFFSET64
From: Cyril Hrubis @ 2016-11-14 13:45 UTC (permalink / raw)
To: Michael Kerrisk (man-pages)
Cc: Jeff Layton, Florian Weimer, Mike Frysinger, libc-alpha,
linux-fsdevel, Carlos O'Donell, Yuriy Kolerov
In-Reply-To: <8acbfa50-516f-d402-928f-9a391610557d@gmail.com>
Hi!
> >> To be clear, that approach was NAK'ed by Christoph (and I think that's
> >> a good thing, actually -- one more nail in the non-LFS coffin). I think
> >> what we want merged into glibc is this patch that I sent late on
> >> Thursday:
> >>
> >> [glibc PATCHv2] fcntl: don't define OFD lock constants for 32-bit builds with small file offsets
> >>
> >> We'll also need your patch to the fcntl(2) manpage as well, but that's
> >> a separate problem.
> >
> > Hmm, the patch for man-pages should be updated as well. We need
> > somethign as:
> >
> > ...
> > This lock type is Linux-specific, and available since Linux 3.15.
> > On 32bit platform _FILE_OFFSET_BITS must defined to 64 (before including
> > any header files) to make these locks available.
> > ...
> >
> > Michael should I send updated patch or will you take care of this?
>
> I can do it, or you can. At the moment, I'm just holding off until I
> see what is accepted into glibc.
Ping.
Is there any resolve for this?
--
Cyril Hrubis
chrubis@suse.cz
^ permalink raw reply
* Re: [powerpc v4 3/3] Enable storage keys for radix - user mode execution
From: kbuild test robot @ 2016-11-14 13:43 UTC (permalink / raw)
To: Balbir Singh; +Cc: kbuild-all, linuxppc-dev
In-Reply-To: <1479101112-21120-4-git-send-email-bsingharora@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1230 bytes --]
Hi Balbir,
[auto build test WARNING on powerpc/master]
url: https://github.com/0day-ci/linux/commits/Balbir-Singh/Enable-IAMR-storage-keys-for-radix/20161114-133434
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git master
config: powerpc-allyesconfig (attached as .config)
compiler: powerpc64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=powerpc
All warnings (new ones prefixed by >>):
>> WARNING: vmlinux.o(.text+0x645f0): Section mismatch in reference from the function .radix__early_init_mmu_secondary() to the function .init.text:.radix_init_iamr()
The function .radix__early_init_mmu_secondary() references
the function __init .radix_init_iamr().
This is often because .radix__early_init_mmu_secondary lacks a __init
annotation or the annotation of .radix_init_iamr is wrong.
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 50923 bytes --]
^ permalink raw reply
* Re: [PATCH net-next v2 4/5] ethtool: Core impl for ETHTOOL_PHY_DOWNSHIFT tunable
From: Andrew Lunn @ 2016-11-14 13:43 UTC (permalink / raw)
To: Allan W. Nielsen; +Cc: netdev, raju.lakkaraju
In-Reply-To: <1479115760-1182-5-git-send-email-allan.nielsen@microsemi.com>
On Mon, Nov 14, 2016 at 10:29:19AM +0100, Allan W. Nielsen wrote:
> From: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
>
> Adding validation support for the ETHTOOL_PHY_DOWNSHIFT. Functional
> implementation needs to be done in the individual PHY drivers.
>
> Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply
* [U-Boot] [PATCH RESEND 6/9] eeprom: Add DS2431 support
From: Maxime Ripard @ 2016-11-14 13:42 UTC (permalink / raw)
To: u-boot
In-Reply-To: <CAAtXAHf+tfT0isifb7QYhHtbxtJns0-qs39ie67uNUZgCVi5LA@mail.gmail.com>
Hi,
On Fri, Nov 11, 2016 at 11:16:39AM -0800, Moritz Fischer wrote:
> > +U_BOOT_DRIVER(ds2431) = {
> > + .name = "ds2431",
> > + .id = UCLASS_EEPROM,
> > + .ops = &ds2431_ops,
>
> Do you want to add a .flags = DM_UC_FLAG_SEQ_ALIAS here?
I don't know. I was kind of wondering why U-Boot relies on aliases so
much, especially when the Linux DT maintainers are saying that aliases
should be avoided entirely, and we'll won't be able to upstream those
changes.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* Re: [PATCH 2/2] mmc: sdhci-pci: Add support for HS200 tuning mode on AMD, eMMC-4.5.1
From: Adrian Hunter @ 2016-11-14 13:37 UTC (permalink / raw)
To: Shyam Sundar S K
Cc: Ulf Hansson, linux-mmc, Sen, Pankaj, Agrawal, Nitesh-kumar,
Shah, Nehal-bakulchandra
In-Reply-To: <dbebff7a-d144-9dc5-6e59-3a39274ee21d@amd.com>
On 14/11/16 08:38, Shyam Sundar S K wrote:
>
>
> On 11/11/2016 6:11 PM, Adrian Hunter wrote:
>> On 10/11/16 14:51, Shyam Sundar S K wrote:
>>> This patch adds support for HS200 tuning mode on AMD eMMC-4.5.1
>>>
>>> Reviewed-by: Sen, Pankaj <Pankaj.Sen@amd.com>
>>> Reviewed-by: Shah, Nehal-bakulchandra <Nehal-bakulchandra.Shah@amd.com>
>>> Signed-off-by: S-k, Shyam-sundar <Shyam-sundar.S-k@amd.com>
>>> ---
>>> drivers/mmc/host/sdhci-pci-core.c | 178 +++++++++++++++++++++++++++++++++++++-
>>> 1 file changed, 177 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c
>>> index 782c8d2..9576f82 100644
>>> --- a/drivers/mmc/host/sdhci-pci-core.c
>>> +++ b/drivers/mmc/host/sdhci-pci-core.c
>>> @@ -817,6 +817,171 @@ enum amd_chipset_gen {
>>> AMD_CHIPSET_UNKNOWN,
>>> };
>>>
>>> +static const struct sdhci_ops amd_sdhci_pci_ops;
>>> +
>>> +struct amd_tuning_descriptor {
>>> + u8 tune_around;
>>> + bool this_tune_ok;
>>> + bool last_tune_ok;
>>> + u8 valid_front;
>>> + u8 valid_window_max;
>>> + u8 tune_low_max;
>>> + u8 tune_low;
>>> + u8 valid_window;
>>> + u8 tune_result;
>>> +};
>>> +
>>> +static int amd_tuning_reset(struct sdhci_host *host)
>>> +{
>>> + unsigned int val;
>>> + unsigned long flags;
>>> +
>>> + spin_lock_irqsave(&host->lock, flags);
>>> +
>>> + val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
>>> + val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
>>> + sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
>>> +
>>> + val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
>>> + val &= ~SDHCI_CTRL_EXEC_TUNING;
>>> + sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
>>> +
>>> + spin_unlock_irqrestore(&host->lock, flags);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int amd_config_tuning_phase(struct sdhci_host *host, u8 phase)
>>> +{
>>> + struct sdhci_pci_slot *slot = sdhci_priv(host);
>>> + struct pci_dev *pdev = slot->chip->pdev;
>>> + unsigned int val;
>>> + unsigned long flags;
>>> +
>>> + spin_lock_irqsave(&host->lock, flags);
>>> +
>>> + pci_read_config_dword(pdev, 0xb8, &val);
>>> + val &= ~0x1f;
>>> + val |= (0x10800 | (phase << 1));
>>> + pci_write_config_dword(pdev, 0xb8, val);
>>> +
>>> + spin_unlock_irqrestore(&host->lock, flags);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int amd_find_good_phase(struct sdhci_host *host)
>>> +{
>>> + struct sdhci_pci_slot *slot = sdhci_priv(host);
>>> + struct pci_dev *pdev = slot->chip->pdev;
>>> + struct amd_tuning_descriptor *td = sdhci_pci_priv(slot);
>>> +
>>> + unsigned int val;
>>> + unsigned long flags;
>>> +
>>> + spin_lock_irqsave(&host->lock, flags);
>>> +
>>> + if (td->this_tune_ok)
>>> + td->valid_front += 1;
>>> + if ((!td->this_tune_ok && td->last_tune_ok) ||
>>> + (td->tune_around == 11)) {
>>> + if (td->valid_window > td->valid_window_max) {
>>> + td->valid_window_max = td->valid_window;
>>> + td->tune_low_max = td->tune_low;
>>> + }
>>> + }
>>> + if (td->this_tune_ok && (!td->last_tune_ok))
>>> + td->tune_low = td->tune_around;
>>> + if (!td->this_tune_ok && td->last_tune_ok)
>>> + td->valid_window = 0;
>>> + else if (td->this_tune_ok)
>>> + td->valid_window += 1;
>>> +
>>> + td->last_tune_ok = td->this_tune_ok;
>>> +
>>> + if (td->tune_around == 11) {
>>> + if ((td->valid_front + td->valid_window) >
>>> + td->valid_window_max) {
>>> + if (td->valid_front > td->valid_window)
>>> + td->tune_result = ((td->valid_front -
>>> + td->valid_window) >> 1);
>>> + else
>>> + td->tune_result = td->tune_low +
>>> + ((td->valid_window + td->valid_front) >> 1);
>>> + } else {
>>> + td->tune_result = td->tune_low_max +
>>> + (td->valid_window_max >> 1);
>>> + }
>>> +
>>> + if (td->tune_result > 0x0b)
>>> + td->tune_result = 0x0b;
>>> +
>>> + pci_read_config_dword(pdev, 0xb8, &val);
>>> + val &= ~0x1f;
>>> + val |= (0x10800 | (td->tune_result << 1));
>>> + pci_write_config_dword(pdev, 0xb8, val);
>>> + }
>>> +
>>> + spin_unlock_irqrestore(&host->lock, flags);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int amd_enable_manual_tuning(struct sdhci_pci_slot *slot)
>>> +{
>>> + struct pci_dev *pdev = slot->chip->pdev;
>>> + unsigned int val;
>>> +
>>> + pci_read_config_dword(pdev, 0xd0, &val);
>>> + val &= 0xffffffcf;
>>> + val |= 0x30;
>>> + pci_write_config_dword(pdev, 0xd0, val);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int amd_execute_tuning(struct sdhci_host *host, u32 opcode)
>>> +{
>>> + struct sdhci_pci_slot *slot = sdhci_priv(host);
>>> + struct amd_tuning_descriptor *td = sdhci_pci_priv(slot);
>>> + u8 ctrl;
>>> +
>>> + amd_tuning_reset(host);
>>> + memset(td, 0, sizeof(struct amd_tuning_descriptor));
>>
>> I didn't notice last time that you are always clearing all the values in the
>> tuning descriptor, so it doesn't need to be kept between calls to
>> amd_execute_tuning(). So it should be a local variable that you pass to the
>> functions that need it. Then you don't need the patch I sent at all.
>>
>> Does that make sense?
>>
>
> Hi Adrian,
>
> Thanks for pointing this out. Your patch will help, so will remove the memset()
> and redo the submission. Is this OK ?
Sure
^ permalink raw reply
* [PATCH v18 2/2] drm/bridge: Add I2C based driver for ps8640 bridge
From: Jitao Shi @ 2016-11-14 13:41 UTC (permalink / raw)
To: David Airlie, Thierry Reding, Matthias Brugger
Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Jitao Shi, Ajay Kumar, Inki Dae, Rahul Sharma, Sean Paul,
Vincent Palatin, Andy Yan, Philipp Zabel, Russell King,
devicetree, linux-kernel, dri-devel, linux-arm-kernel,
linux-mediatek, srv_heupstream, Sascha Hauer, yingjoe.chen,
eddie.huang, cawa.cheng, bibby.hsieh, ck.hu, stonea168
In-Reply-To: <1479130908-17593-1-git-send-email-jitao.shi@mediatek.com>
This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
Changes since v17:
- remove some unused head files.
- add macros for ps8640 pages.
- remove ddc_i2c client
- add mipi_dsi_device_register_full
- remove the manufacturer from the name and i2c_device_id
Changes since v16:
- Disable ps8640 DSI MCS Function.
- Rename gpios name more clearly.
- Tune the ps8640 power on sequence.
Changes since v15:
- Drop drm_connector_(un)register calls from parade ps8640.
The main DRM driver mtk_drm_drv now calls
drm_connector_register_all() after drm_dev_register() in the
mtk_drm_bind() function. That function should iterate over all
connectors and call drm_connector_register() for each of them.
So, remove drm_connector_(un)register calls from parade ps8640.
Changes since v14:
- update copyright info.
- change bridge_to_ps8640 and connector_to_ps8640 to inline function.
- fix some coding style.
- use sizeof as array counter.
- use drm_get_edid when read edid.
- add mutex when firmware updating.
Changes since v13:
- add const on data, ps8640_write_bytes(struct i2c_client *client, const u8 *data, u16 data_len)
- fix PAGE2_SW_REST tyro.
- move the buf[3] init to entrance of the function.
Changes since v12:
- fix hw_chip_id build warning
Changes since v11:
- Remove depends on I2C, add DRM depends
- Reuse ps8640_write_bytes() in ps8640_write_byte()
- Use timer check for polling like the routines in <linux/iopoll.h>
- Fix no drm_connector_unregister/drm_connector_cleanup when ps8640_bridge_attach fail
- Check the ps8640 hardware id in ps8640_validate_firmware
- Remove fw_version check
- Move ps8640_validate_firmware before ps8640_enter_bl
- Add ddc_i2c unregister when probe fail and ps8640_remove
---
drivers/gpu/drm/bridge/Kconfig | 12 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/parade-ps8640.c | 1079 ++++++++++++++++++++++++++++++++
3 files changed, 1092 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/parade-ps8640.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 10e12e7..7f41bbc 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -57,6 +57,18 @@ config DRM_PARADE_PS8622
---help---
Parade eDP-LVDS bridge chip driver.
+config DRM_PARADE_PS8640
+ tristate "Parade PS8640 MIPI DSI to eDP Converter"
+ depends on DRM
+ depends on OF
+ select DRM_KMS_HELPER
+ select DRM_MIPI_DSI
+ select DRM_PANEL
+ ---help---
+ Choose this option if you have PS8640 for display
+ The PS8640 is a high-performance and low-power
+ MIPI DSI to eDP converter
+
config DRM_SII902X
tristate "Silicon Image sii902x RGB/HDMI bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index cdf3a3c..7d93d40 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
+obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o
obj-$(CONFIG_DRM_SII902X) += sii902x.o
obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c
new file mode 100644
index 0000000..2d9c337
--- /dev/null
+++ b/drivers/gpu/drm/bridge/parade-ps8640.c
@@ -0,0 +1,1079 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/firmware.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/of_graph.h>
+#include <linux/regulator/consumer.h>
+#include <asm/unaligned.h>
+#include <drm/drm_panel.h>
+
+#include <drmP.h>
+#include <drm_atomic_helper.h>
+#include <drm_crtc_helper.h>
+#include <drm_edid.h>
+#include <drm_mipi_dsi.h>
+
+#define PAGE1_VSTART 0x6b
+#define PAGE2_SPI_CFG3 0x82
+#define I2C_TO_SPI_RESET 0x20
+#define PAGE2_ROMADD_BYTE1 0x8e
+#define PAGE2_ROMADD_BYTE2 0x8f
+#define PAGE2_SWSPI_WDATA 0x90
+#define PAGE2_SWSPI_RDATA 0x91
+#define PAGE2_SWSPI_LEN 0x92
+#define PAGE2_SWSPI_CTL 0x93
+#define TRIGGER_NO_READBACK 0x05
+#define TRIGGER_READBACK 0x01
+#define PAGE2_SPI_STATUS 0x9e
+#define SPI_READY 0x0c
+#define PAGE2_GPIO_L 0xa6
+#define PAGE2_GPIO_H 0xa7
+#define PS_GPIO9 BIT(1)
+#define PAGE2_IROM_CTRL 0xb0
+#define IROM_ENABLE 0xc0
+#define IROM_DISABLE 0x80
+#define PAGE2_SW_RESET 0xbc
+#define SPI_SW_RESET BIT(7)
+#define MPU_SW_RESET BIT(6)
+#define PAGE2_ENCTLSPI_WR 0xda
+#define PAGE2_I2C_BYPASS 0xea
+#define I2C_BYPASS_EN 0xd0
+#define PAGE2_MCS_EN 0xf3
+#define MCS_EN BIT(0)
+#define PAGE3_SET_ADD 0xfe
+#define PAGE3_SET_VAL 0xff
+#define VDO_CTL_ADD 0x13
+#define VDO_DIS 0x18
+#define VDO_EN 0x1c
+#define PAGE4_REV_L 0xf0
+#define PAGE4_REV_H 0xf1
+#define PAGE4_CHIP_L 0xf2
+#define PAGE4_CHIP_H 0xf3
+
+#define PAGE0_DP_CNTL 0
+#define PAGE1_VDO_BDG 1
+#define PAGE2_TOP_CNTL 2
+#define PAGE3_DSI_CNTL1 3
+#define PAGE4_MIPI_PHY 4
+#define PAGE5_VPLL 5
+#define PAGE6_DSI_CNTL2 6
+#define PAGE7_SPI_CNTL 7
+#define MAX_DEVS 0x8
+
+/* Firmware */
+#define PS_FW_NAME "ps864x_fw.bin"
+
+#define FW_CHIP_ID_OFFSET 0
+#define FW_VERSION_OFFSET 2
+#define EDID_I2C_ADDR 0x50
+
+#define WRITE_STATUS_REG_CMD 0x01
+#define READ_STATUS_REG_CMD 0x05
+#define BUSY BIT(0)
+#define CLEAR_ALL_PROTECT 0x00
+#define BLK_PROTECT_BITS 0x0c
+#define STATUS_REG_PROTECT BIT(7)
+#define WRITE_ENABLE_CMD 0x06
+#define CHIP_ERASE_CMD 0xc7
+
+struct ps8640_info {
+ u8 family_id;
+ u8 variant_id;
+ u16 version;
+};
+
+struct ps8640 {
+ struct drm_connector connector;
+ struct drm_bridge bridge;
+ struct edid *edid;
+ struct mipi_dsi_device *dsi;
+ struct i2c_client *page[MAX_DEVS];
+ struct regulator_bulk_data supplies[2];
+ struct drm_panel *panel;
+ struct gpio_desc *gpio_reset;
+ struct gpio_desc *gpio_power_down;
+ struct gpio_desc *gpio_mode_sel;
+ bool enabled;
+
+ /* firmware file info */
+ struct ps8640_info info;
+ bool in_fw_update;
+ /* for firmware update protect */
+ struct mutex fw_mutex;
+};
+
+static const u8 enc_ctrl_code[6] = { 0xaa, 0x55, 0x50, 0x41, 0x52, 0x44 };
+static const u8 hw_chip_id[4] = { 0x00, 0x0a, 0x00, 0x30 };
+
+static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e)
+{
+ return container_of(e, struct ps8640, bridge);
+}
+
+static inline struct ps8640 *connector_to_ps8640(struct drm_connector *e)
+{
+ return container_of(e, struct ps8640, connector);
+}
+
+static int ps8640_read(struct i2c_client *client, u8 reg, u8 *data,
+ u16 data_len)
+{
+ int ret;
+ struct i2c_msg msgs[] = {
+ {
+ .addr = client->addr,
+ .flags = 0,
+ .len = 1,
+ .buf = ®,
+ },
+ {
+ .addr = client->addr,
+ .flags = I2C_M_RD,
+ .len = data_len,
+ .buf = data,
+ }
+ };
+
+ ret = i2c_transfer(client->adapter, msgs, 2);
+
+ if (ret == 2)
+ return 0;
+ if (ret < 0)
+ return ret;
+ else
+ return -EIO;
+}
+
+static int ps8640_write_bytes(struct i2c_client *client, const u8 *data,
+ u16 data_len)
+{
+ int ret;
+ struct i2c_msg msg;
+
+ msg.addr = client->addr;
+ msg.flags = 0;
+ msg.len = data_len;
+ msg.buf = (u8 *)data;
+
+ ret = i2c_transfer(client->adapter, &msg, 1);
+ if (ret == 1)
+ return 0;
+ if (ret < 0)
+ return ret;
+ else
+ return -EIO;
+}
+
+static int ps8640_write_byte(struct i2c_client *client, u8 reg, u8 data)
+{
+ u8 buf[] = { reg, data };
+
+ return ps8640_write_bytes(client, buf, sizeof(buf));
+}
+
+static void ps8640_get_mcu_fw_version(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE5_VPLL];
+ u8 fw_ver[2];
+
+ ps8640_read(client, 0x4, fw_ver, sizeof(fw_ver));
+ ps_bridge->info.version = (fw_ver[0] << 8) | fw_ver[1];
+
+ DRM_INFO_ONCE("ps8640 rom fw version %d.%d\n", fw_ver[0], fw_ver[1]);
+}
+
+static int ps8640_bridge_unmute(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE3_DSI_CNTL1];
+ u8 vdo_ctrl_buf[3] = { PAGE3_SET_ADD, VDO_CTL_ADD, VDO_EN };
+
+ return ps8640_write_bytes(client, vdo_ctrl_buf, sizeof(vdo_ctrl_buf));
+}
+
+static int ps8640_bridge_mute(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE3_DSI_CNTL1];
+ u8 vdo_ctrl_buf[3] = { PAGE3_SET_ADD, VDO_CTL_ADD, VDO_DIS };
+
+ return ps8640_write_bytes(client, vdo_ctrl_buf, sizeof(vdo_ctrl_buf));
+}
+
+static void ps8640_pre_enable(struct drm_bridge *bridge)
+{
+ struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+ struct i2c_client *page1 = ps_bridge->page[PAGE1_VDO_BDG];
+ int err;
+ u8 set_vdo_done, mcs_en, vstart;
+ ktime_t timeout;
+
+ if (ps_bridge->in_fw_update)
+ return;
+
+ if (ps_bridge->enabled)
+ return;
+
+ err = drm_panel_prepare(ps_bridge->panel);
+ if (err < 0) {
+ DRM_ERROR("failed to prepare panel: %d\n", err);
+ return;
+ }
+
+ err = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies),
+ ps_bridge->supplies);
+ if (err < 0) {
+ DRM_ERROR("cannot enable regulators %d\n", err);
+ goto err_panel_unprepare;
+ }
+
+ gpiod_set_value(ps_bridge->gpio_power_down, 1);
+ gpiod_set_value(ps_bridge->gpio_reset, 0);
+ usleep_range(2000, 2500);
+ gpiod_set_value(ps_bridge->gpio_reset, 1);
+
+ /*
+ * Wait for the ps8640 embed mcu ready
+ * First wait 200ms and then check the mcu ready flag every 20ms
+ */
+ msleep(200);
+
+ timeout = ktime_add_ms(ktime_get(), 200);
+ for (;;) {
+ err = ps8640_read(client, PAGE2_GPIO_H, &set_vdo_done, 1);
+ if (err < 0) {
+ DRM_ERROR("failed read PAGE2_GPIO_H: %d\n", err);
+ goto err_regulators_disable;
+ }
+ if ((set_vdo_done & PS_GPIO9) == PS_GPIO9)
+ break;
+ if (ktime_compare(ktime_get(), timeout) > 0)
+ break;
+ msleep(20);
+ }
+
+ msleep(50);
+
+ ps8640_read(page1, PAGE1_VSTART, &vstart, 1);
+ DRM_INFO("PS8640 PAGE1.0x6B = 0x%x\n", vstart);
+
+ /**
+ * The Manufacturer Command Set (MCS) is a device dependent interface
+ * intended for factory programming of the display module default
+ * parameters. Once the display module is configured, the MCS shall be
+ * disabled by the manufacturer. Once disabled, all MCS commands are
+ * ignored by the display interface.
+ */
+ ps8640_read(client, PAGE2_MCS_EN, &mcs_en, 1);
+ ps8640_write_byte(client, PAGE2_MCS_EN, mcs_en & ~MCS_EN);
+
+ if (ps_bridge->info.version == 0)
+ ps8640_get_mcu_fw_version(ps_bridge);
+
+ err = ps8640_bridge_unmute(ps_bridge);
+ if (err)
+ DRM_ERROR("failed to enable unmutevideo: %d\n", err);
+ /* Switch access edp panel's edid through i2c */
+ ps8640_write_byte(client, PAGE2_I2C_BYPASS, I2C_BYPASS_EN);
+ ps_bridge->enabled = true;
+
+ return;
+
+err_regulators_disable:
+ regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
+ ps_bridge->supplies);
+err_panel_unprepare:
+ drm_panel_unprepare(ps_bridge->panel);
+}
+
+static void ps8640_enable(struct drm_bridge *bridge)
+{
+ struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
+ int err;
+
+ err = drm_panel_enable(ps_bridge->panel);
+ if (err < 0)
+ DRM_ERROR("failed to enable panel: %d\n", err);
+}
+
+static void ps8640_disable(struct drm_bridge *bridge)
+{
+ struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
+ int err;
+
+ err = drm_panel_disable(ps_bridge->panel);
+ if (err < 0)
+ DRM_ERROR("failed to disable panel: %d\n", err);
+}
+
+static void ps8640_post_disable(struct drm_bridge *bridge)
+{
+ struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
+ int err;
+
+ if (ps_bridge->in_fw_update)
+ return;
+
+ if (!ps_bridge->enabled)
+ return;
+
+ ps_bridge->enabled = false;
+
+ err = ps8640_bridge_mute(ps_bridge);
+ if (err < 0)
+ DRM_ERROR("failed to unmutevideo: %d\n", err);
+
+ gpiod_set_value(ps_bridge->gpio_reset, 0);
+ gpiod_set_value(ps_bridge->gpio_power_down, 0);
+ err = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
+ ps_bridge->supplies);
+ if (err < 0)
+ DRM_ERROR("cannot disable regulators %d\n", err);
+
+ err = drm_panel_unprepare(ps_bridge->panel);
+ if (err)
+ DRM_ERROR("failed to unprepare panel: %d\n", err);
+}
+
+static int ps8640_get_modes(struct drm_connector *connector)
+{
+ struct ps8640 *ps_bridge = connector_to_ps8640(connector);
+ struct edid *edid;
+ int num_modes = 0;
+ bool power_off;
+
+ if (ps_bridge->edid)
+ return drm_add_edid_modes(connector, ps_bridge->edid);
+
+ power_off = !ps_bridge->enabled;
+ ps8640_pre_enable(&ps_bridge->bridge);
+
+ edid = drm_get_edid(connector, ps_bridge->page[0]->adapter);
+ if (!edid)
+ goto out;
+
+ ps_bridge->edid = edid;
+ drm_mode_connector_update_edid_property(connector, ps_bridge->edid);
+ num_modes = drm_add_edid_modes(connector, ps_bridge->edid);
+
+out:
+ if (power_off)
+ ps8640_post_disable(&ps_bridge->bridge);
+
+ return num_modes;
+}
+
+static const struct drm_connector_helper_funcs ps8640_connector_helper_funcs = {
+ .get_modes = ps8640_get_modes,
+};
+
+static enum drm_connector_status ps8640_detect(struct drm_connector *connector,
+ bool force)
+{
+ return connector_status_connected;
+}
+
+static const struct drm_connector_funcs ps8640_connector_funcs = {
+ .dpms = drm_atomic_helper_connector_dpms,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .detect = ps8640_detect,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+int ps8640_bridge_attach(struct drm_bridge *bridge)
+{
+ struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
+ struct device *dev = &ps_bridge->page[0]->dev;
+ struct device_node *in_ep, *dsi_node = NULL;
+ struct mipi_dsi_device *dsi;
+ struct mipi_dsi_host *host = NULL;
+ int ret;
+ const struct mipi_dsi_device_info info = { .type = "ps8640",
+ .channel = 0,
+ .node = NULL,
+ };
+
+ ret = drm_connector_init(bridge->dev, &ps_bridge->connector,
+ &ps8640_connector_funcs,
+ DRM_MODE_CONNECTOR_eDP);
+
+ if (ret) {
+ DRM_ERROR("Failed to initialize connector with drm: %d\n", ret);
+ return ret;
+ }
+
+ drm_connector_helper_add(&ps_bridge->connector,
+ &ps8640_connector_helper_funcs);
+
+ ps_bridge->connector.dpms = DRM_MODE_DPMS_ON;
+ drm_mode_connector_attach_encoder(&ps_bridge->connector,
+ bridge->encoder);
+
+ if (ps_bridge->panel)
+ drm_panel_attach(ps_bridge->panel, &ps_bridge->connector);
+
+ /* port@0 is ps8640 dsi input port */
+ in_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
+ if (in_ep) {
+ dsi_node = of_graph_get_remote_port_parent(in_ep);
+ of_node_put(in_ep);
+ }
+
+ if (dsi_node) {
+ host = of_find_mipi_dsi_host_by_node(dsi_node);
+ of_node_put(dsi_node);
+ if (!host) {
+ ret = -ENODEV;
+ goto err;
+ }
+ }
+
+ dsi = mipi_dsi_device_register_full(host, &info);
+ if (IS_ERR(dsi)) {
+ dev_err(dev, "failed to create dsi device\n");
+ ret = PTR_ERR(dsi);
+ goto err;
+ }
+
+ ps_bridge->dsi = dsi;
+
+ dsi->host = host;
+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
+ dsi->format = MIPI_DSI_FMT_RGB888;
+ dsi->lanes = 4;
+ ret = mipi_dsi_attach(dsi);
+ if (ret)
+ goto err_dsi_attach;
+
+ return 0;
+
+err_dsi_attach:
+ mipi_dsi_device_unregister(dsi);
+err:
+ if (ps_bridge->panel)
+ drm_panel_detach(ps_bridge->panel);
+ drm_connector_cleanup(&ps_bridge->connector);
+ return ret;
+}
+
+static const struct drm_bridge_funcs ps8640_bridge_funcs = {
+ .attach = ps8640_bridge_attach,
+ .disable = ps8640_disable,
+ .post_disable = ps8640_post_disable,
+ .pre_enable = ps8640_pre_enable,
+ .enable = ps8640_enable,
+};
+
+/* Firmware Version is returned as Major.Minor */
+static ssize_t ps8640_fw_version_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct ps8640 *ps_bridge = dev_get_drvdata(dev);
+ struct ps8640_info *info = &ps_bridge->info;
+
+ return scnprintf(buf, PAGE_SIZE, "%u.%u\n", info->version >> 8,
+ info->version & 0xff);
+}
+
+/* Hardware Version is returned as FamilyID.VariantID */
+static ssize_t ps8640_hw_version_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct ps8640 *ps_bridge = dev_get_drvdata(dev);
+ struct ps8640_info *info = &ps_bridge->info;
+
+ return scnprintf(buf, PAGE_SIZE, "ps%u.%u\n", info->family_id,
+ info->variant_id);
+}
+
+static int ps8640_spi_send_cmd(struct ps8640 *ps_bridge, u8 *cmd, u8 cmd_len)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+ u8 i, buf[3] = { PAGE2_SWSPI_LEN, cmd_len - 1, TRIGGER_NO_READBACK };
+ int ret;
+
+ ret = ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_ENABLE);
+ if (ret)
+ goto err;
+
+ /* write command in write port */
+ for (i = 0; i < cmd_len; i++) {
+ ret = ps8640_write_byte(client, PAGE2_SWSPI_WDATA, cmd[i]);
+ if (ret)
+ goto err_irom_disable;
+ }
+
+ ret = ps8640_write_bytes(client, buf, sizeof(buf));
+ if (ret)
+ goto err_irom_disable;
+
+ ret = ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_DISABLE);
+ if (ret)
+ goto err;
+
+ return 0;
+err_irom_disable:
+ ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_DISABLE);
+err:
+ dev_err(&client->dev, "send command err: %d\n", ret);
+ return ret;
+}
+
+static int ps8640_wait_spi_ready(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+ u8 spi_rdy_st;
+ ktime_t timeout;
+
+ timeout = ktime_add_ms(ktime_get(), 200);
+ for (;;) {
+ ps8640_read(client, PAGE2_SPI_STATUS, &spi_rdy_st, 1);
+ if ((spi_rdy_st & SPI_READY) != SPI_READY)
+ break;
+
+ if (ktime_compare(ktime_get(), timeout) > 0) {
+ dev_err(&client->dev, "wait spi ready timeout\n");
+ return -EBUSY;
+ }
+
+ msleep(20);
+ }
+
+ return 0;
+}
+
+static int ps8640_wait_spi_nobusy(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+ u8 spi_status, buf[3] = { PAGE2_SWSPI_LEN, 0, TRIGGER_READBACK };
+ int ret;
+ ktime_t timeout;
+
+ timeout = ktime_add_ms(ktime_get(), 500);
+ for (;;) {
+ /* 0x05 RDSR; Read-Status-Register */
+ ret = ps8640_write_byte(client, PAGE2_SWSPI_WDATA,
+ READ_STATUS_REG_CMD);
+ if (ret)
+ goto err_send_cmd_exit;
+
+ ret = ps8640_write_bytes(client, buf, 3);
+ if (ret)
+ goto err_send_cmd_exit;
+
+ /* delay for cmd send */
+ usleep_range(300, 500);
+ /* wait for SPI ROM until not busy */
+ ret = ps8640_read(client, PAGE2_SWSPI_RDATA, &spi_status, 1);
+ if (ret)
+ goto err_send_cmd_exit;
+
+ if (!(spi_status & BUSY))
+ break;
+
+ if (ktime_compare(ktime_get(), timeout) > 0) {
+ dev_err(&client->dev, "wait spi no busy timeout: %d\n",
+ ret);
+ return -EBUSY;
+ }
+ }
+
+ return 0;
+
+err_send_cmd_exit:
+ dev_err(&client->dev, "send command err: %d\n", ret);
+ return ret;
+}
+
+static int ps8640_wait_rom_idle(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE0_DP_CNTL];
+ int ret;
+
+ ret = ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_ENABLE);
+ if (ret)
+ goto exit;
+
+ ret = ps8640_wait_spi_ready(ps_bridge);
+ if (ret)
+ goto err_spi;
+
+ ret = ps8640_wait_spi_nobusy(ps_bridge);
+ if (ret)
+ goto err_spi;
+
+ ret = ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_DISABLE);
+ if (ret)
+ goto exit;
+
+ return 0;
+
+err_spi:
+ ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_DISABLE);
+exit:
+ dev_err(&client->dev, "wait ps8640 rom idle fail: %d\n", ret);
+
+ return ret;
+}
+
+static int ps8640_spi_dl_mode(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+ int ret;
+
+ /* switch ps8640 mode to spi dl mode */
+ if (ps_bridge->gpio_mode_sel)
+ gpiod_set_value(ps_bridge->gpio_mode_sel, 0);
+
+ /* reset spi interface */
+ ret = ps8640_write_byte(client, PAGE2_SW_RESET,
+ SPI_SW_RESET | MPU_SW_RESET);
+ if (ret)
+ goto exit;
+
+ ret = ps8640_write_byte(client, PAGE2_SW_RESET, MPU_SW_RESET);
+ if (ret)
+ goto exit;
+
+ return 0;
+
+exit:
+ dev_err(&client->dev, "fail reset spi interface: %d\n", ret);
+
+ return ret;
+}
+
+static int ps8640_rom_prepare(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+ struct device *dev = &client->dev;
+ u8 i, cmd[2];
+ int ret;
+
+ cmd[0] = WRITE_ENABLE_CMD;
+ ret = ps8640_spi_send_cmd(ps_bridge, cmd, 1);
+ if (ret) {
+ dev_err(dev, "failed enable-write-status-register: %d\n", ret);
+ return ret;
+ }
+
+ cmd[0] = WRITE_STATUS_REG_CMD;
+ cmd[1] = CLEAR_ALL_PROTECT;
+ ret = ps8640_spi_send_cmd(ps_bridge, cmd, 2);
+ if (ret) {
+ dev_err(dev, "fail disable all protection: %d\n", ret);
+ return ret;
+ }
+
+ /* wait for SPI module ready */
+ ret = ps8640_wait_rom_idle(ps_bridge);
+ if (ret) {
+ dev_err(dev, "fail wait rom idle: %d\n", ret);
+ return ret;
+ }
+
+ ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_ENABLE);
+ for (i = 0; i < ARRAY_SIZE(enc_ctrl_code); i++)
+ ps8640_write_byte(client, PAGE2_ENCTLSPI_WR, enc_ctrl_code[i]);
+ ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_DISABLE);
+
+ /* Enable-Write-Status-Register */
+ cmd[0] = WRITE_ENABLE_CMD;
+ ret = ps8640_spi_send_cmd(ps_bridge, cmd, 1);
+ if (ret) {
+ dev_err(dev, "fail enable-write-status-register: %d\n", ret);
+ return ret;
+ }
+
+ /* chip erase command */
+ cmd[0] = CHIP_ERASE_CMD;
+ ret = ps8640_spi_send_cmd(ps_bridge, cmd, 1);
+ if (ret) {
+ dev_err(dev, "fail disable all protection: %d\n", ret);
+ return ret;
+ }
+
+ ret = ps8640_wait_rom_idle(ps_bridge);
+ if (ret) {
+ dev_err(dev, "fail wait rom idle: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ps8640_check_chip_id(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE4_MIPI_PHY];
+ u8 buf[4];
+
+ ps8640_read(client, PAGE4_REV_L, buf, 4);
+ return memcmp(buf, hw_chip_id, sizeof(buf));
+}
+
+static int ps8640_validate_firmware(struct ps8640 *ps_bridge,
+ const struct firmware *fw)
+{
+ struct i2c_client *client = ps_bridge->page[0];
+ u16 fw_chip_id;
+
+ /*
+ * Get the chip_id from the firmware. Make sure that it is the
+ * right controller to do the firmware and config update.
+ */
+ fw_chip_id = get_unaligned_le16(fw->data + FW_CHIP_ID_OFFSET);
+
+ if (fw_chip_id != 0x8640 && ps8640_check_chip_id(ps_bridge) == 0) {
+ dev_err(&client->dev,
+ "chip id mismatch: fw 0x%x vs. chip 0x8640\n",
+ fw_chip_id);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int ps8640_write_rom(struct ps8640 *ps_bridge, const struct firmware *fw)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE0_DP_CNTL];
+ struct device *dev = &client->dev;
+ struct i2c_client *client2 = ps_bridge->page[PAGE2_TOP_CNTL];
+ struct i2c_client *client7 = ps_bridge->page[PAGE7_SPI_CNTL];
+ size_t pos, cpy_len;
+ u8 buf[257];
+ int ret;
+
+ ps8640_write_byte(client2, PAGE2_SPI_CFG3, I2C_TO_SPI_RESET);
+ msleep(100);
+ ps8640_write_byte(client2, PAGE2_SPI_CFG3, 0x00);
+
+ for (pos = 0; pos < fw->size; pos += cpy_len) {
+ buf[0] = PAGE2_ROMADD_BYTE1;
+ buf[1] = pos >> 8;
+ buf[2] = pos >> 16;
+ ret = ps8640_write_bytes(client2, buf, 3);
+ if (ret)
+ goto error;
+ cpy_len = fw->size >= 256 + pos ? 256 : fw->size - pos;
+ buf[0] = 0;
+ memcpy(buf + 1, fw->data + pos, cpy_len);
+ ret = ps8640_write_bytes(client7, buf, cpy_len + 1);
+ if (ret)
+ goto error;
+
+ dev_dbg(dev, "fw update completed %zu / %zu bytes\n", pos,
+ fw->size);
+ }
+ return 0;
+
+error:
+ dev_err(dev, "failed write external flash, %d\n", ret);
+ return ret;
+}
+
+static int ps8640_spi_normal_mode(struct ps8640 *ps_bridge)
+{
+ u8 cmd[2];
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+
+ /* Enable-Write-Status-Register */
+ cmd[0] = WRITE_ENABLE_CMD;
+ ps8640_spi_send_cmd(ps_bridge, cmd, 1);
+
+ /* protect BPL/BP0/BP1 */
+ cmd[0] = WRITE_STATUS_REG_CMD;
+ cmd[1] = BLK_PROTECT_BITS | STATUS_REG_PROTECT;
+ ps8640_spi_send_cmd(ps_bridge, cmd, 2);
+
+ /* wait for SPI rom ready */
+ ps8640_wait_rom_idle(ps_bridge);
+
+ /* disable PS8640 mapping function */
+ ps8640_write_byte(client, PAGE2_ENCTLSPI_WR, 0x00);
+
+ if (ps_bridge->gpio_mode_sel)
+ gpiod_set_value(ps_bridge->gpio_mode_sel, 1);
+ return 0;
+}
+
+static int ps8640_enter_bl(struct ps8640 *ps_bridge)
+{
+ ps_bridge->in_fw_update = true;
+ return ps8640_spi_dl_mode(ps_bridge);
+}
+
+static void ps8640_exit_bl(struct ps8640 *ps_bridge, const struct firmware *fw)
+{
+ ps8640_spi_normal_mode(ps_bridge);
+ ps_bridge->in_fw_update = false;
+}
+
+static int ps8640_load_fw(struct ps8640 *ps_bridge, const struct firmware *fw)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE0_DP_CNTL];
+ struct device *dev = &client->dev;
+ int ret;
+ bool ps8640_status_backup = ps_bridge->enabled;
+
+ ret = ps8640_validate_firmware(ps_bridge, fw);
+ if (ret)
+ return ret;
+
+ mutex_lock(&ps_bridge->fw_mutex);
+ if (!ps_bridge->in_fw_update) {
+ if (!ps8640_status_backup)
+ ps8640_pre_enable(&ps_bridge->bridge);
+
+ ret = ps8640_enter_bl(ps_bridge);
+ if (ret)
+ goto exit;
+ }
+
+ ret = ps8640_rom_prepare(ps_bridge);
+ if (ret)
+ goto exit;
+
+ ret = ps8640_write_rom(ps_bridge, fw);
+
+exit:
+ if (ret)
+ dev_err(dev, "Failed to load firmware, %d\n", ret);
+
+ ps8640_exit_bl(ps_bridge, fw);
+ if (!ps8640_status_backup)
+ ps8640_post_disable(&ps_bridge->bridge);
+ mutex_unlock(&ps_bridge->fw_mutex);
+ return ret;
+}
+
+static ssize_t ps8640_update_fw_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct ps8640 *ps_bridge = i2c_get_clientdata(client);
+ const struct firmware *fw;
+ int error;
+
+ error = request_firmware(&fw, PS_FW_NAME, dev);
+ if (error) {
+ dev_err(dev, "Unable to open firmware %s: %d\n",
+ PS_FW_NAME, error);
+ return error;
+ }
+
+ error = ps8640_load_fw(ps_bridge, fw);
+ if (error)
+ dev_err(dev, "The firmware update failed(%d)\n", error);
+ else
+ dev_info(dev, "The firmware update succeeded\n");
+
+ release_firmware(fw);
+ return error ? error : count;
+}
+
+static DEVICE_ATTR(fw_version, S_IRUGO, ps8640_fw_version_show, NULL);
+static DEVICE_ATTR(hw_version, S_IRUGO, ps8640_hw_version_show, NULL);
+static DEVICE_ATTR(update_fw, S_IWUSR, NULL, ps8640_update_fw_store);
+
+static struct attribute *ps8640_attrs[] = {
+ &dev_attr_fw_version.attr,
+ &dev_attr_hw_version.attr,
+ &dev_attr_update_fw.attr,
+ NULL
+};
+
+static const struct attribute_group ps8640_attr_group = {
+ .attrs = ps8640_attrs,
+};
+
+static void ps8640_remove_sysfs_group(void *data)
+{
+ struct ps8640 *ps_bridge = data;
+
+ sysfs_remove_group(&ps_bridge->page[0]->dev.kobj, &ps8640_attr_group);
+}
+
+static int ps8640_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct device *dev = &client->dev;
+ struct ps8640 *ps_bridge;
+ struct device_node *np = dev->of_node;
+ struct device_node *port, *out_ep;
+ struct device_node *panel_node = NULL;
+ int ret;
+ u32 i;
+
+ ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL);
+ if (!ps_bridge)
+ return -ENOMEM;
+
+ /* port@1 is ps8640 output port */
+ port = of_graph_get_port_by_id(np, 1);
+ if (port) {
+ out_ep = of_get_child_by_name(port, "endpoint");
+ of_node_put(port);
+ if (out_ep) {
+ panel_node = of_graph_get_remote_port_parent(out_ep);
+ of_node_put(out_ep);
+ }
+ }
+ if (panel_node) {
+ ps_bridge->panel = of_drm_find_panel(panel_node);
+ of_node_put(panel_node);
+ if (!ps_bridge->panel)
+ return -EPROBE_DEFER;
+ }
+
+ mutex_init(&ps_bridge->fw_mutex);
+ ps_bridge->supplies[0].supply = "vdd33";
+ ps_bridge->supplies[1].supply = "vdd12";
+ ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies),
+ ps_bridge->supplies);
+ if (ret) {
+ dev_info(dev, "failed to get regulators: %d\n", ret);
+ return ret;
+ }
+
+ ps_bridge->gpio_mode_sel = devm_gpiod_get_optional(&client->dev,
+ "mode-sel",
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(ps_bridge->gpio_mode_sel)) {
+ ret = PTR_ERR(ps_bridge->gpio_mode_sel);
+ dev_err(dev, "cannot get mode-sel %d\n", ret);
+ return ret;
+ }
+
+ ps_bridge->gpio_power_down = devm_gpiod_get(&client->dev, "sleep",
+ GPIOD_OUT_LOW);
+ if (IS_ERR(ps_bridge->gpio_power_down)) {
+ ret = PTR_ERR(ps_bridge->gpio_power_down);
+ dev_err(dev, "cannot get sleep: %d\n", ret);
+ return ret;
+ }
+
+ /*
+ * Request the reset pin low to avoid the bridge being
+ * initialized prematurely
+ */
+ ps_bridge->gpio_reset = devm_gpiod_get(&client->dev, "reset",
+ GPIOD_OUT_LOW);
+ if (IS_ERR(ps_bridge->gpio_reset)) {
+ ret = PTR_ERR(ps_bridge->gpio_reset);
+ dev_err(dev, "cannot get reset: %d\n", ret);
+ return ret;
+ }
+
+ ps_bridge->bridge.funcs = &ps8640_bridge_funcs;
+ ps_bridge->bridge.of_node = dev->of_node;
+
+ ps_bridge->page[0] = client;
+
+ /*
+ * ps8640 uses multiple addresses, use dummy devices for them
+ * page[0]: for DP control
+ * page[1]: for VIDEO Bridge
+ * page[2]: for control top
+ * page[3]: for DSI Link Control1
+ * page[4]: for MIPI Phy
+ * page[5]: for VPLL
+ * page[6]: for DSI Link Control2
+ * page[7]: for spi rom mapping
+ */
+ for (i = 1; i < MAX_DEVS; i++) {
+ ps_bridge->page[i] = i2c_new_dummy(client->adapter,
+ client->addr + i);
+ if (!ps_bridge->page[i]) {
+ dev_err(dev, "failed i2c dummy device, address%02x\n",
+ client->addr + i);
+ ret = -EBUSY;
+ goto exit_dummy;
+ }
+ }
+ i2c_set_clientdata(client, ps_bridge);
+
+ ret = sysfs_create_group(&client->dev.kobj, &ps8640_attr_group);
+ if (ret) {
+ dev_err(dev, "failed to create sysfs entries: %d\n", ret);
+ goto exit_dummy;
+ }
+
+ ret = devm_add_action(dev, ps8640_remove_sysfs_group, ps_bridge);
+ if (ret) {
+ dev_err(dev, "failed to add sysfs cleanup action: %d\n", ret);
+ goto exit_remove_sysfs;
+ }
+
+ ret = drm_bridge_add(&ps_bridge->bridge);
+ if (ret) {
+ dev_err(dev, "Failed to add bridge: %d\n", ret);
+ goto exit_remove_sysfs;
+ }
+ return 0;
+
+exit_remove_sysfs:
+ sysfs_remove_group(&ps_bridge->page[0]->dev.kobj, &ps8640_attr_group);
+exit_dummy:
+ while (--i)
+ i2c_unregister_device(ps_bridge->page[i]);
+ return ret;
+}
+
+static int ps8640_remove(struct i2c_client *client)
+{
+ struct ps8640 *ps_bridge = i2c_get_clientdata(client);
+ int i = MAX_DEVS;
+
+ drm_bridge_remove(&ps_bridge->bridge);
+ sysfs_remove_group(&ps_bridge->page[0]->dev.kobj, &ps8640_attr_group);
+ while (--i)
+ i2c_unregister_device(ps_bridge->page[i]);
+
+ return 0;
+}
+
+static const struct i2c_device_id ps8640_i2c_table[] = {
+ { "ps8640", 0 },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(i2c, ps8640_i2c_table);
+
+static const struct of_device_id ps8640_match[] = {
+ { .compatible = "parade,ps8640" },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, ps8640_match);
+
+static struct i2c_driver ps8640_driver = {
+ .id_table = ps8640_i2c_table,
+ .probe = ps8640_probe,
+ .remove = ps8640_remove,
+ .driver = {
+ .name = "ps8640",
+ .of_match_table = ps8640_match,
+ },
+};
+module_i2c_driver(ps8640_driver);
+
+MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
+MODULE_AUTHOR("CK Hu <ck.hu@mediatek.com>");
+MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver");
+MODULE_LICENSE("GPL v2");
--
1.7.9.5
^ permalink raw reply related
* Re: [PATCH net-next v2 3/5] ethtool: (uapi) Add ETHTOOL_PHY_DOWNSHIFT to PHY tunables
From: Andrew Lunn @ 2016-11-14 13:42 UTC (permalink / raw)
To: Allan W. Nielsen; +Cc: netdev, raju.lakkaraju
In-Reply-To: <1479115760-1182-4-git-send-email-allan.nielsen@microsemi.com>
On Mon, Nov 14, 2016 at 10:29:18AM +0100, Allan W. Nielsen wrote:
> From: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
>
> For operation in cabling environments that are incompatible with
> 1000BAST-T, PHY device may provide an automatic link speed downshift
> operation. When enabled, the device automatically changes its 1000BAST-T
> auto-negotiation to the next slower speed after a configured number of
> failed attempts at 1000BAST-T. This feature is useful in setting up in
> networks using older cable installations that include only pairs A and B,
> and not pairs C and D.
Hi Allan
A nitpick:
s/BAST/BASE/g
Otherwise, this is good.
Andrew
^ permalink raw reply
* [PATCH v18 1/2] Documentation: bridge: Add documentation for ps8640 DT properties
From: Jitao Shi @ 2016-11-14 13:41 UTC (permalink / raw)
To: David Airlie, Thierry Reding, Matthias Brugger
Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Jitao Shi, Ajay Kumar, Inki Dae, Rahul Sharma, Sean Paul,
Vincent Palatin, Andy Yan, Philipp Zabel, Russell King,
devicetree, linux-kernel, dri-devel, linux-arm-kernel,
linux-mediatek, srv_heupstream, Sascha Hauer, yingjoe.chen,
eddie.huang, cawa.cheng, bibby.hsieh, ck.hu, stonea168
Add documentation for DT properties supported by
ps8640 DSI-eDP converter.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
---
Changes since v17:
- No change.
Changes since v16:
- No change.
Changes since v15:
- No change.
Changes since v14:
- change mode-sel-gpios as optional.
---
.../devicetree/bindings/display/bridge/ps8640.txt | 44 ++++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/ps8640.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/ps8640.txt b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
new file mode 100644
index 0000000..7b13f92
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
@@ -0,0 +1,44 @@
+ps8640-bridge bindings
+
+Required properties:
+ - compatible: "parade,ps8640"
+ - reg: first page address of the bridge.
+ - sleep-gpios: OF device-tree gpio specification for PD pin.
+ - reset-gpios: OF device-tree gpio specification for reset pin.
+ - vdd12-supply: OF device-tree regulator specification for 1.2V power.
+ - vdd33-supply: OF device-tree regulator specification for 3.3V power.
+ - ports: The device node can contain video interface port nodes per
+ the video-interfaces bind[1]. For port@0,set the reg = <0> as
+ ps8640 dsi in and port@1,set the reg = <1> as ps8640 eDP out.
+
+Optional properties:
+ - mode-sel-gpios: OF device-tree gpio specification for mode-sel pin.
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+ edp-bridge@18 {
+ compatible = "parade,ps8640";
+ reg = <0x18>;
+ sleep-gpios = <&pio 116 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>;
+ mode-sel-gpios = <&pio 92 GPIO_ACTIVE_HIGH>;
+ vdd12-supply = <&ps8640_fixed_1v2>;
+ vdd33-supply = <&mt6397_vgp2_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ ps8640_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ ps8640_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
--
1.7.9.5
^ permalink raw reply related
* Re: [Qemu-devel] [PATCH 07/13] virtio-scsi: always use dataplane path if ioeventfd is active
From: Paolo Bonzini @ 2016-11-14 13:41 UTC (permalink / raw)
To: Alex Williamson; +Cc: cornelia.huck, famz, qemu-devel, stefanha, mst
In-Reply-To: <20161111140342.7825fd1b@t450s.home>
On 11/11/2016 22:03, Alex Williamson wrote:
> On Fri, 11 Nov 2016 21:24:33 +0100
> Paolo Bonzini <pbonzini@redhat.com> wrote:
>> If you can post a backtrace of all threads at the time of the hang, from
>> origin/master (so without vhost, and not at ad07cd6) that could help.
>
> Yes, it occurs with all of the vfio devices removed using VNC/Cirrus.
I cannot reproduce it anyway. :(
As you said on IRC it's a pretty standard "event loop doing nothing"
backtrace, so it seems that an eventfd write was lost.
Since I was lucky with the vhost patch, perhaps this can help:
diff --git a/hw/scsi/virtio-scsi-dataplane.c b/hw/scsi/virtio-scsi-dataplane.c
index f2ea29d..22d6cd5 100644
--- a/hw/scsi/virtio-scsi-dataplane.c
+++ b/hw/scsi/virtio-scsi-dataplane.c
@@ -202,13 +202,15 @@ void virtio_scsi_dataplane_stop(VirtIODevice *vdev)
aio_context_acquire(s->ctx);
virtio_scsi_clear_aio(s);
- aio_context_release(s->ctx);
-
- blk_drain_all(); /* ensure there are no in-flight requests */
for (i = 0; i < vs->conf.num_queues + 2; i++) {
+ VirtQueue *vq = virtio_get_queue(vdev, i);
virtio_bus_set_host_notifier(VIRTIO_BUS(qbus), i, false);
+ virtio_queue_host_notifier_aio_read(virtio_queue_get_guest_notifier(vq));
}
+ aio_context_release(s->ctx);
+
+ blk_drain_all(); /* ensure there are no in-flight requests */
/* Clean up guest notifier (irq) */
k->set_guest_notifiers(qbus->parent, vs->conf.num_queues + 2, false);
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 89b0b80..9c894d7 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -2018,7 +2018,7 @@ EventNotifier *virtio_queue_get_guest_notifier(VirtQueue *vq)
return &vq->guest_notifier;
}
-static void virtio_queue_host_notifier_aio_read(EventNotifier *n)
+void virtio_queue_host_notifier_aio_read(EventNotifier *n)
{
VirtQueue *vq = container_of(n, VirtQueue, host_notifier);
if (event_notifier_test_and_clear(n)) {
diff --git a/include/hw/virtio/virtio.h b/include/hw/virtio/virtio.h
index 35ede30..d3dfc69 100644
--- a/include/hw/virtio/virtio.h
+++ b/include/hw/virtio/virtio.h
@@ -274,6 +274,7 @@ int virtio_device_grab_ioeventfd(VirtIODevice *vdev);
void virtio_device_release_ioeventfd(VirtIODevice *vdev);
bool virtio_device_ioeventfd_enabled(VirtIODevice *vdev);
EventNotifier *virtio_queue_get_host_notifier(VirtQueue *vq);
+void virtio_queue_host_notifier_aio_read(EventNotifier *n);
void virtio_queue_host_notifier_read(EventNotifier *n);
void virtio_queue_aio_set_host_notifier_handler(VirtQueue *vq, AioContext *ctx,
void (*fn)(VirtIODevice *,
And if it doesn't work here is some printf debugging. It's pretty verbose but
the interesting part starts pretty much where you issue the virsh shutdown or
system_powerdown command:
diff --git a/hw/scsi/virtio-scsi-dataplane.c b/hw/scsi/virtio-scsi-dataplane.c
index f2ea29d..ec0f750 100644
--- a/hw/scsi/virtio-scsi-dataplane.c
+++ b/hw/scsi/virtio-scsi-dataplane.c
@@ -108,11 +108,13 @@ static void virtio_scsi_clear_aio(VirtIOSCSI *s)
VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(s);
int i;
+ printf("before clear\n");
virtio_queue_aio_set_host_notifier_handler(vs->ctrl_vq, s->ctx, NULL);
virtio_queue_aio_set_host_notifier_handler(vs->event_vq, s->ctx, NULL);
for (i = 0; i < vs->conf.num_queues; i++) {
virtio_queue_aio_set_host_notifier_handler(vs->cmd_vqs[i], s->ctx, NULL);
}
+ printf("after clear\n");
}
/* Context: QEMU global mutex held */
@@ -202,15 +204,20 @@ void virtio_scsi_dataplane_stop(VirtIODevice *vdev)
aio_context_acquire(s->ctx);
virtio_scsi_clear_aio(s);
- aio_context_release(s->ctx);
-
- blk_drain_all(); /* ensure there are no in-flight requests */
for (i = 0; i < vs->conf.num_queues + 2; i++) {
+ VirtQueue *vq = virtio_get_queue(vdev, i);
virtio_bus_set_host_notifier(VIRTIO_BUS(qbus), i, false);
+ virtio_queue_host_notifier_aio_read(virtio_queue_get_guest_notifier(vq));
}
+ aio_context_release(s->ctx);
+
+ printf("before drain\n");
+ blk_drain_all(); /* ensure there are no in-flight requests */
+ printf("after drain\n");
/* Clean up guest notifier (irq) */
+ printf("end of virtio_scsi_dataplane_stop\n");
k->set_guest_notifiers(qbus->parent, vs->conf.num_queues + 2, false);
s->dataplane_stopping = false;
s->dataplane_started = false;
diff --git a/hw/scsi/virtio-scsi.c b/hw/scsi/virtio-scsi.c
index 3e5ae6a..e8b83d4 100644
--- a/hw/scsi/virtio-scsi.c
+++ b/hw/scsi/virtio-scsi.c
@@ -75,6 +75,7 @@ static void virtio_scsi_complete_req(VirtIOSCSIReq *req)
}
if (req->sreq) {
+ printf("finish %x\n", req->sreq->tag);
req->sreq->hba_private = NULL;
scsi_req_unref(req->sreq);
}
@@ -549,6 +549,7 @@ static int virtio_scsi_handle_cmd_req_prepare(VirtIOSCSI *s, VirtIOSCSIReq *req)
return -ENOENT;
}
virtio_scsi_ctx_check(s, d);
+ printf("prepare %lx %x\n", req->req.cmd.tag, req->req.cmd.cdb[0]);
req->sreq = scsi_req_new(d, req->req.cmd.tag,
virtio_scsi_get_lun(req->req.cmd.lun),
req->req.cmd.cdb, req);
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index 62001b4..c75dec3 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -336,11 +336,13 @@ static int virtio_pci_ioeventfd_assign(DeviceState *d, EventNotifier *notifier,
static void virtio_pci_start_ioeventfd(VirtIOPCIProxy *proxy)
{
+ printf("start ioeventfd %s\n", object_class_get_name(object_get_class(OBJECT(proxy))));
virtio_bus_start_ioeventfd(&proxy->bus);
}
static void virtio_pci_stop_ioeventfd(VirtIOPCIProxy *proxy)
{
+ printf("stop ioeventfd %s\n", object_class_get_name(object_get_class(OBJECT(proxy))));
virtio_bus_stop_ioeventfd(&proxy->bus);
}
@@ -376,6 +378,7 @@ static void virtio_ioport_write(void *opaque, uint32_t addr, uint32_t val)
}
break;
case VIRTIO_PCI_STATUS:
+ printf("set status %s %x\n", object_class_get_name(object_get_class(OBJECT(proxy))), val & 0xFF);
if (!(val & VIRTIO_CONFIG_S_DRIVER_OK)) {
virtio_pci_stop_ioeventfd(proxy);
}
@@ -1274,6 +1277,7 @@ static void virtio_pci_common_write(void *opaque, hwaddr addr,
vdev->config_vector = val;
break;
case VIRTIO_PCI_COMMON_STATUS:
+ printf("set status %s %x\n", object_class_get_name(object_get_class(OBJECT(proxy))), (uint8_t)val);
if (!(val & VIRTIO_CONFIG_S_DRIVER_OK)) {
virtio_pci_stop_ioeventfd(proxy);
}
> Backtrace on all threads running 6bbcb76:
>
> Thread 7 (Thread 0x7f5734dff700 (LWP 13136)):
> #0 0x00007f5748adcbd0 in pthread_cond_wait@@GLIBC_2.3.2 () at ../sysdeps/unix/sysv/linux/x86_64/pthread_cond_wait.S:185
> #1 0x0000565105c1b5a1 in qemu_cond_wait (cond=0x565108c8f120, mutex=0x565108c8f150) at util/qemu-thread-posix.c:137
> #2 0x0000565105b2219b in vnc_worker_thread_loop (queue=0x565108c8f120) at ui/vnc-jobs.c:228
> #3 0x0000565105b226d1 in vnc_worker_thread (arg=0x565108c8f120) at ui/vnc-jobs.c:335
> #4 0x00007f5748ad75ca in start_thread (arg=0x7f5734dff700) at pthread_create.c:333
> #5 0x00007f57488110ed in clone () at ../sysdeps/unix/sysv/linux/x86_64/clone.S:109
>
> Thread 6 (Thread 0x7f5736bfe700 (LWP 13133)):
> #0 0x00007f5748806ce7 in ioctl () at ../sysdeps/unix/syscall-template.S:84
> #1 0x000056510579734e in kvm_vcpu_ioctl (cpu=0x565107b21b70, type=44672) at /net/gimli/home/alwillia/Work/qemu.git/kvm-all.c:2079
> #2 0x0000565105796cd5 in kvm_cpu_exec (cpu=0x565107b21b70) at /net/gimli/home/alwillia/Work/qemu.git/kvm-all.c:1929
> #3 0x000056510577dc58 in qemu_kvm_cpu_thread_fn (arg=0x565107b21b70) at /net/gimli/home/alwillia/Work/qemu.git/cpus.c:998
> #4 0x00007f5748ad75ca in start_thread (arg=0x7f5736bfe700) at pthread_create.c:333
> #5 0x00007f57488110ed in clone () at ../sysdeps/unix/sysv/linux/x86_64/clone.S:109
>
> Thread 5 (Thread 0x7f57373ff700 (LWP 13132)):
> #0 0x00007f5748806ce7 in ioctl () at ../sysdeps/unix/syscall-template.S:84
> #1 0x000056510579734e in kvm_vcpu_ioctl (cpu=0x565107b02350, type=44672) at /net/gimli/home/alwillia/Work/qemu.git/kvm-all.c:2079
> #2 0x0000565105796cd5 in kvm_cpu_exec (cpu=0x565107b02350) at /net/gimli/home/alwillia/Work/qemu.git/kvm-all.c:1929
> #3 0x000056510577dc58 in qemu_kvm_cpu_thread_fn (arg=0x565107b02350) at /net/gimli/home/alwillia/Work/qemu.git/cpus.c:998
> #4 0x00007f5748ad75ca in start_thread (arg=0x7f57373ff700) at pthread_create.c:333
> #5 0x00007f57488110ed in clone () at ../sysdeps/unix/sysv/linux/x86_64/clone.S:109
>
> Thread 4 (Thread 0x7f5737c00700 (LWP 13131)):
> #0 0x00007f5748806ce7 in ioctl () at ../sysdeps/unix/syscall-template.S:84
> #1 0x000056510579734e in kvm_vcpu_ioctl (cpu=0x565107ae2b20, type=44672) at /net/gimli/home/alwillia/Work/qemu.git/kvm-all.c:2079
> #2 0x0000565105796cd5 in kvm_cpu_exec (cpu=0x565107ae2b20) at /net/gimli/home/alwillia/Work/qemu.git/kvm-all.c:1929
> #3 0x000056510577dc58 in qemu_kvm_cpu_thread_fn (arg=0x565107ae2b20) at /net/gimli/home/alwillia/Work/qemu.git/cpus.c:998
> #4 0x00007f5748ad75ca in start_thread (arg=0x7f5737c00700) at pthread_create.c:333
> #5 0x00007f57488110ed in clone () at ../sysdeps/unix/sysv/linux/x86_64/clone.S:109
>
> Thread 3 (Thread 0x7f5738401700 (LWP 13130)):
> #0 0x00007f5748806ce7 in ioctl () at ../sysdeps/unix/syscall-template.S:84
> #1 0x000056510579734e in kvm_vcpu_ioctl (cpu=0x565107a85270, type=44672) at /net/gimli/home/alwillia/Work/qemu.git/kvm-all.c:2079
> #2 0x0000565105796cd5 in kvm_cpu_exec (cpu=0x565107a85270) at /net/gimli/home/alwillia/Work/qemu.git/kvm-all.c:1929
> #3 0x000056510577dc58 in qemu_kvm_cpu_thread_fn (arg=0x565107a85270) at /net/gimli/home/alwillia/Work/qemu.git/cpus.c:998
> #4 0x00007f5748ad75ca in start_thread (arg=0x7f5738401700) at pthread_create.c:333
> #5 0x00007f57488110ed in clone () at ../sysdeps/unix/sysv/linux/x86_64/clone.S:109
>
> Thread 2 (Thread 0x7f573b221700 (LWP 13122)):
> #0 0x00007f574880b239 in syscall () at ../sysdeps/unix/sysv/linux/x86_64/syscall.S:38
> #1 0x0000565105c1b92f in futex_wait (ev=0x5651066c5624 <rcu_call_ready_event>, val=4294967295) at util/qemu-thread-posix.c:306
> #2 0x0000565105c1ba32 in qemu_event_wait (ev=0x5651066c5624 <rcu_call_ready_event>) at util/qemu-thread-posix.c:422
> #3 0x0000565105c31f30 in call_rcu_thread (opaque=0x0) at util/rcu.c:249
> #4 0x00007f5748ad75ca in start_thread (arg=0x7f573b221700) at pthread_create.c:333
> #5 0x00007f57488110ed in clone () at ../sysdeps/unix/sysv/linux/x86_64/clone.S:109
>
> Thread 1 (Thread 0x7f57638c4f80 (LWP 13114)):
> #0 0x00007f5748805631 in __GI_ppoll (fds=0x565108f6e6b0, nfds=13, timeout=<optimized out>, sigmask=0x0) at ../sysdeps/unix/sysv/linux/ppoll.c:50
> #1 0x0000565105b3b20b in qemu_poll_ns (fds=0x565108f6e6b0, nfds=13, timeout=2999772164) at qemu-timer.c:325
> #2 0x0000565105b3a630 in os_host_main_loop_wait (timeout=2999772164) at main-loop.c:254
> #3 0x0000565105b3a6f3 in main_loop_wait (nonblocking=0) at main-loop.c:508
> #4 0x00005651058c9d80 in main_loop () at vl.c:1966
> #5 0x00005651058d169e in main (argc=64, argv=0x7fff56193428, envp=0x7fff56193630) at vl.c:4684
>
>
^ permalink raw reply related
* [PATCH v18 2/2] drm/bridge: Add I2C based driver for ps8640 bridge
From: Jitao Shi @ 2016-11-14 13:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479130908-17593-1-git-send-email-jitao.shi@mediatek.com>
This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
Changes since v17:
- remove some unused head files.
- add macros for ps8640 pages.
- remove ddc_i2c client
- add mipi_dsi_device_register_full
- remove the manufacturer from the name and i2c_device_id
Changes since v16:
- Disable ps8640 DSI MCS Function.
- Rename gpios name more clearly.
- Tune the ps8640 power on sequence.
Changes since v15:
- Drop drm_connector_(un)register calls from parade ps8640.
The main DRM driver mtk_drm_drv now calls
drm_connector_register_all() after drm_dev_register() in the
mtk_drm_bind() function. That function should iterate over all
connectors and call drm_connector_register() for each of them.
So, remove drm_connector_(un)register calls from parade ps8640.
Changes since v14:
- update copyright info.
- change bridge_to_ps8640 and connector_to_ps8640 to inline function.
- fix some coding style.
- use sizeof as array counter.
- use drm_get_edid when read edid.
- add mutex when firmware updating.
Changes since v13:
- add const on data, ps8640_write_bytes(struct i2c_client *client, const u8 *data, u16 data_len)
- fix PAGE2_SW_REST tyro.
- move the buf[3] init to entrance of the function.
Changes since v12:
- fix hw_chip_id build warning
Changes since v11:
- Remove depends on I2C, add DRM depends
- Reuse ps8640_write_bytes() in ps8640_write_byte()
- Use timer check for polling like the routines in <linux/iopoll.h>
- Fix no drm_connector_unregister/drm_connector_cleanup when ps8640_bridge_attach fail
- Check the ps8640 hardware id in ps8640_validate_firmware
- Remove fw_version check
- Move ps8640_validate_firmware before ps8640_enter_bl
- Add ddc_i2c unregister when probe fail and ps8640_remove
---
drivers/gpu/drm/bridge/Kconfig | 12 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/parade-ps8640.c | 1079 ++++++++++++++++++++++++++++++++
3 files changed, 1092 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/parade-ps8640.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 10e12e7..7f41bbc 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -57,6 +57,18 @@ config DRM_PARADE_PS8622
---help---
Parade eDP-LVDS bridge chip driver.
+config DRM_PARADE_PS8640
+ tristate "Parade PS8640 MIPI DSI to eDP Converter"
+ depends on DRM
+ depends on OF
+ select DRM_KMS_HELPER
+ select DRM_MIPI_DSI
+ select DRM_PANEL
+ ---help---
+ Choose this option if you have PS8640 for display
+ The PS8640 is a high-performance and low-power
+ MIPI DSI to eDP converter
+
config DRM_SII902X
tristate "Silicon Image sii902x RGB/HDMI bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index cdf3a3c..7d93d40 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
+obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o
obj-$(CONFIG_DRM_SII902X) += sii902x.o
obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c
new file mode 100644
index 0000000..2d9c337
--- /dev/null
+++ b/drivers/gpu/drm/bridge/parade-ps8640.c
@@ -0,0 +1,1079 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/firmware.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/of_graph.h>
+#include <linux/regulator/consumer.h>
+#include <asm/unaligned.h>
+#include <drm/drm_panel.h>
+
+#include <drmP.h>
+#include <drm_atomic_helper.h>
+#include <drm_crtc_helper.h>
+#include <drm_edid.h>
+#include <drm_mipi_dsi.h>
+
+#define PAGE1_VSTART 0x6b
+#define PAGE2_SPI_CFG3 0x82
+#define I2C_TO_SPI_RESET 0x20
+#define PAGE2_ROMADD_BYTE1 0x8e
+#define PAGE2_ROMADD_BYTE2 0x8f
+#define PAGE2_SWSPI_WDATA 0x90
+#define PAGE2_SWSPI_RDATA 0x91
+#define PAGE2_SWSPI_LEN 0x92
+#define PAGE2_SWSPI_CTL 0x93
+#define TRIGGER_NO_READBACK 0x05
+#define TRIGGER_READBACK 0x01
+#define PAGE2_SPI_STATUS 0x9e
+#define SPI_READY 0x0c
+#define PAGE2_GPIO_L 0xa6
+#define PAGE2_GPIO_H 0xa7
+#define PS_GPIO9 BIT(1)
+#define PAGE2_IROM_CTRL 0xb0
+#define IROM_ENABLE 0xc0
+#define IROM_DISABLE 0x80
+#define PAGE2_SW_RESET 0xbc
+#define SPI_SW_RESET BIT(7)
+#define MPU_SW_RESET BIT(6)
+#define PAGE2_ENCTLSPI_WR 0xda
+#define PAGE2_I2C_BYPASS 0xea
+#define I2C_BYPASS_EN 0xd0
+#define PAGE2_MCS_EN 0xf3
+#define MCS_EN BIT(0)
+#define PAGE3_SET_ADD 0xfe
+#define PAGE3_SET_VAL 0xff
+#define VDO_CTL_ADD 0x13
+#define VDO_DIS 0x18
+#define VDO_EN 0x1c
+#define PAGE4_REV_L 0xf0
+#define PAGE4_REV_H 0xf1
+#define PAGE4_CHIP_L 0xf2
+#define PAGE4_CHIP_H 0xf3
+
+#define PAGE0_DP_CNTL 0
+#define PAGE1_VDO_BDG 1
+#define PAGE2_TOP_CNTL 2
+#define PAGE3_DSI_CNTL1 3
+#define PAGE4_MIPI_PHY 4
+#define PAGE5_VPLL 5
+#define PAGE6_DSI_CNTL2 6
+#define PAGE7_SPI_CNTL 7
+#define MAX_DEVS 0x8
+
+/* Firmware */
+#define PS_FW_NAME "ps864x_fw.bin"
+
+#define FW_CHIP_ID_OFFSET 0
+#define FW_VERSION_OFFSET 2
+#define EDID_I2C_ADDR 0x50
+
+#define WRITE_STATUS_REG_CMD 0x01
+#define READ_STATUS_REG_CMD 0x05
+#define BUSY BIT(0)
+#define CLEAR_ALL_PROTECT 0x00
+#define BLK_PROTECT_BITS 0x0c
+#define STATUS_REG_PROTECT BIT(7)
+#define WRITE_ENABLE_CMD 0x06
+#define CHIP_ERASE_CMD 0xc7
+
+struct ps8640_info {
+ u8 family_id;
+ u8 variant_id;
+ u16 version;
+};
+
+struct ps8640 {
+ struct drm_connector connector;
+ struct drm_bridge bridge;
+ struct edid *edid;
+ struct mipi_dsi_device *dsi;
+ struct i2c_client *page[MAX_DEVS];
+ struct regulator_bulk_data supplies[2];
+ struct drm_panel *panel;
+ struct gpio_desc *gpio_reset;
+ struct gpio_desc *gpio_power_down;
+ struct gpio_desc *gpio_mode_sel;
+ bool enabled;
+
+ /* firmware file info */
+ struct ps8640_info info;
+ bool in_fw_update;
+ /* for firmware update protect */
+ struct mutex fw_mutex;
+};
+
+static const u8 enc_ctrl_code[6] = { 0xaa, 0x55, 0x50, 0x41, 0x52, 0x44 };
+static const u8 hw_chip_id[4] = { 0x00, 0x0a, 0x00, 0x30 };
+
+static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e)
+{
+ return container_of(e, struct ps8640, bridge);
+}
+
+static inline struct ps8640 *connector_to_ps8640(struct drm_connector *e)
+{
+ return container_of(e, struct ps8640, connector);
+}
+
+static int ps8640_read(struct i2c_client *client, u8 reg, u8 *data,
+ u16 data_len)
+{
+ int ret;
+ struct i2c_msg msgs[] = {
+ {
+ .addr = client->addr,
+ .flags = 0,
+ .len = 1,
+ .buf = ®,
+ },
+ {
+ .addr = client->addr,
+ .flags = I2C_M_RD,
+ .len = data_len,
+ .buf = data,
+ }
+ };
+
+ ret = i2c_transfer(client->adapter, msgs, 2);
+
+ if (ret == 2)
+ return 0;
+ if (ret < 0)
+ return ret;
+ else
+ return -EIO;
+}
+
+static int ps8640_write_bytes(struct i2c_client *client, const u8 *data,
+ u16 data_len)
+{
+ int ret;
+ struct i2c_msg msg;
+
+ msg.addr = client->addr;
+ msg.flags = 0;
+ msg.len = data_len;
+ msg.buf = (u8 *)data;
+
+ ret = i2c_transfer(client->adapter, &msg, 1);
+ if (ret == 1)
+ return 0;
+ if (ret < 0)
+ return ret;
+ else
+ return -EIO;
+}
+
+static int ps8640_write_byte(struct i2c_client *client, u8 reg, u8 data)
+{
+ u8 buf[] = { reg, data };
+
+ return ps8640_write_bytes(client, buf, sizeof(buf));
+}
+
+static void ps8640_get_mcu_fw_version(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE5_VPLL];
+ u8 fw_ver[2];
+
+ ps8640_read(client, 0x4, fw_ver, sizeof(fw_ver));
+ ps_bridge->info.version = (fw_ver[0] << 8) | fw_ver[1];
+
+ DRM_INFO_ONCE("ps8640 rom fw version %d.%d\n", fw_ver[0], fw_ver[1]);
+}
+
+static int ps8640_bridge_unmute(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE3_DSI_CNTL1];
+ u8 vdo_ctrl_buf[3] = { PAGE3_SET_ADD, VDO_CTL_ADD, VDO_EN };
+
+ return ps8640_write_bytes(client, vdo_ctrl_buf, sizeof(vdo_ctrl_buf));
+}
+
+static int ps8640_bridge_mute(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE3_DSI_CNTL1];
+ u8 vdo_ctrl_buf[3] = { PAGE3_SET_ADD, VDO_CTL_ADD, VDO_DIS };
+
+ return ps8640_write_bytes(client, vdo_ctrl_buf, sizeof(vdo_ctrl_buf));
+}
+
+static void ps8640_pre_enable(struct drm_bridge *bridge)
+{
+ struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+ struct i2c_client *page1 = ps_bridge->page[PAGE1_VDO_BDG];
+ int err;
+ u8 set_vdo_done, mcs_en, vstart;
+ ktime_t timeout;
+
+ if (ps_bridge->in_fw_update)
+ return;
+
+ if (ps_bridge->enabled)
+ return;
+
+ err = drm_panel_prepare(ps_bridge->panel);
+ if (err < 0) {
+ DRM_ERROR("failed to prepare panel: %d\n", err);
+ return;
+ }
+
+ err = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies),
+ ps_bridge->supplies);
+ if (err < 0) {
+ DRM_ERROR("cannot enable regulators %d\n", err);
+ goto err_panel_unprepare;
+ }
+
+ gpiod_set_value(ps_bridge->gpio_power_down, 1);
+ gpiod_set_value(ps_bridge->gpio_reset, 0);
+ usleep_range(2000, 2500);
+ gpiod_set_value(ps_bridge->gpio_reset, 1);
+
+ /*
+ * Wait for the ps8640 embed mcu ready
+ * First wait 200ms and then check the mcu ready flag every 20ms
+ */
+ msleep(200);
+
+ timeout = ktime_add_ms(ktime_get(), 200);
+ for (;;) {
+ err = ps8640_read(client, PAGE2_GPIO_H, &set_vdo_done, 1);
+ if (err < 0) {
+ DRM_ERROR("failed read PAGE2_GPIO_H: %d\n", err);
+ goto err_regulators_disable;
+ }
+ if ((set_vdo_done & PS_GPIO9) == PS_GPIO9)
+ break;
+ if (ktime_compare(ktime_get(), timeout) > 0)
+ break;
+ msleep(20);
+ }
+
+ msleep(50);
+
+ ps8640_read(page1, PAGE1_VSTART, &vstart, 1);
+ DRM_INFO("PS8640 PAGE1.0x6B = 0x%x\n", vstart);
+
+ /**
+ * The Manufacturer Command Set (MCS) is a device dependent interface
+ * intended for factory programming of the display module default
+ * parameters. Once the display module is configured, the MCS shall be
+ * disabled by the manufacturer. Once disabled, all MCS commands are
+ * ignored by the display interface.
+ */
+ ps8640_read(client, PAGE2_MCS_EN, &mcs_en, 1);
+ ps8640_write_byte(client, PAGE2_MCS_EN, mcs_en & ~MCS_EN);
+
+ if (ps_bridge->info.version == 0)
+ ps8640_get_mcu_fw_version(ps_bridge);
+
+ err = ps8640_bridge_unmute(ps_bridge);
+ if (err)
+ DRM_ERROR("failed to enable unmutevideo: %d\n", err);
+ /* Switch access edp panel's edid through i2c */
+ ps8640_write_byte(client, PAGE2_I2C_BYPASS, I2C_BYPASS_EN);
+ ps_bridge->enabled = true;
+
+ return;
+
+err_regulators_disable:
+ regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
+ ps_bridge->supplies);
+err_panel_unprepare:
+ drm_panel_unprepare(ps_bridge->panel);
+}
+
+static void ps8640_enable(struct drm_bridge *bridge)
+{
+ struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
+ int err;
+
+ err = drm_panel_enable(ps_bridge->panel);
+ if (err < 0)
+ DRM_ERROR("failed to enable panel: %d\n", err);
+}
+
+static void ps8640_disable(struct drm_bridge *bridge)
+{
+ struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
+ int err;
+
+ err = drm_panel_disable(ps_bridge->panel);
+ if (err < 0)
+ DRM_ERROR("failed to disable panel: %d\n", err);
+}
+
+static void ps8640_post_disable(struct drm_bridge *bridge)
+{
+ struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
+ int err;
+
+ if (ps_bridge->in_fw_update)
+ return;
+
+ if (!ps_bridge->enabled)
+ return;
+
+ ps_bridge->enabled = false;
+
+ err = ps8640_bridge_mute(ps_bridge);
+ if (err < 0)
+ DRM_ERROR("failed to unmutevideo: %d\n", err);
+
+ gpiod_set_value(ps_bridge->gpio_reset, 0);
+ gpiod_set_value(ps_bridge->gpio_power_down, 0);
+ err = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
+ ps_bridge->supplies);
+ if (err < 0)
+ DRM_ERROR("cannot disable regulators %d\n", err);
+
+ err = drm_panel_unprepare(ps_bridge->panel);
+ if (err)
+ DRM_ERROR("failed to unprepare panel: %d\n", err);
+}
+
+static int ps8640_get_modes(struct drm_connector *connector)
+{
+ struct ps8640 *ps_bridge = connector_to_ps8640(connector);
+ struct edid *edid;
+ int num_modes = 0;
+ bool power_off;
+
+ if (ps_bridge->edid)
+ return drm_add_edid_modes(connector, ps_bridge->edid);
+
+ power_off = !ps_bridge->enabled;
+ ps8640_pre_enable(&ps_bridge->bridge);
+
+ edid = drm_get_edid(connector, ps_bridge->page[0]->adapter);
+ if (!edid)
+ goto out;
+
+ ps_bridge->edid = edid;
+ drm_mode_connector_update_edid_property(connector, ps_bridge->edid);
+ num_modes = drm_add_edid_modes(connector, ps_bridge->edid);
+
+out:
+ if (power_off)
+ ps8640_post_disable(&ps_bridge->bridge);
+
+ return num_modes;
+}
+
+static const struct drm_connector_helper_funcs ps8640_connector_helper_funcs = {
+ .get_modes = ps8640_get_modes,
+};
+
+static enum drm_connector_status ps8640_detect(struct drm_connector *connector,
+ bool force)
+{
+ return connector_status_connected;
+}
+
+static const struct drm_connector_funcs ps8640_connector_funcs = {
+ .dpms = drm_atomic_helper_connector_dpms,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .detect = ps8640_detect,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+int ps8640_bridge_attach(struct drm_bridge *bridge)
+{
+ struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
+ struct device *dev = &ps_bridge->page[0]->dev;
+ struct device_node *in_ep, *dsi_node = NULL;
+ struct mipi_dsi_device *dsi;
+ struct mipi_dsi_host *host = NULL;
+ int ret;
+ const struct mipi_dsi_device_info info = { .type = "ps8640",
+ .channel = 0,
+ .node = NULL,
+ };
+
+ ret = drm_connector_init(bridge->dev, &ps_bridge->connector,
+ &ps8640_connector_funcs,
+ DRM_MODE_CONNECTOR_eDP);
+
+ if (ret) {
+ DRM_ERROR("Failed to initialize connector with drm: %d\n", ret);
+ return ret;
+ }
+
+ drm_connector_helper_add(&ps_bridge->connector,
+ &ps8640_connector_helper_funcs);
+
+ ps_bridge->connector.dpms = DRM_MODE_DPMS_ON;
+ drm_mode_connector_attach_encoder(&ps_bridge->connector,
+ bridge->encoder);
+
+ if (ps_bridge->panel)
+ drm_panel_attach(ps_bridge->panel, &ps_bridge->connector);
+
+ /* port at 0 is ps8640 dsi input port */
+ in_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
+ if (in_ep) {
+ dsi_node = of_graph_get_remote_port_parent(in_ep);
+ of_node_put(in_ep);
+ }
+
+ if (dsi_node) {
+ host = of_find_mipi_dsi_host_by_node(dsi_node);
+ of_node_put(dsi_node);
+ if (!host) {
+ ret = -ENODEV;
+ goto err;
+ }
+ }
+
+ dsi = mipi_dsi_device_register_full(host, &info);
+ if (IS_ERR(dsi)) {
+ dev_err(dev, "failed to create dsi device\n");
+ ret = PTR_ERR(dsi);
+ goto err;
+ }
+
+ ps_bridge->dsi = dsi;
+
+ dsi->host = host;
+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
+ dsi->format = MIPI_DSI_FMT_RGB888;
+ dsi->lanes = 4;
+ ret = mipi_dsi_attach(dsi);
+ if (ret)
+ goto err_dsi_attach;
+
+ return 0;
+
+err_dsi_attach:
+ mipi_dsi_device_unregister(dsi);
+err:
+ if (ps_bridge->panel)
+ drm_panel_detach(ps_bridge->panel);
+ drm_connector_cleanup(&ps_bridge->connector);
+ return ret;
+}
+
+static const struct drm_bridge_funcs ps8640_bridge_funcs = {
+ .attach = ps8640_bridge_attach,
+ .disable = ps8640_disable,
+ .post_disable = ps8640_post_disable,
+ .pre_enable = ps8640_pre_enable,
+ .enable = ps8640_enable,
+};
+
+/* Firmware Version is returned as Major.Minor */
+static ssize_t ps8640_fw_version_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct ps8640 *ps_bridge = dev_get_drvdata(dev);
+ struct ps8640_info *info = &ps_bridge->info;
+
+ return scnprintf(buf, PAGE_SIZE, "%u.%u\n", info->version >> 8,
+ info->version & 0xff);
+}
+
+/* Hardware Version is returned as FamilyID.VariantID */
+static ssize_t ps8640_hw_version_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct ps8640 *ps_bridge = dev_get_drvdata(dev);
+ struct ps8640_info *info = &ps_bridge->info;
+
+ return scnprintf(buf, PAGE_SIZE, "ps%u.%u\n", info->family_id,
+ info->variant_id);
+}
+
+static int ps8640_spi_send_cmd(struct ps8640 *ps_bridge, u8 *cmd, u8 cmd_len)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+ u8 i, buf[3] = { PAGE2_SWSPI_LEN, cmd_len - 1, TRIGGER_NO_READBACK };
+ int ret;
+
+ ret = ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_ENABLE);
+ if (ret)
+ goto err;
+
+ /* write command in write port */
+ for (i = 0; i < cmd_len; i++) {
+ ret = ps8640_write_byte(client, PAGE2_SWSPI_WDATA, cmd[i]);
+ if (ret)
+ goto err_irom_disable;
+ }
+
+ ret = ps8640_write_bytes(client, buf, sizeof(buf));
+ if (ret)
+ goto err_irom_disable;
+
+ ret = ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_DISABLE);
+ if (ret)
+ goto err;
+
+ return 0;
+err_irom_disable:
+ ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_DISABLE);
+err:
+ dev_err(&client->dev, "send command err: %d\n", ret);
+ return ret;
+}
+
+static int ps8640_wait_spi_ready(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+ u8 spi_rdy_st;
+ ktime_t timeout;
+
+ timeout = ktime_add_ms(ktime_get(), 200);
+ for (;;) {
+ ps8640_read(client, PAGE2_SPI_STATUS, &spi_rdy_st, 1);
+ if ((spi_rdy_st & SPI_READY) != SPI_READY)
+ break;
+
+ if (ktime_compare(ktime_get(), timeout) > 0) {
+ dev_err(&client->dev, "wait spi ready timeout\n");
+ return -EBUSY;
+ }
+
+ msleep(20);
+ }
+
+ return 0;
+}
+
+static int ps8640_wait_spi_nobusy(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+ u8 spi_status, buf[3] = { PAGE2_SWSPI_LEN, 0, TRIGGER_READBACK };
+ int ret;
+ ktime_t timeout;
+
+ timeout = ktime_add_ms(ktime_get(), 500);
+ for (;;) {
+ /* 0x05 RDSR; Read-Status-Register */
+ ret = ps8640_write_byte(client, PAGE2_SWSPI_WDATA,
+ READ_STATUS_REG_CMD);
+ if (ret)
+ goto err_send_cmd_exit;
+
+ ret = ps8640_write_bytes(client, buf, 3);
+ if (ret)
+ goto err_send_cmd_exit;
+
+ /* delay for cmd send */
+ usleep_range(300, 500);
+ /* wait for SPI ROM until not busy */
+ ret = ps8640_read(client, PAGE2_SWSPI_RDATA, &spi_status, 1);
+ if (ret)
+ goto err_send_cmd_exit;
+
+ if (!(spi_status & BUSY))
+ break;
+
+ if (ktime_compare(ktime_get(), timeout) > 0) {
+ dev_err(&client->dev, "wait spi no busy timeout: %d\n",
+ ret);
+ return -EBUSY;
+ }
+ }
+
+ return 0;
+
+err_send_cmd_exit:
+ dev_err(&client->dev, "send command err: %d\n", ret);
+ return ret;
+}
+
+static int ps8640_wait_rom_idle(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE0_DP_CNTL];
+ int ret;
+
+ ret = ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_ENABLE);
+ if (ret)
+ goto exit;
+
+ ret = ps8640_wait_spi_ready(ps_bridge);
+ if (ret)
+ goto err_spi;
+
+ ret = ps8640_wait_spi_nobusy(ps_bridge);
+ if (ret)
+ goto err_spi;
+
+ ret = ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_DISABLE);
+ if (ret)
+ goto exit;
+
+ return 0;
+
+err_spi:
+ ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_DISABLE);
+exit:
+ dev_err(&client->dev, "wait ps8640 rom idle fail: %d\n", ret);
+
+ return ret;
+}
+
+static int ps8640_spi_dl_mode(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+ int ret;
+
+ /* switch ps8640 mode to spi dl mode */
+ if (ps_bridge->gpio_mode_sel)
+ gpiod_set_value(ps_bridge->gpio_mode_sel, 0);
+
+ /* reset spi interface */
+ ret = ps8640_write_byte(client, PAGE2_SW_RESET,
+ SPI_SW_RESET | MPU_SW_RESET);
+ if (ret)
+ goto exit;
+
+ ret = ps8640_write_byte(client, PAGE2_SW_RESET, MPU_SW_RESET);
+ if (ret)
+ goto exit;
+
+ return 0;
+
+exit:
+ dev_err(&client->dev, "fail reset spi interface: %d\n", ret);
+
+ return ret;
+}
+
+static int ps8640_rom_prepare(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+ struct device *dev = &client->dev;
+ u8 i, cmd[2];
+ int ret;
+
+ cmd[0] = WRITE_ENABLE_CMD;
+ ret = ps8640_spi_send_cmd(ps_bridge, cmd, 1);
+ if (ret) {
+ dev_err(dev, "failed enable-write-status-register: %d\n", ret);
+ return ret;
+ }
+
+ cmd[0] = WRITE_STATUS_REG_CMD;
+ cmd[1] = CLEAR_ALL_PROTECT;
+ ret = ps8640_spi_send_cmd(ps_bridge, cmd, 2);
+ if (ret) {
+ dev_err(dev, "fail disable all protection: %d\n", ret);
+ return ret;
+ }
+
+ /* wait for SPI module ready */
+ ret = ps8640_wait_rom_idle(ps_bridge);
+ if (ret) {
+ dev_err(dev, "fail wait rom idle: %d\n", ret);
+ return ret;
+ }
+
+ ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_ENABLE);
+ for (i = 0; i < ARRAY_SIZE(enc_ctrl_code); i++)
+ ps8640_write_byte(client, PAGE2_ENCTLSPI_WR, enc_ctrl_code[i]);
+ ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_DISABLE);
+
+ /* Enable-Write-Status-Register */
+ cmd[0] = WRITE_ENABLE_CMD;
+ ret = ps8640_spi_send_cmd(ps_bridge, cmd, 1);
+ if (ret) {
+ dev_err(dev, "fail enable-write-status-register: %d\n", ret);
+ return ret;
+ }
+
+ /* chip erase command */
+ cmd[0] = CHIP_ERASE_CMD;
+ ret = ps8640_spi_send_cmd(ps_bridge, cmd, 1);
+ if (ret) {
+ dev_err(dev, "fail disable all protection: %d\n", ret);
+ return ret;
+ }
+
+ ret = ps8640_wait_rom_idle(ps_bridge);
+ if (ret) {
+ dev_err(dev, "fail wait rom idle: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ps8640_check_chip_id(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE4_MIPI_PHY];
+ u8 buf[4];
+
+ ps8640_read(client, PAGE4_REV_L, buf, 4);
+ return memcmp(buf, hw_chip_id, sizeof(buf));
+}
+
+static int ps8640_validate_firmware(struct ps8640 *ps_bridge,
+ const struct firmware *fw)
+{
+ struct i2c_client *client = ps_bridge->page[0];
+ u16 fw_chip_id;
+
+ /*
+ * Get the chip_id from the firmware. Make sure that it is the
+ * right controller to do the firmware and config update.
+ */
+ fw_chip_id = get_unaligned_le16(fw->data + FW_CHIP_ID_OFFSET);
+
+ if (fw_chip_id != 0x8640 && ps8640_check_chip_id(ps_bridge) == 0) {
+ dev_err(&client->dev,
+ "chip id mismatch: fw 0x%x vs. chip 0x8640\n",
+ fw_chip_id);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int ps8640_write_rom(struct ps8640 *ps_bridge, const struct firmware *fw)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE0_DP_CNTL];
+ struct device *dev = &client->dev;
+ struct i2c_client *client2 = ps_bridge->page[PAGE2_TOP_CNTL];
+ struct i2c_client *client7 = ps_bridge->page[PAGE7_SPI_CNTL];
+ size_t pos, cpy_len;
+ u8 buf[257];
+ int ret;
+
+ ps8640_write_byte(client2, PAGE2_SPI_CFG3, I2C_TO_SPI_RESET);
+ msleep(100);
+ ps8640_write_byte(client2, PAGE2_SPI_CFG3, 0x00);
+
+ for (pos = 0; pos < fw->size; pos += cpy_len) {
+ buf[0] = PAGE2_ROMADD_BYTE1;
+ buf[1] = pos >> 8;
+ buf[2] = pos >> 16;
+ ret = ps8640_write_bytes(client2, buf, 3);
+ if (ret)
+ goto error;
+ cpy_len = fw->size >= 256 + pos ? 256 : fw->size - pos;
+ buf[0] = 0;
+ memcpy(buf + 1, fw->data + pos, cpy_len);
+ ret = ps8640_write_bytes(client7, buf, cpy_len + 1);
+ if (ret)
+ goto error;
+
+ dev_dbg(dev, "fw update completed %zu / %zu bytes\n", pos,
+ fw->size);
+ }
+ return 0;
+
+error:
+ dev_err(dev, "failed write external flash, %d\n", ret);
+ return ret;
+}
+
+static int ps8640_spi_normal_mode(struct ps8640 *ps_bridge)
+{
+ u8 cmd[2];
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+
+ /* Enable-Write-Status-Register */
+ cmd[0] = WRITE_ENABLE_CMD;
+ ps8640_spi_send_cmd(ps_bridge, cmd, 1);
+
+ /* protect BPL/BP0/BP1 */
+ cmd[0] = WRITE_STATUS_REG_CMD;
+ cmd[1] = BLK_PROTECT_BITS | STATUS_REG_PROTECT;
+ ps8640_spi_send_cmd(ps_bridge, cmd, 2);
+
+ /* wait for SPI rom ready */
+ ps8640_wait_rom_idle(ps_bridge);
+
+ /* disable PS8640 mapping function */
+ ps8640_write_byte(client, PAGE2_ENCTLSPI_WR, 0x00);
+
+ if (ps_bridge->gpio_mode_sel)
+ gpiod_set_value(ps_bridge->gpio_mode_sel, 1);
+ return 0;
+}
+
+static int ps8640_enter_bl(struct ps8640 *ps_bridge)
+{
+ ps_bridge->in_fw_update = true;
+ return ps8640_spi_dl_mode(ps_bridge);
+}
+
+static void ps8640_exit_bl(struct ps8640 *ps_bridge, const struct firmware *fw)
+{
+ ps8640_spi_normal_mode(ps_bridge);
+ ps_bridge->in_fw_update = false;
+}
+
+static int ps8640_load_fw(struct ps8640 *ps_bridge, const struct firmware *fw)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE0_DP_CNTL];
+ struct device *dev = &client->dev;
+ int ret;
+ bool ps8640_status_backup = ps_bridge->enabled;
+
+ ret = ps8640_validate_firmware(ps_bridge, fw);
+ if (ret)
+ return ret;
+
+ mutex_lock(&ps_bridge->fw_mutex);
+ if (!ps_bridge->in_fw_update) {
+ if (!ps8640_status_backup)
+ ps8640_pre_enable(&ps_bridge->bridge);
+
+ ret = ps8640_enter_bl(ps_bridge);
+ if (ret)
+ goto exit;
+ }
+
+ ret = ps8640_rom_prepare(ps_bridge);
+ if (ret)
+ goto exit;
+
+ ret = ps8640_write_rom(ps_bridge, fw);
+
+exit:
+ if (ret)
+ dev_err(dev, "Failed to load firmware, %d\n", ret);
+
+ ps8640_exit_bl(ps_bridge, fw);
+ if (!ps8640_status_backup)
+ ps8640_post_disable(&ps_bridge->bridge);
+ mutex_unlock(&ps_bridge->fw_mutex);
+ return ret;
+}
+
+static ssize_t ps8640_update_fw_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct ps8640 *ps_bridge = i2c_get_clientdata(client);
+ const struct firmware *fw;
+ int error;
+
+ error = request_firmware(&fw, PS_FW_NAME, dev);
+ if (error) {
+ dev_err(dev, "Unable to open firmware %s: %d\n",
+ PS_FW_NAME, error);
+ return error;
+ }
+
+ error = ps8640_load_fw(ps_bridge, fw);
+ if (error)
+ dev_err(dev, "The firmware update failed(%d)\n", error);
+ else
+ dev_info(dev, "The firmware update succeeded\n");
+
+ release_firmware(fw);
+ return error ? error : count;
+}
+
+static DEVICE_ATTR(fw_version, S_IRUGO, ps8640_fw_version_show, NULL);
+static DEVICE_ATTR(hw_version, S_IRUGO, ps8640_hw_version_show, NULL);
+static DEVICE_ATTR(update_fw, S_IWUSR, NULL, ps8640_update_fw_store);
+
+static struct attribute *ps8640_attrs[] = {
+ &dev_attr_fw_version.attr,
+ &dev_attr_hw_version.attr,
+ &dev_attr_update_fw.attr,
+ NULL
+};
+
+static const struct attribute_group ps8640_attr_group = {
+ .attrs = ps8640_attrs,
+};
+
+static void ps8640_remove_sysfs_group(void *data)
+{
+ struct ps8640 *ps_bridge = data;
+
+ sysfs_remove_group(&ps_bridge->page[0]->dev.kobj, &ps8640_attr_group);
+}
+
+static int ps8640_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct device *dev = &client->dev;
+ struct ps8640 *ps_bridge;
+ struct device_node *np = dev->of_node;
+ struct device_node *port, *out_ep;
+ struct device_node *panel_node = NULL;
+ int ret;
+ u32 i;
+
+ ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL);
+ if (!ps_bridge)
+ return -ENOMEM;
+
+ /* port at 1 is ps8640 output port */
+ port = of_graph_get_port_by_id(np, 1);
+ if (port) {
+ out_ep = of_get_child_by_name(port, "endpoint");
+ of_node_put(port);
+ if (out_ep) {
+ panel_node = of_graph_get_remote_port_parent(out_ep);
+ of_node_put(out_ep);
+ }
+ }
+ if (panel_node) {
+ ps_bridge->panel = of_drm_find_panel(panel_node);
+ of_node_put(panel_node);
+ if (!ps_bridge->panel)
+ return -EPROBE_DEFER;
+ }
+
+ mutex_init(&ps_bridge->fw_mutex);
+ ps_bridge->supplies[0].supply = "vdd33";
+ ps_bridge->supplies[1].supply = "vdd12";
+ ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies),
+ ps_bridge->supplies);
+ if (ret) {
+ dev_info(dev, "failed to get regulators: %d\n", ret);
+ return ret;
+ }
+
+ ps_bridge->gpio_mode_sel = devm_gpiod_get_optional(&client->dev,
+ "mode-sel",
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(ps_bridge->gpio_mode_sel)) {
+ ret = PTR_ERR(ps_bridge->gpio_mode_sel);
+ dev_err(dev, "cannot get mode-sel %d\n", ret);
+ return ret;
+ }
+
+ ps_bridge->gpio_power_down = devm_gpiod_get(&client->dev, "sleep",
+ GPIOD_OUT_LOW);
+ if (IS_ERR(ps_bridge->gpio_power_down)) {
+ ret = PTR_ERR(ps_bridge->gpio_power_down);
+ dev_err(dev, "cannot get sleep: %d\n", ret);
+ return ret;
+ }
+
+ /*
+ * Request the reset pin low to avoid the bridge being
+ * initialized prematurely
+ */
+ ps_bridge->gpio_reset = devm_gpiod_get(&client->dev, "reset",
+ GPIOD_OUT_LOW);
+ if (IS_ERR(ps_bridge->gpio_reset)) {
+ ret = PTR_ERR(ps_bridge->gpio_reset);
+ dev_err(dev, "cannot get reset: %d\n", ret);
+ return ret;
+ }
+
+ ps_bridge->bridge.funcs = &ps8640_bridge_funcs;
+ ps_bridge->bridge.of_node = dev->of_node;
+
+ ps_bridge->page[0] = client;
+
+ /*
+ * ps8640 uses multiple addresses, use dummy devices for them
+ * page[0]: for DP control
+ * page[1]: for VIDEO Bridge
+ * page[2]: for control top
+ * page[3]: for DSI Link Control1
+ * page[4]: for MIPI Phy
+ * page[5]: for VPLL
+ * page[6]: for DSI Link Control2
+ * page[7]: for spi rom mapping
+ */
+ for (i = 1; i < MAX_DEVS; i++) {
+ ps_bridge->page[i] = i2c_new_dummy(client->adapter,
+ client->addr + i);
+ if (!ps_bridge->page[i]) {
+ dev_err(dev, "failed i2c dummy device, address%02x\n",
+ client->addr + i);
+ ret = -EBUSY;
+ goto exit_dummy;
+ }
+ }
+ i2c_set_clientdata(client, ps_bridge);
+
+ ret = sysfs_create_group(&client->dev.kobj, &ps8640_attr_group);
+ if (ret) {
+ dev_err(dev, "failed to create sysfs entries: %d\n", ret);
+ goto exit_dummy;
+ }
+
+ ret = devm_add_action(dev, ps8640_remove_sysfs_group, ps_bridge);
+ if (ret) {
+ dev_err(dev, "failed to add sysfs cleanup action: %d\n", ret);
+ goto exit_remove_sysfs;
+ }
+
+ ret = drm_bridge_add(&ps_bridge->bridge);
+ if (ret) {
+ dev_err(dev, "Failed to add bridge: %d\n", ret);
+ goto exit_remove_sysfs;
+ }
+ return 0;
+
+exit_remove_sysfs:
+ sysfs_remove_group(&ps_bridge->page[0]->dev.kobj, &ps8640_attr_group);
+exit_dummy:
+ while (--i)
+ i2c_unregister_device(ps_bridge->page[i]);
+ return ret;
+}
+
+static int ps8640_remove(struct i2c_client *client)
+{
+ struct ps8640 *ps_bridge = i2c_get_clientdata(client);
+ int i = MAX_DEVS;
+
+ drm_bridge_remove(&ps_bridge->bridge);
+ sysfs_remove_group(&ps_bridge->page[0]->dev.kobj, &ps8640_attr_group);
+ while (--i)
+ i2c_unregister_device(ps_bridge->page[i]);
+
+ return 0;
+}
+
+static const struct i2c_device_id ps8640_i2c_table[] = {
+ { "ps8640", 0 },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(i2c, ps8640_i2c_table);
+
+static const struct of_device_id ps8640_match[] = {
+ { .compatible = "parade,ps8640" },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, ps8640_match);
+
+static struct i2c_driver ps8640_driver = {
+ .id_table = ps8640_i2c_table,
+ .probe = ps8640_probe,
+ .remove = ps8640_remove,
+ .driver = {
+ .name = "ps8640",
+ .of_match_table = ps8640_match,
+ },
+};
+module_i2c_driver(ps8640_driver);
+
+MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
+MODULE_AUTHOR("CK Hu <ck.hu@mediatek.com>");
+MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver");
+MODULE_LICENSE("GPL v2");
--
1.7.9.5
^ permalink raw reply related
* [PATCH v18 2/2] drm/bridge: Add I2C based driver for ps8640 bridge
From: Jitao Shi @ 2016-11-14 13:41 UTC (permalink / raw)
To: David Airlie, Thierry Reding, Matthias Brugger
Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Jitao Shi, Ajay Kumar, Inki Dae, Rahul Sharma, Sean Paul,
Vincent Palatin, Andy Yan, Philipp Zabel, Russell King,
devicetree, linux-kernel, dri-devel, linux-arm-kernel,
linux-mediatek, srv_heupstream
In-Reply-To: <1479130908-17593-1-git-send-email-jitao.shi@mediatek.com>
This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
Changes since v17:
- remove some unused head files.
- add macros for ps8640 pages.
- remove ddc_i2c client
- add mipi_dsi_device_register_full
- remove the manufacturer from the name and i2c_device_id
Changes since v16:
- Disable ps8640 DSI MCS Function.
- Rename gpios name more clearly.
- Tune the ps8640 power on sequence.
Changes since v15:
- Drop drm_connector_(un)register calls from parade ps8640.
The main DRM driver mtk_drm_drv now calls
drm_connector_register_all() after drm_dev_register() in the
mtk_drm_bind() function. That function should iterate over all
connectors and call drm_connector_register() for each of them.
So, remove drm_connector_(un)register calls from parade ps8640.
Changes since v14:
- update copyright info.
- change bridge_to_ps8640 and connector_to_ps8640 to inline function.
- fix some coding style.
- use sizeof as array counter.
- use drm_get_edid when read edid.
- add mutex when firmware updating.
Changes since v13:
- add const on data, ps8640_write_bytes(struct i2c_client *client, const u8 *data, u16 data_len)
- fix PAGE2_SW_REST tyro.
- move the buf[3] init to entrance of the function.
Changes since v12:
- fix hw_chip_id build warning
Changes since v11:
- Remove depends on I2C, add DRM depends
- Reuse ps8640_write_bytes() in ps8640_write_byte()
- Use timer check for polling like the routines in <linux/iopoll.h>
- Fix no drm_connector_unregister/drm_connector_cleanup when ps8640_bridge_attach fail
- Check the ps8640 hardware id in ps8640_validate_firmware
- Remove fw_version check
- Move ps8640_validate_firmware before ps8640_enter_bl
- Add ddc_i2c unregister when probe fail and ps8640_remove
---
drivers/gpu/drm/bridge/Kconfig | 12 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/parade-ps8640.c | 1079 ++++++++++++++++++++++++++++++++
3 files changed, 1092 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/parade-ps8640.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 10e12e7..7f41bbc 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -57,6 +57,18 @@ config DRM_PARADE_PS8622
---help---
Parade eDP-LVDS bridge chip driver.
+config DRM_PARADE_PS8640
+ tristate "Parade PS8640 MIPI DSI to eDP Converter"
+ depends on DRM
+ depends on OF
+ select DRM_KMS_HELPER
+ select DRM_MIPI_DSI
+ select DRM_PANEL
+ ---help---
+ Choose this option if you have PS8640 for display
+ The PS8640 is a high-performance and low-power
+ MIPI DSI to eDP converter
+
config DRM_SII902X
tristate "Silicon Image sii902x RGB/HDMI bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index cdf3a3c..7d93d40 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
+obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o
obj-$(CONFIG_DRM_SII902X) += sii902x.o
obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c
new file mode 100644
index 0000000..2d9c337
--- /dev/null
+++ b/drivers/gpu/drm/bridge/parade-ps8640.c
@@ -0,0 +1,1079 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/firmware.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/of_graph.h>
+#include <linux/regulator/consumer.h>
+#include <asm/unaligned.h>
+#include <drm/drm_panel.h>
+
+#include <drmP.h>
+#include <drm_atomic_helper.h>
+#include <drm_crtc_helper.h>
+#include <drm_edid.h>
+#include <drm_mipi_dsi.h>
+
+#define PAGE1_VSTART 0x6b
+#define PAGE2_SPI_CFG3 0x82
+#define I2C_TO_SPI_RESET 0x20
+#define PAGE2_ROMADD_BYTE1 0x8e
+#define PAGE2_ROMADD_BYTE2 0x8f
+#define PAGE2_SWSPI_WDATA 0x90
+#define PAGE2_SWSPI_RDATA 0x91
+#define PAGE2_SWSPI_LEN 0x92
+#define PAGE2_SWSPI_CTL 0x93
+#define TRIGGER_NO_READBACK 0x05
+#define TRIGGER_READBACK 0x01
+#define PAGE2_SPI_STATUS 0x9e
+#define SPI_READY 0x0c
+#define PAGE2_GPIO_L 0xa6
+#define PAGE2_GPIO_H 0xa7
+#define PS_GPIO9 BIT(1)
+#define PAGE2_IROM_CTRL 0xb0
+#define IROM_ENABLE 0xc0
+#define IROM_DISABLE 0x80
+#define PAGE2_SW_RESET 0xbc
+#define SPI_SW_RESET BIT(7)
+#define MPU_SW_RESET BIT(6)
+#define PAGE2_ENCTLSPI_WR 0xda
+#define PAGE2_I2C_BYPASS 0xea
+#define I2C_BYPASS_EN 0xd0
+#define PAGE2_MCS_EN 0xf3
+#define MCS_EN BIT(0)
+#define PAGE3_SET_ADD 0xfe
+#define PAGE3_SET_VAL 0xff
+#define VDO_CTL_ADD 0x13
+#define VDO_DIS 0x18
+#define VDO_EN 0x1c
+#define PAGE4_REV_L 0xf0
+#define PAGE4_REV_H 0xf1
+#define PAGE4_CHIP_L 0xf2
+#define PAGE4_CHIP_H 0xf3
+
+#define PAGE0_DP_CNTL 0
+#define PAGE1_VDO_BDG 1
+#define PAGE2_TOP_CNTL 2
+#define PAGE3_DSI_CNTL1 3
+#define PAGE4_MIPI_PHY 4
+#define PAGE5_VPLL 5
+#define PAGE6_DSI_CNTL2 6
+#define PAGE7_SPI_CNTL 7
+#define MAX_DEVS 0x8
+
+/* Firmware */
+#define PS_FW_NAME "ps864x_fw.bin"
+
+#define FW_CHIP_ID_OFFSET 0
+#define FW_VERSION_OFFSET 2
+#define EDID_I2C_ADDR 0x50
+
+#define WRITE_STATUS_REG_CMD 0x01
+#define READ_STATUS_REG_CMD 0x05
+#define BUSY BIT(0)
+#define CLEAR_ALL_PROTECT 0x00
+#define BLK_PROTECT_BITS 0x0c
+#define STATUS_REG_PROTECT BIT(7)
+#define WRITE_ENABLE_CMD 0x06
+#define CHIP_ERASE_CMD 0xc7
+
+struct ps8640_info {
+ u8 family_id;
+ u8 variant_id;
+ u16 version;
+};
+
+struct ps8640 {
+ struct drm_connector connector;
+ struct drm_bridge bridge;
+ struct edid *edid;
+ struct mipi_dsi_device *dsi;
+ struct i2c_client *page[MAX_DEVS];
+ struct regulator_bulk_data supplies[2];
+ struct drm_panel *panel;
+ struct gpio_desc *gpio_reset;
+ struct gpio_desc *gpio_power_down;
+ struct gpio_desc *gpio_mode_sel;
+ bool enabled;
+
+ /* firmware file info */
+ struct ps8640_info info;
+ bool in_fw_update;
+ /* for firmware update protect */
+ struct mutex fw_mutex;
+};
+
+static const u8 enc_ctrl_code[6] = { 0xaa, 0x55, 0x50, 0x41, 0x52, 0x44 };
+static const u8 hw_chip_id[4] = { 0x00, 0x0a, 0x00, 0x30 };
+
+static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e)
+{
+ return container_of(e, struct ps8640, bridge);
+}
+
+static inline struct ps8640 *connector_to_ps8640(struct drm_connector *e)
+{
+ return container_of(e, struct ps8640, connector);
+}
+
+static int ps8640_read(struct i2c_client *client, u8 reg, u8 *data,
+ u16 data_len)
+{
+ int ret;
+ struct i2c_msg msgs[] = {
+ {
+ .addr = client->addr,
+ .flags = 0,
+ .len = 1,
+ .buf = ®,
+ },
+ {
+ .addr = client->addr,
+ .flags = I2C_M_RD,
+ .len = data_len,
+ .buf = data,
+ }
+ };
+
+ ret = i2c_transfer(client->adapter, msgs, 2);
+
+ if (ret == 2)
+ return 0;
+ if (ret < 0)
+ return ret;
+ else
+ return -EIO;
+}
+
+static int ps8640_write_bytes(struct i2c_client *client, const u8 *data,
+ u16 data_len)
+{
+ int ret;
+ struct i2c_msg msg;
+
+ msg.addr = client->addr;
+ msg.flags = 0;
+ msg.len = data_len;
+ msg.buf = (u8 *)data;
+
+ ret = i2c_transfer(client->adapter, &msg, 1);
+ if (ret == 1)
+ return 0;
+ if (ret < 0)
+ return ret;
+ else
+ return -EIO;
+}
+
+static int ps8640_write_byte(struct i2c_client *client, u8 reg, u8 data)
+{
+ u8 buf[] = { reg, data };
+
+ return ps8640_write_bytes(client, buf, sizeof(buf));
+}
+
+static void ps8640_get_mcu_fw_version(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE5_VPLL];
+ u8 fw_ver[2];
+
+ ps8640_read(client, 0x4, fw_ver, sizeof(fw_ver));
+ ps_bridge->info.version = (fw_ver[0] << 8) | fw_ver[1];
+
+ DRM_INFO_ONCE("ps8640 rom fw version %d.%d\n", fw_ver[0], fw_ver[1]);
+}
+
+static int ps8640_bridge_unmute(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE3_DSI_CNTL1];
+ u8 vdo_ctrl_buf[3] = { PAGE3_SET_ADD, VDO_CTL_ADD, VDO_EN };
+
+ return ps8640_write_bytes(client, vdo_ctrl_buf, sizeof(vdo_ctrl_buf));
+}
+
+static int ps8640_bridge_mute(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE3_DSI_CNTL1];
+ u8 vdo_ctrl_buf[3] = { PAGE3_SET_ADD, VDO_CTL_ADD, VDO_DIS };
+
+ return ps8640_write_bytes(client, vdo_ctrl_buf, sizeof(vdo_ctrl_buf));
+}
+
+static void ps8640_pre_enable(struct drm_bridge *bridge)
+{
+ struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+ struct i2c_client *page1 = ps_bridge->page[PAGE1_VDO_BDG];
+ int err;
+ u8 set_vdo_done, mcs_en, vstart;
+ ktime_t timeout;
+
+ if (ps_bridge->in_fw_update)
+ return;
+
+ if (ps_bridge->enabled)
+ return;
+
+ err = drm_panel_prepare(ps_bridge->panel);
+ if (err < 0) {
+ DRM_ERROR("failed to prepare panel: %d\n", err);
+ return;
+ }
+
+ err = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies),
+ ps_bridge->supplies);
+ if (err < 0) {
+ DRM_ERROR("cannot enable regulators %d\n", err);
+ goto err_panel_unprepare;
+ }
+
+ gpiod_set_value(ps_bridge->gpio_power_down, 1);
+ gpiod_set_value(ps_bridge->gpio_reset, 0);
+ usleep_range(2000, 2500);
+ gpiod_set_value(ps_bridge->gpio_reset, 1);
+
+ /*
+ * Wait for the ps8640 embed mcu ready
+ * First wait 200ms and then check the mcu ready flag every 20ms
+ */
+ msleep(200);
+
+ timeout = ktime_add_ms(ktime_get(), 200);
+ for (;;) {
+ err = ps8640_read(client, PAGE2_GPIO_H, &set_vdo_done, 1);
+ if (err < 0) {
+ DRM_ERROR("failed read PAGE2_GPIO_H: %d\n", err);
+ goto err_regulators_disable;
+ }
+ if ((set_vdo_done & PS_GPIO9) == PS_GPIO9)
+ break;
+ if (ktime_compare(ktime_get(), timeout) > 0)
+ break;
+ msleep(20);
+ }
+
+ msleep(50);
+
+ ps8640_read(page1, PAGE1_VSTART, &vstart, 1);
+ DRM_INFO("PS8640 PAGE1.0x6B = 0x%x\n", vstart);
+
+ /**
+ * The Manufacturer Command Set (MCS) is a device dependent interface
+ * intended for factory programming of the display module default
+ * parameters. Once the display module is configured, the MCS shall be
+ * disabled by the manufacturer. Once disabled, all MCS commands are
+ * ignored by the display interface.
+ */
+ ps8640_read(client, PAGE2_MCS_EN, &mcs_en, 1);
+ ps8640_write_byte(client, PAGE2_MCS_EN, mcs_en & ~MCS_EN);
+
+ if (ps_bridge->info.version == 0)
+ ps8640_get_mcu_fw_version(ps_bridge);
+
+ err = ps8640_bridge_unmute(ps_bridge);
+ if (err)
+ DRM_ERROR("failed to enable unmutevideo: %d\n", err);
+ /* Switch access edp panel's edid through i2c */
+ ps8640_write_byte(client, PAGE2_I2C_BYPASS, I2C_BYPASS_EN);
+ ps_bridge->enabled = true;
+
+ return;
+
+err_regulators_disable:
+ regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
+ ps_bridge->supplies);
+err_panel_unprepare:
+ drm_panel_unprepare(ps_bridge->panel);
+}
+
+static void ps8640_enable(struct drm_bridge *bridge)
+{
+ struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
+ int err;
+
+ err = drm_panel_enable(ps_bridge->panel);
+ if (err < 0)
+ DRM_ERROR("failed to enable panel: %d\n", err);
+}
+
+static void ps8640_disable(struct drm_bridge *bridge)
+{
+ struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
+ int err;
+
+ err = drm_panel_disable(ps_bridge->panel);
+ if (err < 0)
+ DRM_ERROR("failed to disable panel: %d\n", err);
+}
+
+static void ps8640_post_disable(struct drm_bridge *bridge)
+{
+ struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
+ int err;
+
+ if (ps_bridge->in_fw_update)
+ return;
+
+ if (!ps_bridge->enabled)
+ return;
+
+ ps_bridge->enabled = false;
+
+ err = ps8640_bridge_mute(ps_bridge);
+ if (err < 0)
+ DRM_ERROR("failed to unmutevideo: %d\n", err);
+
+ gpiod_set_value(ps_bridge->gpio_reset, 0);
+ gpiod_set_value(ps_bridge->gpio_power_down, 0);
+ err = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
+ ps_bridge->supplies);
+ if (err < 0)
+ DRM_ERROR("cannot disable regulators %d\n", err);
+
+ err = drm_panel_unprepare(ps_bridge->panel);
+ if (err)
+ DRM_ERROR("failed to unprepare panel: %d\n", err);
+}
+
+static int ps8640_get_modes(struct drm_connector *connector)
+{
+ struct ps8640 *ps_bridge = connector_to_ps8640(connector);
+ struct edid *edid;
+ int num_modes = 0;
+ bool power_off;
+
+ if (ps_bridge->edid)
+ return drm_add_edid_modes(connector, ps_bridge->edid);
+
+ power_off = !ps_bridge->enabled;
+ ps8640_pre_enable(&ps_bridge->bridge);
+
+ edid = drm_get_edid(connector, ps_bridge->page[0]->adapter);
+ if (!edid)
+ goto out;
+
+ ps_bridge->edid = edid;
+ drm_mode_connector_update_edid_property(connector, ps_bridge->edid);
+ num_modes = drm_add_edid_modes(connector, ps_bridge->edid);
+
+out:
+ if (power_off)
+ ps8640_post_disable(&ps_bridge->bridge);
+
+ return num_modes;
+}
+
+static const struct drm_connector_helper_funcs ps8640_connector_helper_funcs = {
+ .get_modes = ps8640_get_modes,
+};
+
+static enum drm_connector_status ps8640_detect(struct drm_connector *connector,
+ bool force)
+{
+ return connector_status_connected;
+}
+
+static const struct drm_connector_funcs ps8640_connector_funcs = {
+ .dpms = drm_atomic_helper_connector_dpms,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .detect = ps8640_detect,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+int ps8640_bridge_attach(struct drm_bridge *bridge)
+{
+ struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
+ struct device *dev = &ps_bridge->page[0]->dev;
+ struct device_node *in_ep, *dsi_node = NULL;
+ struct mipi_dsi_device *dsi;
+ struct mipi_dsi_host *host = NULL;
+ int ret;
+ const struct mipi_dsi_device_info info = { .type = "ps8640",
+ .channel = 0,
+ .node = NULL,
+ };
+
+ ret = drm_connector_init(bridge->dev, &ps_bridge->connector,
+ &ps8640_connector_funcs,
+ DRM_MODE_CONNECTOR_eDP);
+
+ if (ret) {
+ DRM_ERROR("Failed to initialize connector with drm: %d\n", ret);
+ return ret;
+ }
+
+ drm_connector_helper_add(&ps_bridge->connector,
+ &ps8640_connector_helper_funcs);
+
+ ps_bridge->connector.dpms = DRM_MODE_DPMS_ON;
+ drm_mode_connector_attach_encoder(&ps_bridge->connector,
+ bridge->encoder);
+
+ if (ps_bridge->panel)
+ drm_panel_attach(ps_bridge->panel, &ps_bridge->connector);
+
+ /* port@0 is ps8640 dsi input port */
+ in_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
+ if (in_ep) {
+ dsi_node = of_graph_get_remote_port_parent(in_ep);
+ of_node_put(in_ep);
+ }
+
+ if (dsi_node) {
+ host = of_find_mipi_dsi_host_by_node(dsi_node);
+ of_node_put(dsi_node);
+ if (!host) {
+ ret = -ENODEV;
+ goto err;
+ }
+ }
+
+ dsi = mipi_dsi_device_register_full(host, &info);
+ if (IS_ERR(dsi)) {
+ dev_err(dev, "failed to create dsi device\n");
+ ret = PTR_ERR(dsi);
+ goto err;
+ }
+
+ ps_bridge->dsi = dsi;
+
+ dsi->host = host;
+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
+ dsi->format = MIPI_DSI_FMT_RGB888;
+ dsi->lanes = 4;
+ ret = mipi_dsi_attach(dsi);
+ if (ret)
+ goto err_dsi_attach;
+
+ return 0;
+
+err_dsi_attach:
+ mipi_dsi_device_unregister(dsi);
+err:
+ if (ps_bridge->panel)
+ drm_panel_detach(ps_bridge->panel);
+ drm_connector_cleanup(&ps_bridge->connector);
+ return ret;
+}
+
+static const struct drm_bridge_funcs ps8640_bridge_funcs = {
+ .attach = ps8640_bridge_attach,
+ .disable = ps8640_disable,
+ .post_disable = ps8640_post_disable,
+ .pre_enable = ps8640_pre_enable,
+ .enable = ps8640_enable,
+};
+
+/* Firmware Version is returned as Major.Minor */
+static ssize_t ps8640_fw_version_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct ps8640 *ps_bridge = dev_get_drvdata(dev);
+ struct ps8640_info *info = &ps_bridge->info;
+
+ return scnprintf(buf, PAGE_SIZE, "%u.%u\n", info->version >> 8,
+ info->version & 0xff);
+}
+
+/* Hardware Version is returned as FamilyID.VariantID */
+static ssize_t ps8640_hw_version_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct ps8640 *ps_bridge = dev_get_drvdata(dev);
+ struct ps8640_info *info = &ps_bridge->info;
+
+ return scnprintf(buf, PAGE_SIZE, "ps%u.%u\n", info->family_id,
+ info->variant_id);
+}
+
+static int ps8640_spi_send_cmd(struct ps8640 *ps_bridge, u8 *cmd, u8 cmd_len)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+ u8 i, buf[3] = { PAGE2_SWSPI_LEN, cmd_len - 1, TRIGGER_NO_READBACK };
+ int ret;
+
+ ret = ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_ENABLE);
+ if (ret)
+ goto err;
+
+ /* write command in write port */
+ for (i = 0; i < cmd_len; i++) {
+ ret = ps8640_write_byte(client, PAGE2_SWSPI_WDATA, cmd[i]);
+ if (ret)
+ goto err_irom_disable;
+ }
+
+ ret = ps8640_write_bytes(client, buf, sizeof(buf));
+ if (ret)
+ goto err_irom_disable;
+
+ ret = ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_DISABLE);
+ if (ret)
+ goto err;
+
+ return 0;
+err_irom_disable:
+ ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_DISABLE);
+err:
+ dev_err(&client->dev, "send command err: %d\n", ret);
+ return ret;
+}
+
+static int ps8640_wait_spi_ready(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+ u8 spi_rdy_st;
+ ktime_t timeout;
+
+ timeout = ktime_add_ms(ktime_get(), 200);
+ for (;;) {
+ ps8640_read(client, PAGE2_SPI_STATUS, &spi_rdy_st, 1);
+ if ((spi_rdy_st & SPI_READY) != SPI_READY)
+ break;
+
+ if (ktime_compare(ktime_get(), timeout) > 0) {
+ dev_err(&client->dev, "wait spi ready timeout\n");
+ return -EBUSY;
+ }
+
+ msleep(20);
+ }
+
+ return 0;
+}
+
+static int ps8640_wait_spi_nobusy(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+ u8 spi_status, buf[3] = { PAGE2_SWSPI_LEN, 0, TRIGGER_READBACK };
+ int ret;
+ ktime_t timeout;
+
+ timeout = ktime_add_ms(ktime_get(), 500);
+ for (;;) {
+ /* 0x05 RDSR; Read-Status-Register */
+ ret = ps8640_write_byte(client, PAGE2_SWSPI_WDATA,
+ READ_STATUS_REG_CMD);
+ if (ret)
+ goto err_send_cmd_exit;
+
+ ret = ps8640_write_bytes(client, buf, 3);
+ if (ret)
+ goto err_send_cmd_exit;
+
+ /* delay for cmd send */
+ usleep_range(300, 500);
+ /* wait for SPI ROM until not busy */
+ ret = ps8640_read(client, PAGE2_SWSPI_RDATA, &spi_status, 1);
+ if (ret)
+ goto err_send_cmd_exit;
+
+ if (!(spi_status & BUSY))
+ break;
+
+ if (ktime_compare(ktime_get(), timeout) > 0) {
+ dev_err(&client->dev, "wait spi no busy timeout: %d\n",
+ ret);
+ return -EBUSY;
+ }
+ }
+
+ return 0;
+
+err_send_cmd_exit:
+ dev_err(&client->dev, "send command err: %d\n", ret);
+ return ret;
+}
+
+static int ps8640_wait_rom_idle(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE0_DP_CNTL];
+ int ret;
+
+ ret = ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_ENABLE);
+ if (ret)
+ goto exit;
+
+ ret = ps8640_wait_spi_ready(ps_bridge);
+ if (ret)
+ goto err_spi;
+
+ ret = ps8640_wait_spi_nobusy(ps_bridge);
+ if (ret)
+ goto err_spi;
+
+ ret = ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_DISABLE);
+ if (ret)
+ goto exit;
+
+ return 0;
+
+err_spi:
+ ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_DISABLE);
+exit:
+ dev_err(&client->dev, "wait ps8640 rom idle fail: %d\n", ret);
+
+ return ret;
+}
+
+static int ps8640_spi_dl_mode(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+ int ret;
+
+ /* switch ps8640 mode to spi dl mode */
+ if (ps_bridge->gpio_mode_sel)
+ gpiod_set_value(ps_bridge->gpio_mode_sel, 0);
+
+ /* reset spi interface */
+ ret = ps8640_write_byte(client, PAGE2_SW_RESET,
+ SPI_SW_RESET | MPU_SW_RESET);
+ if (ret)
+ goto exit;
+
+ ret = ps8640_write_byte(client, PAGE2_SW_RESET, MPU_SW_RESET);
+ if (ret)
+ goto exit;
+
+ return 0;
+
+exit:
+ dev_err(&client->dev, "fail reset spi interface: %d\n", ret);
+
+ return ret;
+}
+
+static int ps8640_rom_prepare(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+ struct device *dev = &client->dev;
+ u8 i, cmd[2];
+ int ret;
+
+ cmd[0] = WRITE_ENABLE_CMD;
+ ret = ps8640_spi_send_cmd(ps_bridge, cmd, 1);
+ if (ret) {
+ dev_err(dev, "failed enable-write-status-register: %d\n", ret);
+ return ret;
+ }
+
+ cmd[0] = WRITE_STATUS_REG_CMD;
+ cmd[1] = CLEAR_ALL_PROTECT;
+ ret = ps8640_spi_send_cmd(ps_bridge, cmd, 2);
+ if (ret) {
+ dev_err(dev, "fail disable all protection: %d\n", ret);
+ return ret;
+ }
+
+ /* wait for SPI module ready */
+ ret = ps8640_wait_rom_idle(ps_bridge);
+ if (ret) {
+ dev_err(dev, "fail wait rom idle: %d\n", ret);
+ return ret;
+ }
+
+ ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_ENABLE);
+ for (i = 0; i < ARRAY_SIZE(enc_ctrl_code); i++)
+ ps8640_write_byte(client, PAGE2_ENCTLSPI_WR, enc_ctrl_code[i]);
+ ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_DISABLE);
+
+ /* Enable-Write-Status-Register */
+ cmd[0] = WRITE_ENABLE_CMD;
+ ret = ps8640_spi_send_cmd(ps_bridge, cmd, 1);
+ if (ret) {
+ dev_err(dev, "fail enable-write-status-register: %d\n", ret);
+ return ret;
+ }
+
+ /* chip erase command */
+ cmd[0] = CHIP_ERASE_CMD;
+ ret = ps8640_spi_send_cmd(ps_bridge, cmd, 1);
+ if (ret) {
+ dev_err(dev, "fail disable all protection: %d\n", ret);
+ return ret;
+ }
+
+ ret = ps8640_wait_rom_idle(ps_bridge);
+ if (ret) {
+ dev_err(dev, "fail wait rom idle: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ps8640_check_chip_id(struct ps8640 *ps_bridge)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE4_MIPI_PHY];
+ u8 buf[4];
+
+ ps8640_read(client, PAGE4_REV_L, buf, 4);
+ return memcmp(buf, hw_chip_id, sizeof(buf));
+}
+
+static int ps8640_validate_firmware(struct ps8640 *ps_bridge,
+ const struct firmware *fw)
+{
+ struct i2c_client *client = ps_bridge->page[0];
+ u16 fw_chip_id;
+
+ /*
+ * Get the chip_id from the firmware. Make sure that it is the
+ * right controller to do the firmware and config update.
+ */
+ fw_chip_id = get_unaligned_le16(fw->data + FW_CHIP_ID_OFFSET);
+
+ if (fw_chip_id != 0x8640 && ps8640_check_chip_id(ps_bridge) == 0) {
+ dev_err(&client->dev,
+ "chip id mismatch: fw 0x%x vs. chip 0x8640\n",
+ fw_chip_id);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int ps8640_write_rom(struct ps8640 *ps_bridge, const struct firmware *fw)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE0_DP_CNTL];
+ struct device *dev = &client->dev;
+ struct i2c_client *client2 = ps_bridge->page[PAGE2_TOP_CNTL];
+ struct i2c_client *client7 = ps_bridge->page[PAGE7_SPI_CNTL];
+ size_t pos, cpy_len;
+ u8 buf[257];
+ int ret;
+
+ ps8640_write_byte(client2, PAGE2_SPI_CFG3, I2C_TO_SPI_RESET);
+ msleep(100);
+ ps8640_write_byte(client2, PAGE2_SPI_CFG3, 0x00);
+
+ for (pos = 0; pos < fw->size; pos += cpy_len) {
+ buf[0] = PAGE2_ROMADD_BYTE1;
+ buf[1] = pos >> 8;
+ buf[2] = pos >> 16;
+ ret = ps8640_write_bytes(client2, buf, 3);
+ if (ret)
+ goto error;
+ cpy_len = fw->size >= 256 + pos ? 256 : fw->size - pos;
+ buf[0] = 0;
+ memcpy(buf + 1, fw->data + pos, cpy_len);
+ ret = ps8640_write_bytes(client7, buf, cpy_len + 1);
+ if (ret)
+ goto error;
+
+ dev_dbg(dev, "fw update completed %zu / %zu bytes\n", pos,
+ fw->size);
+ }
+ return 0;
+
+error:
+ dev_err(dev, "failed write external flash, %d\n", ret);
+ return ret;
+}
+
+static int ps8640_spi_normal_mode(struct ps8640 *ps_bridge)
+{
+ u8 cmd[2];
+ struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
+
+ /* Enable-Write-Status-Register */
+ cmd[0] = WRITE_ENABLE_CMD;
+ ps8640_spi_send_cmd(ps_bridge, cmd, 1);
+
+ /* protect BPL/BP0/BP1 */
+ cmd[0] = WRITE_STATUS_REG_CMD;
+ cmd[1] = BLK_PROTECT_BITS | STATUS_REG_PROTECT;
+ ps8640_spi_send_cmd(ps_bridge, cmd, 2);
+
+ /* wait for SPI rom ready */
+ ps8640_wait_rom_idle(ps_bridge);
+
+ /* disable PS8640 mapping function */
+ ps8640_write_byte(client, PAGE2_ENCTLSPI_WR, 0x00);
+
+ if (ps_bridge->gpio_mode_sel)
+ gpiod_set_value(ps_bridge->gpio_mode_sel, 1);
+ return 0;
+}
+
+static int ps8640_enter_bl(struct ps8640 *ps_bridge)
+{
+ ps_bridge->in_fw_update = true;
+ return ps8640_spi_dl_mode(ps_bridge);
+}
+
+static void ps8640_exit_bl(struct ps8640 *ps_bridge, const struct firmware *fw)
+{
+ ps8640_spi_normal_mode(ps_bridge);
+ ps_bridge->in_fw_update = false;
+}
+
+static int ps8640_load_fw(struct ps8640 *ps_bridge, const struct firmware *fw)
+{
+ struct i2c_client *client = ps_bridge->page[PAGE0_DP_CNTL];
+ struct device *dev = &client->dev;
+ int ret;
+ bool ps8640_status_backup = ps_bridge->enabled;
+
+ ret = ps8640_validate_firmware(ps_bridge, fw);
+ if (ret)
+ return ret;
+
+ mutex_lock(&ps_bridge->fw_mutex);
+ if (!ps_bridge->in_fw_update) {
+ if (!ps8640_status_backup)
+ ps8640_pre_enable(&ps_bridge->bridge);
+
+ ret = ps8640_enter_bl(ps_bridge);
+ if (ret)
+ goto exit;
+ }
+
+ ret = ps8640_rom_prepare(ps_bridge);
+ if (ret)
+ goto exit;
+
+ ret = ps8640_write_rom(ps_bridge, fw);
+
+exit:
+ if (ret)
+ dev_err(dev, "Failed to load firmware, %d\n", ret);
+
+ ps8640_exit_bl(ps_bridge, fw);
+ if (!ps8640_status_backup)
+ ps8640_post_disable(&ps_bridge->bridge);
+ mutex_unlock(&ps_bridge->fw_mutex);
+ return ret;
+}
+
+static ssize_t ps8640_update_fw_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct ps8640 *ps_bridge = i2c_get_clientdata(client);
+ const struct firmware *fw;
+ int error;
+
+ error = request_firmware(&fw, PS_FW_NAME, dev);
+ if (error) {
+ dev_err(dev, "Unable to open firmware %s: %d\n",
+ PS_FW_NAME, error);
+ return error;
+ }
+
+ error = ps8640_load_fw(ps_bridge, fw);
+ if (error)
+ dev_err(dev, "The firmware update failed(%d)\n", error);
+ else
+ dev_info(dev, "The firmware update succeeded\n");
+
+ release_firmware(fw);
+ return error ? error : count;
+}
+
+static DEVICE_ATTR(fw_version, S_IRUGO, ps8640_fw_version_show, NULL);
+static DEVICE_ATTR(hw_version, S_IRUGO, ps8640_hw_version_show, NULL);
+static DEVICE_ATTR(update_fw, S_IWUSR, NULL, ps8640_update_fw_store);
+
+static struct attribute *ps8640_attrs[] = {
+ &dev_attr_fw_version.attr,
+ &dev_attr_hw_version.attr,
+ &dev_attr_update_fw.attr,
+ NULL
+};
+
+static const struct attribute_group ps8640_attr_group = {
+ .attrs = ps8640_attrs,
+};
+
+static void ps8640_remove_sysfs_group(void *data)
+{
+ struct ps8640 *ps_bridge = data;
+
+ sysfs_remove_group(&ps_bridge->page[0]->dev.kobj, &ps8640_attr_group);
+}
+
+static int ps8640_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct device *dev = &client->dev;
+ struct ps8640 *ps_bridge;
+ struct device_node *np = dev->of_node;
+ struct device_node *port, *out_ep;
+ struct device_node *panel_node = NULL;
+ int ret;
+ u32 i;
+
+ ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL);
+ if (!ps_bridge)
+ return -ENOMEM;
+
+ /* port@1 is ps8640 output port */
+ port = of_graph_get_port_by_id(np, 1);
+ if (port) {
+ out_ep = of_get_child_by_name(port, "endpoint");
+ of_node_put(port);
+ if (out_ep) {
+ panel_node = of_graph_get_remote_port_parent(out_ep);
+ of_node_put(out_ep);
+ }
+ }
+ if (panel_node) {
+ ps_bridge->panel = of_drm_find_panel(panel_node);
+ of_node_put(panel_node);
+ if (!ps_bridge->panel)
+ return -EPROBE_DEFER;
+ }
+
+ mutex_init(&ps_bridge->fw_mutex);
+ ps_bridge->supplies[0].supply = "vdd33";
+ ps_bridge->supplies[1].supply = "vdd12";
+ ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies),
+ ps_bridge->supplies);
+ if (ret) {
+ dev_info(dev, "failed to get regulators: %d\n", ret);
+ return ret;
+ }
+
+ ps_bridge->gpio_mode_sel = devm_gpiod_get_optional(&client->dev,
+ "mode-sel",
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(ps_bridge->gpio_mode_sel)) {
+ ret = PTR_ERR(ps_bridge->gpio_mode_sel);
+ dev_err(dev, "cannot get mode-sel %d\n", ret);
+ return ret;
+ }
+
+ ps_bridge->gpio_power_down = devm_gpiod_get(&client->dev, "sleep",
+ GPIOD_OUT_LOW);
+ if (IS_ERR(ps_bridge->gpio_power_down)) {
+ ret = PTR_ERR(ps_bridge->gpio_power_down);
+ dev_err(dev, "cannot get sleep: %d\n", ret);
+ return ret;
+ }
+
+ /*
+ * Request the reset pin low to avoid the bridge being
+ * initialized prematurely
+ */
+ ps_bridge->gpio_reset = devm_gpiod_get(&client->dev, "reset",
+ GPIOD_OUT_LOW);
+ if (IS_ERR(ps_bridge->gpio_reset)) {
+ ret = PTR_ERR(ps_bridge->gpio_reset);
+ dev_err(dev, "cannot get reset: %d\n", ret);
+ return ret;
+ }
+
+ ps_bridge->bridge.funcs = &ps8640_bridge_funcs;
+ ps_bridge->bridge.of_node = dev->of_node;
+
+ ps_bridge->page[0] = client;
+
+ /*
+ * ps8640 uses multiple addresses, use dummy devices for them
+ * page[0]: for DP control
+ * page[1]: for VIDEO Bridge
+ * page[2]: for control top
+ * page[3]: for DSI Link Control1
+ * page[4]: for MIPI Phy
+ * page[5]: for VPLL
+ * page[6]: for DSI Link Control2
+ * page[7]: for spi rom mapping
+ */
+ for (i = 1; i < MAX_DEVS; i++) {
+ ps_bridge->page[i] = i2c_new_dummy(client->adapter,
+ client->addr + i);
+ if (!ps_bridge->page[i]) {
+ dev_err(dev, "failed i2c dummy device, address%02x\n",
+ client->addr + i);
+ ret = -EBUSY;
+ goto exit_dummy;
+ }
+ }
+ i2c_set_clientdata(client, ps_bridge);
+
+ ret = sysfs_create_group(&client->dev.kobj, &ps8640_attr_group);
+ if (ret) {
+ dev_err(dev, "failed to create sysfs entries: %d\n", ret);
+ goto exit_dummy;
+ }
+
+ ret = devm_add_action(dev, ps8640_remove_sysfs_group, ps_bridge);
+ if (ret) {
+ dev_err(dev, "failed to add sysfs cleanup action: %d\n", ret);
+ goto exit_remove_sysfs;
+ }
+
+ ret = drm_bridge_add(&ps_bridge->bridge);
+ if (ret) {
+ dev_err(dev, "Failed to add bridge: %d\n", ret);
+ goto exit_remove_sysfs;
+ }
+ return 0;
+
+exit_remove_sysfs:
+ sysfs_remove_group(&ps_bridge->page[0]->dev.kobj, &ps8640_attr_group);
+exit_dummy:
+ while (--i)
+ i2c_unregister_device(ps_bridge->page[i]);
+ return ret;
+}
+
+static int ps8640_remove(struct i2c_client *client)
+{
+ struct ps8640 *ps_bridge = i2c_get_clientdata(client);
+ int i = MAX_DEVS;
+
+ drm_bridge_remove(&ps_bridge->bridge);
+ sysfs_remove_group(&ps_bridge->page[0]->dev.kobj, &ps8640_attr_group);
+ while (--i)
+ i2c_unregister_device(ps_bridge->page[i]);
+
+ return 0;
+}
+
+static const struct i2c_device_id ps8640_i2c_table[] = {
+ { "ps8640", 0 },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(i2c, ps8640_i2c_table);
+
+static const struct of_device_id ps8640_match[] = {
+ { .compatible = "parade,ps8640" },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, ps8640_match);
+
+static struct i2c_driver ps8640_driver = {
+ .id_table = ps8640_i2c_table,
+ .probe = ps8640_probe,
+ .remove = ps8640_remove,
+ .driver = {
+ .name = "ps8640",
+ .of_match_table = ps8640_match,
+ },
+};
+module_i2c_driver(ps8640_driver);
+
+MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
+MODULE_AUTHOR("CK Hu <ck.hu@mediatek.com>");
+MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver");
+MODULE_LICENSE("GPL v2");
--
1.7.9.5
^ permalink raw reply related
* [PATCH v18 1/2] Documentation: bridge: Add documentation for ps8640 DT properties
From: Jitao Shi @ 2016-11-14 13:41 UTC (permalink / raw)
To: linux-arm-kernel
Add documentation for DT properties supported by
ps8640 DSI-eDP converter.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
---
Changes since v17:
- No change.
Changes since v16:
- No change.
Changes since v15:
- No change.
Changes since v14:
- change mode-sel-gpios as optional.
---
.../devicetree/bindings/display/bridge/ps8640.txt | 44 ++++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/ps8640.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/ps8640.txt b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
new file mode 100644
index 0000000..7b13f92
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
@@ -0,0 +1,44 @@
+ps8640-bridge bindings
+
+Required properties:
+ - compatible: "parade,ps8640"
+ - reg: first page address of the bridge.
+ - sleep-gpios: OF device-tree gpio specification for PD pin.
+ - reset-gpios: OF device-tree gpio specification for reset pin.
+ - vdd12-supply: OF device-tree regulator specification for 1.2V power.
+ - vdd33-supply: OF device-tree regulator specification for 3.3V power.
+ - ports: The device node can contain video interface port nodes per
+ the video-interfaces bind[1]. For port at 0,set the reg = <0> as
+ ps8640 dsi in and port at 1,set the reg = <1> as ps8640 eDP out.
+
+Optional properties:
+ - mode-sel-gpios: OF device-tree gpio specification for mode-sel pin.
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+ edp-bridge at 18 {
+ compatible = "parade,ps8640";
+ reg = <0x18>;
+ sleep-gpios = <&pio 116 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>;
+ mode-sel-gpios = <&pio 92 GPIO_ACTIVE_HIGH>;
+ vdd12-supply = <&ps8640_fixed_1v2>;
+ vdd33-supply = <&mt6397_vgp2_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port at 0 {
+ reg = <0>;
+ ps8640_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ port at 1 {
+ reg = <1>;
+ ps8640_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
--
1.7.9.5
^ permalink raw reply related
* [PATCH v18 1/2] Documentation: bridge: Add documentation for ps8640 DT properties
From: Jitao Shi @ 2016-11-14 13:41 UTC (permalink / raw)
To: David Airlie, Thierry Reding, Matthias Brugger
Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Jitao Shi, Ajay Kumar, Inki Dae, Rahul Sharma, Sean Paul,
Vincent Palatin, Andy Yan, Philipp Zabel, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w
Add documentation for DT properties supported by
ps8640 DSI-eDP converter.
Signed-off-by: Jitao Shi <jitao.shi-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Reviewed-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
Changes since v17:
- No change.
Changes since v16:
- No change.
Changes since v15:
- No change.
Changes since v14:
- change mode-sel-gpios as optional.
---
.../devicetree/bindings/display/bridge/ps8640.txt | 44 ++++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/ps8640.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/ps8640.txt b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
new file mode 100644
index 0000000..7b13f92
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ps8640.txt
@@ -0,0 +1,44 @@
+ps8640-bridge bindings
+
+Required properties:
+ - compatible: "parade,ps8640"
+ - reg: first page address of the bridge.
+ - sleep-gpios: OF device-tree gpio specification for PD pin.
+ - reset-gpios: OF device-tree gpio specification for reset pin.
+ - vdd12-supply: OF device-tree regulator specification for 1.2V power.
+ - vdd33-supply: OF device-tree regulator specification for 3.3V power.
+ - ports: The device node can contain video interface port nodes per
+ the video-interfaces bind[1]. For port@0,set the reg = <0> as
+ ps8640 dsi in and port@1,set the reg = <1> as ps8640 eDP out.
+
+Optional properties:
+ - mode-sel-gpios: OF device-tree gpio specification for mode-sel pin.
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+ edp-bridge@18 {
+ compatible = "parade,ps8640";
+ reg = <0x18>;
+ sleep-gpios = <&pio 116 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>;
+ mode-sel-gpios = <&pio 92 GPIO_ACTIVE_HIGH>;
+ vdd12-supply = <&ps8640_fixed_1v2>;
+ vdd33-supply = <&mt6397_vgp2_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ ps8640_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ ps8640_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
--
1.7.9.5
--
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^ permalink raw reply related
* Re: [PATCH 0/2] Salvator-X: Add GPIO keys support
From: Laurent Pinchart @ 2016-11-14 13:41 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Laurent Pinchart, Linux-Renesas, Kieran Bingham
In-Reply-To: <CAMuHMdWwEoH79DnVwret7bK9i-f-tXfSVMRSQdk=k-Ps5PUMGQ@mail.gmail.com>
Hi Geert,
On Monday 14 Nov 2016 14:35:26 Geert Uytterhoeven wrote:
> On Mon, Nov 14, 2016 at 2:07 PM, Laurent Pinchart wrote:
> > This simple series adds GPIO keys support to both the H3- and M3-W-based
> > Salvator-X boards. Please see individual patches for details.
>
> Thanks for your series!
>
> The main reason I haven't sent out a similar series yet is because the GPIOs
> used for the 3 push buttons are shared with the 3 user LEDs. For each of
> them, you have to choose at DT time if you want to use them as buttons or
> as LEDs.
>
> On ULCB, the same issue is present. For those, we settled on 1 key and 2
> LEDs...
>
> Looking forward to more comments...
In theory the GPIOs could be shared by the gpio-keys and LED drivers in open-
drain mode. I'm not sure the GPIO subsystem supports that though.
--
Regards,
Laurent Pinchart
^ permalink raw reply
* Re: [PATCH] Add the support for setting wpan-ping interval
From: Stefan Schmidt @ 2016-11-14 13:41 UTC (permalink / raw)
To: Xue, Wenqian, linux-wpan@vger.kernel.org
In-Reply-To: <576133E7D398244EA0325FF7CE2A09E5CD56E161@G08CNEXMBPEKD02.g08.fujitsu.local>
Hello.
Thanks for your patch. Find my comments below.
On 14/11/16 04:09, Xue, Wenqian wrote:
> Hi, all
>
> Below shows my patch for the support to set wpan-ping interval, you can use the command `-I $interval(ms)` to set the interval value (default is 500ms).
> If you find some errors or unexpected affects on current kernel, please feel free to point it out and give me some advice, thank you all!
>
Please use git send-email to send patches. That way I can properly
review and more important apply and test them here.
Bonus points if you use a wpan-tools prefix in the patch like this:
git format-patch --subject-prefix="PATCH wpan-tools" ...
> diff --git a/wpan-ping.c b/wpan-ping.c
> index 2c63758..4a0f00d 100644
> --- a/wpan-ping.c
> +++ b/wpan-ping.c
> @@ -49,6 +49,7 @@
> #define IEEE802154_ADDR_LEN 8
> /* Set the dispatch header to not 6lowpan for compat */
> #define NOT_A_6LOWPAN_FRAME 0x00
> +#define DEFAULT_INTERVAL 500
>
> #define DEBUG 0
>
> @@ -96,6 +97,7 @@ struct config {
> int nl802154_id;
> struct sockaddr_ieee802154 src;
> struct sockaddr_ieee802154 dst;
> + unsigned short interval;
> };
>
> extern char *optarg;
> @@ -109,6 +111,7 @@ static void usage(const char *name) {
> "--count | -c number of packets\n"
> "--size | -s packet length\n"
> "--interface | -i listen on this interface (default wpan0)\n"
> + "--interval | -I wait interval milliseconds between sending each packet (default 500ms)\n"
Maybe write: wait interval in milliseconds between sending packets
(default 500ms)
> "--version | -v print out version\n"
> "--help | -h this usage text\n", name);
> }
> @@ -232,6 +235,27 @@ static int print_address(char *addr, uint8_t dst_extended[IEEE802154_ADDR_LEN])
> return 0;
> }
>
> +static void sleeping(struct timeval ping_start_time, struct timeval timeout)
> +{
> + struct timeval curr_time;
> + long sec, usec, interval_usec, timeout_usec;
> + long sleep_usec = 0;
> + gettimeofday(&curr_time, NULL);
> + sec = curr_time.tv_sec - ping_start_time.tv_sec;
> + usec = curr_time.tv_usec - ping_start_time.tv_usec;
> + if (usec < 0)
> + {
> + usec += 1000000;
> + sec--;
> + }
> + interval_usec = sec * 1000000 + usec;
> + timeout_usec = timeout.tv_sec * 1000000 + timeout.tv_usec;
> + if (interval_usec < timeout_usec){
> + sleep_usec = timeout_usec - interval_usec;
> + usleep(sleep_usec);
> + }
> +}
> +
> static int measure_roundtrip(struct config *conf, int sd) {
> unsigned char *buf;
> struct timeval start_time, end_time, timeout;
> @@ -256,9 +280,17 @@ static int measure_roundtrip(struct config *conf, int sd) {
> conf->dst.addr.short_addr, conf->dst.addr.pan_id, conf->packet_len);
> buf = (unsigned char *)malloc(MAX_PAYLOAD_LEN);
>
> - /* 500ms seconds packet receive timeout */
> - timeout.tv_sec = 0;
> - timeout.tv_usec = 500000;
> + /* default 500ms seconds packet receive timeout */
> + // timeout.tv_sec = 0;
> + // timeout.tv_usec = 500000;
Please do not leave commented out code here. You moved the default value
into a define and use it accordingly so you can safely remove this here.
> + if (conf->interval >= 1000){ // when interval is larger than 1s
No C++ style comments please. Use /* */
> + double intervalD = (conf->interval * 1.0) / 1000;
intervalD as variable name is not very nice. Please choose something else.
> + timeout.tv_sec = (int)intervalD;
> + timeout.tv_usec = (int)((intervalD - timeout.tv_sec) * 1000000);
> + } else {
> + timeout.tv_sec = 0;
> + timeout.tv_usec = conf->interval * 1000;
> + }
> ret = setsockopt(sd, SOL_SOCKET, SO_RCVTIMEO, (struct timeval *)&timeout,sizeof(struct timeval));
> if (ret < 0) {
> perror("setsockopt receive timeout");
> @@ -266,6 +298,7 @@ static int measure_roundtrip(struct config *conf, int sd) {
>
> count = 0;
> for (i = 0; i < conf->packets; i++) {
> + gettimeofday(&ping_start_time, NULL);
> generate_packet(buf, conf, i);
> seq_num = (buf[2] << 8)| buf[3];
> ret = sendto(sd, buf, conf->packet_len, 0, (struct sockaddr *)&conf->dst, sizeof(conf->dst));
> @@ -309,7 +342,9 @@ static int measure_roundtrip(struct config *conf, int sd) {
> fprintf(stdout, "%i bytes from 0x%04x seq=%i time=%.1f ms\n", ret,
> conf->dst.addr.short_addr, (int)seq_num, (float)usec/1000);
> } else
> - fprintf(stderr, "Hit 500 ms packet timeout\n");
> + fprintf(stderr, "Hit %d ms packet timeout\n", conf->interval);
> + // sleeping
>
C++ comment. See above.
+ sleeping(ping_start_time, timeout);
> }
>
> if (count)
> @@ -456,6 +491,9 @@ int main(int argc, char *argv[]) {
> /* Default to 65535 packets being sent */
> conf->packets = USHRT_MAX;
>
> + /* Default to 500ms for interval value */
> + conf->interval = DEFAULT_INTERVAL;
> +
> if (argc < 2) {
> usage(argv[0]);
> exit(1);
> @@ -464,9 +502,9 @@ int main(int argc, char *argv[]) {
> while (1) {
> #ifdef _GNU_SOURCE
> int opt_idx = -1;
> - c = getopt_long(argc, argv, "a:ec:s:i:dvh", perf_long_opts, &opt_idx);
> + c = getopt_long(argc, argv, "a:ec:s:i:dvhI:", perf_long_opts, &opt_idx);
> #else
> - c = getopt(argc, argv, "a:ec:s:i:dvh");
> + c = getopt(argc, argv, "a:ec:s:i:dvhI:");
> #endif
> if (c == -1)
> break;
> @@ -495,6 +533,9 @@ int main(int argc, char *argv[]) {
> case 'i':
> conf->interface = optarg;
> break;
> + case 'I':
> + conf->interval = atoi(optarg);
> + break;
> case 'v':
> fprintf(stdout, "wpan-ping " PACKAGE_VERSION "\n");
> free(conf);
>
Please change what I mentioned above and resend this patch with git
send-email. Write a good commit message and do not forgot the signed-off
line (-s for git format-patch can also generate this for you)
The change itself looks ok on a first glance at the code but I need to
actual compile and test it.
regards
Stefan Schmidt
^ permalink raw reply
* Re: [RFC v4 08/21] media: Enable allocating the media device dynamically
From: Sakari Ailus @ 2016-11-14 13:40 UTC (permalink / raw)
To: Shuah Khan
Cc: Sakari Ailus, linux-media, hverkuil, mchehab, shuahkh,
laurent.pinchart
In-Reply-To: <CAKocOONNR9NBszp5Qq+geRdR+qAD70GYXguN7c3Q0Ptoz0Vzhg@mail.gmail.com>
Hi Shuah,
On Tue, Nov 08, 2016 at 12:20:29PM -0700, Shuah Khan wrote:
> On Tue, Nov 8, 2016 at 6:55 AM, Sakari Ailus
> <sakari.ailus@linux.intel.com> wrote:
> > From: Sakari Ailus <sakari.ailus@iki.fi>
> >
> > Allow allocating the media device dynamically. As the struct media_device
> > embeds struct media_devnode, the lifetime of that object is that same than
> > that of the media_device.
> >
> > Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> > ---
> > drivers/media/media-device.c | 15 +++++++++++++++
> > include/media/media-device.h | 13 +++++++++++++
> > 2 files changed, 28 insertions(+)
> >
> > diff --git a/drivers/media/media-device.c b/drivers/media/media-device.c
> > index a31329d..496195e 100644
> > --- a/drivers/media/media-device.c
> > +++ b/drivers/media/media-device.c
> > @@ -684,6 +684,21 @@ void media_device_init(struct media_device *mdev)
> > }
> > EXPORT_SYMBOL_GPL(media_device_init);
> >
> > +struct media_device *media_device_alloc(struct device *dev)
> > +{
> > + struct media_device *mdev;
> > +
> > + mdev = kzalloc(sizeof(*mdev), GFP_KERNEL);
> > + if (!mdev)
> > + return NULL;
> > +
> > + mdev->dev = dev;
> > + media_device_init(mdev);
> > +
> > + return mdev;
> > +}
> > +EXPORT_SYMBOL_GPL(media_device_alloc);
> > +
>
> One problem with this allocation is, this media device can't be shared across
> drivers. For au0828 and snd-usb-audio should be able to share the
> media_device. That is what the Media Allocator API patch series does.
> This a quick review and I will review the patch series and get back to
> you.
The assumption has always been there that a media device has a single struct
device related to it. It hasn't been visible in the function call API
though, just in the data structures.
I have to admit I may have forgotten something that was discussed back then,
but do you need to share the same media device over multiple devices in the
system? I don't see that at least in the allocator patch itself. It's
"[PATCH v3] media: Media Device Allocator API", isn't it?
--
Kind regards,
Sakari Ailus
e-mail: sakari.ailus@iki.fi XMPP: sailus@retiisi.org.uk
^ permalink raw reply
* [PATCH v2] diffcore-delta: remove unused parameter to diffcore_count_changes()
From: Tobias Klauser @ 2016-11-14 13:39 UTC (permalink / raw)
To: git, gitster; +Cc: Jeff King
The delta_limit parameter to diffcore_count_changes() has been unused
since commit ba23bbc8e ("diffcore-delta: make change counter to byte
oriented again.", 2006-03-04).
Remove the parameter and adjust all callers.
Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
---
v2: In the commit message, reference the correct commit where the parameter
usage was removed. Spotted by Jeff King.
diff.c | 2 +-
diffcore-break.c | 1 -
diffcore-delta.c | 1 -
diffcore-rename.c | 4 ----
diffcore.h | 1 -
5 files changed, 1 insertion(+), 8 deletions(-)
diff --git a/diff.c b/diff.c
index 8981477c436d..ec8728362dae 100644
--- a/diff.c
+++ b/diff.c
@@ -2023,7 +2023,7 @@ static void show_dirstat(struct diff_options *options)
if (DIFF_FILE_VALID(p->one) && DIFF_FILE_VALID(p->two)) {
diff_populate_filespec(p->one, 0);
diff_populate_filespec(p->two, 0);
- diffcore_count_changes(p->one, p->two, NULL, NULL, 0,
+ diffcore_count_changes(p->one, p->two, NULL, NULL,
&copied, &added);
diff_free_filespec_data(p->one);
diff_free_filespec_data(p->two);
diff --git a/diffcore-break.c b/diffcore-break.c
index 881a74f29e4f..c64359f489c8 100644
--- a/diffcore-break.c
+++ b/diffcore-break.c
@@ -73,7 +73,6 @@ static int should_break(struct diff_filespec *src,
if (diffcore_count_changes(src, dst,
&src->cnt_data, &dst->cnt_data,
- 0,
&src_copied, &literal_added))
return 0;
diff --git a/diffcore-delta.c b/diffcore-delta.c
index 2ebedb32d18a..ebe70fb06851 100644
--- a/diffcore-delta.c
+++ b/diffcore-delta.c
@@ -166,7 +166,6 @@ int diffcore_count_changes(struct diff_filespec *src,
struct diff_filespec *dst,
void **src_count_p,
void **dst_count_p,
- unsigned long delta_limit,
unsigned long *src_copied,
unsigned long *literal_added)
{
diff --git a/diffcore-rename.c b/diffcore-rename.c
index 54a2396653df..f7444c86bde3 100644
--- a/diffcore-rename.c
+++ b/diffcore-rename.c
@@ -145,7 +145,6 @@ static int estimate_similarity(struct diff_filespec *src,
* call into this function in that case.
*/
unsigned long max_size, delta_size, base_size, src_copied, literal_added;
- unsigned long delta_limit;
int score;
/* We deal only with regular files. Symlink renames are handled
@@ -191,11 +190,8 @@ static int estimate_similarity(struct diff_filespec *src,
if (!dst->cnt_data && diff_populate_filespec(dst, 0))
return 0;
- delta_limit = (unsigned long)
- (base_size * (MAX_SCORE-minimum_score) / MAX_SCORE);
if (diffcore_count_changes(src, dst,
&src->cnt_data, &dst->cnt_data,
- delta_limit,
&src_copied, &literal_added))
return 0;
diff --git a/diffcore.h b/diffcore.h
index c11b8465fc8e..623024135478 100644
--- a/diffcore.h
+++ b/diffcore.h
@@ -142,7 +142,6 @@ extern int diffcore_count_changes(struct diff_filespec *src,
struct diff_filespec *dst,
void **src_count_p,
void **dst_count_p,
- unsigned long delta_limit,
unsigned long *src_copied,
unsigned long *literal_added);
--
2.9.0
^ permalink raw reply related
* Re: libdbus-c++
From: thilo.cestonaro @ 2016-11-14 13:33 UTC (permalink / raw)
To: ross.burton@intel.com; +Cc: openembedded-core@lists.openembedded.org
In-Reply-To: <CAJTo0LZ68DbpCMpHy=5AKuxsHNCjzw2vJMJBd1WC27VTga=fqg@mail.gmail.com>
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Am Montag, den 14.11.2016, 10:53 +0000 schrieb Burton, Ross:
>
> On 14 November 2016 at 10:33, thilo.cestonaro@ts.fujitsu.com <thilo.cestonaro@ts.fujitsu.com> wrote:
> > I wanted to build an executable using libdbus-c++ but OE-Core has no recipe providing libdbus-c++, please correct me if I'm wrong here!
> >
> > Is there a reason, other than no one wanted a recipe for libdbus-c++ yet, against the usage of dbus-c++ implementation or why isn't there a recipe for libdbus-c++?
> >
>
> There isn't a recipe in oe-core because nothing in oe-core needs it, and it isn't considered fundamental enough. It seems that every six months someone writes a recipe for dbus-c++ (because they
> have problems and ask for help on the lists) but nobody yet has actually submitted a recipe to meta-oe. You can be that person!
>
Yeah I propably can and will be if I need to write my own. But the funny thing is, that there ones was a meta-oe dbus-c++ recipe and this was removed with the comment, that it didn't work and it's
better to use the one from oe-core :)
http://lists.openembedded.org/pipermail/openembedded-devel/2011-August/079834.html
So I just wanted to make sure, that none exists.
Thanks for that approval!
Cheers,
Thilo
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^ permalink raw reply
* Re: [PATCH] ARM: ftrace: fix syscall name matching
From: Russell King - ARM Linux @ 2016-11-14 13:40 UTC (permalink / raw)
To: Rabin Vincent; +Cc: rostedt, linux-arm-kernel, linux-kernel, Rabin Vincent
In-Reply-To: <1479128625-20948-1-git-send-email-rabin.vincent@axis.com>
On Mon, Nov 14, 2016 at 02:03:45PM +0100, Rabin Vincent wrote:
> From: Rabin Vincent <rabinv@axis.com>
>
> ARM has a few system calls (most notably mmap) for which the names of
> the functions which are referenced in the syscall table do not match the
> names of the syscall tracepoints. As a consequence of this, these
> tracepoints are not made available. Implement
> arch_syscall_match_sym_name to fix this and allow tracing even these
> system calls.
>
> Signed-off-by: Rabin Vincent <rabinv@axis.com>
> ---
> arch/arm/include/asm/ftrace.h | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h
> index bfe2a2f..8467909 100644
> --- a/arch/arm/include/asm/ftrace.h
> +++ b/arch/arm/include/asm/ftrace.h
> @@ -54,6 +54,27 @@ static inline void *return_address(unsigned int level)
>
> #define ftrace_return_address(n) return_address(n)
>
> +#define ARCH_HAS_SYSCALL_MATCH_SYM_NAME
> +
> +static inline bool arch_syscall_match_sym_name(const char *sym,
> + const char *name)
> +{
> + /* Skip sys_ */
> + sym += 4;
> + name += 4;
Is this really safe? What guarantees that we can wind forward four
bytes here? If it's always safe, it needs a better comment than just
two words.
> +
> + if (!strcmp(sym, "mmap2"))
> + sym = "mmap_pgoff";
> + else if (!strcmp(sym, "statfs64_wrapper"))
> + sym = "statfs64";
> + else if (!strcmp(sym, "fstatfs64_wrapper"))
> + sym = "fstatfs64";
> + else if (!strcmp(sym, "arm_fadvise64_64"))
> + sym = "fadvise64_64";
> +
> + return !strcmp(sym, name);
> +}
> +
> #endif /* ifndef __ASSEMBLY__ */
>
> #endif /* _ASM_ARM_FTRACE */
> --
> 2.1.4
>
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply
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