* [RFC v1 0/3] drm/i915/vrr: HDMI 2.1 VRR support
@ 2026-10-30 20:32 Alan Stead
2026-10-30 20:32 ` [RFC v1 1/3] drm/i915/dip: Send HDMI EMPs early in V. Blank when VRR is in range Alan Stead
` (5 more replies)
0 siblings, 6 replies; 10+ messages in thread
From: Alan Stead @ 2026-10-30 20:32 UTC (permalink / raw)
To: rodrigo.vivi, jani.nikula, intel-gfx, intel-xe, vivek.kasireddy,
dongwon.kim, james.xiong
Variable Refresh Rate is currently only enabled for DP/eDP. This series
enables it on HDMI 2.1 sinks that advertise a VRR range in the HDMI Forum
VSDB, for display version 20+.
HDMI 2.1 VRR is signalled to the sink with a Video Timing Extended
Metadata (VTEM) packet sent through the HDMI EMP registers. The VRR
timing generator programming already in the driver is reused as is. The
series adds:
1. The EMP transmission line for HDMI: send the EMPs on the 2nd line of
the V. Blank instead of the start of the VSYNC pulse used for the DP
AS SDP.
2. The VTEM packet, written when VRR is enabled and disabled.
3. Enabling VRR (and the vrr_capable property) on HDMI, using the VRR
range that the DRM core now parses into display_info.hdmi.vrr_cap.
The patches are ordered so that HDMI VRR stays disabled until the last
one.
Testing: related implementations have been exercised on a WCL
(display version 30) board with an HDMI 2.1 VRR monitor advertising
48-120 Hz. With VRR enabled, measured vblank intervals were
approximately 20.83 ms (48 Hz) at idle and 16.67 ms (60 Hz) during
verified atomic page flipping. Fullscreen glmark2 under GNOME Wayland
also enabled VRR, with intervals predominantly at 60 Hz and occasional
longer intervals up to 20.83 ms. VTEM enable/disable programming was
observed in the driver logs.
Alan Stead (3):
drm/i915/dip: Send HDMI EMPs early in V. Blank when VRR is in range
drm/i915/dip: Send the HDMI 2.1 VTEM when VRR is enabled
drm/i915/vrr: Allow VRR on HDMI 2.1 sinks
drivers/gpu/drm/i915/display/intel_dip.c | 94 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dip.h | 2 +
drivers/gpu/drm/i915/display/intel_dip_regs.h | 17 ++++
drivers/gpu/drm/i915/display/intel_hdmi.c | 8 ++
drivers/gpu/drm/i915/display/intel_vrr.c | 58 ++++++++++--
5 files changed, 170 insertions(+), 9 deletions(-)
--
2.53.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [RFC v1 1/3] drm/i915/dip: Send HDMI EMPs early in V. Blank when VRR is in range
2026-10-30 20:32 [RFC v1 0/3] drm/i915/vrr: HDMI 2.1 VRR support Alan Stead
@ 2026-10-30 20:32 ` Alan Stead
2026-10-30 20:46 ` sashiko-bot
2026-10-30 20:32 ` [RFC v1 2/3] drm/i915/dip: Send the HDMI 2.1 VTEM when VRR is enabled Alan Stead
` (4 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Alan Stead @ 2026-10-30 20:32 UTC (permalink / raw)
To: rodrigo.vivi, jani.nikula, intel-gfx, intel-xe, vivek.kasireddy,
dongwon.kim, james.xiong
EMP_AS_SDP_TL defines the line, counted back from the next V. Active, on
which HDMI 2.1 Extended Metadata Packets (EMPs) and DP Adaptive Sync SDPs
are sent. It is always programmed to the start of the VSYNC pulse, which
is right for the DP AS SDP, but HDMI 2.1 expects EMPs (such as the VTEM
used to signal VRR) within the first half of V. Blank.
When VRR is in range on an HDMI output, send the EMPs on the 2nd line of
the V. Blank instead, keeping the line within the SCL + guardband region
as required by the hardware. Nothing changes for DP/eDP or for HDMI
outputs where VRR is not in range.
HDMI VRR is not enabled by the driver yet, so this has no effect until
the following patches.
Signed-off-by: Alan Stead <alan.stead@intel.com>
Assisted-by: LLM
---
drivers/gpu/drm/i915/display/intel_dip.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dip.c b/drivers/gpu/drm/i915/display/intel_dip.c
index f447150ff7bc..831881e6c15e 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.c
+++ b/drivers/gpu/drm/i915/display/intel_dip.c
@@ -19,6 +19,25 @@ static int intel_dip_get_as_sdp_transmission_line(const struct intel_crtc_state
if (!HAS_EMP_AS_SDP_TL(display))
return 0;
+ /*
+ * HDMI 2.1 expects the EMPs (such as the VTEM used for VRR) within
+ * the first half of V. Blank, so send them on the 2nd line of the
+ * V. Blank rather than at the start of the VSYNC pulse. The line
+ * must also stay within the SCL + guardband region.
+ */
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
+ crtc_state->vrr.in_range) {
+ const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;
+ int max_tl = crtc_state->set_context_latency +
+ crtc_state->vrr.guardband - 1;
+ int tl = mode->crtc_vtotal - mode->crtc_vdisplay - 1;
+
+ if (max_tl > 0)
+ tl = min(tl, max_tl);
+
+ return tl;
+ }
+
/*
* EMP_AS_SDP_TL defines the T1 position as the default AS SDP
* Transmission Line, which corresponds to the start of the
--
2.53.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [RFC v1 2/3] drm/i915/dip: Send the HDMI 2.1 VTEM when VRR is enabled
2026-10-30 20:32 [RFC v1 0/3] drm/i915/vrr: HDMI 2.1 VRR support Alan Stead
2026-10-30 20:32 ` [RFC v1 1/3] drm/i915/dip: Send HDMI EMPs early in V. Blank when VRR is in range Alan Stead
@ 2026-10-30 20:32 ` Alan Stead
2026-10-30 20:59 ` sashiko-bot
2026-10-30 20:32 ` [RFC v1 3/3] drm/i915/vrr: Allow VRR on HDMI 2.1 sinks Alan Stead
` (3 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Alan Stead @ 2026-10-30 20:32 UTC (permalink / raw)
To: rodrigo.vivi, jani.nikula, intel-gfx, intel-xe, vivek.kasireddy,
dongwon.kim, james.xiong
An HDMI 2.1 sink is told that VRR is active with a Video Timing Extended
Metadata (VTEM) packet. Without it, the sink treats every refresh rate
change as a new video timing and blanks while it resyncs.
Program a Class 0 (Gaming-VRR) VTEM through HDMI_EMP_CTL/HDMI_EMP_DATA/
HDMI_EMP_HEADER whenever VRR is enabled on an HDMI transcoder, and send a
final VTEM with VRR_EN=0 and END set when it is disabled. Both the
modeset and the fastset paths go through intel_vrr_enable() and
intel_vrr_disable().
Notes on the programming:
- HB0 in HDMI_EMP_HEADER must be set to the EMP packet type (0x7f). The
hardware doesn't fill it in, and sinks ignore the VTEM without it.
- MD2 bit 2 (RB in HDMI 2.1a) is reserved since HDMI 2.1b and sent as 0.
- Base_Vfront and Base_Refresh_Rate are only sent for timings without a
VIC, as required by the HDMI 2.1 spec.
- The 11 byte payload is zero padded to a full packet body.
HDMI VRR is not enabled by the driver yet, so this has no effect until
the following patch.
Signed-off-by: Alan Stead <alan.stead@intel.com>
Assisted-by: LLM
---
drivers/gpu/drm/i915/display/intel_dip.c | 75 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dip.h | 2 +
drivers/gpu/drm/i915/display/intel_dip_regs.h | 17 +++++
drivers/gpu/drm/i915/display/intel_vrr.c | 4 +
4 files changed, 98 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dip.c b/drivers/gpu/drm/i915/display/intel_dip.c
index 831881e6c15e..4748f6012337 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.c
+++ b/drivers/gpu/drm/i915/display/intel_dip.c
@@ -4,11 +4,14 @@
*
*/
+#include <linux/minmax.h>
+
#include <drm/drm_print.h>
#include "intel_de.h"
#include "intel_dip.h"
#include "intel_dip_regs.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_hdmi.h"
@@ -74,6 +77,78 @@ void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
EMP_AS_SDP_DB_TL(crtc_state->dip.emp_as_sdp_tl));
}
+/* VTEM: 7 byte EM Data Set header (PB0-PB6) + 4 byte data set (MD0-MD3) */
+#define VTEM_DATA_SET_LENGTH 4
+#define VTEM_EMP_SIZE (7 + VTEM_DATA_SET_LENGTH)
+/* Payload bytes carried by one EMP data island packet */
+#define HDMI_EMP_PACKET_BODY 28
+
+/*
+ * Tell an HDMI 2.1 sink whether VRR is active with a Class 0 (Gaming-VRR)
+ * Video Timing Extended Metadata (VTEM) packet. It is a periodic
+ * pseudo-static EM Data Set: the hardware sends it every frame until it is
+ * reprogrammed. On disable, a last VTEM with VRR_EN=0 and END set is sent,
+ * after which the hardware stops sending it.
+ */
+void intel_dip_write_hdmi_vtem(const struct intel_crtc_state *crtc_state,
+ bool enable)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;
+ u8 vic = crtc_state->infoframes.avi.avi.video_code;
+ int base_rr = drm_mode_vrefresh(mode);
+ u8 pb[HDMI_EMP_PACKET_BODY] = {};
+ int i;
+
+ if (DISPLAY_VER(display) < 20 ||
+ !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
+ !crtc_state->vrr.in_range)
+ return;
+
+ /* PB0-PB6: EM Data Set header (Sync = 0, DS_Type = pseudo-static) */
+ pb[0] = BIT(7) | /* NEW */
+ BIT(2) | /* VFR */
+ (enable ? 0 : BIT(6)); /* END */
+ pb[2] = 1; /* Organization_ID: HDMI */
+ pb[4] = 1; /* Data_Set_Tag: VTEM */
+ pb[6] = VTEM_DATA_SET_LENGTH; /* Data_Set_Length */
+
+ /* PB7-PB10: MD0-MD3 (M_CONST = 0, FVA_Factor_M1 = 0, MD2 bit 2 reserved) */
+ if (enable) {
+ pb[7] = BIT(0); /* VRR_EN */
+ /* Base_Vfront and Base_Refresh_Rate are only sent without a VIC */
+ if (!vic) {
+ pb[8] = min(mode->crtc_vsync_start - mode->crtc_vdisplay, 255);
+ pb[9] = (base_rr >> 8) & 0x3;
+ pb[10] = base_rr & 0xff;
+ }
+ }
+
+ drm_dbg_kms(display->drm,
+ "[TRANSCODER %s] VTEM: VRR_EN=%d VIC=%u Base_Vfront=%u Base_RR=%u\n",
+ transcoder_name(cpu_transcoder), enable, vic, pb[8],
+ pb[9] << 8 | pb[10]);
+
+ /*
+ * HDMI_EMP_CTL first, then the payload dwords (PB0 in bits 7:0), then
+ * the header, whose write clock crosses the whole packet. HB0 must be
+ * set to the EMP packet type, the hardware doesn't fill it in.
+ */
+ intel_de_write(display, HDMI_EMP_CTL(display, cpu_transcoder),
+ HDMI_EMP_CTL_TYPE_VTEM);
+ for (i = 0; i < ARRAY_SIZE(pb); i += 4)
+ intel_de_write(display, HDMI_EMP_DATA(display, cpu_transcoder),
+ pb[i] | pb[i + 1] << 8 | pb[i + 2] << 16 |
+ pb[i + 3] << 24);
+ intel_de_write(display, HDMI_EMP_HEADER(display, cpu_transcoder),
+ HDMI_EMP_HEADER_HB0_EMP |
+ HDMI_EMP_HEADER_DS_TYPE_PSEUDO_STATIC |
+ (enable ? 0 : HDMI_EMP_HEADER_END) |
+ HDMI_EMP_HEADER_NUM_PACKETS(DIV_ROUND_UP(VTEM_EMP_SIZE,
+ HDMI_EMP_PACKET_BODY)));
+}
+
static int intel_dip_sdp_stagger_to_tl(struct intel_crtc_state *crtc_state,
int stagger)
{
diff --git a/drivers/gpu/drm/i915/display/intel_dip.h b/drivers/gpu/drm/i915/display/intel_dip.h
index 7c64c84cb1be..243bca435c1d 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.h
+++ b/drivers/gpu/drm/i915/display/intel_dip.h
@@ -45,6 +45,8 @@ struct intel_crtc_state;
u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
+void intel_dip_write_hdmi_vtem(const struct intel_crtc_state *crtc_state, bool enable);
+
void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state);
void intel_dip_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state);
void intel_dip_cmn_sdp_transmission_line_enable(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dip_regs.h b/drivers/gpu/drm/i915/display/intel_dip_regs.h
index d7e40a613913..273daaab8234 100644
--- a/drivers/gpu/drm/i915/display/intel_dip_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dip_regs.h
@@ -15,6 +15,23 @@
#define EMP_AS_SDP_DB_TL(db_transmit_line) REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK, \
(db_transmit_line))
+/* HDMI 2.1 Extended Metadata Packet (EMP) control/header; payload is HDMI_EMP_DATA */
+#define _HDMI_EMP_CTL_A 0x600d0
+#define HDMI_EMP_CTL(display, trans) _MMIO_TRANS2((display), (trans), _HDMI_EMP_CTL_A)
+#define HDMI_EMP_CTL_TYPE_MASK REG_GENMASK(3, 0)
+#define HDMI_EMP_CTL_TYPE_VTEM REG_FIELD_PREP(HDMI_EMP_CTL_TYPE_MASK, 1)
+
+#define _HDMI_EMP_HEADER_A 0x600d4
+#define HDMI_EMP_HEADER(display, trans) _MMIO_TRANS2((display), (trans), _HDMI_EMP_HEADER_A)
+#define HDMI_EMP_HEADER_END REG_BIT(26)
+#define HDMI_EMP_HEADER_DS_TYPE_MASK REG_GENMASK(25, 24)
+#define HDMI_EMP_HEADER_DS_TYPE_PSEUDO_STATIC REG_FIELD_PREP(HDMI_EMP_HEADER_DS_TYPE_MASK, 0)
+#define HDMI_EMP_HEADER_NUM_PACKETS_MASK REG_GENMASK(23, 16)
+#define HDMI_EMP_HEADER_NUM_PACKETS(n) REG_FIELD_PREP(HDMI_EMP_HEADER_NUM_PACKETS_MASK, \
+ (n))
+#define HDMI_EMP_HEADER_HB0_MASK REG_GENMASK(7, 0)
+#define HDMI_EMP_HEADER_HB0_EMP REG_FIELD_PREP(HDMI_EMP_HEADER_HB0_MASK, 0x7f)
+
/* COMMON SDP TRANSMISSION LINE */
#define _CMN_SDP_TL_A 0x6020c
#define CMN_SDP_TL(display, trans) _MMIO_TRANS2(display, (trans), _CMN_SDP_TL_A)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index b14750692ae0..f4cc4148d3a1 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -1010,6 +1010,8 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
if (!intel_vrr_always_use_vrr_tg(display))
intel_vrr_tg_enable(crtc_state);
+
+ intel_dip_write_hdmi_vtem(crtc_state, true);
}
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@@ -1024,6 +1026,8 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
intel_vrr_disable_dc_balancing(old_crtc_state);
intel_vrr_set_fixed_rr_timings(old_crtc_state, old_crtc_state->cpu_transcoder);
+
+ intel_dip_write_hdmi_vtem(old_crtc_state, false);
}
void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
--
2.53.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [RFC v1 3/3] drm/i915/vrr: Allow VRR on HDMI 2.1 sinks
2026-10-30 20:32 [RFC v1 0/3] drm/i915/vrr: HDMI 2.1 VRR support Alan Stead
2026-10-30 20:32 ` [RFC v1 1/3] drm/i915/dip: Send HDMI EMPs early in V. Blank when VRR is in range Alan Stead
2026-10-30 20:32 ` [RFC v1 2/3] drm/i915/dip: Send the HDMI 2.1 VTEM when VRR is enabled Alan Stead
@ 2026-10-30 20:32 ` Alan Stead
2026-10-30 20:58 ` sashiko-bot
2026-10-30 21:09 ` ✓ CI.KUnit: success for drm/i915/vrr: HDMI 2.1 VRR support Patchwork
` (2 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Alan Stead @ 2026-10-30 20:32 UTC (permalink / raw)
To: rodrigo.vivi, jani.nikula, intel-gfx, intel-xe, vivek.kasireddy,
dongwon.kim, james.xiong
Let intel_vrr_is_capable() accept HDMI sinks that advertise a VRR range
in the HDMI Forum VSDB (parsed by the DRM core into
display_info.hdmi.vrr_cap), and use that range instead of the EDID range
descriptor for the in-range check and for vmax. A VRRmax of 0 means the
refresh rate of the video timing, in which case the maximum comes from
the EDID range descriptor.
Attach the vrr_capable connector property to HDMI connectors and update
it whenever the EDID is read or dropped, as is done for DP.
HDMI 2.1 VRR is signalled to the sink with the VTEM, which needs the
HDMI EMP hardware of display version 20+, so restrict it to those.
Signed-off-by: Alan Stead <alan.stead@intel.com>
Assisted-by: LLM
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 8 ++++
drivers/gpu/drm/i915/display/intel_vrr.c | 54 +++++++++++++++++++----
2 files changed, 53 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index b6fa1a1558b8..4854e86c1762 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2490,6 +2490,8 @@ intel_hdmi_unset_edid(struct drm_connector *_connector)
drm_edid_free(connector->detect_edid);
connector->detect_edid = NULL;
+
+ drm_connector_set_vrr_capable_property(&connector->base, false);
}
static void
@@ -2573,6 +2575,9 @@ intel_hdmi_set_edid(struct drm_connector *_connector)
connector->detect_edid = drm_edid;
+ drm_connector_set_vrr_capable_property(&connector->base,
+ intel_vrr_is_capable(connector));
+
if (drm_edid_is_digital(drm_edid)) {
intel_hdmi_dp_dual_mode_detect(&connector->base);
@@ -2726,6 +2731,9 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *_
if (!HAS_GMCH(display))
drm_connector_attach_max_bpc_property(&connector->base, 8, 12);
+
+ if (HAS_VRR(display) && DISPLAY_VER(display) >= 20)
+ drm_connector_attach_vrr_capable_property(&connector->base);
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index f4cc4148d3a1..ae3863c523b6 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -39,11 +39,33 @@
#define DCB_CORRECTION_AGGRESSIVENESS 1000 /* ms × 100; 10 ms */
#define DCB_BLANK_TARGET 50
+/*
+ * The refresh rate range the sink supports VRR in. HDMI 2.1 sinks advertise
+ * it in the HDMI Forum VSDB, where VRRmax = 0 means "the refresh rate of the
+ * video timing" (fall back to the EDID range descriptor for the maximum).
+ */
+static void intel_vrr_sink_range(struct intel_connector *connector,
+ int *min_vfreq, int *max_vfreq)
+{
+ const struct drm_display_info *info = &connector->base.display_info;
+ const struct drm_hdmi_vrr_cap *vrr_cap = &info->hdmi.vrr_cap;
+
+ *min_vfreq = info->monitor_range.min_vfreq;
+ *max_vfreq = info->monitor_range.max_vfreq;
+
+ if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA &&
+ vrr_cap->supported) {
+ *min_vfreq = vrr_cap->vrr_min;
+ if (vrr_cap->vrr_max)
+ *max_vfreq = vrr_cap->vrr_max;
+ }
+}
+
bool intel_vrr_is_capable(struct intel_connector *connector)
{
struct intel_display *display = to_intel_display(connector);
- const struct drm_display_info *info = &connector->base.display_info;
struct intel_dp *intel_dp;
+ int min_vfreq, max_vfreq;
if (!HAS_VRR(display))
return false;
@@ -78,24 +100,36 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
return false;
break;
+ case DRM_MODE_CONNECTOR_HDMIA:
+ /*
+ * HDMI 2.1 VRR is signalled to the sink with the VTEM, which
+ * is sent using the EMP hardware of display version 20+.
+ */
+ if (DISPLAY_VER(display) < 20 ||
+ !connector->base.display_info.hdmi.vrr_cap.supported)
+ return false;
+ break;
default:
return false;
}
- if (!info->monitor_range.min_vfreq || !info->monitor_range.max_vfreq ||
- info->monitor_range.min_vfreq > info->monitor_range.max_vfreq)
+ intel_vrr_sink_range(connector, &min_vfreq, &max_vfreq);
+
+ if (!min_vfreq || !max_vfreq || min_vfreq > max_vfreq)
return false;
- return info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
+ return max_vfreq - min_vfreq > 10;
}
bool intel_vrr_is_in_range(struct intel_connector *connector, int vrefresh)
{
- const struct drm_display_info *info = &connector->base.display_info;
+ int min_vfreq, max_vfreq;
+
+ intel_vrr_sink_range(connector, &min_vfreq, &max_vfreq);
return intel_vrr_is_capable(connector) &&
- vrefresh >= info->monitor_range.min_vfreq &&
- vrefresh <= info->monitor_range.max_vfreq;
+ vrefresh >= min_vfreq &&
+ vrefresh <= max_vfreq;
}
bool intel_vrr_possible(const struct intel_crtc_state *crtc_state)
@@ -413,11 +447,13 @@ static
int intel_vrr_compute_vmax(struct intel_connector *connector,
const struct drm_display_mode *adjusted_mode)
{
- const struct drm_display_info *info = &connector->base.display_info;
+ int min_vfreq, max_vfreq;
int vmax;
+ intel_vrr_sink_range(connector, &min_vfreq, &max_vfreq);
+
vmax = adjusted_mode->crtc_clock * 1000 /
- (adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq);
+ (adjusted_mode->crtc_htotal * min_vfreq);
vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal);
return vmax;
--
2.53.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [RFC v1 1/3] drm/i915/dip: Send HDMI EMPs early in V. Blank when VRR is in range
2026-10-30 20:32 ` [RFC v1 1/3] drm/i915/dip: Send HDMI EMPs early in V. Blank when VRR is in range Alan Stead
@ 2026-10-30 20:46 ` sashiko-bot
0 siblings, 0 replies; 10+ messages in thread
From: sashiko-bot @ 2026-10-30 20:46 UTC (permalink / raw)
To: Alan Stead, intel-gfx, intel-xe
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915/dip: unreachable HDMI branch in intel_dip_get_as_sdp_transmission_line()
--
commit d831d02efdf03e1121867448c9abebc827f0c335
Author: Alan Stead <alan.stead@intel.com>
drm/i915/dip: Send HDMI EMPs early in V. Blank when VRR is in range
This commit updates intel_dip_get_as_sdp_transmission_line() so that HDMI
outputs with VRR in range send EMPs on the second line of V. Blank within
the SCL + guardband region rather than at the start of the VSYNC pulse.
> diff --git a/drivers/gpu/drm/i915/display/intel_dip.c b/drivers/gpu/drm/i915/display/intel_dip.c
> index f447150ff7bc0..831881e6c15ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_dip.c
> +++ b/drivers/gpu/drm/i915/display/intel_dip.c
> @@ -19,6 +19,25 @@ static int intel_dip_get_as_sdp_transmission_line(const struct intel_crtc_state
> if (!HAS_EMP_AS_SDP_TL(display))
> return 0;
>
> + /*
> + * HDMI 2.1 expects the EMPs (such as the VTEM used for VRR) within
> + * the first half of V. Blank, so send them on the 2nd line of the
> + * V. Blank rather than at the start of the VSYNC pulse. The line
> + * must also stay within the SCL + guardband region.
> + */
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> + crtc_state->vrr.in_range) {
> + const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;
> + int max_tl = crtc_state->set_context_latency +
> + crtc_state->vrr.guardband - 1;
> + int tl = mode->crtc_vtotal - mode->crtc_vdisplay - 1;
> +
> + if (max_tl > 0)
> + tl = min(tl, max_tl);
> +
> + return tl;
> + }
[Severity: High]
Can this HDMI branch in intel_dip_get_as_sdp_transmission_line() ever be
reached?
Looking at the call chain, intel_dip_get_as_sdp_transmission_line() is only
called from intel_dip_sdp_tl_compute_config_late():
drivers/gpu/drm/i915/display/intel_dip.c:
void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state)
{
crtc_state->dip.emp_as_sdp_tl = intel_dip_get_as_sdp_transmission_line(crtc_state);
intel_dip_cmn_sdp_tl_compute_config_late(crtc_state);
}
And intel_dip_sdp_tl_compute_config_late() is only called from
intel_dp_compute_config_late() -> intel_dp_sdp_compute_config_late(), which
is gated on intel_crtc_has_dp_encoder(crtc_state) in
intel_ddi_compute_config_late():
drivers/gpu/drm/i915/display/intel_ddi.c:
static int intel_ddi_compute_config_late(struct intel_atomic_state *state,
struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
{
...
if (intel_crtc_has_dp_encoder(crtc_state))
ret = intel_dp_compute_config_late(encoder, crtc_state, conn_state);
Because DDI encoders are not cloneable, intel_crtc_has_dp_encoder(crtc_state)
is false whenever intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) is true,
leaving crtc_state->dip.emp_as_sdp_tl at 0 for HDMI outputs.
In addition, if intel_dip_sdp_tl_compute_config_late() were called for HDMI,
non-VRR HDMI modes (!crtc_state->vrr.in_range) would fall through to return
crtc_state->vrr.vsync_start instead of 0, and
intel_dip_cmn_sdp_tl_compute_config_late() would populate
crtc_state->dip.cmn_sdp_tl and the SDP stagger fields that are only
programmed on DP in mtl_ddi_pre_enable_dp(), causing state verification
mismatches in intel_pipe_config_compare() on platforms with
HAS_COMMON_SDP_TL(display).
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261030203314.1085262-1-alan.stead@intel.com?part=1
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [RFC v1 3/3] drm/i915/vrr: Allow VRR on HDMI 2.1 sinks
2026-10-30 20:32 ` [RFC v1 3/3] drm/i915/vrr: Allow VRR on HDMI 2.1 sinks Alan Stead
@ 2026-10-30 20:58 ` sashiko-bot
0 siblings, 0 replies; 10+ messages in thread
From: sashiko-bot @ 2026-10-30 20:58 UTC (permalink / raw)
To: Alan Stead, intel-gfx, intel-xe
Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
- [High] drm/i915/dip: emp_as_sdp_tl not computed for HDMI VRR due to DP-only call
- [Medium] drm/i915/hdmi: stale vrr_capable property on disconnect in intel_hdmi_detect()
- [Medium] drm/i915/vrr: fallback to monitor_range.max_vfreq fails when vrr_max is 0
- [Medium] drm/i915/vrr: VRR enabled in DVI mode in intel_vrr_compute_config()
- [Low] drm/i915/dip: undeclared HDMI_EMP_DATA() macro in intel_dip_write_hdmi_vtem()
--
commit d2e831520b52e253f435c04bcef565c5c658d639
Author: Alan Stead <alan.stead@intel.com>
drm/i915/vrr: Allow VRR on HDMI 2.1 sinks
This commit enables VRR support on HDMI 2.1 sinks for display version 20+
by using the VRR range from the HDMI Forum VSDB in display_info.hdmi.vrr_cap
and attaching and updating the vrr_capable property on HDMI connectors.
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index b6fa1a1558b82..4854e86c1762a 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2490,6 +2490,8 @@ intel_hdmi_unset_edid(struct drm_connector *_connector)
>
> drm_edid_free(connector->detect_edid);
> connector->detect_edid = NULL;
> +
> + drm_connector_set_vrr_capable_property(&connector->base, false);
> }
[Severity: Medium]
When an HDMI 2.1 VRR-capable sink is unplugged on display version 20+
platforms, will intel_hdmi_unset_edid() actually be reached to reset the
vrr_capable property to false?
In drivers/gpu/drm/i915/display/intel_hdmi.c, intel_hdmi_detect() checks if
the port is connected before calling intel_hdmi_unset_edid():
if (DISPLAY_VER(display) >= 11 &&
!intel_digital_port_connected(encoder))
goto out;
intel_hdmi_unset_edid(&connector->base);
if (intel_hdmi_set_edid(&connector->base))
status = connector_status_connected;
out:
intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref);
if (status != connector_status_connected)
cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
Because DISPLAY_VER(display) >= 11 is true for all display version 20+
hardware, unplugging the sink causes intel_hdmi_detect() to jump directly to
out without calling intel_hdmi_unset_edid(), leaving the connector's
vrr_capable property stuck at true while disconnected.
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 142ba2db52fda..c2774fd690473 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -39,11 +39,33 @@
> #define DCB_CORRECTION_AGGRESSIVENESS 1000 /* ms × 100; 10 ms */
> #define DCB_BLANK_TARGET 50
>
> +/*
> + * The refresh rate range the sink supports VRR in. HDMI 2.1 sinks advertise
> + * it in the HDMI Forum VSDB, where VRRmax = 0 means "the refresh rate of the
> + * video timing" (fall back to the EDID range descriptor for the maximum).
> + */
> +static void intel_vrr_sink_range(struct intel_connector *connector,
> + int *min_vfreq, int *max_vfreq)
> +{
> + const struct drm_display_info *info = &connector->base.display_info;
> + const struct drm_hdmi_vrr_cap *vrr_cap = &info->hdmi.vrr_cap;
> +
> + *min_vfreq = info->monitor_range.min_vfreq;
> + *max_vfreq = info->monitor_range.max_vfreq;
> +
> + if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA &&
> + vrr_cap->supported) {
> + *min_vfreq = vrr_cap->vrr_min;
> + if (vrr_cap->vrr_max)
> + *max_vfreq = vrr_cap->vrr_max;
> + }
> +}
[Severity: Medium]
Can falling back to info->monitor_range.max_vfreq when vrr_cap->vrr_max is 0
reject valid HDMI 2.1 VRR sinks?
Per the HDMI 2.1 specification and struct drm_hdmi_vrr_cap, vrr_max == 0
indicates that the upper VRR bound is the refresh rate of the active video
timing (and vrr_max == 0 is required for any sink whose maximum VRR rate is
below 100 Hz, since HF-VSDB only encodes 0 or values >= 100).
However, drm_get_monitor_range() in drivers/gpu/drm/drm_edid.c only populates
info->monitor_range.max_vfreq when the EDID revision is >= 4,
DRM_EDID_FEATURE_CONTINUOUS_FREQ is set, and a 0xfd Display Range Limits
descriptor with DRM_EDID_RANGE_LIMITS_ONLY_FLAG is present. On HDMI 2.1 sinks
that advertise vrr_max == 0 in the HF-VSDB without a DisplayPort-style
continuous-frequency Range Limits Only descriptor,
info->monitor_range.max_vfreq remains 0, causing intel_vrr_sink_range() to
set *max_vfreq = 0 and both intel_vrr_is_capable() and
intel_vrr_is_in_range() to return false.
[ ... ]
> @@ -78,24 +100,36 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
> return false;
>
> break;
> + case DRM_MODE_CONNECTOR_HDMIA:
> + /*
> + * HDMI 2.1 VRR is signalled to the sink with the VTEM, which
> + * is sent using the EMP hardware of display version 20+.
> + */
> + if (DISPLAY_VER(display) < 20 ||
> + !connector->base.display_info.hdmi.vrr_cap.supported)
> + return false;
> + break;
[Severity: High]
When VRR is enabled on an HDMI connector, does crtc_state->dip.emp_as_sdp_tl
ever get computed?
In drivers/gpu/drm/i915/display/intel_dip.c,
intel_dip_get_as_sdp_transmission_line() has an HDMI VRR branch:
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
crtc_state->vrr.in_range) {
const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;
int max_tl = crtc_state->set_context_latency +
crtc_state->vrr.guardband - 1;
int tl = mode->crtc_vtotal - mode->crtc_vdisplay - 1;
if (max_tl > 0)
tl = min(tl, max_tl);
return tl;
}
That helper is only called from intel_dip_sdp_tl_compute_config_late(), which
in turn is only called via intel_ddi_compute_config_late() ->
intel_dp_compute_config_late() -> intel_dp_sdp_compute_config_late(). In
drivers/gpu/drm/i915/display/intel_ddi.c, intel_ddi_compute_config_late()
guards that call behind intel_crtc_has_dp_encoder():
if (intel_crtc_has_dp_encoder(crtc_state))
ret = intel_dp_compute_config_late(encoder, crtc_state, conn_state);
For INTEL_OUTPUT_HDMI, intel_dip_sdp_tl_compute_config_late() is never
called, so crtc_state->dip.emp_as_sdp_tl stays 0 and
intel_vrr_set_transcoder_timings() -> intel_dip_write_emp_as_sdp_tl()
programs EMP_AS_SDP_TL to 0 instead of the calculated transmission line.
[Severity: Low]
Also in the HDMI VTEM support enabled by this path, does
intel_dip_write_hdmi_vtem() in drivers/gpu/drm/i915/display/intel_dip.c build
when CONFIG_DRM_I915 or CONFIG_DRM_XE is enabled?
intel_dip_write_hdmi_vtem() writes the packet body using HDMI_EMP_DATA():
for (i = 0; i < ARRAY_SIZE(pb); i += 4)
intel_de_write(display, HDMI_EMP_DATA(display, cpu_transcoder),
pb[i] | pb[i + 1] << 8 | pb[i + 2] << 16 |
pb[i + 3] << 24);
However, drivers/gpu/drm/i915/display/intel_dip_regs.h only defines
HDMI_EMP_CTL and HDMI_EMP_HEADER:
/* HDMI 2.1 Extended Metadata Packet (EMP) control/header; payload is HDMI_EMP_DATA */
#define _HDMI_EMP_CTL_A 0x600d0
#define HDMI_EMP_CTL(display, trans) _MMIO_TRANS2((display), (trans), _HDMI_EMP_CTL_A)
...
#define _HDMI_EMP_HEADER_A 0x600d4
#define HDMI_EMP_HEADER(display, trans) _MMIO_TRANS2((display), (trans), _HDMI_EMP_HEADER_A)
HDMI_EMP_DATA is not defined in intel_dip_regs.h or anywhere else in the
tree, resulting in an implicit declaration build failure in
intel_dip_write_hdmi_vtem().
> default:
> return false;
> }
>
> - if (!info->monitor_range.min_vfreq || !info->monitor_range.max_vfreq ||
> - info->monitor_range.min_vfreq > info->monitor_range.max_vfreq)
> + intel_vrr_sink_range(connector, &min_vfreq, &max_vfreq);
> +
> + if (!min_vfreq || !max_vfreq || min_vfreq > max_vfreq)
> return false;
>
> - return info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
> + return max_vfreq - min_vfreq > 10;
> }
>
> bool intel_vrr_is_in_range(struct intel_connector *connector, int vrefresh)
> {
> - const struct drm_display_info *info = &connector->base.display_info;
> + int min_vfreq, max_vfreq;
> +
> + intel_vrr_sink_range(connector, &min_vfreq, &max_vfreq);
>
> return intel_vrr_is_capable(connector) &&
> - vrefresh >= info->monitor_range.min_vfreq &&
> - vrefresh <= info->monitor_range.max_vfreq;
> + vrefresh >= min_vfreq &&
> + vrefresh <= max_vfreq;
> }
[Severity: Medium]
Should intel_vrr_compute_config() also verify that crtc_state->has_hdmi_sink
(or crtc_state->has_infoframe) is true before enabling VRR on an HDMI
connector?
If userspace forces DVI mode via the connector audio property (setting
force_audio to HDMI_AUDIO_OFF_DVI) while an HDMI 2.1 VRR sink is connected,
intel_hdmi_compute_config() leaves pipe_config->has_hdmi_sink and
pipe_config->has_infoframe as false, and intel_ddi_enable_transcoder_func()
programs TRANS_DDI_MODE_SELECT_DVI:
if (crtc_state->has_hdmi_sink)
temp |= TRANS_DDI_MODE_SELECT_HDMI;
else
temp |= TRANS_DDI_MODE_SELECT_DVI;
Because intel_vrr_compute_config() only checks intel_vrr_is_in_range()
against connector->base.display_info, it still sets crtc_state->vrr.in_range
and crtc_state->vrr.enable to true in DVI mode, even though the AVI InfoFrame
is not computed and the transcoder cannot transmit HDMI data island packets
such as the VTEM.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261030203314.1085262-1-alan.stead@intel.com?part=3
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [RFC v1 2/3] drm/i915/dip: Send the HDMI 2.1 VTEM when VRR is enabled
2026-10-30 20:32 ` [RFC v1 2/3] drm/i915/dip: Send the HDMI 2.1 VTEM when VRR is enabled Alan Stead
@ 2026-10-30 20:59 ` sashiko-bot
0 siblings, 0 replies; 10+ messages in thread
From: sashiko-bot @ 2026-10-30 20:59 UTC (permalink / raw)
To: Alan Stead, intel-gfx, intel-xe
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] drm/i915/dip: undeclared HDMI_EMP_DATA in intel_dip_write_hdmi_vtem()
- [Medium] drm/i915/dip: misordered and unsent VRR disable VTEM in intel_vrr_disable()
- [Medium] drm/i915/dip: unpopulated vrr.in_range check in intel_dip_write_hdmi_vtem()
--
commit a0eb4dbdb4fb231ddf6c7b2a3526d3d1a7f9707a
Author: Alan Stead <alan.stead@intel.com>
drm/i915/dip: Send the HDMI 2.1 VTEM when VRR is enabled
This commit adds intel_dip_write_hdmi_vtem() to program an HDMI 2.1 Video
Timing Extended Metadata (VTEM) packet when enabling or disabling VRR on
an HDMI transcoder via intel_vrr_enable() and intel_vrr_disable().
> diff --git a/drivers/gpu/drm/i915/display/intel_dip.c b/drivers/gpu/drm/i915/display/intel_dip.c
> index 831881e6c15ec..4748f6012337b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dip.c
> +++ b/drivers/gpu/drm/i915/display/intel_dip.c
[ ... ]
> @@ -74,6 +77,78 @@ void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
> EMP_AS_SDP_DB_TL(crtc_state->dip.emp_as_sdp_tl));
> }
>
> +/* VTEM: 7 byte EM Data Set header (PB0-PB6) + 4 byte data set (MD0-MD3) */
> +#define VTEM_DATA_SET_LENGTH 4
> +#define VTEM_EMP_SIZE (7 + VTEM_DATA_SET_LENGTH)
> +/* Payload bytes carried by one EMP data island packet */
> +#define HDMI_EMP_PACKET_BODY 28
> +
> +/*
> + * Tell an HDMI 2.1 sink whether VRR is active with a Class 0 (Gaming-VRR)
> + * Video Timing Extended Metadata (VTEM) packet. It is a periodic
> + * pseudo-static EM Data Set: the hardware sends it every frame until it is
> + * reprogrammed. On disable, a last VTEM with VRR_EN=0 and END set is sent,
> + * after which the hardware stops sending it.
> + */
> +void intel_dip_write_hdmi_vtem(const struct intel_crtc_state *crtc_state,
> + bool enable)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;
> + u8 vic = crtc_state->infoframes.avi.avi.video_code;
> + int base_rr = drm_mode_vrefresh(mode);
> + u8 pb[HDMI_EMP_PACKET_BODY] = {};
> + int i;
> +
> + if (DISPLAY_VER(display) < 20 ||
> + !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
> + !crtc_state->vrr.in_range)
> + return;
[Severity: Medium]
When intel_vrr_disable() calls intel_dip_write_hdmi_vtem(old_crtc_state,
false) to disable VRR from an inherited hardware state read out at driver
load, will this !crtc_state->vrr.in_range check cause an early return and
skip sending the terminating VTEM packet (VRR_EN=0 and END=1)?
During hardware state readout in intel_modeset_readout_hw_state() ->
intel_vrr_get_config(), old_crtc_state->vrr.enable is populated from
TRANS_VRR_CTL, but old_crtc_state->vrr.in_range is never set:
drivers/gpu/drm/i915/display/intel_vrr.c:intel_vrr_get_config() {
...
if (intel_vrr_always_use_vrr_tg(display))
crtc_state->vrr.enable = vrr_enable && !intel_vrr_is_fixed_rr(crtc_state);
else
crtc_state->vrr.enable = vrr_enable;
...
}
Since both callers of intel_dip_write_hdmi_vtem() — intel_vrr_enable() and
intel_vrr_disable() — already guard on crtc_state->vrr.enable (and
intel_vrr_compute_config() only sets vrr.enable when vrr.in_range is true),
is the !crtc_state->vrr.in_range check in intel_dip_write_hdmi_vtem()
needed?
> +
> + /* PB0-PB6: EM Data Set header (Sync = 0, DS_Type = pseudo-static) */
> + pb[0] = BIT(7) | /* NEW */
> + BIT(2) | /* VFR */
> + (enable ? 0 : BIT(6)); /* END */
> + pb[2] = 1; /* Organization_ID: HDMI */
> + pb[4] = 1; /* Data_Set_Tag: VTEM */
> + pb[6] = VTEM_DATA_SET_LENGTH; /* Data_Set_Length */
> +
> + /* PB7-PB10: MD0-MD3 (M_CONST = 0, FVA_Factor_M1 = 0, MD2 bit 2 reserved) */
> + if (enable) {
> + pb[7] = BIT(0); /* VRR_EN */
> + /* Base_Vfront and Base_Refresh_Rate are only sent without a VIC */
> + if (!vic) {
> + pb[8] = min(mode->crtc_vsync_start - mode->crtc_vdisplay, 255);
> + pb[9] = (base_rr >> 8) & 0x3;
> + pb[10] = base_rr & 0xff;
> + }
> + }
> +
> + drm_dbg_kms(display->drm,
> + "[TRANSCODER %s] VTEM: VRR_EN=%d VIC=%u Base_Vfront=%u Base_RR=%u\n",
> + transcoder_name(cpu_transcoder), enable, vic, pb[8],
> + pb[9] << 8 | pb[10]);
> +
> + /*
> + * HDMI_EMP_CTL first, then the payload dwords (PB0 in bits 7:0), then
> + * the header, whose write clock crosses the whole packet. HB0 must be
> + * set to the EMP packet type, the hardware doesn't fill it in.
> + */
> + intel_de_write(display, HDMI_EMP_CTL(display, cpu_transcoder),
> + HDMI_EMP_CTL_TYPE_VTEM);
> + for (i = 0; i < ARRAY_SIZE(pb); i += 4)
> + intel_de_write(display, HDMI_EMP_DATA(display, cpu_transcoder),
> + pb[i] | pb[i + 1] << 8 | pb[i + 2] << 16 |
> + pb[i + 3] << 24);
[Severity: High]
Does drivers/gpu/drm/i915/display/intel_dip.c fail to compile here because
HDMI_EMP_DATA is not defined?
In drivers/gpu/drm/i915/display/intel_dip_regs.h, the patch defines
HDMI_EMP_CTL and HDMI_EMP_HEADER with a comment noting that the payload is
HDMI_EMP_DATA, but neither intel_dip_regs.h nor intel_display_regs.h (nor
follow-up commit d2e831520b52) defines HDMI_EMP_DATA or _HDMI_EMP_DATA_A,
causing an implicit declaration build failure when CONFIG_DRM_I915 or
CONFIG_DRM_XE_DISPLAY is enabled.
In addition, the loop writes all 7 payload dwords to HDMI_EMP_DATA(display,
cpu_transcoder) without a dword index, whereas the transcoder Video DIP
Adaptive Sync / EMP packet buffer uses indexed data registers
ADL_TVIDEO_DIP_AS_SDP_DATA(display, trans, i) (0x60484 + i * 4) controlled
via VIDEO_DIP_ENABLE_AS_ADL in HSW_TVIDEO_DIP_CTL (0x60200). Should this
be programming the indexed Video DIP AS SDP / EMP buffer instead of
HDMI_EMP_CTL, HDMI_EMP_DATA, and HDMI_EMP_HEADER?
[ ... ]
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index d43a06907d18a..142ba2db52fda 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -1010,6 +1010,8 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>
> if (!intel_vrr_always_use_vrr_tg(display))
> intel_vrr_tg_enable(crtc_state);
> +
> + intel_dip_write_hdmi_vtem(crtc_state, true);
> }
>
> void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
> @@ -1024,6 +1026,8 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
>
> intel_vrr_disable_dc_balancing(old_crtc_state);
> intel_vrr_set_fixed_rr_timings(old_crtc_state, old_crtc_state->cpu_transcoder);
> +
> + intel_dip_write_hdmi_vtem(old_crtc_state, false);
> }
[Severity: Medium]
Is placing intel_dip_write_hdmi_vtem(old_crtc_state, false) at the end of
intel_vrr_disable() ordered and guarded as intended across the disable and
fastset paths?
1. On platforms where !intel_vrr_always_use_vrr_tg(display) (such as
display version 20), intel_vrr_tg_disable() clears VRR_CTL_VRR_ENABLE in
TRANS_VRR_CTL and waits for VRR_STATUS_VRR_EN_LIVE to clear at the next
vblank before intel_dip_write_hdmi_vtem(old_crtc_state, false) is called:
drivers/gpu/drm/i915/display/intel_vrr.c:intel_vrr_tg_disable() {
...
if (intel_de_wait_for_clear_ms(display,
TRANS_VRR_STATUS(display, cpu_transcoder),
VRR_STATUS_VRR_EN_LIVE, 1000))
drm_err(display->drm, "Timed out waiting for VRR live status to clear\n");
...
}
Because the VRR_EN=0, END=1 VTEM is only written after that vblank wait
completes, the vblank in which the VRR timing generator turns off will
still transmit the old VTEM with VRR_EN=1 and END=0.
2. On a full modeset in intel_commit_modeset_disables(),
intel_pre_plane_update() calls intel_vrr_disable(old_crtc_state) and then
intel_old_crtc_state_disables() -> hsw_crtc_disable() ->
intel_ddi_post_disable_hdmi_or_sst() -> intel_disable_transcoder() clears
TRANSCONF_ENABLE without waiting for another vblank after
intel_dip_write_hdmi_vtem(old_crtc_state, false), so the final VTEM with
VRR_EN=0 and END=1 is never transmitted before the transcoder stops.
3. In drivers/gpu/drm/i915/display/intel_display.c,
intel_crtc_vrr_disabling() also returns true during seamless fastsets where
VRR stays enabled (old_crtc_state->vrr.enable && new_crtc_state->vrr.enable)
if update_m_n, update_lrr, or vrr_params_changed() is set:
drivers/gpu/drm/i915/display/intel_display.c:intel_crtc_vrr_disabling() {
return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
(old_crtc_state->vrr.enable &&
(new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
vrr_params_changed(old_crtc_state, new_crtc_state)));
}
In that case, intel_pre_update_crtc() -> intel_pre_plane_update() ->
intel_vrr_disable() programs a VTEM with VRR_EN=0 and END=1 before vblank
evasion even though VRR remains enabled in new_crtc_state. Should
intel_dip_write_hdmi_vtem(old_crtc_state, false) be programmed before the
vblank wait and avoided when VRR is only being reconfigured across a
fastset?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261030203314.1085262-1-alan.stead@intel.com?part=2
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ CI.KUnit: success for drm/i915/vrr: HDMI 2.1 VRR support
2026-10-30 20:32 [RFC v1 0/3] drm/i915/vrr: HDMI 2.1 VRR support Alan Stead
` (2 preceding siblings ...)
2026-10-30 20:32 ` [RFC v1 3/3] drm/i915/vrr: Allow VRR on HDMI 2.1 sinks Alan Stead
@ 2026-10-30 21:09 ` Patchwork
2026-10-30 21:29 ` ✓ i915.CI.BAT: " Patchwork
2026-10-30 21:45 ` ✓ Xe.CI.BAT: " Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2026-10-30 21:09 UTC (permalink / raw)
To: Alan Stead; +Cc: intel-xe
== Series Details ==
Series: drm/i915/vrr: HDMI 2.1 VRR support
URL : https://patchwork.freedesktop.org/series/177287/
State : success
== Summary ==
+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[21:07:10] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:07:15] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:07:35] Starting KUnit Kernel (1/1)...
[21:07:35] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:07:35] ================= gpu_buddy (14 subtests) ==================
[21:07:35] [PASSED] gpu_test_buddy_alloc_limit
[21:07:35] [PASSED] gpu_test_buddy_alloc_optimistic
[21:07:35] [PASSED] gpu_test_buddy_alloc_pessimistic
[21:07:35] [PASSED] gpu_test_buddy_alloc_pathological
[21:07:35] [PASSED] gpu_test_buddy_alloc_contiguous
[21:07:35] [PASSED] gpu_test_buddy_alloc_clear
[21:07:35] [PASSED] gpu_test_buddy_alloc_range
[21:07:35] [PASSED] gpu_test_buddy_alloc_range_bias
[21:07:36] [PASSED] gpu_test_buddy_fragmentation_performance
[21:07:37] [PASSED] gpu_test_buddy_dirty_tracker_performance
[21:07:37] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[21:07:37] [PASSED] gpu_test_buddy_offset_aligned_allocation
[21:07:37] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[21:07:37] [PASSED] gpu_test_buddy_addr_to_block
[21:07:37] ==================== [PASSED] gpu_buddy ====================
[21:07:37] ============================================================
[21:07:37] Testing complete. Ran 14 tests: passed: 14
[21:07:37] Elapsed time: 26.748s total, 4.454s configuring, 20.276s building, 1.952s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[21:07:37] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:07:39] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:08:18] Starting KUnit Kernel (1/1)...
[21:08:18] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:08:18] ================== guc_buf (11 subtests) ===================
[21:08:18] [PASSED] test_smallest
[21:08:18] [PASSED] test_largest
[21:08:18] [PASSED] test_granular
[21:08:18] [PASSED] test_unique
[21:08:18] [PASSED] test_overlap
[21:08:18] [PASSED] test_reusable
[21:08:18] [PASSED] test_too_big
[21:08:18] [PASSED] test_flush
[21:08:18] [PASSED] test_lookup
[21:08:18] [PASSED] test_data
[21:08:18] [PASSED] test_class
[21:08:18] ===================== [PASSED] guc_buf =====================
[21:08:18] =================== guc_dbm (7 subtests) ===================
[21:08:18] [PASSED] test_empty
[21:08:18] [PASSED] test_default
[21:08:18] ======================== test_size ========================
[21:08:18] [PASSED] 4
[21:08:18] [PASSED] 8
[21:08:18] [PASSED] 32
[21:08:18] [PASSED] 256
[21:08:18] ==================== [PASSED] test_size ====================
[21:08:18] ======================= test_reuse ========================
[21:08:18] [PASSED] 4
[21:08:18] [PASSED] 8
[21:08:18] [PASSED] 32
[21:08:18] [PASSED] 256
[21:08:18] =================== [PASSED] test_reuse ====================
[21:08:18] =================== test_range_overlap ====================
[21:08:18] [PASSED] 4
[21:08:18] [PASSED] 8
[21:08:18] [PASSED] 32
[21:08:18] [PASSED] 256
[21:08:18] =============== [PASSED] test_range_overlap ================
[21:08:18] =================== test_range_compact ====================
[21:08:18] [PASSED] 4
[21:08:18] [PASSED] 8
[21:08:18] [PASSED] 32
[21:08:18] [PASSED] 256
[21:08:18] =============== [PASSED] test_range_compact ================
[21:08:18] ==================== test_range_spare =====================
[21:08:18] [PASSED] 4
[21:08:18] [PASSED] 8
[21:08:18] [PASSED] 32
[21:08:18] [PASSED] 256
[21:08:18] ================ [PASSED] test_range_spare =================
[21:08:18] ===================== [PASSED] guc_dbm =====================
[21:08:18] ================== guc_idm (22 subtests) ===================
[21:08:18] [PASSED] bad_init
[21:08:18] [PASSED] no_init
[21:08:18] [PASSED] init_fini
[21:08:18] [PASSED] check_init_small
[21:08:18] [PASSED] check_init_shared
[21:08:18] [PASSED] check_used
[21:08:18] [PASSED] check_quota
[21:08:18] [PASSED] check_all
[21:08:18] [PASSED] check_limits
[21:08:18] [PASSED] check_overlap
[21:08:18] [PASSED] check_overlap_alloc
[21:08:18] [PASSED] check_overlap_release
[21:08:18] [PASSED] check_overlap_partial_init
[21:08:18] [PASSED] check_overlap_partial_shared_range_blocking
[21:08:18] [PASSED] check_used_usable
[21:08:18] [PASSED] check_used_shareable
[21:08:18] [PASSED] check_used_mixed
[21:08:18] [PASSED] check_release_usable_range
[21:08:18] [PASSED] check_release_shareable_range
[21:08:18] [PASSED] check_split_boundaries
[21:08:18] [PASSED] check_shareable_spare
[21:08:18] [PASSED] check_shareable_spare_fragmented_tail
[21:08:18] ===================== [PASSED] guc_idm =====================
[21:08:18] ============== guc_klv_helpers (13 subtests) ===============
[21:08:18] [PASSED] test_count
[21:08:18] [PASSED] test_encode_u32
[21:08:18] [PASSED] test_encode_u64
[21:08:18] [PASSED] test_encode_string
[21:08:18] [PASSED] test_encode_object_raw
[21:08:18] [PASSED] test_encode_object_klv
[21:08:18] [PASSED] test_encode_object_nested
[21:08:18] [PASSED] test_encode_object_basic
[21:08:18] ===================== test_decode_u16 =====================
[21:08:18] [PASSED] empty
[21:08:18] [PASSED] valid
[21:08:18] [PASSED] max
[21:08:18] [PASSED] big
[21:08:18] [PASSED] long
[21:08:18] ================= [PASSED] test_decode_u16 =================
[21:08:18] ===================== test_decode_u32 =====================
[21:08:18] [PASSED] empty
[21:08:18] [PASSED] valid
[21:08:18] [PASSED] max
[21:08:18] [PASSED] long
[21:08:18] ================= [PASSED] test_decode_u32 =================
[21:08:18] ===================== test_decode_u64 =====================
[21:08:18] [PASSED] empty
[21:08:18] [PASSED] short
[21:08:18] [PASSED] valid
[21:08:18] [PASSED] max
[21:08:18] [PASSED] long
[21:08:18] ================= [PASSED] test_decode_u64 =================
[21:08:18] ===================== test_decode_str =====================
[21:08:18] [PASSED] empty
[21:08:18] [PASSED] one
[21:08:18] [PASSED] one_trash
[21:08:18] [PASSED] two
[21:08:18] [PASSED] two_trash
[21:08:18] [PASSED] three
[21:08:18] [PASSED] dword
[21:08:18] [PASSED] four
[21:08:18] [PASSED] five
[21:08:18] [PASSED] six
[21:08:18] [PASSED] seven
[21:08:18] [PASSED] qword
[21:08:18] ================= [PASSED] test_decode_str =================
[21:08:18] [PASSED] test_print
[21:08:18] ================= [PASSED] guc_klv_helpers =================
[21:08:18] =================== xe_log (4 subtests) ====================
[21:08:18] [PASSED] demo_cper
[21:08:18] [PASSED] demo_dmesg
[21:08:18] ======================= test_dmesg ========================
[21:08:18] [PASSED] test_fatal
[21:08:18] [PASSED] test_fatal_tile
[21:08:18] [PASSED] test_fatal_gt
[21:08:18] [PASSED] test_fatal_comp
[21:08:18] [PASSED] test_fatal_comp_tile
[21:08:18] [PASSED] test_fatal_comp_gt
[21:08:18] [PASSED] test_fatal_all
[21:08:18] [PASSED] test_recoverable
[21:08:18] [PASSED] test_recoverable_tile
[21:08:18] [PASSED] test_recoverable_gt
[21:08:18] [PASSED] test_recoverable_comp
[21:08:18] [PASSED] test_recoverable_comp_tile
[21:08:18] [PASSED] test_recoverable_comp_gt
[21:08:18] [PASSED] test_recoverable_all
[21:08:18] [PASSED] test_info
[21:08:18] [PASSED] test_info_tile
[21:08:18] [PASSED] test_info_gt
[21:08:18] [PASSED] test_info_err
[21:08:18] [PASSED] test_info_comp
[21:08:18] [PASSED] test_info_comp_tile
[21:08:18] [PASSED] test_info_comp_gt
[21:08:18] [PASSED] test_info_all
[21:08:18] [PASSED] test_hw_fatal
[21:08:18] [PASSED] test_hw_recoverable
[21:08:18] [PASSED] test_hw_corrected
[21:08:18] [PASSED] test_hw_informational
[21:08:18] =================== [PASSED] test_dmesg ====================
[21:08:18] ====================== test_invalid =======================
[21:08:18] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[21:08:18] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[21:08:18] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[21:08:18] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[21:08:18] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[21:08:18] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[21:08:18] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[21:08:18] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[21:08:18] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[21:08:18] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[21:08:18] ================== [SKIPPED] test_invalid ==================
[21:08:18] ===================== [PASSED] xe_log ======================
[21:08:18] ================== no_relay (3 subtests) ===================
[21:08:18] [PASSED] xe_drops_guc2pf_if_not_ready
[21:08:18] [PASSED] xe_drops_guc2vf_if_not_ready
[21:08:18] [PASSED] xe_rejects_send_if_not_ready
[21:08:18] ==================== [PASSED] no_relay =====================
[21:08:18] ================== pf_relay (14 subtests) ==================
[21:08:18] [PASSED] pf_rejects_guc2pf_too_short
[21:08:18] [PASSED] pf_rejects_guc2pf_too_long
[21:08:18] [PASSED] pf_rejects_guc2pf_no_payload
[21:08:18] [PASSED] pf_fails_no_payload
[21:08:18] [PASSED] pf_fails_bad_origin
[21:08:18] [PASSED] pf_fails_bad_type
[21:08:18] [PASSED] pf_txn_reports_error
[21:08:18] [PASSED] pf_txn_sends_pf2guc
[21:08:18] [PASSED] pf_sends_pf2guc
[21:08:18] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:08:18] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:08:18] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:08:18] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:08:18] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:08:18] ==================== [PASSED] pf_relay =====================
[21:08:18] ================== vf_relay (3 subtests) ===================
[21:08:18] [PASSED] vf_rejects_guc2vf_too_short
[21:08:18] [PASSED] vf_rejects_guc2vf_too_long
[21:08:18] [PASSED] vf_rejects_guc2vf_no_payload
[21:08:18] ==================== [PASSED] vf_relay =====================
[21:08:18] ================ pf_gt_config (9 subtests) =================
[21:08:18] [PASSED] fair_contexts_1vf
[21:08:18] [PASSED] fair_doorbells_1vf
[21:08:18] [PASSED] fair_ggtt_1vf
[21:08:18] ====================== fair_vram_1vf ======================
[21:08:18] [PASSED] 3.50 GiB
[21:08:18] [PASSED] 11.5 GiB
[21:08:18] [PASSED] 15.5 GiB
[21:08:18] [PASSED] 31.5 GiB
[21:08:18] [PASSED] 63.5 GiB
[21:08:18] [PASSED] 1.91 GiB
[21:08:18] ================== [PASSED] fair_vram_1vf ==================
[21:08:18] ================ fair_vram_1vf_admin_only =================
[21:08:18] [PASSED] 3.50 GiB
[21:08:18] [PASSED] 11.5 GiB
[21:08:18] [PASSED] 15.5 GiB
[21:08:18] [PASSED] 31.5 GiB
[21:08:18] [PASSED] 63.5 GiB
[21:08:18] [PASSED] 1.91 GiB
[21:08:18] ============ [PASSED] fair_vram_1vf_admin_only =============
[21:08:18] ====================== fair_contexts ======================
[21:08:18] [PASSED] 1 VF
[21:08:18] [PASSED] 2 VFs
[21:08:18] [PASSED] 3 VFs
[21:08:18] [PASSED] 4 VFs
[21:08:18] [PASSED] 5 VFs
[21:08:18] [PASSED] 6 VFs
[21:08:18] [PASSED] 7 VFs
[21:08:18] [PASSED] 8 VFs
[21:08:18] [PASSED] 9 VFs
[21:08:18] [PASSED] 10 VFs
[21:08:18] [PASSED] 11 VFs
[21:08:18] [PASSED] 12 VFs
[21:08:18] [PASSED] 13 VFs
[21:08:18] [PASSED] 14 VFs
[21:08:18] [PASSED] 15 VFs
[21:08:18] [PASSED] 16 VFs
[21:08:18] [PASSED] 17 VFs
[21:08:18] [PASSED] 18 VFs
[21:08:18] [PASSED] 19 VFs
[21:08:18] [PASSED] 20 VFs
[21:08:18] [PASSED] 21 VFs
[21:08:18] [PASSED] 22 VFs
[21:08:18] [PASSED] 23 VFs
[21:08:18] [PASSED] 24 VFs
[21:08:18] [PASSED] 25 VFs
[21:08:18] [PASSED] 26 VFs
[21:08:18] [PASSED] 27 VFs
[21:08:18] [PASSED] 28 VFs
[21:08:18] [PASSED] 29 VFs
[21:08:18] [PASSED] 30 VFs
[21:08:18] [PASSED] 31 VFs
[21:08:18] [PASSED] 32 VFs
[21:08:18] [PASSED] 33 VFs
[21:08:18] [PASSED] 34 VFs
[21:08:18] [PASSED] 35 VFs
[21:08:18] [PASSED] 36 VFs
[21:08:19] [PASSED] 37 VFs
[21:08:19] [PASSED] 38 VFs
[21:08:19] [PASSED] 39 VFs
[21:08:19] [PASSED] 40 VFs
[21:08:19] [PASSED] 41 VFs
[21:08:19] [PASSED] 42 VFs
[21:08:19] [PASSED] 43 VFs
[21:08:19] [PASSED] 44 VFs
[21:08:19] [PASSED] 45 VFs
[21:08:19] [PASSED] 46 VFs
[21:08:19] [PASSED] 47 VFs
[21:08:19] [PASSED] 48 VFs
[21:08:19] [PASSED] 49 VFs
[21:08:19] [PASSED] 50 VFs
[21:08:19] [PASSED] 51 VFs
[21:08:19] [PASSED] 52 VFs
[21:08:19] [PASSED] 53 VFs
[21:08:19] [PASSED] 54 VFs
[21:08:19] [PASSED] 55 VFs
[21:08:19] [PASSED] 56 VFs
[21:08:19] [PASSED] 57 VFs
[21:08:19] [PASSED] 58 VFs
[21:08:19] [PASSED] 59 VFs
[21:08:19] [PASSED] 60 VFs
[21:08:19] [PASSED] 61 VFs
[21:08:19] [PASSED] 62 VFs
[21:08:19] [PASSED] 63 VFs
[21:08:19] ================== [PASSED] fair_contexts ==================
[21:08:19] ===================== fair_doorbells ======================
[21:08:19] [PASSED] 1 VF
[21:08:19] [PASSED] 2 VFs
[21:08:19] [PASSED] 3 VFs
[21:08:19] [PASSED] 4 VFs
[21:08:19] [PASSED] 5 VFs
[21:08:19] [PASSED] 6 VFs
[21:08:19] [PASSED] 7 VFs
[21:08:19] [PASSED] 8 VFs
[21:08:19] [PASSED] 9 VFs
[21:08:19] [PASSED] 10 VFs
[21:08:19] [PASSED] 11 VFs
[21:08:19] [PASSED] 12 VFs
[21:08:19] [PASSED] 13 VFs
[21:08:19] [PASSED] 14 VFs
[21:08:19] [PASSED] 15 VFs
[21:08:19] [PASSED] 16 VFs
[21:08:19] [PASSED] 17 VFs
[21:08:19] [PASSED] 18 VFs
[21:08:19] [PASSED] 19 VFs
[21:08:19] [PASSED] 20 VFs
[21:08:19] [PASSED] 21 VFs
[21:08:19] [PASSED] 22 VFs
[21:08:19] [PASSED] 23 VFs
[21:08:19] [PASSED] 24 VFs
[21:08:19] [PASSED] 25 VFs
[21:08:19] [PASSED] 26 VFs
[21:08:19] [PASSED] 27 VFs
[21:08:19] [PASSED] 28 VFs
[21:08:19] [PASSED] 29 VFs
[21:08:19] [PASSED] 30 VFs
[21:08:19] [PASSED] 31 VFs
[21:08:19] [PASSED] 32 VFs
[21:08:19] [PASSED] 33 VFs
[21:08:19] [PASSED] 34 VFs
[21:08:19] [PASSED] 35 VFs
[21:08:19] [PASSED] 36 VFs
[21:08:19] [PASSED] 37 VFs
[21:08:19] [PASSED] 38 VFs
[21:08:19] [PASSED] 39 VFs
[21:08:19] [PASSED] 40 VFs
[21:08:19] [PASSED] 41 VFs
[21:08:19] [PASSED] 42 VFs
[21:08:19] [PASSED] 43 VFs
[21:08:19] [PASSED] 44 VFs
[21:08:19] [PASSED] 45 VFs
[21:08:19] [PASSED] 46 VFs
[21:08:19] [PASSED] 47 VFs
[21:08:19] [PASSED] 48 VFs
[21:08:19] [PASSED] 49 VFs
[21:08:19] [PASSED] 50 VFs
[21:08:19] [PASSED] 51 VFs
[21:08:19] [PASSED] 52 VFs
[21:08:19] [PASSED] 53 VFs
[21:08:19] [PASSED] 54 VFs
[21:08:19] [PASSED] 55 VFs
[21:08:19] [PASSED] 56 VFs
[21:08:19] [PASSED] 57 VFs
[21:08:19] [PASSED] 58 VFs
[21:08:19] [PASSED] 59 VFs
[21:08:19] [PASSED] 60 VFs
[21:08:19] [PASSED] 61 VFs
[21:08:19] [PASSED] 62 VFs
[21:08:19] [PASSED] 63 VFs
[21:08:19] ================= [PASSED] fair_doorbells ==================
[21:08:19] ======================== fair_ggtt ========================
[21:08:19] [PASSED] 1 VF
[21:08:19] [PASSED] 2 VFs
[21:08:19] [PASSED] 3 VFs
[21:08:19] [PASSED] 4 VFs
[21:08:19] [PASSED] 5 VFs
[21:08:19] [PASSED] 6 VFs
[21:08:19] [PASSED] 7 VFs
[21:08:19] [PASSED] 8 VFs
[21:08:19] [PASSED] 9 VFs
[21:08:19] [PASSED] 10 VFs
[21:08:19] [PASSED] 11 VFs
[21:08:19] [PASSED] 12 VFs
[21:08:19] [PASSED] 13 VFs
[21:08:19] [PASSED] 14 VFs
[21:08:19] [PASSED] 15 VFs
[21:08:19] [PASSED] 16 VFs
[21:08:19] [PASSED] 17 VFs
[21:08:19] [PASSED] 18 VFs
[21:08:19] [PASSED] 19 VFs
[21:08:19] [PASSED] 20 VFs
[21:08:19] [PASSED] 21 VFs
[21:08:19] [PASSED] 22 VFs
[21:08:19] [PASSED] 23 VFs
[21:08:19] [PASSED] 24 VFs
[21:08:19] [PASSED] 25 VFs
[21:08:19] [PASSED] 26 VFs
[21:08:19] [PASSED] 27 VFs
[21:08:19] [PASSED] 28 VFs
[21:08:19] [PASSED] 29 VFs
[21:08:19] [PASSED] 30 VFs
[21:08:19] [PASSED] 31 VFs
[21:08:19] [PASSED] 32 VFs
[21:08:19] [PASSED] 33 VFs
[21:08:19] [PASSED] 34 VFs
[21:08:19] [PASSED] 35 VFs
[21:08:19] [PASSED] 36 VFs
[21:08:19] [PASSED] 37 VFs
[21:08:19] [PASSED] 38 VFs
[21:08:19] [PASSED] 39 VFs
[21:08:19] [PASSED] 40 VFs
[21:08:19] [PASSED] 41 VFs
[21:08:19] [PASSED] 42 VFs
[21:08:19] [PASSED] 43 VFs
[21:08:19] [PASSED] 44 VFs
[21:08:19] [PASSED] 45 VFs
[21:08:19] [PASSED] 46 VFs
[21:08:19] [PASSED] 47 VFs
[21:08:19] [PASSED] 48 VFs
[21:08:19] [PASSED] 49 VFs
[21:08:19] [PASSED] 50 VFs
[21:08:19] [PASSED] 51 VFs
[21:08:19] [PASSED] 52 VFs
[21:08:19] [PASSED] 53 VFs
[21:08:19] [PASSED] 54 VFs
[21:08:19] [PASSED] 55 VFs
[21:08:19] [PASSED] 56 VFs
[21:08:19] [PASSED] 57 VFs
[21:08:19] [PASSED] 58 VFs
[21:08:19] [PASSED] 59 VFs
[21:08:19] [PASSED] 60 VFs
[21:08:19] [PASSED] 61 VFs
[21:08:19] [PASSED] 62 VFs
[21:08:19] [PASSED] 63 VFs
[21:08:19] ==================== [PASSED] fair_ggtt ====================
[21:08:19] ======================== fair_vram ========================
[21:08:19] [PASSED] 1 VF
[21:08:19] [PASSED] 2 VFs
[21:08:19] [PASSED] 3 VFs
[21:08:19] [PASSED] 4 VFs
[21:08:19] [PASSED] 5 VFs
[21:08:19] [PASSED] 6 VFs
[21:08:19] [PASSED] 7 VFs
[21:08:19] [PASSED] 8 VFs
[21:08:19] [PASSED] 9 VFs
[21:08:19] [PASSED] 10 VFs
[21:08:19] [PASSED] 11 VFs
[21:08:19] [PASSED] 12 VFs
[21:08:19] [PASSED] 13 VFs
[21:08:19] [PASSED] 14 VFs
[21:08:19] [PASSED] 15 VFs
[21:08:19] [PASSED] 16 VFs
[21:08:19] [PASSED] 17 VFs
[21:08:19] [PASSED] 18 VFs
[21:08:19] [PASSED] 19 VFs
[21:08:19] [PASSED] 20 VFs
[21:08:19] [PASSED] 21 VFs
[21:08:19] [PASSED] 22 VFs
[21:08:19] [PASSED] 23 VFs
[21:08:19] [PASSED] 24 VFs
[21:08:19] [PASSED] 25 VFs
[21:08:19] [PASSED] 26 VFs
[21:08:19] [PASSED] 27 VFs
[21:08:19] [PASSED] 28 VFs
[21:08:19] [PASSED] 29 VFs
[21:08:19] [PASSED] 30 VFs
[21:08:19] [PASSED] 31 VFs
[21:08:19] [PASSED] 32 VFs
[21:08:19] [PASSED] 33 VFs
[21:08:19] [PASSED] 34 VFs
[21:08:19] [PASSED] 35 VFs
[21:08:19] [PASSED] 36 VFs
[21:08:19] [PASSED] 37 VFs
[21:08:19] [PASSED] 38 VFs
[21:08:19] [PASSED] 39 VFs
[21:08:19] [PASSED] 40 VFs
[21:08:19] [PASSED] 41 VFs
[21:08:19] [PASSED] 42 VFs
[21:08:19] [PASSED] 43 VFs
[21:08:19] [PASSED] 44 VFs
[21:08:19] [PASSED] 45 VFs
[21:08:19] [PASSED] 46 VFs
[21:08:19] [PASSED] 47 VFs
[21:08:19] [PASSED] 48 VFs
[21:08:19] [PASSED] 49 VFs
[21:08:19] [PASSED] 50 VFs
[21:08:19] [PASSED] 51 VFs
[21:08:19] [PASSED] 52 VFs
[21:08:19] [PASSED] 53 VFs
[21:08:19] [PASSED] 54 VFs
[21:08:19] [PASSED] 55 VFs
[21:08:19] [PASSED] 56 VFs
[21:08:19] [PASSED] 57 VFs
[21:08:19] [PASSED] 58 VFs
[21:08:19] [PASSED] 59 VFs
[21:08:19] [PASSED] 60 VFs
[21:08:19] [PASSED] 61 VFs
[21:08:19] [PASSED] 62 VFs
[21:08:19] [PASSED] 63 VFs
[21:08:19] ==================== [PASSED] fair_vram ====================
[21:08:19] ================== [PASSED] pf_gt_config ===================
[21:08:19] ===================== lmtt (1 subtest) =====================
[21:08:19] ======================== test_ops =========================
[21:08:19] [PASSED] 2-level
[21:08:19] [PASSED] multi-level
[21:08:19] ==================== [PASSED] test_ops =====================
[21:08:19] ====================== [PASSED] lmtt =======================
[21:08:19] ================= sriov_packet (1 subtest) =================
[21:08:19] [PASSED] test_descriptor_init
[21:08:19] ================== [PASSED] sriov_packet ===================
[21:08:19] ================= pf_service (11 subtests) =================
[21:08:19] [PASSED] pf_negotiate_any
[21:08:19] [PASSED] pf_negotiate_base_match
[21:08:19] [PASSED] pf_negotiate_base_newer
[21:08:19] [PASSED] pf_negotiate_base_next
[21:08:19] [SKIPPED] pf_negotiate_base_older (no older minor)
[21:08:19] [PASSED] pf_negotiate_base_prev
[21:08:19] [PASSED] pf_negotiate_latest_match
[21:08:19] [PASSED] pf_negotiate_latest_newer
[21:08:19] [PASSED] pf_negotiate_latest_next
[21:08:19] [SKIPPED] pf_negotiate_latest_older (no older minor)
[21:08:19] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[21:08:19] =================== [PASSED] pf_service ====================
[21:08:19] ================= xe_guc_g2g (2 subtests) ==================
[21:08:19] ============== xe_live_guc_g2g_kunit_default ==============
[21:08:19] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[21:08:19] ============== xe_live_guc_g2g_kunit_allmem ===============
[21:08:19] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[21:08:19] =================== [SKIPPED] xe_guc_g2g ===================
[21:08:19] =================== xe_mocs (2 subtests) ===================
[21:08:19] ================ xe_live_mocs_kernel_kunit ================
[21:08:19] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[21:08:19] ================ xe_live_mocs_reset_kunit =================
[21:08:19] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[21:08:19] ==================== [SKIPPED] xe_mocs =====================
[21:08:19] ================= xe_migrate (3 subtests) ==================
[21:08:19] ================= xe_migrate_sanity_kunit =================
[21:08:19] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[21:08:19] ================== xe_validate_ccs_kunit ==================
[21:08:19] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[21:08:19] ============= xe_migrate_access_memory_kunit ==============
[21:08:19] ========= [SKIPPED] xe_migrate_access_memory_kunit =========
[21:08:19] =================== [SKIPPED] xe_migrate ===================
[21:08:19] ================== xe_dma_buf (1 subtest) ==================
[21:08:19] ==================== xe_dma_buf_kunit =====================
[21:08:19] ================ [SKIPPED] xe_dma_buf_kunit ================
[21:08:19] =================== [SKIPPED] xe_dma_buf ===================
[21:08:19] ================= xe_bo_shrink (1 subtest) =================
[21:08:19] =================== xe_bo_shrink_kunit ====================
[21:08:19] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[21:08:19] ================== [SKIPPED] xe_bo_shrink ==================
[21:08:19] ==================== xe_bo (2 subtests) ====================
[21:08:19] ================== xe_ccs_migrate_kunit ===================
[21:08:19] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[21:08:19] ==================== xe_bo_evict_kunit ====================
[21:08:19] =============== [SKIPPED] xe_bo_evict_kunit ================
[21:08:19] ===================== [SKIPPED] xe_bo ======================
[21:08:19] =================== xe_any (9 subtests) ====================
[21:08:19] [PASSED] test_to_xe
[21:08:19] [PASSED] test_to_dev
[21:08:19] [PASSED] test_to_pdev
[21:08:19] [PASSED] test_to_drm
[21:08:19] [PASSED] test_if_pdev
[21:08:19] [PASSED] test_if_xe
[21:08:19] [PASSED] test_if_tile
[21:08:19] [PASSED] test_if_gt
[21:08:19] [PASSED] test_to_id
[21:08:19] ===================== [PASSED] xe_any ======================
[21:08:19] ==================== args (13 subtests) ====================
[21:08:19] [PASSED] count_args_test
[21:08:19] [PASSED] call_args_example
[21:08:19] [PASSED] call_args_test
[21:08:19] [PASSED] drop_first_arg_example
[21:08:19] [PASSED] drop_first_arg_test
[21:08:19] [PASSED] first_arg_example
[21:08:19] [PASSED] first_arg_test
[21:08:19] [PASSED] last_arg_example
[21:08:19] [PASSED] last_arg_test
[21:08:19] [PASSED] pick_arg_example
[21:08:19] [PASSED] if_args_example
[21:08:19] [PASSED] if_args_test
[21:08:19] [PASSED] sep_comma_example
[21:08:19] ====================== [PASSED] args =======================
[21:08:19] =================== xe_pci (3 subtests) ====================
[21:08:19] ==================== check_graphics_ip ====================
[21:08:19] [PASSED] 12.00 Xe_LP
[21:08:19] [PASSED] 12.10 Xe_LP+
[21:08:19] [PASSED] 12.55 Xe_HPG
[21:08:19] [PASSED] 12.60 Xe_HPC
[21:08:19] [PASSED] 12.70 Xe_LPG
[21:08:19] [PASSED] 12.71 Xe_LPG
[21:08:19] [PASSED] 12.74 Xe_LPG+
[21:08:19] [PASSED] 20.01 Xe2_HPG
[21:08:19] [PASSED] 20.02 Xe2_HPG
[21:08:19] [PASSED] 20.04 Xe2_LPG
[21:08:19] [PASSED] 30.00 Xe3_LPG
[21:08:19] [PASSED] 30.01 Xe3_LPG
[21:08:19] [PASSED] 30.03 Xe3_LPG
[21:08:19] [PASSED] 30.04 Xe3_LPG
[21:08:19] [PASSED] 30.05 Xe3_LPG
[21:08:19] [PASSED] 35.10 Xe3p_LPG
[21:08:19] [PASSED] 35.11 Xe3p_XPC
[21:08:19] ================ [PASSED] check_graphics_ip ================
[21:08:19] ===================== check_media_ip ======================
[21:08:19] [PASSED] 12.00 Xe_M
[21:08:19] [PASSED] 12.55 Xe_HPM
[21:08:19] [PASSED] 13.00 Xe_LPM+
[21:08:19] [PASSED] 13.01 Xe2_HPM
[21:08:19] [PASSED] 20.00 Xe2_LPM
[21:08:19] [PASSED] 30.00 Xe3_LPM
[21:08:19] [PASSED] 30.02 Xe3_LPM
[21:08:19] [PASSED] 35.00 Xe3p_LPM
[21:08:19] [PASSED] 35.03 Xe3p_HPM
[21:08:19] ================= [PASSED] check_media_ip ==================
[21:08:19] =================== check_platform_desc ===================
[21:08:19] [PASSED] 0x9A60 (TIGERLAKE)
[21:08:19] [PASSED] 0x9A68 (TIGERLAKE)
[21:08:19] [PASSED] 0x9A70 (TIGERLAKE)
[21:08:19] [PASSED] 0x9A40 (TIGERLAKE)
[21:08:19] [PASSED] 0x9A49 (TIGERLAKE)
[21:08:19] [PASSED] 0x9A59 (TIGERLAKE)
[21:08:19] [PASSED] 0x9A78 (TIGERLAKE)
[21:08:19] [PASSED] 0x9AC0 (TIGERLAKE)
[21:08:19] [PASSED] 0x9AC9 (TIGERLAKE)
[21:08:19] [PASSED] 0x9AD9 (TIGERLAKE)
[21:08:19] [PASSED] 0x9AF8 (TIGERLAKE)
[21:08:19] [PASSED] 0x4C80 (ROCKETLAKE)
[21:08:19] [PASSED] 0x4C8A (ROCKETLAKE)
[21:08:19] [PASSED] 0x4C8B (ROCKETLAKE)
[21:08:19] [PASSED] 0x4C8C (ROCKETLAKE)
[21:08:19] [PASSED] 0x4C90 (ROCKETLAKE)
[21:08:19] [PASSED] 0x4C9A (ROCKETLAKE)
[21:08:19] [PASSED] 0x4680 (ALDERLAKE_S)
[21:08:19] [PASSED] 0x4682 (ALDERLAKE_S)
[21:08:19] [PASSED] 0x4688 (ALDERLAKE_S)
[21:08:19] [PASSED] 0x468A (ALDERLAKE_S)
[21:08:19] [PASSED] 0x468B (ALDERLAKE_S)
[21:08:19] [PASSED] 0x4690 (ALDERLAKE_S)
[21:08:19] [PASSED] 0x4692 (ALDERLAKE_S)
[21:08:19] [PASSED] 0x4693 (ALDERLAKE_S)
[21:08:19] [PASSED] 0x46A0 (ALDERLAKE_P)
[21:08:19] [PASSED] 0x46A1 (ALDERLAKE_P)
[21:08:19] [PASSED] 0x46A2 (ALDERLAKE_P)
[21:08:19] [PASSED] 0x46A3 (ALDERLAKE_P)
[21:08:19] [PASSED] 0x46A6 (ALDERLAKE_P)
[21:08:19] [PASSED] 0x46A8 (ALDERLAKE_P)
[21:08:19] [PASSED] 0x46AA (ALDERLAKE_P)
[21:08:19] [PASSED] 0x462A (ALDERLAKE_P)
[21:08:19] [PASSED] 0x4626 (ALDERLAKE_P)
[21:08:19] [PASSED] 0x4628 (ALDERLAKE_P)
[21:08:19] [PASSED] 0x46B0 (ALDERLAKE_P)
[21:08:19] [PASSED] 0x46B1 (ALDERLAKE_P)
[21:08:19] [PASSED] 0x46B2 (ALDERLAKE_P)
[21:08:19] [PASSED] 0x46B3 (ALDERLAKE_P)
[21:08:19] [PASSED] 0x46C0 (ALDERLAKE_P)
[21:08:19] [PASSED] 0x46C1 (ALDERLAKE_P)
[21:08:19] [PASSED] 0x46C2 (ALDERLAKE_P)
[21:08:19] [PASSED] 0x46C3 (ALDERLAKE_P)
[21:08:19] [PASSED] 0x46D0 (ALDERLAKE_N)
[21:08:19] [PASSED] 0x46D1 (ALDERLAKE_N)
[21:08:19] [PASSED] 0x46D2 (ALDERLAKE_N)
[21:08:19] [PASSED] 0x46D3 (ALDERLAKE_N)
[21:08:19] [PASSED] 0x46D4 (ALDERLAKE_N)
[21:08:19] [PASSED] 0xA721 (ALDERLAKE_P)
[21:08:19] [PASSED] 0xA7A1 (ALDERLAKE_P)
[21:08:19] [PASSED] 0xA7A9 (ALDERLAKE_P)
[21:08:19] [PASSED] 0xA7AC (ALDERLAKE_P)
[21:08:19] [PASSED] 0xA7AD (ALDERLAKE_P)
[21:08:19] [PASSED] 0xA720 (ALDERLAKE_P)
[21:08:19] [PASSED] 0xA7A0 (ALDERLAKE_P)
[21:08:19] [PASSED] 0xA7A8 (ALDERLAKE_P)
[21:08:19] [PASSED] 0xA7AA (ALDERLAKE_P)
[21:08:19] [PASSED] 0xA7AB (ALDERLAKE_P)
[21:08:19] [PASSED] 0xA780 (ALDERLAKE_S)
[21:08:19] [PASSED] 0xA781 (ALDERLAKE_S)
[21:08:19] [PASSED] 0xA782 (ALDERLAKE_S)
[21:08:19] [PASSED] 0xA783 (ALDERLAKE_S)
[21:08:19] [PASSED] 0xA788 (ALDERLAKE_S)
[21:08:19] [PASSED] 0xA789 (ALDERLAKE_S)
[21:08:19] [PASSED] 0xA78A (ALDERLAKE_S)
[21:08:19] [PASSED] 0xA78B (ALDERLAKE_S)
[21:08:19] [PASSED] 0x4905 (DG1)
[21:08:19] [PASSED] 0x4906 (DG1)
[21:08:19] [PASSED] 0x4907 (DG1)
[21:08:19] [PASSED] 0x4908 (DG1)
[21:08:19] [PASSED] 0x4909 (DG1)
[21:08:19] [PASSED] 0x56C0 (DG2)
[21:08:19] [PASSED] 0x56C2 (DG2)
[21:08:19] [PASSED] 0x56C1 (DG2)
[21:08:19] [PASSED] 0x7D51 (METEORLAKE)
[21:08:19] [PASSED] 0x7DD1 (METEORLAKE)
[21:08:19] [PASSED] 0x7D41 (METEORLAKE)
[21:08:19] [PASSED] 0x7D67 (METEORLAKE)
[21:08:19] [PASSED] 0xB640 (METEORLAKE)
[21:08:19] [PASSED] 0x56A0 (DG2)
[21:08:19] [PASSED] 0x56A1 (DG2)
[21:08:19] [PASSED] 0x56A2 (DG2)
[21:08:19] [PASSED] 0x56BE (DG2)
[21:08:19] [PASSED] 0x56BF (DG2)
[21:08:19] [PASSED] 0x5690 (DG2)
[21:08:19] [PASSED] 0x5691 (DG2)
[21:08:19] [PASSED] 0x5692 (DG2)
[21:08:19] [PASSED] 0x56A5 (DG2)
[21:08:19] [PASSED] 0x56A6 (DG2)
[21:08:19] [PASSED] 0x56B0 (DG2)
[21:08:19] [PASSED] 0x56B1 (DG2)
[21:08:19] [PASSED] 0x56BA (DG2)
[21:08:19] [PASSED] 0x56BB (DG2)
[21:08:19] [PASSED] 0x56BC (DG2)
[21:08:19] [PASSED] 0x56BD (DG2)
[21:08:19] [PASSED] 0x5693 (DG2)
[21:08:19] [PASSED] 0x5694 (DG2)
[21:08:19] [PASSED] 0x5695 (DG2)
[21:08:19] [PASSED] 0x56A3 (DG2)
[21:08:19] [PASSED] 0x56A4 (DG2)
[21:08:19] [PASSED] 0x56B2 (DG2)
[21:08:19] [PASSED] 0x56B3 (DG2)
[21:08:19] [PASSED] 0x5696 (DG2)
[21:08:19] [PASSED] 0x5697 (DG2)
[21:08:19] [PASSED] 0xB69 (PVC)
[21:08:19] [PASSED] 0xB6E (PVC)
[21:08:19] [PASSED] 0xBD4 (PVC)
[21:08:19] [PASSED] 0xBD5 (PVC)
[21:08:19] [PASSED] 0xBD6 (PVC)
[21:08:19] [PASSED] 0xBD7 (PVC)
[21:08:19] [PASSED] 0xBD8 (PVC)
[21:08:19] [PASSED] 0xBD9 (PVC)
[21:08:19] [PASSED] 0xBDA (PVC)
[21:08:19] [PASSED] 0xBDB (PVC)
[21:08:19] [PASSED] 0xBE0 (PVC)
[21:08:19] [PASSED] 0xBE1 (PVC)
[21:08:19] [PASSED] 0xBE5 (PVC)
[21:08:19] [PASSED] 0x7D40 (METEORLAKE)
[21:08:19] [PASSED] 0x7D45 (METEORLAKE)
[21:08:19] [PASSED] 0x7D55 (METEORLAKE)
[21:08:19] [PASSED] 0x7D60 (METEORLAKE)
[21:08:19] [PASSED] 0x7DD5 (METEORLAKE)
[21:08:19] [PASSED] 0x6420 (LUNARLAKE)
[21:08:19] [PASSED] 0x64A0 (LUNARLAKE)
[21:08:19] [PASSED] 0x64B0 (LUNARLAKE)
[21:08:19] [PASSED] 0xE202 (BATTLEMAGE)
[21:08:19] [PASSED] 0xE209 (BATTLEMAGE)
[21:08:19] [PASSED] 0xE20B (BATTLEMAGE)
[21:08:19] [PASSED] 0xE20C (BATTLEMAGE)
[21:08:19] [PASSED] 0xE20D (BATTLEMAGE)
[21:08:19] [PASSED] 0xE210 (BATTLEMAGE)
[21:08:19] [PASSED] 0xE211 (BATTLEMAGE)
[21:08:19] [PASSED] 0xE212 (BATTLEMAGE)
[21:08:19] [PASSED] 0xE216 (BATTLEMAGE)
[21:08:19] [PASSED] 0xE220 (BATTLEMAGE)
[21:08:19] [PASSED] 0xE221 (BATTLEMAGE)
[21:08:19] [PASSED] 0xE222 (BATTLEMAGE)
[21:08:19] [PASSED] 0xE223 (BATTLEMAGE)
[21:08:19] [PASSED] 0xB080 (PANTHERLAKE)
[21:08:19] [PASSED] 0xB081 (PANTHERLAKE)
[21:08:19] [PASSED] 0xB082 (PANTHERLAKE)
[21:08:19] [PASSED] 0xB083 (PANTHERLAKE)
[21:08:19] [PASSED] 0xB084 (PANTHERLAKE)
[21:08:19] [PASSED] 0xB085 (PANTHERLAKE)
[21:08:19] [PASSED] 0xB086 (PANTHERLAKE)
[21:08:19] [PASSED] 0xB087 (PANTHERLAKE)
[21:08:19] [PASSED] 0xB08F (PANTHERLAKE)
[21:08:19] [PASSED] 0xB090 (PANTHERLAKE)
[21:08:19] [PASSED] 0xB0A0 (PANTHERLAKE)
[21:08:19] [PASSED] 0xB0A1 (PANTHERLAKE)
[21:08:19] [PASSED] 0xB0B0 (PANTHERLAKE)
[21:08:19] [PASSED] 0xFD80 (PANTHERLAKE)
[21:08:19] [PASSED] 0xFD81 (PANTHERLAKE)
[21:08:19] [PASSED] 0xD740 (NOVALAKE_S)
[21:08:19] [PASSED] 0xD741 (NOVALAKE_S)
[21:08:19] [PASSED] 0xD742 (NOVALAKE_S)
[21:08:19] [PASSED] 0xD743 (NOVALAKE_S)
[21:08:19] [PASSED] 0xD745 (NOVALAKE_S)
[21:08:19] [PASSED] 0xD74A (NOVALAKE_S)
[21:08:19] [PASSED] 0xD74B (NOVALAKE_S)
[21:08:19] [PASSED] 0x674C (CRESCENTISLAND)
[21:08:19] [PASSED] 0x674D (CRESCENTISLAND)
[21:08:19] [PASSED] 0x674E (CRESCENTISLAND)
[21:08:19] [PASSED] 0x674F (CRESCENTISLAND)
[21:08:19] [PASSED] 0x6750 (CRESCENTISLAND)
[21:08:19] [PASSED] 0x6751 (CRESCENTISLAND)
[21:08:19] [PASSED] 0x6752 (CRESCENTISLAND)
[21:08:19] [PASSED] 0xD750 (NOVALAKE_P)
[21:08:19] [PASSED] 0xD751 (NOVALAKE_P)
[21:08:19] [PASSED] 0xD752 (NOVALAKE_P)
[21:08:19] [PASSED] 0xD753 (NOVALAKE_P)
[21:08:19] [PASSED] 0xD754 (NOVALAKE_P)
[21:08:19] [PASSED] 0xD755 (NOVALAKE_P)
[21:08:19] [PASSED] 0xD756 (NOVALAKE_P)
[21:08:19] [PASSED] 0xD757 (NOVALAKE_P)
[21:08:19] [PASSED] 0xD75F (NOVALAKE_P)
[21:08:19] =============== [PASSED] check_platform_desc ===============
[21:08:19] ===================== [PASSED] xe_pci ======================
[21:08:19] ============= xe_rtp_tables_test (5 subtests) ==============
[21:08:19] ================== xe_rtp_table_gt_test ===================
[21:08:19] [PASSED] gt_was/14011060649
[21:08:19] [PASSED] gt_was/14011059788
[21:08:19] [PASSED] gt_was/14015795083
[21:08:19] [PASSED] gt_was/16021867713
[21:08:19] [PASSED] gt_was/14019449301
[21:08:19] [PASSED] gt_was/16028005424
[21:08:19] [PASSED] gt_was/14026578760
[21:08:19] [PASSED] gt_was/1409420604
[21:08:19] [PASSED] gt_was/1408615072
[21:08:19] [PASSED] gt_was/22010523718
[21:08:19] [PASSED] gt_was/14011006942
[21:08:19] [PASSED] gt_was/14014830051
[21:08:19] [PASSED] gt_was/18018781329
[21:08:19] [PASSED] gt_was/1509235366
[21:08:19] [PASSED] gt_was/18018781329
[21:08:19] [PASSED] gt_was/16016694945
[21:08:19] [PASSED] gt_was/14018575942
[21:08:19] [PASSED] gt_was/22016670082
[21:08:19] [PASSED] gt_was/22016670082
[21:08:19] [PASSED] gt_was/14017421178
[21:08:19] [PASSED] gt_was/16025250150
[21:08:19] [PASSED] gt_was/14021871409
[21:08:19] [PASSED] gt_was/16021865536
[21:08:19] [PASSED] gt_was/14021486841
[21:08:19] [PASSED] gt_was/14025160223
[21:08:19] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[21:08:19] [PASSED] gt_was/14025635424
[21:08:19] [PASSED] gt_was/16028005424
[21:08:19] ============== [PASSED] xe_rtp_table_gt_test ===============
[21:08:19] ================== xe_rtp_table_gt_test ===================
[21:08:19] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[21:08:19] [PASSED] gt_tunings/Tuning: 32B Access Enable
[21:08:19] [PASSED] gt_tunings/Tuning: L3 cache
[21:08:19] [PASSED] gt_tunings/Tuning: L3 cache - media
[21:08:19] [PASSED] gt_tunings/Tuning: Compression Overfetch
[21:08:19] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[21:08:19] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[21:08:19] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[21:08:19] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[21:08:19] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[21:08:19] [PASSED] gt_tunings/Tuning: Stateless compression control
[21:08:19] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[21:08:19] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[21:08:19] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[21:08:19] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[21:08:19] [PASSED] gt_tunings/Tuning: Force All Non-Compressible Memory Reads to be 256B Overfetches
[21:08:19] ============== [PASSED] xe_rtp_table_gt_test ===============
[21:08:19] ================== xe_rtp_table_oob_test ==================
[21:08:19] [PASSED] oob_was/1607983814
[21:08:19] [PASSED] oob_was/16010904313
[21:08:19] [PASSED] oob_was/18022495364
[21:08:19] [PASSED] oob_was/22012773006
[21:08:19] [PASSED] oob_was/14014475959
[21:08:19] [PASSED] oob_was/22011391025
[21:08:19] [PASSED] oob_was/22012727170
[21:08:19] [PASSED] oob_was/22012727685
[21:08:19] [PASSED] oob_was/22016596838
[21:08:19] [PASSED] oob_was/18020744125
[21:08:19] [PASSED] oob_was/1409600907
[21:08:19] [PASSED] oob_was/22014953428
[21:08:19] [PASSED] oob_was/16017236439
[21:08:19] [PASSED] oob_was/14019821291
[21:08:19] [PASSED] oob_was/14015076503
[21:08:19] [PASSED] oob_was/22016122933
[21:08:19] [PASSED] oob_was/14018913170
[21:08:19] [PASSED] oob_was/14018094691
[21:08:19] [PASSED] oob_was/18024947630
[21:08:19] [PASSED] oob_was/16022287689
[21:08:19] [PASSED] oob_was/13011645652
[21:08:19] [PASSED] oob_was/14022293748
[21:08:19] [PASSED] oob_was/22019794406
[21:08:19] [PASSED] oob_was/22019338487
[21:08:19] [PASSED] oob_was/16023588340
[21:08:19] [PASSED] oob_was/14019789679
[21:08:19] [PASSED] oob_was/14022866841
[21:08:19] [PASSED] oob_was/16021333562
[21:08:19] [PASSED] oob_was/14016712196
[21:08:19] [PASSED] oob_was/14015568240
[21:08:19] [PASSED] oob_was/18013179988
[21:08:19] [PASSED] oob_was/1508761755
[21:08:19] [PASSED] oob_was/16023105232
[21:08:19] [PASSED] oob_was/16026508708
[21:08:19] [PASSED] oob_was/14020001231
[21:08:19] [PASSED] oob_was/16023683509
[21:08:19] [PASSED] oob_was/14025515070
[21:08:19] [PASSED] oob_was/15015404425_disable
[21:08:19] [PASSED] oob_was/16026007364
[21:08:19] [PASSED] oob_was/14020316580
[21:08:19] [PASSED] oob_was/14025883347
[21:08:19] [PASSED] oob_was/16029380221
[21:08:19] [PASSED] oob_was/22022079272
[21:08:19] [PASSED] oob_was/16029897822
[21:08:19] [PASSED] oob_was/14026539277
[21:08:19] [PASSED] oob_was/14027054324
[21:08:19] [PASSED] oob_was/14025941587
[21:08:19] [PASSED] oob_was/16030224309
[21:08:19] ============== [PASSED] xe_rtp_table_oob_test ==============
[21:08:19] ================ xe_rtp_table_dev_oob_test ================
[21:08:19] [PASSED] device_oob_was/22010954014
[21:08:19] [PASSED] device_oob_was/15015404425
[21:08:19] [PASSED] device_oob_was/22019338487_display
[21:08:19] [PASSED] device_oob_was/14022085890
[21:08:19] [PASSED] device_oob_was/14026633728
[21:08:19] [PASSED] device_oob_was/14026746987
[21:08:19] [PASSED] device_oob_was/14026779378
[21:08:19] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[21:08:19] ========== xe_rtp_table_missing_upper_bound_test ==========
[21:08:19] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[21:08:19] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[21:08:19] [PASSED] register_whitelist/1806527549
[21:08:19] [PASSED] register_whitelist/allow_read_ctx_timestamp
[21:08:19] [PASSED] register_whitelist/allow_read_queue_timestamp
[21:08:19] [PASSED] register_whitelist/16014440446
[21:08:19] [PASSED] register_whitelist/16017236439
[21:08:19] [PASSED] register_whitelist/16020183090
[21:08:19] [PASSED] register_whitelist/14024997852
[21:08:19] [PASSED] register_whitelist/14024997852
[21:08:19] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[21:08:19] =============== [PASSED] xe_rtp_tables_test ================
[21:08:19] =================== xe_rtp (3 subtests) ====================
[21:08:19] =================== xe_rtp_rules_tests ====================
[21:08:19] [PASSED] no
[21:08:19] [PASSED] yes
[21:08:19] [PASSED] no-and-no
[21:08:19] [PASSED] no-and-yes
[21:08:19] [PASSED] yes-and-no
[21:08:19] [PASSED] yes-and-yes
[21:08:19] [PASSED] no-or-no
[21:08:19] [PASSED] no-or-yes
[21:08:19] [PASSED] yes-or-no
[21:08:19] [PASSED] yes-or-yes
[21:08:19] [PASSED] no-yes-or-yes-no
[21:08:19] [PASSED] no-yes-or-yes-yes
[21:08:19] [PASSED] yes-yes-or-no-yes
[21:08:19] [PASSED] yes-yes-or-yes-yes
[21:08:19] [PASSED] no-no-or-yes-or-no
[21:08:19] [PASSED] or
[21:08:19] [PASSED] or-yes
[21:08:19] [PASSED] or-no
[21:08:19] [PASSED] yes-or
[21:08:19] [PASSED] no-or
[21:08:19] [PASSED] no-or-or-yes
[21:08:19] [PASSED] yes-or-or-no
[21:08:19] [PASSED] no-or-or-no
[21:08:19] [PASSED] missing-context-engine-class
[21:08:19] [PASSED] missing-context-engine-class-or-yes
[21:08:19] [PASSED] missing-context-engine-class-or-or-yes
[21:08:19] =============== [PASSED] xe_rtp_rules_tests ================
[21:08:19] =============== xe_rtp_process_to_sr_tests ================
[21:08:19] [PASSED] coalesce-same-reg
[21:08:19] [PASSED] coalesce-same-reg-literal-and-func
[21:08:19] [PASSED] no-match-no-add
[21:08:19] [PASSED] two-regs-two-entries
[21:08:19] [PASSED] clr-one-set-other
[21:08:19] [PASSED] set-field
[21:08:19] [PASSED] conflict-duplicate
[21:08:19] [PASSED] conflict-not-disjoint
[21:08:19] [PASSED] conflict-not-disjoint-literal-and-func
[21:08:19] [PASSED] conflict-reg-type
[21:08:19] [PASSED] bad-mcr-reg-forced-to-regular
[21:08:19] [PASSED] bad-regular-reg-forced-to-mcr
[21:08:19] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[21:08:19] ================== xe_rtp_process_tests ===================
[21:08:19] [PASSED] active1
[21:08:19] [PASSED] active2
[21:08:19] [PASSED] active-inactive
[21:08:19] [PASSED] inactive-active
[21:08:19] [PASSED] inactive-active-inactive
[21:08:19] [PASSED] inactive-inactive-inactive
[21:08:19] ============== [PASSED] xe_rtp_process_tests ===============
[21:08:19] ===================== [PASSED] xe_rtp ======================
[21:08:19] ==================== xe_wa (1 subtest) =====================
[21:08:19] ======================== xe_wa_gt =========================
[21:08:19] [PASSED] TIGERLAKE B0
[21:08:19] [PASSED] DG1 A0
[21:08:19] [PASSED] DG1 B0
[21:08:19] [PASSED] ALDERLAKE_S A0
[21:08:19] [PASSED] ALDERLAKE_S B0
[21:08:19] [PASSED] ALDERLAKE_S C0
[21:08:19] [PASSED] ALDERLAKE_S D0
[21:08:19] [PASSED] ALDERLAKE_P A0
[21:08:19] [PASSED] ALDERLAKE_P B0
[21:08:19] [PASSED] ALDERLAKE_P C0
[21:08:19] [PASSED] ALDERLAKE_S RPLS D0
[21:08:19] [PASSED] ALDERLAKE_P RPLU E0
[21:08:19] [PASSED] DG2 G10 C0
[21:08:19] [PASSED] DG2 G11 B1
[21:08:19] [PASSED] DG2 G12 A1
[21:08:19] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:08:19] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:08:19] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[21:08:19] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[21:08:19] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[21:08:19] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[21:08:19] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[21:08:19] ==================== [PASSED] xe_wa_gt =====================
[21:08:19] ====================== [PASSED] xe_wa ======================
[21:08:19] ============================================================
[21:08:19] Testing complete. Ran 839 tests: passed: 810, skipped: 29
[21:08:19] Elapsed time: 41.909s total, 1.846s configuring, 39.296s building, 0.723s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[21:08:19] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:08:21] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:08:46] Starting KUnit Kernel (1/1)...
[21:08:46] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:08:46] ============ drm_test_pick_cmdline (2 subtests) ============
[21:08:46] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[21:08:46] =============== drm_test_pick_cmdline_named ===============
[21:08:46] [PASSED] NTSC
[21:08:46] [PASSED] NTSC-J
[21:08:46] [PASSED] PAL
[21:08:46] [PASSED] PAL-M
[21:08:46] =========== [PASSED] drm_test_pick_cmdline_named ===========
[21:08:46] ============== [PASSED] drm_test_pick_cmdline ==============
[21:08:46] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[21:08:46] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[21:08:46] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[21:08:46] =========== drm_validate_clone_mode (2 subtests) ===========
[21:08:46] ============== drm_test_check_in_clone_mode ===============
[21:08:46] [PASSED] in_clone_mode
[21:08:46] [PASSED] not_in_clone_mode
[21:08:46] ========== [PASSED] drm_test_check_in_clone_mode ===========
[21:08:46] =============== drm_test_check_valid_clones ===============
[21:08:46] [PASSED] not_in_clone_mode
[21:08:46] [PASSED] valid_clone
[21:08:46] [PASSED] invalid_clone
[21:08:46] =========== [PASSED] drm_test_check_valid_clones ===========
[21:08:46] ============= [PASSED] drm_validate_clone_mode =============
[21:08:46] ============= drm_validate_modeset (1 subtest) =============
[21:08:46] [PASSED] drm_test_check_connector_changed_modeset
[21:08:46] ============== [PASSED] drm_validate_modeset ===============
[21:08:46] ====== drm_test_bridge_get_current_state (1 subtest) =======
[21:08:46] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[21:08:46] ======== [PASSED] drm_test_bridge_get_current_state ========
[21:08:46] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[21:08:46] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[21:08:46] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[21:08:46] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[21:08:46] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[21:08:46] ============== drm_bridge_alloc (2 subtests) ===============
[21:08:46] [PASSED] drm_test_drm_bridge_alloc_basic
[21:08:46] [PASSED] drm_test_drm_bridge_alloc_get_put
[21:08:46] ================ [PASSED] drm_bridge_alloc =================
[21:08:46] ============= drm_bridge_bus_fmt (5 subtests) ==============
[21:08:46] [PASSED] drm_test_bridge_rgb_yuv_rgb
[21:08:46] [PASSED] drm_test_bridge_must_convert_to_yuv444
[21:08:46] [PASSED] drm_test_bridge_hdmi_auto_rgb
[21:08:46] [PASSED] drm_test_bridge_auto_first
[21:08:46] [PASSED] drm_test_bridge_rgb_yuv_no_path
[21:08:46] =============== [PASSED] drm_bridge_bus_fmt ================
[21:08:46] ============= drm_cmdline_parser (40 subtests) =============
[21:08:46] [PASSED] drm_test_cmdline_force_d_only
[21:08:46] [PASSED] drm_test_cmdline_force_D_only_dvi
[21:08:46] [PASSED] drm_test_cmdline_force_D_only_hdmi
[21:08:46] [PASSED] drm_test_cmdline_force_D_only_not_digital
[21:08:46] [PASSED] drm_test_cmdline_force_e_only
[21:08:46] [PASSED] drm_test_cmdline_res
[21:08:46] [PASSED] drm_test_cmdline_res_vesa
[21:08:46] [PASSED] drm_test_cmdline_res_vesa_rblank
[21:08:46] [PASSED] drm_test_cmdline_res_rblank
[21:08:46] [PASSED] drm_test_cmdline_res_bpp
[21:08:46] [PASSED] drm_test_cmdline_res_refresh
[21:08:46] [PASSED] drm_test_cmdline_res_bpp_refresh
[21:08:46] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[21:08:46] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[21:08:46] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[21:08:46] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[21:08:46] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[21:08:46] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[21:08:46] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[21:08:46] [PASSED] drm_test_cmdline_res_margins_force_on
[21:08:46] [PASSED] drm_test_cmdline_res_vesa_margins
[21:08:46] [PASSED] drm_test_cmdline_name
[21:08:46] [PASSED] drm_test_cmdline_name_bpp
[21:08:46] [PASSED] drm_test_cmdline_name_option
[21:08:46] [PASSED] drm_test_cmdline_name_bpp_option
[21:08:46] [PASSED] drm_test_cmdline_rotate_0
[21:08:46] [PASSED] drm_test_cmdline_rotate_90
[21:08:46] [PASSED] drm_test_cmdline_rotate_180
[21:08:46] [PASSED] drm_test_cmdline_rotate_270
[21:08:46] [PASSED] drm_test_cmdline_hmirror
[21:08:46] [PASSED] drm_test_cmdline_vmirror
[21:08:46] [PASSED] drm_test_cmdline_margin_options
[21:08:46] [PASSED] drm_test_cmdline_multiple_options
[21:08:46] [PASSED] drm_test_cmdline_bpp_extra_and_option
[21:08:46] [PASSED] drm_test_cmdline_extra_and_option
[21:08:46] [PASSED] drm_test_cmdline_freestanding_options
[21:08:46] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[21:08:46] [PASSED] drm_test_cmdline_panel_orientation
[21:08:46] ================ drm_test_cmdline_invalid =================
[21:08:46] [PASSED] margin_only
[21:08:46] [PASSED] interlace_only
[21:08:46] [PASSED] res_missing_x
[21:08:46] [PASSED] res_missing_y
[21:08:46] [PASSED] res_bad_y
[21:08:46] [PASSED] res_missing_y_bpp
[21:08:46] [PASSED] res_bad_bpp
[21:08:46] [PASSED] res_bad_refresh
[21:08:46] [PASSED] res_bpp_refresh_force_on_off
[21:08:46] [PASSED] res_invalid_mode
[21:08:46] [PASSED] res_bpp_wrong_place_mode
[21:08:46] [PASSED] name_bpp_refresh
[21:08:46] [PASSED] name_refresh
[21:08:46] [PASSED] name_refresh_wrong_mode
[21:08:46] [PASSED] name_refresh_invalid_mode
[21:08:46] [PASSED] rotate_multiple
[21:08:46] [PASSED] rotate_invalid_val
[21:08:46] [PASSED] rotate_truncated
[21:08:46] [PASSED] invalid_option
[21:08:46] [PASSED] invalid_tv_option
[21:08:46] [PASSED] truncated_tv_option
[21:08:46] ============ [PASSED] drm_test_cmdline_invalid =============
[21:08:46] =============== drm_test_cmdline_tv_options ===============
[21:08:46] [PASSED] NTSC
[21:08:46] [PASSED] NTSC_443
[21:08:46] [PASSED] NTSC_J
[21:08:46] [PASSED] PAL
[21:08:46] [PASSED] PAL_M
[21:08:46] [PASSED] PAL_N
[21:08:46] [PASSED] SECAM
[21:08:46] [PASSED] MONO_525
[21:08:46] [PASSED] MONO_625
[21:08:46] =========== [PASSED] drm_test_cmdline_tv_options ===========
[21:08:46] =============== [PASSED] drm_cmdline_parser ================
[21:08:46] ========== drmm_connector_hdmi_init (20 subtests) ==========
[21:08:46] [PASSED] drm_test_connector_hdmi_init_valid
[21:08:46] [PASSED] drm_test_connector_hdmi_init_bpc_8
[21:08:46] [PASSED] drm_test_connector_hdmi_init_bpc_10
[21:08:46] [PASSED] drm_test_connector_hdmi_init_bpc_12
[21:08:46] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[21:08:46] [PASSED] drm_test_connector_hdmi_init_bpc_null
[21:08:46] [PASSED] drm_test_connector_hdmi_init_formats_empty
[21:08:46] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[21:08:46] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:08:46] [PASSED] supported_formats=0x9 yuv420_allowed=1
[21:08:46] [PASSED] supported_formats=0x9 yuv420_allowed=0
[21:08:46] [PASSED] supported_formats=0x5 yuv420_allowed=1
[21:08:46] [PASSED] supported_formats=0x5 yuv420_allowed=0
[21:08:46] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:08:46] [PASSED] drm_test_connector_hdmi_init_null_ddc
[21:08:46] [PASSED] drm_test_connector_hdmi_init_null_product
[21:08:46] [PASSED] drm_test_connector_hdmi_init_null_vendor
[21:08:46] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[21:08:46] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[21:08:46] [PASSED] drm_test_connector_hdmi_init_product_valid
[21:08:46] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[21:08:46] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[21:08:46] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[21:08:46] ========= drm_test_connector_hdmi_init_type_valid =========
[21:08:46] [PASSED] HDMI-A
[21:08:46] [PASSED] HDMI-B
[21:08:46] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[21:08:46] ======== drm_test_connector_hdmi_init_type_invalid ========
[21:08:46] [PASSED] Unknown
[21:08:46] [PASSED] VGA
[21:08:46] [PASSED] DVI-I
[21:08:46] [PASSED] DVI-D
[21:08:46] [PASSED] DVI-A
[21:08:46] [PASSED] Composite
[21:08:46] [PASSED] SVIDEO
[21:08:46] [PASSED] LVDS
[21:08:46] [PASSED] Component
[21:08:46] [PASSED] DIN
[21:08:46] [PASSED] DP
[21:08:46] [PASSED] TV
[21:08:46] [PASSED] eDP
[21:08:46] [PASSED] Virtual
[21:08:46] [PASSED] DSI
[21:08:46] [PASSED] DPI
[21:08:46] [PASSED] Writeback
[21:08:46] [PASSED] SPI
[21:08:46] [PASSED] USB
[21:08:46] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[21:08:46] ============ [PASSED] drmm_connector_hdmi_init =============
[21:08:46] ============= drmm_connector_init (3 subtests) =============
[21:08:46] [PASSED] drm_test_drmm_connector_init
[21:08:46] [PASSED] drm_test_drmm_connector_init_null_ddc
[21:08:46] ========= drm_test_drmm_connector_init_type_valid =========
[21:08:46] [PASSED] Unknown
[21:08:46] [PASSED] VGA
[21:08:46] [PASSED] DVI-I
[21:08:46] [PASSED] DVI-D
[21:08:46] [PASSED] DVI-A
[21:08:46] [PASSED] Composite
[21:08:46] [PASSED] SVIDEO
[21:08:46] [PASSED] LVDS
[21:08:46] [PASSED] Component
[21:08:46] [PASSED] DIN
[21:08:46] [PASSED] DP
[21:08:46] [PASSED] HDMI-A
[21:08:46] [PASSED] HDMI-B
[21:08:46] [PASSED] TV
[21:08:46] [PASSED] eDP
[21:08:46] [PASSED] Virtual
[21:08:46] [PASSED] DSI
[21:08:46] [PASSED] DPI
[21:08:46] [PASSED] Writeback
[21:08:46] [PASSED] SPI
[21:08:46] [PASSED] USB
[21:08:46] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[21:08:46] =============== [PASSED] drmm_connector_init ===============
[21:08:46] ========= drm_connector_dynamic_init (6 subtests) ==========
[21:08:46] [PASSED] drm_test_drm_connector_dynamic_init
[21:08:46] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[21:08:46] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[21:08:46] [PASSED] drm_test_drm_connector_dynamic_init_properties
[21:08:46] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[21:08:46] [PASSED] Unknown
[21:08:46] [PASSED] VGA
[21:08:46] [PASSED] DVI-I
[21:08:46] [PASSED] DVI-D
[21:08:46] [PASSED] DVI-A
[21:08:46] [PASSED] Composite
[21:08:46] [PASSED] SVIDEO
[21:08:46] [PASSED] LVDS
[21:08:46] [PASSED] Component
[21:08:46] [PASSED] DIN
[21:08:46] [PASSED] DP
[21:08:46] [PASSED] HDMI-A
[21:08:46] [PASSED] HDMI-B
[21:08:46] [PASSED] TV
[21:08:46] [PASSED] eDP
[21:08:46] [PASSED] Virtual
[21:08:46] [PASSED] DSI
[21:08:46] [PASSED] DPI
[21:08:46] [PASSED] Writeback
[21:08:46] [PASSED] SPI
[21:08:46] [PASSED] USB
[21:08:46] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[21:08:46] ======== drm_test_drm_connector_dynamic_init_name =========
[21:08:46] [PASSED] Unknown
[21:08:46] [PASSED] VGA
[21:08:46] [PASSED] DVI-I
[21:08:46] [PASSED] DVI-D
[21:08:46] [PASSED] DVI-A
[21:08:46] [PASSED] Composite
[21:08:46] [PASSED] SVIDEO
[21:08:46] [PASSED] LVDS
[21:08:46] [PASSED] Component
[21:08:46] [PASSED] DIN
[21:08:46] [PASSED] DP
[21:08:46] [PASSED] HDMI-A
[21:08:46] [PASSED] HDMI-B
[21:08:46] [PASSED] TV
[21:08:46] [PASSED] eDP
[21:08:46] [PASSED] Virtual
[21:08:46] [PASSED] DSI
[21:08:46] [PASSED] DPI
[21:08:46] [PASSED] Writeback
[21:08:46] [PASSED] SPI
[21:08:46] [PASSED] USB
[21:08:46] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[21:08:46] =========== [PASSED] drm_connector_dynamic_init ============
[21:08:46] ==== drm_connector_dynamic_register_early (4 subtests) =====
[21:08:46] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[21:08:46] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[21:08:46] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[21:08:46] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[21:08:46] ====== [PASSED] drm_connector_dynamic_register_early =======
[21:08:46] ======= drm_connector_dynamic_register (7 subtests) ========
[21:08:46] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[21:08:46] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[21:08:46] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[21:08:46] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[21:08:46] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[21:08:46] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[21:08:46] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[21:08:46] ========= [PASSED] drm_connector_dynamic_register ==========
[21:08:46] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[21:08:46] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[21:08:46] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[21:08:46] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[21:08:46] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[21:08:46] ========== drm_test_get_tv_mode_from_name_valid ===========
[21:08:46] [PASSED] NTSC
[21:08:46] [PASSED] NTSC-443
[21:08:46] [PASSED] NTSC-J
[21:08:46] [PASSED] PAL
[21:08:46] [PASSED] PAL-M
[21:08:46] [PASSED] PAL-N
[21:08:46] [PASSED] SECAM
[21:08:46] [PASSED] Mono
[21:08:46] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[21:08:46] [PASSED] drm_test_get_tv_mode_from_name_truncated
[21:08:46] ============ [PASSED] drm_get_tv_mode_from_name ============
[21:08:46] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[21:08:46] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[21:08:46] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[21:08:46] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[21:08:46] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[21:08:46] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[21:08:46] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[21:08:46] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[21:08:46] [PASSED] VIC 96
[21:08:46] [PASSED] VIC 97
[21:08:46] [PASSED] VIC 101
[21:08:46] [PASSED] VIC 102
[21:08:46] [PASSED] VIC 106
[21:08:46] [PASSED] VIC 107
[21:08:46] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[21:08:46] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[21:08:46] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[21:08:46] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[21:08:46] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[21:08:46] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[21:08:46] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[21:08:46] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[21:08:46] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[21:08:46] [PASSED] Automatic
[21:08:46] [PASSED] Full
[21:08:46] [PASSED] Limited 16:235
[21:08:46] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[21:08:46] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[21:08:46] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[21:08:46] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[21:08:46] === drm_test_drm_hdmi_connector_get_output_format_name ====
[21:08:46] [PASSED] RGB
[21:08:46] [PASSED] YUV 4:2:0
[21:08:46] [PASSED] YUV 4:2:2
[21:08:46] [PASSED] YUV 4:4:4
[21:08:46] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[21:08:46] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[21:08:46] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[21:08:46] ============= drm_damage_helper (21 subtests) ==============
[21:08:46] [PASSED] drm_test_damage_iter_no_damage
[21:08:46] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[21:08:46] [PASSED] drm_test_damage_iter_no_damage_src_moved
[21:08:46] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[21:08:46] [PASSED] drm_test_damage_iter_no_damage_not_visible
[21:08:46] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[21:08:46] [PASSED] drm_test_damage_iter_no_damage_no_fb
[21:08:46] [PASSED] drm_test_damage_iter_simple_damage
[21:08:46] [PASSED] drm_test_damage_iter_single_damage
[21:08:46] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[21:08:46] [PASSED] drm_test_damage_iter_single_damage_outside_src
[21:08:46] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[21:08:46] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[21:08:46] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[21:08:46] [PASSED] drm_test_damage_iter_single_damage_src_moved
[21:08:46] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[21:08:46] [PASSED] drm_test_damage_iter_damage
[21:08:46] [PASSED] drm_test_damage_iter_damage_one_intersect
[21:08:46] [PASSED] drm_test_damage_iter_damage_one_outside
[21:08:46] [PASSED] drm_test_damage_iter_damage_src_moved
[21:08:46] [PASSED] drm_test_damage_iter_damage_not_visible
[21:08:46] ================ [PASSED] drm_damage_helper ================
[21:08:46] ============== drm_dp_mst_helper (3 subtests) ==============
[21:08:46] ============== drm_test_dp_mst_calc_pbn_mode ==============
[21:08:46] [PASSED] Clock 154000 BPP 30 DSC disabled
[21:08:46] [PASSED] Clock 234000 BPP 30 DSC disabled
[21:08:46] [PASSED] Clock 297000 BPP 24 DSC disabled
[21:08:46] [PASSED] Clock 332880 BPP 24 DSC enabled
[21:08:46] [PASSED] Clock 324540 BPP 24 DSC enabled
[21:08:46] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[21:08:46] ============== drm_test_dp_mst_calc_pbn_div ===============
[21:08:46] [PASSED] Link rate 2000000 lane count 4
[21:08:46] [PASSED] Link rate 2000000 lane count 2
[21:08:46] [PASSED] Link rate 2000000 lane count 1
[21:08:46] [PASSED] Link rate 1350000 lane count 4
[21:08:46] [PASSED] Link rate 1350000 lane count 2
[21:08:46] [PASSED] Link rate 1350000 lane count 1
[21:08:46] [PASSED] Link rate 1000000 lane count 4
[21:08:46] [PASSED] Link rate 1000000 lane count 2
[21:08:46] [PASSED] Link rate 1000000 lane count 1
[21:08:46] [PASSED] Link rate 810000 lane count 4
[21:08:46] [PASSED] Link rate 810000 lane count 2
[21:08:46] [PASSED] Link rate 810000 lane count 1
[21:08:46] [PASSED] Link rate 540000 lane count 4
[21:08:46] [PASSED] Link rate 540000 lane count 2
[21:08:46] [PASSED] Link rate 540000 lane count 1
[21:08:46] [PASSED] Link rate 270000 lane count 4
[21:08:46] [PASSED] Link rate 270000 lane count 2
[21:08:46] [PASSED] Link rate 270000 lane count 1
[21:08:46] [PASSED] Link rate 162000 lane count 4
[21:08:46] [PASSED] Link rate 162000 lane count 2
[21:08:46] [PASSED] Link rate 162000 lane count 1
[21:08:46] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[21:08:46] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[21:08:46] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[21:08:46] [PASSED] DP_POWER_UP_PHY with port number
[21:08:46] [PASSED] DP_POWER_DOWN_PHY with port number
[21:08:46] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[21:08:46] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[21:08:46] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[21:08:46] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[21:08:46] [PASSED] DP_QUERY_PAYLOAD with port number
[21:08:46] [PASSED] DP_QUERY_PAYLOAD with VCPI
[21:08:46] [PASSED] DP_REMOTE_DPCD_READ with port number
[21:08:46] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[21:08:46] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[21:08:46] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[21:08:46] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[21:08:46] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[21:08:46] [PASSED] DP_REMOTE_I2C_READ with port number
[21:08:46] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[21:08:46] [PASSED] DP_REMOTE_I2C_READ with transactions array
[21:08:46] [PASSED] DP_REMOTE_I2C_WRITE with port number
[21:08:46] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[21:08:46] [PASSED] DP_REMOTE_I2C_WRITE with data array
[21:08:46] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[21:08:46] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[21:08:46] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[21:08:46] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[21:08:46] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[21:08:46] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[21:08:46] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[21:08:46] ================ [PASSED] drm_dp_mst_helper ================
[21:08:46] ================== drm_exec (7 subtests) ===================
[21:08:46] [PASSED] sanitycheck
[21:08:46] [PASSED] test_lock
[21:08:46] [PASSED] test_lock_unlock
[21:08:46] [PASSED] test_duplicates
[21:08:46] [PASSED] test_prepare
[21:08:46] [PASSED] test_prepare_array
[21:08:46] [PASSED] test_multiple_loops
[21:08:46] ==================== [PASSED] drm_exec =====================
[21:08:46] =========== drm_format_helper_test (17 subtests) ===========
[21:08:46] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[21:08:46] [PASSED] single_pixel_source_buffer
[21:08:46] [PASSED] single_pixel_clip_rectangle
[21:08:46] [PASSED] well_known_colors
[21:08:46] [PASSED] destination_pitch
[21:08:46] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[21:08:46] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[21:08:46] [PASSED] single_pixel_source_buffer
[21:08:46] [PASSED] single_pixel_clip_rectangle
[21:08:46] [PASSED] well_known_colors
[21:08:46] [PASSED] destination_pitch
[21:08:46] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[21:08:46] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[21:08:46] [PASSED] single_pixel_source_buffer
[21:08:46] [PASSED] single_pixel_clip_rectangle
[21:08:46] [PASSED] well_known_colors
[21:08:46] [PASSED] destination_pitch
[21:08:46] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[21:08:46] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[21:08:46] [PASSED] single_pixel_source_buffer
[21:08:46] [PASSED] single_pixel_clip_rectangle
[21:08:46] [PASSED] well_known_colors
[21:08:46] [PASSED] destination_pitch
[21:08:46] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[21:08:46] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[21:08:46] [PASSED] single_pixel_source_buffer
[21:08:46] [PASSED] single_pixel_clip_rectangle
[21:08:46] [PASSED] well_known_colors
[21:08:46] [PASSED] destination_pitch
[21:08:46] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[21:08:46] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[21:08:46] [PASSED] single_pixel_source_buffer
[21:08:46] [PASSED] single_pixel_clip_rectangle
[21:08:46] [PASSED] well_known_colors
[21:08:46] [PASSED] destination_pitch
[21:08:46] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[21:08:46] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[21:08:46] [PASSED] single_pixel_source_buffer
[21:08:46] [PASSED] single_pixel_clip_rectangle
[21:08:46] [PASSED] well_known_colors
[21:08:46] [PASSED] destination_pitch
[21:08:46] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[21:08:46] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[21:08:46] [PASSED] single_pixel_source_buffer
[21:08:46] [PASSED] single_pixel_clip_rectangle
[21:08:46] [PASSED] well_known_colors
[21:08:46] [PASSED] destination_pitch
[21:08:46] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[21:08:46] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[21:08:46] [PASSED] single_pixel_source_buffer
[21:08:46] [PASSED] single_pixel_clip_rectangle
[21:08:46] [PASSED] well_known_colors
[21:08:46] [PASSED] destination_pitch
[21:08:46] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[21:08:46] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[21:08:46] [PASSED] single_pixel_source_buffer
[21:08:46] [PASSED] single_pixel_clip_rectangle
[21:08:46] [PASSED] well_known_colors
[21:08:46] [PASSED] destination_pitch
[21:08:46] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[21:08:46] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[21:08:46] [PASSED] single_pixel_source_buffer
[21:08:46] [PASSED] single_pixel_clip_rectangle
[21:08:46] [PASSED] well_known_colors
[21:08:46] [PASSED] destination_pitch
[21:08:46] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[21:08:46] ============== drm_test_fb_xrgb8888_to_mono ===============
[21:08:46] [PASSED] single_pixel_source_buffer
[21:08:46] [PASSED] single_pixel_clip_rectangle
[21:08:46] [PASSED] well_known_colors
[21:08:46] [PASSED] destination_pitch
[21:08:46] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[21:08:46] ==================== drm_test_fb_swab =====================
[21:08:46] [PASSED] single_pixel_source_buffer
[21:08:46] [PASSED] single_pixel_clip_rectangle
[21:08:46] [PASSED] well_known_colors
[21:08:46] [PASSED] destination_pitch
[21:08:46] ================ [PASSED] drm_test_fb_swab =================
[21:08:46] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[21:08:46] [PASSED] single_pixel_source_buffer
[21:08:46] [PASSED] single_pixel_clip_rectangle
[21:08:46] [PASSED] well_known_colors
[21:08:46] [PASSED] destination_pitch
[21:08:46] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[21:08:46] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[21:08:46] [PASSED] single_pixel_source_buffer
[21:08:46] [PASSED] single_pixel_clip_rectangle
[21:08:46] [PASSED] well_known_colors
[21:08:46] [PASSED] destination_pitch
[21:08:46] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[21:08:46] ================= drm_test_fb_clip_offset =================
[21:08:46] [PASSED] pass through
[21:08:46] [PASSED] horizontal offset
[21:08:46] [PASSED] vertical offset
[21:08:46] [PASSED] horizontal and vertical offset
[21:08:46] [PASSED] horizontal offset (custom pitch)
[21:08:46] [PASSED] vertical offset (custom pitch)
[21:08:46] [PASSED] horizontal and vertical offset (custom pitch)
[21:08:46] ============= [PASSED] drm_test_fb_clip_offset =============
[21:08:46] =================== drm_test_fb_memcpy ====================
[21:08:46] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[21:08:46] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[21:08:46] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[21:08:46] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[21:08:46] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[21:08:46] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[21:08:46] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[21:08:46] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[21:08:46] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[21:08:46] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[21:08:46] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[21:08:46] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[21:08:46] =============== [PASSED] drm_test_fb_memcpy ================
[21:08:46] ============= [PASSED] drm_format_helper_test ==============
[21:08:46] ================= drm_format (18 subtests) =================
[21:08:46] [PASSED] drm_test_format_block_width_invalid
[21:08:46] [PASSED] drm_test_format_block_width_one_plane
[21:08:46] [PASSED] drm_test_format_block_width_two_plane
[21:08:46] [PASSED] drm_test_format_block_width_three_plane
[21:08:46] [PASSED] drm_test_format_block_width_tiled
[21:08:46] [PASSED] drm_test_format_block_height_invalid
[21:08:46] [PASSED] drm_test_format_block_height_one_plane
[21:08:46] [PASSED] drm_test_format_block_height_two_plane
[21:08:46] [PASSED] drm_test_format_block_height_three_plane
[21:08:46] [PASSED] drm_test_format_block_height_tiled
[21:08:46] [PASSED] drm_test_format_min_pitch_invalid
[21:08:46] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[21:08:46] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[21:08:46] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[21:08:46] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[21:08:46] [PASSED] drm_test_format_min_pitch_two_plane
[21:08:46] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[21:08:46] [PASSED] drm_test_format_min_pitch_tiled
[21:08:46] =================== [PASSED] drm_format ====================
[21:08:46] ============== drm_framebuffer (10 subtests) ===============
[21:08:46] ========== drm_test_framebuffer_check_src_coords ==========
[21:08:46] [PASSED] Success: source fits into fb
[21:08:46] [PASSED] Fail: overflowing fb with x-axis coordinate
[21:08:46] [PASSED] Fail: overflowing fb with y-axis coordinate
[21:08:46] [PASSED] Fail: overflowing fb with source width
[21:08:46] [PASSED] Fail: overflowing fb with source height
[21:08:46] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[21:08:46] [PASSED] drm_test_framebuffer_cleanup
[21:08:46] =============== drm_test_framebuffer_create ===============
[21:08:46] [PASSED] ABGR8888 normal sizes
[21:08:46] [PASSED] ABGR8888 max sizes
[21:08:46] [PASSED] ABGR8888 pitch greater than min required
[21:08:46] [PASSED] ABGR8888 pitch less than min required
[21:08:46] [PASSED] ABGR8888 Invalid width
[21:08:46] [PASSED] ABGR8888 Invalid buffer handle
[21:08:46] [PASSED] No pixel format
[21:08:46] [PASSED] ABGR8888 Width 0
[21:08:46] [PASSED] ABGR8888 Height 0
[21:08:46] [PASSED] ABGR8888 Out of bound height * pitch combination
[21:08:46] [PASSED] ABGR8888 Large buffer offset
[21:08:46] [PASSED] ABGR8888 Buffer offset for inexistent plane
[21:08:46] [PASSED] ABGR8888 Invalid flag
[21:08:46] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[21:08:46] [PASSED] ABGR8888 Valid buffer modifier
[21:08:46] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[21:08:46] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[21:08:46] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[21:08:46] [PASSED] NV12 Normal sizes
[21:08:46] [PASSED] NV12 Max sizes
[21:08:46] [PASSED] NV12 Invalid pitch
[21:08:46] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[21:08:46] [PASSED] NV12 different modifier per-plane
[21:08:46] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[21:08:46] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[21:08:46] [PASSED] NV12 Modifier for inexistent plane
[21:08:46] [PASSED] NV12 Handle for inexistent plane
[21:08:46] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[21:08:46] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[21:08:46] [PASSED] YVU420 Normal sizes
[21:08:46] [PASSED] YVU420 Max sizes
[21:08:46] [PASSED] YVU420 Invalid pitch
[21:08:46] [PASSED] YVU420 Different pitches
[21:08:46] [PASSED] YVU420 Different buffer offsets/pitches
[21:08:46] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[21:08:46] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[21:08:46] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[21:08:46] [PASSED] YVU420 Valid modifier
[21:08:46] [PASSED] YVU420 Different modifiers per plane
[21:08:46] [PASSED] YVU420 Modifier for inexistent plane
[21:08:46] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[21:08:46] [PASSED] X0L2 Normal sizes
[21:08:46] [PASSED] X0L2 Max sizes
[21:08:46] [PASSED] X0L2 Invalid pitch
[21:08:46] [PASSED] X0L2 Pitch greater than minimum required
[21:08:46] [PASSED] X0L2 Handle for inexistent plane
[21:08:46] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[21:08:46] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[21:08:46] [PASSED] X0L2 Valid modifier
[21:08:46] [PASSED] X0L2 Modifier for inexistent plane
[21:08:46] =========== [PASSED] drm_test_framebuffer_create ===========
[21:08:46] [PASSED] drm_test_framebuffer_free
[21:08:46] [PASSED] drm_test_framebuffer_init
[21:08:46] [PASSED] drm_test_framebuffer_init_bad_format
[21:08:46] [PASSED] drm_test_framebuffer_init_dev_mismatch
[21:08:46] [PASSED] drm_test_framebuffer_lookup
[21:08:46] [PASSED] drm_test_framebuffer_lookup_inexistent
[21:08:46] [PASSED] drm_test_framebuffer_modifiers_not_supported
[21:08:46] ================= [PASSED] drm_framebuffer =================
[21:08:46] ================ drm_gem_shmem (8 subtests) ================
[21:08:46] [PASSED] drm_gem_shmem_test_obj_create
[21:08:46] [PASSED] drm_gem_shmem_test_obj_create_private
[21:08:46] [PASSED] drm_gem_shmem_test_pin_pages
[21:08:46] [PASSED] drm_gem_shmem_test_vmap
[21:08:46] [PASSED] drm_gem_shmem_test_get_sg_table
[21:08:46] [PASSED] drm_gem_shmem_test_get_pages_sgt
[21:08:46] [PASSED] drm_gem_shmem_test_madvise
[21:08:46] [PASSED] drm_gem_shmem_test_purge
[21:08:46] ================== [PASSED] drm_gem_shmem ==================
[21:08:46] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[21:08:46] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[21:08:46] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[21:08:46] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[21:08:46] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[21:08:46] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[21:08:46] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[21:08:46] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[21:08:46] [PASSED] Automatic
[21:08:46] [PASSED] Full
[21:08:46] [PASSED] Limited 16:235
[21:08:46] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[21:08:46] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[21:08:46] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[21:08:46] [PASSED] drm_test_check_disable_connector
[21:08:46] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[21:08:46] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[21:08:46] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[21:08:46] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[21:08:46] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[21:08:46] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[21:08:46] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[21:08:46] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[21:08:46] [PASSED] drm_test_check_output_bpc_dvi
[21:08:46] [PASSED] drm_test_check_output_bpc_format_vic_1
[21:08:46] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[21:08:46] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[21:08:46] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[21:08:46] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[21:08:46] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[21:08:46] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[21:08:46] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[21:08:46] ============ drm_test_check_hdmi_color_format =============
[21:08:46] [PASSED] AUTO -> RGB
[21:08:46] [PASSED] YCBCR422 -> YUV422
[21:08:46] [PASSED] YCBCR420 -> YUV420
[21:08:46] [PASSED] YCBCR444 -> YUV444
[21:08:46] [PASSED] RGB -> RGB
[21:08:46] ======== [PASSED] drm_test_check_hdmi_color_format =========
[21:08:46] ======== drm_test_check_hdmi_color_format_420_only ========
[21:08:46] [PASSED] RGB should fail
[21:08:46] [PASSED] YUV444 should fail
[21:08:46] [PASSED] YUV422 should fail
[21:08:46] [PASSED] YUV420 should work
[21:08:46] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[21:08:46] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[21:08:46] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[21:08:46] [PASSED] drm_test_check_broadcast_rgb_value
[21:08:46] [PASSED] drm_test_check_bpc_8_value
[21:08:46] [PASSED] drm_test_check_bpc_10_value
[21:08:46] [PASSED] drm_test_check_bpc_12_value
[21:08:46] [PASSED] drm_test_check_format_value
[21:08:46] [PASSED] drm_test_check_tmds_char_value
[21:08:46] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[21:08:46] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[21:08:46] [PASSED] drm_test_check_mode_valid
[21:08:46] [PASSED] drm_test_check_mode_valid_reject
[21:08:46] [PASSED] drm_test_check_mode_valid_reject_rate
[21:08:46] [PASSED] drm_test_check_mode_valid_reject_max_clock
[21:08:46] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[21:08:46] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[21:08:46] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[21:08:46] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[21:08:46] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[21:08:46] [PASSED] drm_test_check_infoframes
[21:08:46] [PASSED] drm_test_check_reject_avi_infoframe
[21:08:46] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[21:08:46] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[21:08:46] [PASSED] drm_test_check_reject_audio_infoframe
[21:08:46] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[21:08:46] ================= drm_managed (2 subtests) =================
[21:08:46] [PASSED] drm_test_managed_release_action
[21:08:46] [PASSED] drm_test_managed_run_action
[21:08:46] =================== [PASSED] drm_managed ===================
[21:08:46] =================== drm_mm (6 subtests) ====================
[21:08:46] [PASSED] drm_test_mm_init
[21:08:46] [PASSED] drm_test_mm_debug
[21:08:46] [PASSED] drm_test_mm_align32
[21:08:46] [PASSED] drm_test_mm_align64
[21:08:46] [PASSED] drm_test_mm_lowest
[21:08:46] [PASSED] drm_test_mm_highest
[21:08:46] ===================== [PASSED] drm_mm ======================
[21:08:46] ============= drm_modes_analog_tv (5 subtests) =============
[21:08:46] [PASSED] drm_test_modes_analog_tv_mono_576i
[21:08:46] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[21:08:46] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[21:08:46] [PASSED] drm_test_modes_analog_tv_pal_576i
[21:08:46] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[21:08:46] =============== [PASSED] drm_modes_analog_tv ===============
[21:08:46] ============== drm_panic_helper (3 subtests) ===============
[21:08:46] ============= drm_test_panic_screen_user_map ==============
[21:08:46] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[21:08:46] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[21:08:46] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[21:08:46] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[21:08:46] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[21:08:46] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[21:08:46] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[21:08:46] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[21:08:46] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[21:08:46] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[21:08:46] ========= [PASSED] drm_test_panic_screen_user_map ==========
[21:08:46] ============= drm_test_panic_screen_user_page =============
[21:08:46] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[21:08:46] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[21:08:46] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[21:08:46] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[21:08:46] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[21:08:46] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[21:08:46] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[21:08:46] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[21:08:46] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[21:08:46] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[21:08:46] ========= [PASSED] drm_test_panic_screen_user_page =========
[21:08:46] ========== drm_test_panic_screen_user_set_pixel ===========
[21:08:46] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[21:08:46] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[21:08:46] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[21:08:46] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[21:08:46] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[21:08:46] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[21:08:46] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[21:08:46] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[21:08:46] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[21:08:46] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[21:08:46] ====== [PASSED] drm_test_panic_screen_user_set_pixel =======
[21:08:46] ================ [PASSED] drm_panic_helper =================
[21:08:46] ============== drm_plane_helper (2 subtests) ===============
[21:08:46] =============== drm_test_check_plane_state ================
[21:08:46] [PASSED] clipping_simple
[21:08:46] [PASSED] clipping_rotate_reflect
[21:08:46] [PASSED] positioning_simple
[21:08:46] [PASSED] upscaling
[21:08:46] [PASSED] downscaling
[21:08:46] [PASSED] rounding1
[21:08:46] [PASSED] rounding2
[21:08:46] [PASSED] rounding3
[21:08:46] [PASSED] rounding4
[21:08:46] =========== [PASSED] drm_test_check_plane_state ============
[21:08:46] =========== drm_test_check_invalid_plane_state ============
[21:08:46] [PASSED] positioning_invalid
[21:08:46] [PASSED] upscaling_invalid
[21:08:46] [PASSED] downscaling_invalid
[21:08:46] ======= [PASSED] drm_test_check_invalid_plane_state ========
[21:08:46] ================ [PASSED] drm_plane_helper =================
[21:08:46] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[21:08:46] ====== drm_test_connector_helper_tv_get_modes_check =======
[21:08:46] [PASSED] None
[21:08:46] [PASSED] PAL
[21:08:46] [PASSED] NTSC
[21:08:46] [PASSED] Both, NTSC Default
[21:08:46] [PASSED] Both, PAL Default
[21:08:46] [PASSED] Both, NTSC Default, with PAL on command-line
[21:08:46] [PASSED] Both, PAL Default, with NTSC on command-line
[21:08:46] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[21:08:46] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[21:08:46] ================== drm_rect (9 subtests) ===================
[21:08:46] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[21:08:46] [PASSED] drm_test_rect_clip_scaled_not_clipped
[21:08:46] [PASSED] drm_test_rect_clip_scaled_clipped
[21:08:46] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[21:08:46] ================= drm_test_rect_intersect =================
[21:08:46] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[21:08:46] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[21:08:46] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[21:08:46] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[21:08:46] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[21:08:46] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[21:08:46] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[21:08:46] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[21:08:46] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[21:08:46] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[21:08:46] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[21:08:46] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[21:08:46] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[21:08:46] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[21:08:46] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[21:08:46] ============= [PASSED] drm_test_rect_intersect =============
[21:08:46] ================ drm_test_rect_calc_hscale ================
[21:08:46] [PASSED] normal use
[21:08:46] [PASSED] out of max range
[21:08:46] [PASSED] out of min range
[21:08:46] [PASSED] zero dst
[21:08:46] [PASSED] negative src
[21:08:46] [PASSED] negative dst
[21:08:46] ============ [PASSED] drm_test_rect_calc_hscale ============
[21:08:46] ================ drm_test_rect_calc_vscale ================
[21:08:46] [PASSED] normal use
[21:08:46] [PASSED] out of max range
[21:08:46] [PASSED] out of min range
[21:08:46] [PASSED] zero dst
[21:08:46] [PASSED] negative src
[21:08:46] [PASSED] negative dst
[21:08:46] ============ [PASSED] drm_test_rect_calc_vscale ============
[21:08:46] ================== drm_test_rect_rotate ===================
[21:08:46] [PASSED] reflect-x
[21:08:46] [PASSED] reflect-y
[21:08:46] [PASSED] rotate-0
[21:08:46] [PASSED] rotate-90
[21:08:46] [PASSED] rotate-180
[21:08:46] [PASSED] rotate-270
[21:08:46] ============== [PASSED] drm_test_rect_rotate ===============
[21:08:46] ================ drm_test_rect_rotate_inv =================
[21:08:46] [PASSED] reflect-x
[21:08:46] [PASSED] reflect-y
[21:08:46] [PASSED] rotate-0
[21:08:46] [PASSED] rotate-90
[21:08:46] [PASSED] rotate-180
[21:08:46] [PASSED] rotate-270
[21:08:46] ============ [PASSED] drm_test_rect_rotate_inv =============
[21:08:46] ==================== [PASSED] drm_rect =====================
[21:08:46] ============ drm_sysfb_modeset_test (1 subtest) ============
[21:08:46] ============ drm_test_sysfb_build_fourcc_list =============
[21:08:46] [PASSED] no native formats
[21:08:46] [PASSED] XRGB8888 as native format
[21:08:46] [PASSED] remove duplicates
[21:08:46] [PASSED] convert alpha formats
[21:08:46] [PASSED] random formats
[21:08:46] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[21:08:46] ============= [PASSED] drm_sysfb_modeset_test ==============
[21:08:46] ================== drm_fixp (2 subtests) ===================
[21:08:46] [PASSED] drm_test_int2fixp
[21:08:46] [PASSED] drm_test_sm2fixp
[21:08:46] ==================== [PASSED] drm_fixp =====================
[21:08:46] ============================================================
[21:08:46] Testing complete. Ran 667 tests: passed: 667
[21:08:46] Elapsed time: 27.186s total, 1.821s configuring, 24.949s building, 0.408s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[21:08:46] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:08:48] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:08:58] Starting KUnit Kernel (1/1)...
[21:08:58] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:08:58] ================= ttm_device (5 subtests) ==================
[21:08:58] [PASSED] ttm_device_init_basic
[21:08:58] [PASSED] ttm_device_init_multiple
[21:08:58] [PASSED] ttm_device_fini_basic
[21:08:58] [PASSED] ttm_device_init_no_vma_man
[21:08:58] ================== ttm_device_init_pools ==================
[21:08:58] [PASSED] No DMA allocations, no DMA32 required
[21:08:58] [PASSED] DMA allocations, DMA32 required
[21:08:58] [PASSED] No DMA allocations, DMA32 required
[21:08:58] [PASSED] DMA allocations, no DMA32 required
[21:08:58] ============== [PASSED] ttm_device_init_pools ==============
[21:08:58] =================== [PASSED] ttm_device ====================
[21:08:58] ================== ttm_pool (8 subtests) ===================
[21:08:58] ================== ttm_pool_alloc_basic ===================
[21:08:58] [PASSED] One page
[21:08:58] [PASSED] More than one page
[21:08:58] [PASSED] Above the allocation limit
[21:08:58] [PASSED] One page, with coherent DMA mappings enabled
[21:08:58] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:08:58] ============== [PASSED] ttm_pool_alloc_basic ===============
[21:08:58] ============== ttm_pool_alloc_basic_dma_addr ==============
[21:08:58] [PASSED] One page
[21:08:58] [PASSED] More than one page
[21:08:58] [PASSED] Above the allocation limit
[21:08:58] [PASSED] One page, with coherent DMA mappings enabled
[21:08:58] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:08:58] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[21:08:58] [PASSED] ttm_pool_alloc_order_caching_match
[21:08:58] [PASSED] ttm_pool_alloc_caching_mismatch
[21:08:58] [PASSED] ttm_pool_alloc_order_mismatch
[21:08:58] [PASSED] ttm_pool_free_dma_alloc
[21:08:58] [PASSED] ttm_pool_free_no_dma_alloc
[21:08:58] [PASSED] ttm_pool_fini_basic
[21:08:58] ==================== [PASSED] ttm_pool =====================
[21:08:58] ================ ttm_resource (8 subtests) =================
[21:08:58] ================= ttm_resource_init_basic =================
[21:08:58] [PASSED] Init resource in TTM_PL_SYSTEM
[21:08:58] [PASSED] Init resource in TTM_PL_VRAM
[21:08:58] [PASSED] Init resource in a private placement
[21:08:58] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[21:08:58] ============= [PASSED] ttm_resource_init_basic =============
[21:08:58] [PASSED] ttm_resource_init_pinned
[21:08:58] [PASSED] ttm_resource_fini_basic
[21:08:58] [PASSED] ttm_resource_manager_init_basic
[21:08:58] [PASSED] ttm_resource_manager_usage_basic
[21:08:58] [PASSED] ttm_resource_manager_set_used_basic
[21:08:58] [PASSED] ttm_sys_man_alloc_basic
[21:08:58] [PASSED] ttm_sys_man_free_basic
[21:08:58] ================== [PASSED] ttm_resource ===================
[21:08:58] =================== ttm_tt (15 subtests) ===================
[21:08:58] ==================== ttm_tt_init_basic ====================
[21:08:58] [PASSED] Page-aligned size
[21:08:58] [PASSED] Extra pages requested
[21:08:58] ================ [PASSED] ttm_tt_init_basic ================
[21:08:58] [PASSED] ttm_tt_init_misaligned
[21:08:58] [PASSED] ttm_tt_fini_basic
[21:08:58] [PASSED] ttm_tt_fini_sg
[21:08:58] [PASSED] ttm_tt_fini_shmem
[21:08:58] [PASSED] ttm_tt_create_basic
[21:08:58] [PASSED] ttm_tt_create_invalid_bo_type
[21:08:58] [PASSED] ttm_tt_create_ttm_exists
[21:08:58] [PASSED] ttm_tt_create_failed
[21:08:58] [PASSED] ttm_tt_destroy_basic
[21:08:58] [PASSED] ttm_tt_populate_null_ttm
[21:08:58] [PASSED] ttm_tt_populate_populated_ttm
[21:08:58] [PASSED] ttm_tt_unpopulate_basic
[21:08:58] [PASSED] ttm_tt_unpopulate_empty_ttm
[21:08:58] [PASSED] ttm_tt_swapin_basic
[21:08:58] ===================== [PASSED] ttm_tt ======================
[21:08:58] =================== ttm_bo (14 subtests) ===================
[21:08:58] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[21:08:58] [PASSED] Cannot be interrupted and sleeps
[21:08:58] [PASSED] Cannot be interrupted, locks straight away
[21:08:58] [PASSED] Can be interrupted, sleeps
[21:08:58] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[21:08:58] [PASSED] ttm_bo_reserve_locked_no_sleep
[21:08:58] [PASSED] ttm_bo_reserve_no_wait_ticket
[21:08:59] [PASSED] ttm_bo_reserve_double_resv
[21:08:59] [PASSED] ttm_bo_reserve_interrupted
[21:08:59] [PASSED] ttm_bo_reserve_deadlock
[21:08:59] [PASSED] ttm_bo_unreserve_basic
[21:08:59] [PASSED] ttm_bo_unreserve_pinned
[21:08:59] [PASSED] ttm_bo_unreserve_bulk
[21:08:59] [PASSED] ttm_bo_fini_basic
[21:08:59] [PASSED] ttm_bo_fini_shared_resv
[21:08:59] [PASSED] ttm_bo_pin_basic
[21:08:59] [PASSED] ttm_bo_pin_unpin_resource
[21:08:59] [PASSED] ttm_bo_multiple_pin_one_unpin
[21:08:59] ===================== [PASSED] ttm_bo ======================
[21:08:59] ============== ttm_bo_validate (22 subtests) ===============
[21:08:59] ============== ttm_bo_init_reserved_sys_man ===============
[21:08:59] [PASSED] Buffer object for userspace
[21:08:59] [PASSED] Kernel buffer object
[21:08:59] [PASSED] Shared buffer object
[21:08:59] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[21:08:59] ============== ttm_bo_init_reserved_mock_man ==============
[21:08:59] [PASSED] Buffer object for userspace
[21:08:59] [PASSED] Kernel buffer object
[21:08:59] [PASSED] Shared buffer object
[21:08:59] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[21:08:59] [PASSED] ttm_bo_init_reserved_resv
[21:08:59] ================== ttm_bo_validate_basic ==================
[21:08:59] [PASSED] Buffer object for userspace
[21:08:59] [PASSED] Kernel buffer object
[21:08:59] [PASSED] Shared buffer object
[21:08:59] ============== [PASSED] ttm_bo_validate_basic ==============
[21:08:59] [PASSED] ttm_bo_validate_invalid_placement
[21:08:59] ============= ttm_bo_validate_same_placement ==============
[21:08:59] [PASSED] System manager
[21:08:59] [PASSED] VRAM manager
[21:08:59] ========= [PASSED] ttm_bo_validate_same_placement ==========
[21:08:59] [PASSED] ttm_bo_validate_failed_alloc
[21:08:59] [PASSED] ttm_bo_validate_pinned
[21:08:59] [PASSED] ttm_bo_validate_busy_placement
[21:08:59] ================ ttm_bo_validate_multihop =================
[21:08:59] [PASSED] Buffer object for userspace
[21:08:59] [PASSED] Kernel buffer object
[21:08:59] [PASSED] Shared buffer object
[21:08:59] ============ [PASSED] ttm_bo_validate_multihop =============
[21:08:59] ========== ttm_bo_validate_no_placement_signaled ==========
[21:08:59] [PASSED] Buffer object in system domain, no page vector
[21:08:59] [PASSED] Buffer object in system domain with an existing page vector
[21:08:59] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[21:08:59] ======== ttm_bo_validate_no_placement_not_signaled ========
[21:08:59] [PASSED] Buffer object for userspace
[21:08:59] [PASSED] Kernel buffer object
[21:08:59] [PASSED] Shared buffer object
[21:08:59] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[21:08:59] [PASSED] ttm_bo_validate_move_fence_signaled
[21:08:59] ========= ttm_bo_validate_move_fence_not_signaled =========
[21:08:59] [PASSED] Waits for GPU
[21:08:59] [PASSED] Tries to lock straight away
[21:08:59] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[21:08:59] [PASSED] ttm_bo_validate_swapout
[21:08:59] [PASSED] ttm_bo_validate_happy_evict
[21:08:59] [PASSED] ttm_bo_validate_all_pinned_evict
[21:08:59] [PASSED] ttm_bo_validate_allowed_only_evict
[21:08:59] [PASSED] ttm_bo_validate_deleted_evict
[21:08:59] [PASSED] ttm_bo_validate_busy_domain_evict
[21:08:59] [PASSED] ttm_bo_validate_evict_gutting
[21:08:59] [PASSED] ttm_bo_validate_recrusive_evict
[21:08:59] ================= [PASSED] ttm_bo_validate =================
[21:08:59] ============================================================
[21:08:59] Testing complete. Ran 102 tests: passed: 102
[21:08:59] Elapsed time: 12.291s total, 1.871s configuring, 10.206s building, 0.176s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[21:08:59] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:09:01] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:09:09] Starting KUnit Kernel (1/1)...
[21:09:09] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:09:09] =============== dma-buf-fence (12 subtests) ================
[21:09:09] [PASSED] test_sanitycheck
[21:09:09] [PASSED] test_signaling
[21:09:09] [PASSED] test_add_callback
[21:09:09] [PASSED] test_late_add_callback
[21:09:09] [PASSED] test_rm_callback
[21:09:09] [PASSED] test_late_rm_callback
[21:09:09] [PASSED] test_status
[21:09:09] [PASSED] test_error
[21:09:09] [PASSED] test_wait
[21:09:09] [PASSED] test_wait_timeout
[21:09:09] [PASSED] test_stub
[21:09:09] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[21:09:09] ================== [PASSED] dma-buf-fence ==================
[21:09:09] ============ dma-buf-fence-chain (11 subtests) =============
[21:09:09] [PASSED] test_sanitycheck
[21:09:09] [PASSED] test_find_seqno
[21:09:09] [PASSED] test_find_signaled
[21:09:09] [PASSED] test_find_out_of_order
[21:09:15] [PASSED] test_find_gap
[21:09:15] [PASSED] test_find_race
[21:09:15] [PASSED] test_signal_forward
[21:09:15] [PASSED] test_signal_backward
[21:09:15] [PASSED] test_wait_forward
[21:09:15] [PASSED] test_wait_backward
[21:09:15] [PASSED] test_wait_random
[21:09:15] =============== [PASSED] dma-buf-fence-chain ===============
[21:09:15] ============ dma-buf-fence-unwrap (11 subtests) ============
[21:09:15] [PASSED] test_sanitycheck
[21:09:15] [PASSED] test_unwrap_array
[21:09:15] [PASSED] test_unwrap_chain
[21:09:15] [PASSED] test_unwrap_chain_array
[21:09:15] [PASSED] test_unwrap_merge
[21:09:15] [PASSED] test_unwrap_merge_duplicate
[21:09:15] [PASSED] test_unwrap_merge_seqno
[21:09:15] [PASSED] test_unwrap_merge_order
[21:09:15] [PASSED] test_unwrap_merge_complex
[21:09:15] [PASSED] test_unwrap_merge_complex_seqno
[21:09:15] [PASSED] test_dedup_empty
[21:09:15] ============== [PASSED] dma-buf-fence-unwrap ===============
[21:09:15] ================ dma-buf-resv (5 subtests) =================
[21:09:15] [PASSED] test_sanitycheck
[21:09:15] ===================== test_signaling ======================
[21:09:15] [PASSED] kernel
[21:09:15] [PASSED] write
[21:09:15] [PASSED] read
[21:09:15] [PASSED] bookkeep
[21:09:15] ================= [PASSED] test_signaling ==================
[21:09:15] ====================== test_for_each ======================
[21:09:15] [PASSED] kernel
[21:09:15] [PASSED] write
[21:09:15] [PASSED] read
[21:09:15] [PASSED] bookkeep
[21:09:15] ================== [PASSED] test_for_each ==================
[21:09:15] ================= test_for_each_unlocked ==================
[21:09:15] [PASSED] kernel
[21:09:15] [PASSED] write
[21:09:15] [PASSED] read
[21:09:15] [PASSED] bookkeep
[21:09:15] ============= [PASSED] test_for_each_unlocked ==============
[21:09:15] ===================== test_get_fences =====================
[21:09:15] [PASSED] kernel
[21:09:15] [PASSED] write
[21:09:15] [PASSED] read
[21:09:15] [PASSED] bookkeep
[21:09:15] ================= [PASSED] test_get_fences =================
[21:09:15] ================== [PASSED] dma-buf-resv ===================
[21:09:15] ============================================================
[21:09:15] Testing complete. Ran 51 tests: passed: 50, skipped: 1
[21:09:15] Elapsed time: 15.896s total, 1.861s configuring, 8.764s building, 5.264s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ i915.CI.BAT: success for drm/i915/vrr: HDMI 2.1 VRR support
2026-10-30 20:32 [RFC v1 0/3] drm/i915/vrr: HDMI 2.1 VRR support Alan Stead
` (3 preceding siblings ...)
2026-10-30 21:09 ` ✓ CI.KUnit: success for drm/i915/vrr: HDMI 2.1 VRR support Patchwork
@ 2026-10-30 21:29 ` Patchwork
2026-10-30 21:45 ` ✓ Xe.CI.BAT: " Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2026-10-30 21:29 UTC (permalink / raw)
To: Alan Stead; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 993 bytes --]
== Series Details ==
Series: drm/i915/vrr: HDMI 2.1 VRR support
URL : https://patchwork.freedesktop.org/series/177288/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_19420 -> Patchwork_177288v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_177288v1/index.html
Participating hosts (40 -> 38)
------------------------------
Missing (2): bat-dg2-13 fi-glk-j4005
Changes
-------
No changes found
Build changes
-------------
* Linux: CI_DRM_19420 -> Patchwork_177288v1
CI-20190529: 20190529
CI_DRM_19420: 238c1e3e984e2b7f948cb24165314b8d719a23d6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_9172: 9172
Patchwork_177288v1: 238c1e3e984e2b7f948cb24165314b8d719a23d6 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_177288v1/index.html
[-- Attachment #2: Type: text/html, Size: 1558 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Xe.CI.BAT: success for drm/i915/vrr: HDMI 2.1 VRR support
2026-10-30 20:32 [RFC v1 0/3] drm/i915/vrr: HDMI 2.1 VRR support Alan Stead
` (4 preceding siblings ...)
2026-10-30 21:29 ` ✓ i915.CI.BAT: " Patchwork
@ 2026-10-30 21:45 ` Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2026-10-30 21:45 UTC (permalink / raw)
To: Alan Stead; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 1421 bytes --]
== Series Details ==
Series: drm/i915/vrr: HDMI 2.1 VRR support
URL : https://patchwork.freedesktop.org/series/177287/
State : success
== Summary ==
CI Bug Log - changes from xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6_BAT -> xe-pw-177287v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (15 -> 15)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-177287v1_BAT that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- bat-bmg-2: [ABORT][1] ([Intel XE#9463]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/bat-bmg-2/igt@core_hotunplug@unbind-rebind.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177287v1/bat-bmg-2/igt@core_hotunplug@unbind-rebind.html
[Intel XE#9463]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9463
Build changes
-------------
* Linux: xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6 -> xe-pw-177287v1
IGT_9173: 9173
xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6: 238c1e3e984e2b7f948cb24165314b8d719a23d6
xe-pw-177287v1: 177287v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177287v1/index.html
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-- links below jump to the message on this page --
2026-10-30 20:32 [RFC v1 0/3] drm/i915/vrr: HDMI 2.1 VRR support Alan Stead
2026-10-30 20:32 ` [RFC v1 1/3] drm/i915/dip: Send HDMI EMPs early in V. Blank when VRR is in range Alan Stead
2026-10-30 20:46 ` sashiko-bot
2026-10-30 20:32 ` [RFC v1 2/3] drm/i915/dip: Send the HDMI 2.1 VTEM when VRR is enabled Alan Stead
2026-10-30 20:59 ` sashiko-bot
2026-10-30 20:32 ` [RFC v1 3/3] drm/i915/vrr: Allow VRR on HDMI 2.1 sinks Alan Stead
2026-10-30 20:58 ` sashiko-bot
2026-10-30 21:09 ` ✓ CI.KUnit: success for drm/i915/vrr: HDMI 2.1 VRR support Patchwork
2026-10-30 21:29 ` ✓ i915.CI.BAT: " Patchwork
2026-10-30 21:45 ` ✓ Xe.CI.BAT: " Patchwork
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