* [PATCH v7 00/23] Add CAMSS support for SM8750 and Eliza
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu, Atiya Kailany, Konrad Dybcio
This series adds CAMSS support for the Qualcomm SM8750 and Eliza SoCs.
SM8750 has CSID 980 and VFE 980. Eliza has CSID 970 and VFE 970, which
are register compatible with 980 apart from the VFE RDI write master
client IDs, so Eliza reuses the SM8750 CSID and VFE support. Both SoCs
have TPG v2.3.0. The CSIPHYs are described as standalone
phy-qcom-mipi-csi2 devices, linked to CAMSS through the OF graph.
SM8750 has 6 CSIPHYs, 3 CSID + 2 CSID Lite, 3 VFE + 2 VFE Lite and 3 TPGs.
Eliza has 4 CSIPHYs, 3 CSID + 1 CSID Lite, 3 VFE + 1 VFE Lite and 2 TPGs.
The series depends on the Kaanapali CAMSS series.
https://lore.kernel.org/all/20261112-kaanapali-camss-v25-0-1d709f57f370@oss.qualcomm.com/
Changes in v7:
- Rework the bindings: describe the SM8750 CSI2 PHY with its own
"qcom,sm8750-csi2-phy" compatible (plus the matching phy-qcom-mipi-csi2
entry) and move the CSIPHYs out of CAMSS as sibling PHY devices linked
through the OF graph. Drop the Reviewed-by tags of the CAMSS binding
- Krzysztof
- Add the "top" register region to the CAMSS binding, a PM clock list for
SM8750, and include the CSID clock scaling patch - Loic
- Clean up the CAMSS binding (reg-names, clock names, unused clocks and
interconnects, iommus description) and reuse the SA8775P TPG resources
- Vladimir, bod
- Rework CSID 980 and move VFE 980 into its own camss-vfe-980.c with
dedicated SM8750 resources, dropping its Reviewed-by - bod
- Drop the two-phase CSIPHY patch, the CSIPHYs are now handled by the
standalone PHY driver
- Add the SM8750 DTS and Eliza support (bindings, driver and DTS)
- Link to v6: https://lore.kernel.org/r/20260721-add-support-for-camss-on-sm8750-v6-0-a5f841061d18@oss.qualcomm.com
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
Hangxiang Ma (11):
dt-bindings: phy: qcom,x1e80100-csi2-phy: Add SM8750 CSI2 PHY
dt-bindings: media: qcom,sm8750-camss: Add SM8750 CAMSS
phy: qcom-mipi-csi2: Add SM8750 support
media: qcom: camss: Add SM8750 compatible
media: qcom: camss: Add PM clock definitions for SM8750
media: qcom: camss: csid: Add support for CSID 980
media: qcom: camss: vfe: Add support for VFE 980
media: qcom: camss: tpg: Add support for v2.3.0 TPG
arm64: dts: qcom: sm8750: Add CAMSS and CSIPHY block definitions
arm64: dts: qcom: sm8750: Add CCI definitions
arm64: dts: qcom: sm8750: Add camera MCLK pinctrl
Loic Poulain (1):
media: qcom: camss: csid: Scale the clocks with the CSI-2 link rate
Wenmeng Liu (11):
dt-bindings: phy: qcom,x1e80100-csi2-phy: Add Eliza CSI2 PHY
dt-bindings: media: qcom,eliza-camss: Add Eliza CAMSS
dt-bindings: i2c: qcom-cci: Document Eliza compatible
media: qcom: camss: Add Eliza compatible
arm64: dts: qcom: sm8750-qrd: Enable S5KJN1 camera sensor
arm64: dts: qcom: eliza: Add CAMSS and CSIPHY block definitions
arm64: dts: qcom: eliza: Add CCI definitions
arm64: dts: qcom: eliza: Add camera MCLK pinctrl
arm64: dts: qcom: eliza-mtp: Add PM8010 PMICs
arm64: dts: qcom: eliza-mtp: Enable rear camera
arm64: dts: qcom: eliza-evk-imx577-camera: Add DT overlay
.../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 +
.../bindings/media/qcom,eliza-camss.yaml | 282 ++++++++
.../bindings/media/qcom,sm8750-camss.yaml | 297 +++++++++
.../bindings/phy/qcom,x1e80100-csi2-phy.yaml | 9 +-
arch/arm64/boot/dts/qcom/Makefile | 4 +
.../boot/dts/qcom/eliza-evk-imx577-camera.dtso | 85 +++
arch/arm64/boot/dts/qcom/eliza-mtp.dts | 188 ++++++
arch/arm64/boot/dts/qcom/eliza.dtsi | 512 ++++++++++++++
arch/arm64/boot/dts/qcom/pm8010-eliza.dtsi | 81 +++
arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 72 ++
arch/arm64/boot/dts/qcom/sm8750.dtsi | 735 +++++++++++++++++++++
drivers/media/platform/qcom/camss/Makefile | 2 +
drivers/media/platform/qcom/camss/camss-csid-980.c | 478 ++++++++++++++
drivers/media/platform/qcom/camss/camss-csid.c | 208 ++++--
drivers/media/platform/qcom/camss/camss-csid.h | 1 +
drivers/media/platform/qcom/camss/camss-tpg-gen1.c | 5 +-
drivers/media/platform/qcom/camss/camss-vfe-980.c | 216 ++++++
drivers/media/platform/qcom/camss/camss-vfe.c | 4 +
drivers/media/platform/qcom/camss/camss-vfe.h | 1 +
drivers/media/platform/qcom/camss/camss.c | 229 +++++++
drivers/media/platform/qcom/camss/camss.h | 2 +
drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c | 1 +
22 files changed, 3370 insertions(+), 44 deletions(-)
---
base-commit: 84abb955b1015477aa11a96e2f3ac1b938b77f48
change-id: 20251126-add-support-for-camss-on-sm8750-506c4de36d88
prerequisite-message-id: 20261112-kaanapali-camss-v25-0-1d709f57f370@oss.qualcomm.com
prerequisite-patch-id: 6108fea87bf95e2911f09bbe7e95fa536c3ce397
prerequisite-patch-id: b347ad60c475f3035b04ec76741e0f1b5f095580
prerequisite-patch-id: a38055fcd5b32fbf7f7f03301a48b4ad8601386b
prerequisite-patch-id: 5faef8cef855ce6fa00e2c7f10f125431ede40a4
prerequisite-patch-id: ddf0ddaef84c2d088d08f17de8d20f6b966ace37
prerequisite-patch-id: 5d7b6860d43c9215836a0d50fb27d2d003d0bfd8
prerequisite-patch-id: 610b107ca35300b00e8edae31dfb959a4501ff66
prerequisite-patch-id: 0bfebf965372eab19b73ad9629cec919795b557a
prerequisite-patch-id: d386de6329dabce0b0a459384d28bf290e170552
prerequisite-patch-id: 702e37b99095301ba1dfb2b48a92f33575178d32
prerequisite-patch-id: bc7b2ea560fb0a75ae9b2858a40f7340cc63bebb
prerequisite-patch-id: 83a0f9a6655a615e796ab850955ff764b9dbbf03
prerequisite-patch-id: a579bc3d977dd6869ddd7e78247982e89bd3e86e
prerequisite-patch-id: 4ab7713c2b3b3df586b644772b04d33152f57a4c
prerequisite-patch-id: cf1743d9aeaa627ed310a663621e172a4c095837
Best regards,
--
Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v7 00/23] Add CAMSS support for SM8750 and Eliza
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu, Atiya Kailany, Konrad Dybcio
This series adds CAMSS support for the Qualcomm SM8750 and Eliza SoCs.
SM8750 has CSID 980 and VFE 980. Eliza has CSID 970 and VFE 970, which
are register compatible with 980 apart from the VFE RDI write master
client IDs, so Eliza reuses the SM8750 CSID and VFE support. Both SoCs
have TPG v2.3.0. The CSIPHYs are described as standalone
phy-qcom-mipi-csi2 devices, linked to CAMSS through the OF graph.
SM8750 has 6 CSIPHYs, 3 CSID + 2 CSID Lite, 3 VFE + 2 VFE Lite and 3 TPGs.
Eliza has 4 CSIPHYs, 3 CSID + 1 CSID Lite, 3 VFE + 1 VFE Lite and 2 TPGs.
The series depends on the Kaanapali CAMSS series.
https://lore.kernel.org/all/20261112-kaanapali-camss-v25-0-1d709f57f370@oss.qualcomm.com/
Changes in v7:
- Rework the bindings: describe the SM8750 CSI2 PHY with its own
"qcom,sm8750-csi2-phy" compatible (plus the matching phy-qcom-mipi-csi2
entry) and move the CSIPHYs out of CAMSS as sibling PHY devices linked
through the OF graph. Drop the Reviewed-by tags of the CAMSS binding
- Krzysztof
- Add the "top" register region to the CAMSS binding, a PM clock list for
SM8750, and include the CSID clock scaling patch - Loic
- Clean up the CAMSS binding (reg-names, clock names, unused clocks and
interconnects, iommus description) and reuse the SA8775P TPG resources
- Vladimir, bod
- Rework CSID 980 and move VFE 980 into its own camss-vfe-980.c with
dedicated SM8750 resources, dropping its Reviewed-by - bod
- Drop the two-phase CSIPHY patch, the CSIPHYs are now handled by the
standalone PHY driver
- Add the SM8750 DTS and Eliza support (bindings, driver and DTS)
- Link to v6: https://lore.kernel.org/r/20260721-add-support-for-camss-on-sm8750-v6-0-a5f841061d18@oss.qualcomm.com
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
Hangxiang Ma (11):
dt-bindings: phy: qcom,x1e80100-csi2-phy: Add SM8750 CSI2 PHY
dt-bindings: media: qcom,sm8750-camss: Add SM8750 CAMSS
phy: qcom-mipi-csi2: Add SM8750 support
media: qcom: camss: Add SM8750 compatible
media: qcom: camss: Add PM clock definitions for SM8750
media: qcom: camss: csid: Add support for CSID 980
media: qcom: camss: vfe: Add support for VFE 980
media: qcom: camss: tpg: Add support for v2.3.0 TPG
arm64: dts: qcom: sm8750: Add CAMSS and CSIPHY block definitions
arm64: dts: qcom: sm8750: Add CCI definitions
arm64: dts: qcom: sm8750: Add camera MCLK pinctrl
Loic Poulain (1):
media: qcom: camss: csid: Scale the clocks with the CSI-2 link rate
Wenmeng Liu (11):
dt-bindings: phy: qcom,x1e80100-csi2-phy: Add Eliza CSI2 PHY
dt-bindings: media: qcom,eliza-camss: Add Eliza CAMSS
dt-bindings: i2c: qcom-cci: Document Eliza compatible
media: qcom: camss: Add Eliza compatible
arm64: dts: qcom: sm8750-qrd: Enable S5KJN1 camera sensor
arm64: dts: qcom: eliza: Add CAMSS and CSIPHY block definitions
arm64: dts: qcom: eliza: Add CCI definitions
arm64: dts: qcom: eliza: Add camera MCLK pinctrl
arm64: dts: qcom: eliza-mtp: Add PM8010 PMICs
arm64: dts: qcom: eliza-mtp: Enable rear camera
arm64: dts: qcom: eliza-evk-imx577-camera: Add DT overlay
.../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 +
.../bindings/media/qcom,eliza-camss.yaml | 282 ++++++++
.../bindings/media/qcom,sm8750-camss.yaml | 297 +++++++++
.../bindings/phy/qcom,x1e80100-csi2-phy.yaml | 9 +-
arch/arm64/boot/dts/qcom/Makefile | 4 +
.../boot/dts/qcom/eliza-evk-imx577-camera.dtso | 85 +++
arch/arm64/boot/dts/qcom/eliza-mtp.dts | 188 ++++++
arch/arm64/boot/dts/qcom/eliza.dtsi | 512 ++++++++++++++
arch/arm64/boot/dts/qcom/pm8010-eliza.dtsi | 81 +++
arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 72 ++
arch/arm64/boot/dts/qcom/sm8750.dtsi | 735 +++++++++++++++++++++
drivers/media/platform/qcom/camss/Makefile | 2 +
drivers/media/platform/qcom/camss/camss-csid-980.c | 478 ++++++++++++++
drivers/media/platform/qcom/camss/camss-csid.c | 208 ++++--
drivers/media/platform/qcom/camss/camss-csid.h | 1 +
drivers/media/platform/qcom/camss/camss-tpg-gen1.c | 5 +-
drivers/media/platform/qcom/camss/camss-vfe-980.c | 216 ++++++
drivers/media/platform/qcom/camss/camss-vfe.c | 4 +
drivers/media/platform/qcom/camss/camss-vfe.h | 1 +
drivers/media/platform/qcom/camss/camss.c | 229 +++++++
drivers/media/platform/qcom/camss/camss.h | 2 +
drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c | 1 +
22 files changed, 3370 insertions(+), 44 deletions(-)
---
base-commit: 84abb955b1015477aa11a96e2f3ac1b938b77f48
change-id: 20251126-add-support-for-camss-on-sm8750-506c4de36d88
prerequisite-message-id: 20261112-kaanapali-camss-v25-0-1d709f57f370@oss.qualcomm.com
prerequisite-patch-id: 6108fea87bf95e2911f09bbe7e95fa536c3ce397
prerequisite-patch-id: b347ad60c475f3035b04ec76741e0f1b5f095580
prerequisite-patch-id: a38055fcd5b32fbf7f7f03301a48b4ad8601386b
prerequisite-patch-id: 5faef8cef855ce6fa00e2c7f10f125431ede40a4
prerequisite-patch-id: ddf0ddaef84c2d088d08f17de8d20f6b966ace37
prerequisite-patch-id: 5d7b6860d43c9215836a0d50fb27d2d003d0bfd8
prerequisite-patch-id: 610b107ca35300b00e8edae31dfb959a4501ff66
prerequisite-patch-id: 0bfebf965372eab19b73ad9629cec919795b557a
prerequisite-patch-id: d386de6329dabce0b0a459384d28bf290e170552
prerequisite-patch-id: 702e37b99095301ba1dfb2b48a92f33575178d32
prerequisite-patch-id: bc7b2ea560fb0a75ae9b2858a40f7340cc63bebb
prerequisite-patch-id: 83a0f9a6655a615e796ab850955ff764b9dbbf03
prerequisite-patch-id: a579bc3d977dd6869ddd7e78247982e89bd3e86e
prerequisite-patch-id: 4ab7713c2b3b3df586b644772b04d33152f57a4c
prerequisite-patch-id: cf1743d9aeaa627ed310a663621e172a4c095837
Best regards,
--
Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v7 01/23] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add SM8750 CSI2 PHY
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
The SM8750 camera subsystem has six CSI2 D-PHY blocks. Describe them
with a standalone "qcom,sm8750-csi2-phy" compatible, so the CAMSS
binding can instantiate the CSIPHY nodes as separate phy devices.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
index 6e9eb8e265df93b631101ae13f31f6365b6239b6..8ff3df1d0d2787b2af0499c1e4106b86f56ff82c 100644
--- a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
@@ -19,6 +19,7 @@ properties:
oneOf:
- enum:
- qcom,kaanapali-csi2-phy
+ - qcom,sm8750-csi2-phy
- qcom,x1e80100-csi2-phy
- items:
- const: qcom,glymur-csi2-phy
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 01/23] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add SM8750 CSI2 PHY
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
The SM8750 camera subsystem has six CSI2 D-PHY blocks. Describe them
with a standalone "qcom,sm8750-csi2-phy" compatible, so the CAMSS
binding can instantiate the CSIPHY nodes as separate phy devices.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
index 6e9eb8e265df93b631101ae13f31f6365b6239b6..8ff3df1d0d2787b2af0499c1e4106b86f56ff82c 100644
--- a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
@@ -19,6 +19,7 @@ properties:
oneOf:
- enum:
- qcom,kaanapali-csi2-phy
+ - qcom,sm8750-csi2-phy
- qcom,x1e80100-csi2-phy
- items:
- const: qcom,glymur-csi2-phy
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 02/23] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add Eliza CSI2 PHY
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
Add "qcom,eliza-csi2-phy" falling back to "qcom,x1e80100-csi2-phy", as
Eliza integrates the same CSI2 PHY IP.
Eliza has no MMCX and MXC rails: CX feeds the existing "mmcx" input and
MX the "mx" input, so only the power-domain descriptions need updating.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
index 8ff3df1d0d2787b2af0499c1e4106b86f56ff82c..884984f6f6b9e595df9bb3b0027c0bcf285b8058 100644
--- a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
@@ -22,7 +22,9 @@ properties:
- qcom,sm8750-csi2-phy
- qcom,x1e80100-csi2-phy
- items:
- - const: qcom,glymur-csi2-phy
+ - enum:
+ - qcom,eliza-csi2-phy
+ - qcom,glymur-csi2-phy
- const: qcom,x1e80100-csi2-phy
reg:
@@ -48,8 +50,8 @@ properties:
power-domains:
items:
- description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
- - description: MMCX voltage rail
- - description: MXC or MXA voltage rail
+ - description: MMCX or CX voltage rail
+ - description: MXC, MXA or MX voltage rail
power-domain-names:
items:
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 02/23] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add Eliza CSI2 PHY
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
Add "qcom,eliza-csi2-phy" falling back to "qcom,x1e80100-csi2-phy", as
Eliza integrates the same CSI2 PHY IP.
Eliza has no MMCX and MXC rails: CX feeds the existing "mmcx" input and
MX the "mx" input, so only the power-domain descriptions need updating.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
index 8ff3df1d0d2787b2af0499c1e4106b86f56ff82c..884984f6f6b9e595df9bb3b0027c0bcf285b8058 100644
--- a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
@@ -22,7 +22,9 @@ properties:
- qcom,sm8750-csi2-phy
- qcom,x1e80100-csi2-phy
- items:
- - const: qcom,glymur-csi2-phy
+ - enum:
+ - qcom,eliza-csi2-phy
+ - qcom,glymur-csi2-phy
- const: qcom,x1e80100-csi2-phy
reg:
@@ -48,8 +50,8 @@ properties:
power-domains:
items:
- description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
- - description: MMCX voltage rail
- - description: MXC or MXA voltage rail
+ - description: MMCX or CX voltage rail
+ - description: MXC, MXA or MX voltage rail
power-domain-names:
items:
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 03/23] dt-bindings: media: qcom,sm8750-camss: Add SM8750 CAMSS
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add bindings for Camera Subsystem (CAMSS) on the Qualcomm SM8750 platform.
The SM8750 platform provides:
- 6 x CSIPHY (CSI Physical Layer)
- 3 x TPG (Test Pattern Generator)
- 3 x CSID (CSI Decoder)
- 2 x CSID Lite
- 3 x VFE (Video Front End), 5 RDI per VFE
- 2 x VFE Lite, 4 RDI per VFE Lite
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
.../bindings/media/qcom,sm8750-camss.yaml | 297 +++++++++++++++++++++
1 file changed, 297 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..e7ab61d71ffbdf653f8a3b92b26035a2b29093df
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
@@ -0,0 +1,297 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,sm8750-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8750 Camera Subsystem (CAMSS)
+
+maintainers:
+ - Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
+
+description:
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,sm8750-camss
+
+ reg:
+ maxItems: 14
+
+ reg-names:
+ items:
+ - const: top
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: tpg0
+ - const: tpg1
+ - const: tpg2
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+ - const: vfe_lite1
+
+ clocks:
+ maxItems: 21
+
+ clock-names:
+ items:
+ - const: camnoc_rt_axi
+ - const: cpas_ahb
+ - const: cpas_fast_ahb
+ - const: cpas_vfe0
+ - const: cpas_vfe1
+ - const: cpas_vfe2
+ - const: cpas_vfe_lite
+ - const: csid
+ - const: csiphy_rx
+ - const: gcc_axi_hf
+ - const: vfe0
+ - const: vfe0_fast_ahb
+ - const: vfe1
+ - const: vfe1_fast_ahb
+ - const: vfe2
+ - const: vfe2_fast_ahb
+ - const: vfe_lite
+ - const: vfe_lite_ahb
+ - const: vfe_lite_cphy_rx
+ - const: vfe_lite_csid
+ - const: qdss_debug_xo
+
+ interrupts:
+ maxItems: 10
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+ - const: vfe_lite1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: ahb
+ - const: hf_mnoc
+
+ iommus:
+ items:
+ - description: S1 HLOS IFE and IFE_LITE non-protected stream
+
+ power-domains:
+ items:
+ - description: IFE0 GDSC - Global Distributed Switch Controller for IFE0.
+ - description: IFE1 GDSC - Global Distributed Switch Controller for IFE1.
+ - description: IFE2 GDSC - Global Distributed Switch Controller for IFE2.
+ - description: Titan GDSC - Global Distributed Switch Controller for the entire camss.
+
+ power-domain-names:
+ items:
+ - const: ife0
+ - const: ife1
+ - const: ife2
+ - const: top
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ patternProperties:
+ "^port@[0-5]$":
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input ports for receiving CSI data on CSIPHY 0-5.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ bus-type:
+ enum:
+ - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
+ - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
+
+ required:
+ - data-lanes
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - power-domains
+ - power-domain-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sm8750-gcc.h>
+ #include <dt-bindings/clock/qcom,sm8750-camcc.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ isp@ac04000 {
+ compatible = "qcom,sm8750-camss";
+
+ reg = <0x0 0x0ac04000 0x0 0x1000>,
+ <0x0 0x0ad27000 0x0 0x2b00>,
+ <0x0 0x0ad2a000 0x0 0x2b00>,
+ <0x0 0x0ad2d000 0x0 0x2b00>,
+ <0x0 0x0ad6d000 0x0 0xa00>,
+ <0x0 0x0ad72000 0x0 0xa00>,
+ <0x0 0x0ad8b000 0x0 0x400>,
+ <0x0 0x0ad8c000 0x0 0x400>,
+ <0x0 0x0ad8d000 0x0 0x400>,
+ <0x0 0x0ac86000 0x0 0x10000>,
+ <0x0 0x0ac96000 0x0 0x10000>,
+ <0x0 0x0aca6000 0x0 0x10000>,
+ <0x0 0x0ad6e000 0x0 0x3000>,
+ <0x0 0x0ad73000 0x0 0x3000>;
+ reg-names = "top",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "tpg0",
+ "tpg1",
+ "tpg2",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
+ <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>;
+ clock-names = "camnoc_rt_axi",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe2",
+ "cpas_vfe_lite",
+ "csid",
+ "csiphy_rx",
+ "gcc_axi_hf",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "qdss_debug_xo";
+
+ interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc";
+
+ iommus = <&apps_smmu 0x1c00 0x00>;
+
+ power-domains = <&camcc CAM_CC_TFE_0_GDSC>,
+ <&camcc CAM_CC_TFE_1_GDSC>,
+ <&camcc CAM_CC_TFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "ife2",
+ "top";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ camss_csiphy0_ep: endpoint {
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&csiphy0_out>;
+ };
+ };
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 03/23] dt-bindings: media: qcom,sm8750-camss: Add SM8750 CAMSS
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add bindings for Camera Subsystem (CAMSS) on the Qualcomm SM8750 platform.
The SM8750 platform provides:
- 6 x CSIPHY (CSI Physical Layer)
- 3 x TPG (Test Pattern Generator)
- 3 x CSID (CSI Decoder)
- 2 x CSID Lite
- 3 x VFE (Video Front End), 5 RDI per VFE
- 2 x VFE Lite, 4 RDI per VFE Lite
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
.../bindings/media/qcom,sm8750-camss.yaml | 297 +++++++++++++++++++++
1 file changed, 297 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..e7ab61d71ffbdf653f8a3b92b26035a2b29093df
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
@@ -0,0 +1,297 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,sm8750-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8750 Camera Subsystem (CAMSS)
+
+maintainers:
+ - Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
+
+description:
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,sm8750-camss
+
+ reg:
+ maxItems: 14
+
+ reg-names:
+ items:
+ - const: top
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: tpg0
+ - const: tpg1
+ - const: tpg2
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+ - const: vfe_lite1
+
+ clocks:
+ maxItems: 21
+
+ clock-names:
+ items:
+ - const: camnoc_rt_axi
+ - const: cpas_ahb
+ - const: cpas_fast_ahb
+ - const: cpas_vfe0
+ - const: cpas_vfe1
+ - const: cpas_vfe2
+ - const: cpas_vfe_lite
+ - const: csid
+ - const: csiphy_rx
+ - const: gcc_axi_hf
+ - const: vfe0
+ - const: vfe0_fast_ahb
+ - const: vfe1
+ - const: vfe1_fast_ahb
+ - const: vfe2
+ - const: vfe2_fast_ahb
+ - const: vfe_lite
+ - const: vfe_lite_ahb
+ - const: vfe_lite_cphy_rx
+ - const: vfe_lite_csid
+ - const: qdss_debug_xo
+
+ interrupts:
+ maxItems: 10
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+ - const: vfe_lite1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: ahb
+ - const: hf_mnoc
+
+ iommus:
+ items:
+ - description: S1 HLOS IFE and IFE_LITE non-protected stream
+
+ power-domains:
+ items:
+ - description: IFE0 GDSC - Global Distributed Switch Controller for IFE0.
+ - description: IFE1 GDSC - Global Distributed Switch Controller for IFE1.
+ - description: IFE2 GDSC - Global Distributed Switch Controller for IFE2.
+ - description: Titan GDSC - Global Distributed Switch Controller for the entire camss.
+
+ power-domain-names:
+ items:
+ - const: ife0
+ - const: ife1
+ - const: ife2
+ - const: top
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ patternProperties:
+ "^port@[0-5]$":
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input ports for receiving CSI data on CSIPHY 0-5.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ bus-type:
+ enum:
+ - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
+ - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
+
+ required:
+ - data-lanes
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - power-domains
+ - power-domain-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sm8750-gcc.h>
+ #include <dt-bindings/clock/qcom,sm8750-camcc.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ isp@ac04000 {
+ compatible = "qcom,sm8750-camss";
+
+ reg = <0x0 0x0ac04000 0x0 0x1000>,
+ <0x0 0x0ad27000 0x0 0x2b00>,
+ <0x0 0x0ad2a000 0x0 0x2b00>,
+ <0x0 0x0ad2d000 0x0 0x2b00>,
+ <0x0 0x0ad6d000 0x0 0xa00>,
+ <0x0 0x0ad72000 0x0 0xa00>,
+ <0x0 0x0ad8b000 0x0 0x400>,
+ <0x0 0x0ad8c000 0x0 0x400>,
+ <0x0 0x0ad8d000 0x0 0x400>,
+ <0x0 0x0ac86000 0x0 0x10000>,
+ <0x0 0x0ac96000 0x0 0x10000>,
+ <0x0 0x0aca6000 0x0 0x10000>,
+ <0x0 0x0ad6e000 0x0 0x3000>,
+ <0x0 0x0ad73000 0x0 0x3000>;
+ reg-names = "top",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "tpg0",
+ "tpg1",
+ "tpg2",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
+ <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>;
+ clock-names = "camnoc_rt_axi",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe2",
+ "cpas_vfe_lite",
+ "csid",
+ "csiphy_rx",
+ "gcc_axi_hf",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "qdss_debug_xo";
+
+ interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc";
+
+ iommus = <&apps_smmu 0x1c00 0x00>;
+
+ power-domains = <&camcc CAM_CC_TFE_0_GDSC>,
+ <&camcc CAM_CC_TFE_1_GDSC>,
+ <&camcc CAM_CC_TFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "ife2",
+ "top";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ camss_csiphy0_ep: endpoint {
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&csiphy0_out>;
+ };
+ };
+ };
+ };
+ };
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 04/23] dt-bindings: media: qcom,eliza-camss: Add Eliza CAMSS
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
Add bindings for Camera Subsystem (CAMSS) on the Qualcomm Eliza platform.
The Eliza platform provides:
- 3 x CSID (CSI Decoder, version 970)
- 1 x CSID Lite
- 3 x VFE (Video Front End, version 970), 4 RDI per VFE
- 1 x VFE Lite, 4 RDI per VFE Lite
- 2 x TPG (Test Pattern Generator, version 2.3.0)
The CSIPHYs are standalone PHY devices connected to CAMSS through the OF
graph, so they are not described here.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
.../bindings/media/qcom,eliza-camss.yaml | 282 +++++++++++++++++++++
1 file changed, 282 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,eliza-camss.yaml b/Documentation/devicetree/bindings/media/qcom,eliza-camss.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..8775ec6a2f69bad38bbc3e91c6fe285ede98c219
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,eliza-camss.yaml
@@ -0,0 +1,282 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,eliza-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Eliza Camera Subsystem (CAMSS)
+
+maintainers:
+ - Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
+
+description:
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,eliza-camss
+
+ reg:
+ maxItems: 11
+
+ reg-names:
+ items:
+ - const: top
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: tpg0
+ - const: tpg1
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+
+ clocks:
+ maxItems: 21
+
+ clock-names:
+ items:
+ - const: camnoc_rt_axi
+ - const: cpas_ahb
+ - const: cpas_fast_ahb
+ - const: cpas_vfe0
+ - const: cpas_vfe1
+ - const: cpas_vfe2
+ - const: cpas_vfe_lite
+ - const: csid
+ - const: csiphy_rx
+ - const: gcc_axi_hf
+ - const: vfe0
+ - const: vfe0_fast_ahb
+ - const: vfe1
+ - const: vfe1_fast_ahb
+ - const: vfe2
+ - const: vfe2_fast_ahb
+ - const: vfe_lite
+ - const: vfe_lite_ahb
+ - const: vfe_lite_cphy_rx
+ - const: vfe_lite_csid
+ - const: qdss_debug_xo
+
+ interrupts:
+ maxItems: 8
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: ahb
+ - const: hf_mnoc
+
+ iommus:
+ items:
+ - description: S1 HLOS IFE and IFE_LITE non-protected stream
+
+ power-domains:
+ items:
+ - description: IFE0 GDSC - Global Distributed Switch Controller for IFE0.
+ - description: IFE1 GDSC - Global Distributed Switch Controller for IFE1.
+ - description: IFE2 GDSC - Global Distributed Switch Controller for IFE2.
+ - description: Titan GDSC - Global Distributed Switch Controller for the entire camss.
+
+ power-domain-names:
+ items:
+ - const: ife0
+ - const: ife1
+ - const: ife2
+ - const: top
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ patternProperties:
+ "^port@[0-3]$":
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input ports for receiving CSI data on CSIPHY 0-3.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ bus-type:
+ enum:
+ - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
+ - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
+
+ required:
+ - data-lanes
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - power-domains
+ - power-domain-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,eliza-gcc.h>
+ #include <dt-bindings/clock/qcom,eliza-camcc.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interconnect/qcom,eliza-rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ isp@ac04000 {
+ compatible = "qcom,eliza-camss";
+
+ reg = <0x0 0x0ac04000 0x0 0x1000>,
+ <0x0 0x0ad27000 0x0 0x2b00>,
+ <0x0 0x0ad2a000 0x0 0x2b00>,
+ <0x0 0x0ad2d000 0x0 0x2b00>,
+ <0x0 0x0ad6d000 0x0 0xa00>,
+ <0x0 0x0ad8b000 0x0 0x400>,
+ <0x0 0x0ad8c000 0x0 0x400>,
+ <0x0 0x0ac86000 0x0 0x10000>,
+ <0x0 0x0ac96000 0x0 0x10000>,
+ <0x0 0x0aca6000 0x0 0x10000>,
+ <0x0 0x0ad6e000 0x0 0x3000>;
+ reg-names = "top",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "tpg0",
+ "tpg1",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0";
+
+ clocks = <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
+ <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>;
+ clock-names = "camnoc_rt_axi",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe2",
+ "cpas_vfe_lite",
+ "csid",
+ "csiphy_rx",
+ "gcc_axi_hf",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "qdss_debug_xo";
+
+ interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc";
+
+ iommus = <&apps_smmu 0x1c00 0x00>;
+
+ power-domains = <&camcc CAM_CC_TFE_0_GDSC>,
+ <&camcc CAM_CC_TFE_1_GDSC>,
+ <&camcc CAM_CC_TFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "ife2",
+ "top";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ camss_csiphy0_ep: endpoint {
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&csiphy0_out>;
+ };
+ };
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 04/23] dt-bindings: media: qcom,eliza-camss: Add Eliza CAMSS
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
Add bindings for Camera Subsystem (CAMSS) on the Qualcomm Eliza platform.
The Eliza platform provides:
- 3 x CSID (CSI Decoder, version 970)
- 1 x CSID Lite
- 3 x VFE (Video Front End, version 970), 4 RDI per VFE
- 1 x VFE Lite, 4 RDI per VFE Lite
- 2 x TPG (Test Pattern Generator, version 2.3.0)
The CSIPHYs are standalone PHY devices connected to CAMSS through the OF
graph, so they are not described here.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
.../bindings/media/qcom,eliza-camss.yaml | 282 +++++++++++++++++++++
1 file changed, 282 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,eliza-camss.yaml b/Documentation/devicetree/bindings/media/qcom,eliza-camss.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..8775ec6a2f69bad38bbc3e91c6fe285ede98c219
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,eliza-camss.yaml
@@ -0,0 +1,282 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,eliza-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Eliza Camera Subsystem (CAMSS)
+
+maintainers:
+ - Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
+
+description:
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,eliza-camss
+
+ reg:
+ maxItems: 11
+
+ reg-names:
+ items:
+ - const: top
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: tpg0
+ - const: tpg1
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+
+ clocks:
+ maxItems: 21
+
+ clock-names:
+ items:
+ - const: camnoc_rt_axi
+ - const: cpas_ahb
+ - const: cpas_fast_ahb
+ - const: cpas_vfe0
+ - const: cpas_vfe1
+ - const: cpas_vfe2
+ - const: cpas_vfe_lite
+ - const: csid
+ - const: csiphy_rx
+ - const: gcc_axi_hf
+ - const: vfe0
+ - const: vfe0_fast_ahb
+ - const: vfe1
+ - const: vfe1_fast_ahb
+ - const: vfe2
+ - const: vfe2_fast_ahb
+ - const: vfe_lite
+ - const: vfe_lite_ahb
+ - const: vfe_lite_cphy_rx
+ - const: vfe_lite_csid
+ - const: qdss_debug_xo
+
+ interrupts:
+ maxItems: 8
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: ahb
+ - const: hf_mnoc
+
+ iommus:
+ items:
+ - description: S1 HLOS IFE and IFE_LITE non-protected stream
+
+ power-domains:
+ items:
+ - description: IFE0 GDSC - Global Distributed Switch Controller for IFE0.
+ - description: IFE1 GDSC - Global Distributed Switch Controller for IFE1.
+ - description: IFE2 GDSC - Global Distributed Switch Controller for IFE2.
+ - description: Titan GDSC - Global Distributed Switch Controller for the entire camss.
+
+ power-domain-names:
+ items:
+ - const: ife0
+ - const: ife1
+ - const: ife2
+ - const: top
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ patternProperties:
+ "^port@[0-3]$":
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input ports for receiving CSI data on CSIPHY 0-3.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ bus-type:
+ enum:
+ - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
+ - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
+
+ required:
+ - data-lanes
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - power-domains
+ - power-domain-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,eliza-gcc.h>
+ #include <dt-bindings/clock/qcom,eliza-camcc.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interconnect/qcom,eliza-rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ isp@ac04000 {
+ compatible = "qcom,eliza-camss";
+
+ reg = <0x0 0x0ac04000 0x0 0x1000>,
+ <0x0 0x0ad27000 0x0 0x2b00>,
+ <0x0 0x0ad2a000 0x0 0x2b00>,
+ <0x0 0x0ad2d000 0x0 0x2b00>,
+ <0x0 0x0ad6d000 0x0 0xa00>,
+ <0x0 0x0ad8b000 0x0 0x400>,
+ <0x0 0x0ad8c000 0x0 0x400>,
+ <0x0 0x0ac86000 0x0 0x10000>,
+ <0x0 0x0ac96000 0x0 0x10000>,
+ <0x0 0x0aca6000 0x0 0x10000>,
+ <0x0 0x0ad6e000 0x0 0x3000>;
+ reg-names = "top",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "tpg0",
+ "tpg1",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0";
+
+ clocks = <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
+ <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>;
+ clock-names = "camnoc_rt_axi",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe2",
+ "cpas_vfe_lite",
+ "csid",
+ "csiphy_rx",
+ "gcc_axi_hf",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "qdss_debug_xo";
+
+ interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc";
+
+ iommus = <&apps_smmu 0x1c00 0x00>;
+
+ power-domains = <&camcc CAM_CC_TFE_0_GDSC>,
+ <&camcc CAM_CC_TFE_1_GDSC>,
+ <&camcc CAM_CC_TFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "ife2",
+ "top";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ camss_csiphy0_ep: endpoint {
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&csiphy0_out>;
+ };
+ };
+ };
+ };
+ };
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 05/23] dt-bindings: i2c: qcom-cci: Document Eliza compatible
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
Add Eliza compatible consistent with CAMSS CCI interfaces, falling back
to "qcom,msm8996-cci".
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
index 1e8def25ec0ec1ef6b34859709d10a2a36fe36f5..f16298d94177f906790c18831bfbcc5557a5accf 100644
--- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
@@ -26,6 +26,7 @@ properties:
- items:
- enum:
+ - qcom,eliza-cci
- qcom,glymur-cci
- qcom,kaanapali-cci
- qcom,milos-cci
@@ -136,6 +137,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,eliza-cci
- qcom,glymur-cci
- qcom,kaanapali-cci
- qcom,qcm2290-cci
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 05/23] dt-bindings: i2c: qcom-cci: Document Eliza compatible
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
Add Eliza compatible consistent with CAMSS CCI interfaces, falling back
to "qcom,msm8996-cci".
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
index 1e8def25ec0ec1ef6b34859709d10a2a36fe36f5..f16298d94177f906790c18831bfbcc5557a5accf 100644
--- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
@@ -26,6 +26,7 @@ properties:
- items:
- enum:
+ - qcom,eliza-cci
- qcom,glymur-cci
- qcom,kaanapali-cci
- qcom,milos-cci
@@ -136,6 +137,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,eliza-cci
- qcom,glymur-cci
- qcom,kaanapali-cci
- qcom,qcm2290-cci
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 06/23] phy: qcom-mipi-csi2: Add SM8750 support
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add the SM8750 CSI2 DPHY compatible to the match table, using the 3nm
DPHY configuration.
The SM8750 CSIPHY nodes only carry "qcom,sm8750-csi2-phy" with no
fallback compatible, so without this entry no driver matches them and
the PHYs stay unbound.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c
index 165e3d026872db85e54a99c5dd25ca68a1a4e450..a672bf318487b16aacd1ecf165554cde3f38e292 100644
--- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c
+++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c
@@ -444,6 +444,7 @@ static int phy_qcom_mipi_csi2_probe(struct platform_device *pdev)
static const struct of_device_id phy_qcom_mipi_csi2_of_match_table[] = {
{ .compatible = "qcom,kaanapali-csi2-phy", .data = &mipi_csi2_dphy_3nm_kaanapali },
+ { .compatible = "qcom,sm8750-csi2-phy", .data = &mipi_csi2_dphy_3nm_kaanapali },
{ .compatible = "qcom,x1e80100-csi2-phy", .data = &mipi_csi2_dphy_4nm_x1e },
{ }
};
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 06/23] phy: qcom-mipi-csi2: Add SM8750 support
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add the SM8750 CSI2 DPHY compatible to the match table, using the 3nm
DPHY configuration.
The SM8750 CSIPHY nodes only carry "qcom,sm8750-csi2-phy" with no
fallback compatible, so without this entry no driver matches them and
the PHYs stay unbound.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c
index 165e3d026872db85e54a99c5dd25ca68a1a4e450..a672bf318487b16aacd1ecf165554cde3f38e292 100644
--- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c
+++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c
@@ -444,6 +444,7 @@ static int phy_qcom_mipi_csi2_probe(struct platform_device *pdev)
static const struct of_device_id phy_qcom_mipi_csi2_of_match_table[] = {
{ .compatible = "qcom,kaanapali-csi2-phy", .data = &mipi_csi2_dphy_3nm_kaanapali },
+ { .compatible = "qcom,sm8750-csi2-phy", .data = &mipi_csi2_dphy_3nm_kaanapali },
{ .compatible = "qcom,x1e80100-csi2-phy", .data = &mipi_csi2_dphy_4nm_x1e },
{ }
};
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 07/23] media: qcom: camss: Add SM8750 compatible
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add support for SM8750 in the camss driver. Add high level resource
information along with the bus bandwidth votes. Module level detailed
resource information will be enumerated in the following patches of the
series.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/camss.c | 23 +++++++++++++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
2 files changed, 24 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 73b3850bbc08e857390330032d27bea38b8a10d3..3f9dd3a2ec088fa87a9ea90d25c906d14b9a1896 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -4308,6 +4308,20 @@ static const struct resources_icc icc_res_sa8775p[] = {
},
};
+static const struct resources_icc icc_res_sm8750[] = {
+ {
+ .name = "ahb",
+ .icc_bw_tbl.avg = 150000,
+ .icc_bw_tbl.peak = 300000,
+ },
+ /* Based on 4096 x 3072 30 FPS 2496 Mbps mode */
+ {
+ .name = "hf_mnoc",
+ .icc_bw_tbl.avg = 471860,
+ .icc_bw_tbl.peak = 925857,
+ },
+};
+
static const struct camss_subdev_resources csiphy_res_x1e80100[] = {
/* CSIPHY0 */
{
@@ -6026,6 +6040,14 @@ static const struct camss_resources sm8650_resources = {
.vfe_num = ARRAY_SIZE(vfe_res_sm8650),
};
+static const struct camss_resources sm8750_resources = {
+ .version = CAMSS_8750,
+ .pd_name = "top",
+ .icc_res = icc_res_sm8750,
+ .icc_path_num = ARRAY_SIZE(icc_res_sm8750),
+ .csiphy_num = 6,
+};
+
static const struct camss_resources x1e80100_resources = {
.version = CAMSS_X1E80100,
.pd_name = "top",
@@ -6061,6 +6083,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
{ .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
{ .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
+ { .compatible = "qcom,sm8750-camss", .data = &sm8750_resources },
{ .compatible = "qcom,x1e80100-camss", .data = &x1e80100_resources },
{ .compatible = "qcom,glymur-camss", .data = &x1e80100_resources },
{ }
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index 97fec24e680461a477add23bf5fb0b486903ba5b..3da970d251e728d339d13fdaef23ea5dfa46dd3b 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -95,6 +95,7 @@ enum camss_version {
CAMSS_845,
CAMSS_8550,
CAMSS_8650,
+ CAMSS_8750,
CAMSS_8775P,
CAMSS_KAANAPALI,
CAMSS_X1E80100,
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 07/23] media: qcom: camss: Add SM8750 compatible
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add support for SM8750 in the camss driver. Add high level resource
information along with the bus bandwidth votes. Module level detailed
resource information will be enumerated in the following patches of the
series.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/camss.c | 23 +++++++++++++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
2 files changed, 24 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 73b3850bbc08e857390330032d27bea38b8a10d3..3f9dd3a2ec088fa87a9ea90d25c906d14b9a1896 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -4308,6 +4308,20 @@ static const struct resources_icc icc_res_sa8775p[] = {
},
};
+static const struct resources_icc icc_res_sm8750[] = {
+ {
+ .name = "ahb",
+ .icc_bw_tbl.avg = 150000,
+ .icc_bw_tbl.peak = 300000,
+ },
+ /* Based on 4096 x 3072 30 FPS 2496 Mbps mode */
+ {
+ .name = "hf_mnoc",
+ .icc_bw_tbl.avg = 471860,
+ .icc_bw_tbl.peak = 925857,
+ },
+};
+
static const struct camss_subdev_resources csiphy_res_x1e80100[] = {
/* CSIPHY0 */
{
@@ -6026,6 +6040,14 @@ static const struct camss_resources sm8650_resources = {
.vfe_num = ARRAY_SIZE(vfe_res_sm8650),
};
+static const struct camss_resources sm8750_resources = {
+ .version = CAMSS_8750,
+ .pd_name = "top",
+ .icc_res = icc_res_sm8750,
+ .icc_path_num = ARRAY_SIZE(icc_res_sm8750),
+ .csiphy_num = 6,
+};
+
static const struct camss_resources x1e80100_resources = {
.version = CAMSS_X1E80100,
.pd_name = "top",
@@ -6061,6 +6083,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
{ .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
{ .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
+ { .compatible = "qcom,sm8750-camss", .data = &sm8750_resources },
{ .compatible = "qcom,x1e80100-camss", .data = &x1e80100_resources },
{ .compatible = "qcom,glymur-camss", .data = &x1e80100_resources },
{ }
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index 97fec24e680461a477add23bf5fb0b486903ba5b..3da970d251e728d339d13fdaef23ea5dfa46dd3b 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -95,6 +95,7 @@ enum camss_version {
CAMSS_845,
CAMSS_8550,
CAMSS_8650,
+ CAMSS_8750,
CAMSS_8775P,
CAMSS_KAANAPALI,
CAMSS_X1E80100,
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 08/23] media: qcom: camss: Add PM clock definitions for SM8750
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add cpas_fast_ahb, cpas_ahb and gcc_axi_hf to the PM clock list for
SM8750. The CAMSS core enables them through the shared PM clock helper
when the device is probed.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/camss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 3f9dd3a2ec088fa87a9ea90d25c906d14b9a1896..196eebc2d7d118040319bcf967b91c4ca98a4833 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -6043,6 +6043,7 @@ static const struct camss_resources sm8650_resources = {
static const struct camss_resources sm8750_resources = {
.version = CAMSS_8750,
.pd_name = "top",
+ .pm_clks = { "cpas_fast_ahb", "cpas_ahb", "gcc_axi_hf" },
.icc_res = icc_res_sm8750,
.icc_path_num = ARRAY_SIZE(icc_res_sm8750),
.csiphy_num = 6,
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 08/23] media: qcom: camss: Add PM clock definitions for SM8750
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add cpas_fast_ahb, cpas_ahb and gcc_axi_hf to the PM clock list for
SM8750. The CAMSS core enables them through the shared PM clock helper
when the device is probed.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/camss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 3f9dd3a2ec088fa87a9ea90d25c906d14b9a1896..196eebc2d7d118040319bcf967b91c4ca98a4833 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -6043,6 +6043,7 @@ static const struct camss_resources sm8650_resources = {
static const struct camss_resources sm8750_resources = {
.version = CAMSS_8750,
.pd_name = "top",
+ .pm_clks = { "cpas_fast_ahb", "cpas_ahb", "gcc_axi_hf" },
.icc_res = icc_res_sm8750,
.icc_path_num = ARRAY_SIZE(icc_res_sm8750),
.csiphy_num = 6,
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 09/23] media: qcom: camss: csid: Scale the clocks with the CSI-2 link rate
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
From: Loic Poulain <loic.poulain@oss.qualcomm.com>
Only the gen1 "csiN" clocks are scaled with the link rate of the sensor,
the CSID core and CSIPHY receive clocks of all the other SoCs are set to
the first rate of the resource table. A SoC can therefore only be
described for one sensor bandwidth: the lowest rate first breaks fast
sensors, the highest one burns power with the slow ones.
Compute the minimum rate from the link frequency for all generations.
The CSIPHY passes each D-PHY lane to the CSID over an 8 bit wide
interface clocked by the receive clock, so that clock has to run at the
per lane bit rate divided by 8, which is link_freq / 4. The core clock
must not be slower, hence the same minimum for it and the cap of the
receive clock at the core rate. The clocks are matched by suffix and
voted for with clk_set_rate_range(), as the CSIDs of the recent SoCs
share them.
Up to 1.8 Gbps/lane the selected rates are unchanged on every supported
SoC.
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/camss-csid.c | 208 ++++++++++++++++++++-----
1 file changed, 169 insertions(+), 39 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c
index 51f20907ffde6ad2a40b787fdee6d6525e7603a2..714cea6883a78664e76109d11094f7b6c2b0729e 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.c
+++ b/drivers/media/platform/qcom/camss/camss-csid.c
@@ -16,6 +16,7 @@
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
+#include <linux/string.h>
#include <media/media-entity.h>
#include <media/mipi-csi2.h>
#include <media/v4l2-device.h>
@@ -532,72 +533,197 @@ const struct csid_format_info *csid_get_fmt_entry(const struct csid_format_info
return &formats[0];
}
+/* Match the core clock of the CSID */
+static bool csid_match_core_clock_name(struct camss_clock *clock)
+{
+ /* "csid", "vfe0_csid", "vfe_lite_csid", ... */
+ if (strends(clock->name, "csid"))
+ return true;
+
+ /* Named after the CSI port on the SoCs with a gen1 CSID */
+ return !strcmp(clock->name, "csi0") || !strcmp(clock->name, "csi1") ||
+ !strcmp(clock->name, "csi2") || !strcmp(clock->name, "csi3");
+}
+
+/* Match the clock of the CSIPHY to CSID interface */
+static bool csid_match_phy_rx_clock_name(struct camss_clock *clock)
+{
+ /* "csiphy_rx", "csid_csiphy_rx", "vfe0_cphy_rx", ... */
+ return strends(clock->name, "phy_rx");
+}
+
+/* Match a clock whose rate depends on the CSI-2 link rate */
+static bool csid_match_scaled_clock_name(struct camss_clock *clock)
+{
+ return csid_match_core_clock_name(clock) ||
+ csid_match_phy_rx_clock_name(clock);
+}
+
/*
- * csid_set_clock_rates - Calculate and set clock rates on CSID module
- * @csiphy: CSID device
+ * csid_get_min_clock_rate - Get the rate the CSI-2 link requires
+ * @csid: CSID device
+ *
+ * The CSIPHY deserialises every D-PHY data lane into bytes and passes them to
+ * the CSID over an interface which is, as per the CSID HPG, 8 bits wide per
+ * lane and clocked by the CSIPHY receive clock. That clock has to run at the
+ * per lane bit rate divided by 8 at the very least. The link frequency is the
+ * DDR clock of the link, i.e. half the per lane bit rate, which makes the
+ * minimum rate link_freq / 4.
+ *
+ * Qualcomm recommends clocking the CSID core at least as fast as the CSIPHY
+ * receive clock feeding it, so the same minimum applies to the core clock.
+ *
+ * C-PHY maps 16 bits onto 7 symbols and needs a different ratio, but CAMSS
+ * does not support it so far.
+ *
+ * Return the minimum rate in Hz, clock margin included, or 0 if the link
+ * frequency of the sensor is not known
*/
-static int csid_set_clock_rates(struct csid_device *csid)
+static u64 csid_get_min_clock_rate(struct csid_device *csid)
{
- struct device *dev = csid->camss->dev;
const struct csid_format_info *fmt;
s64 link_freq;
- int i, j;
- int ret;
+ u64 min_rate;
fmt = csid_get_fmt_entry(csid->res->formats->formats, csid->res->formats->nformats,
- csid->fmt[MSM_CSIPHY_PAD_SINK].code);
+ csid->fmt[MSM_CSID_PAD_SINK].code);
link_freq = camss_get_link_freq(&csid->subdev.entity, fmt->bpp,
csid->phy.lane_cnt);
if (link_freq < 0)
- link_freq = 0;
+ return 0;
+
+ min_rate = link_freq / 4;
+ camss_add_clock_margin(&min_rate);
+
+ return min_rate;
+}
+
+/* Get the lowest level of a clock above min_rate, or -EINVAL if there is none */
+static int csid_find_clock_level(struct camss_clock *clock, u64 min_rate)
+{
+ int i;
+
+ /* Play safe with the highest level if the link rate is not known */
+ if (!min_rate)
+ return clock->nfreqs - 1;
+
+ for (i = 0; i < clock->nfreqs; i++)
+ if (clock->freq[i] > min_rate)
+ return i;
+
+ return -EINVAL;
+}
+
+/* Lower a level down to max_rate, but never below what min_rate needs */
+static int csid_cap_clock_level(struct camss_clock *clock, int level,
+ u64 min_rate, u64 max_rate)
+{
+ while (level > 0 && clock->freq[level] > max_rate &&
+ clock->freq[level - 1] > min_rate)
+ level--;
+
+ return level;
+}
+
+/*
+ * csid_set_clock_rates - Calculate and set clock rates on CSID module
+ * @csid: CSID device
+ */
+static int csid_set_clock_rates(struct csid_device *csid)
+{
+ struct device *dev = csid->camss->dev;
+ u64 min_rate = csid_get_min_clock_rate(csid);
+ u64 core_rate = 0;
+ int i, j;
+ int ret;
+
+ /*
+ * Settle the rate of the core clock first, as the receive clock must
+ * not outrun it and the clocks are not listed in a fixed order.
+ */
for (i = 0; i < csid->nclocks; i++) {
struct camss_clock *clock = &csid->clock[i];
- if (!strcmp(clock->name, "csi0") ||
- !strcmp(clock->name, "csi1") ||
- !strcmp(clock->name, "csi2") ||
- !strcmp(clock->name, "csi3")) {
- u64 min_rate = link_freq / 4;
- long rate;
+ if (!clock->nfreqs || !csid_match_core_clock_name(clock))
+ continue;
- camss_add_clock_margin(&min_rate);
+ j = csid_find_clock_level(clock, min_rate);
+ if (j < 0) {
+ dev_err(dev, "Link rate is too high for the %s clock\n",
+ clock->name);
+ return j;
+ }
- for (j = 0; j < clock->nfreqs; j++)
- if (min_rate < clock->freq[j])
- break;
+ core_rate = max_t(u64, core_rate, clock->freq[j]);
+ }
- if (j == clock->nfreqs) {
- dev_err(dev,
- "Pixel clock is too high for CSID\n");
- return -EINVAL;
- }
+ for (i = 0; i < csid->nclocks; i++) {
+ struct camss_clock *clock = &csid->clock[i];
- /* if sensor pixel clock is not available */
- /* set highest possible CSID clock rate */
- if (min_rate == 0)
- j = clock->nfreqs - 1;
+ if (!clock->nfreqs)
+ continue;
- rate = clk_round_rate(clock->clk, clock->freq[j]);
- if (rate < 0) {
- dev_err(dev, "clk round rate failed: %ld\n",
- rate);
- return -EINVAL;
- }
+ if (!csid_match_scaled_clock_name(clock)) {
+ /* The remaining clocks run at their lowest level */
- ret = clk_set_rate(clock->clk, rate);
- if (ret < 0) {
- dev_err(dev, "clk set rate failed: %d\n", ret);
- return ret;
- }
- } else if (clock->nfreqs) {
clk_set_rate(clock->clk, clock->freq[0]);
+ continue;
+ }
+
+ j = csid_find_clock_level(clock, min_rate);
+ if (j < 0) {
+ dev_err(dev, "Link rate is too high for the %s clock\n",
+ clock->name);
+ return j;
+ }
+
+ /*
+ * There is nothing to gain from running the receive clock
+ * faster than the core clock, as long as the link rate is
+ * still covered.
+ */
+ if (core_rate && csid_match_phy_rx_clock_name(clock))
+ j = csid_cap_clock_level(clock, j, min_rate, core_rate);
+
+ /*
+ * Vote for the rate as a minimum, as the clock may be shared
+ * with another CSID which needs it to run faster.
+ */
+ ret = clk_set_rate_range(clock->clk, clock->freq[j], ULONG_MAX);
+ if (ret < 0) {
+ dev_err(dev, "clk set rate range failed: %d\n", ret);
+ return ret;
}
}
return 0;
}
+/*
+ * Drop the minimum rates the CSID votes for and take its clocks back to their
+ * lowest level, or to the lowest level the other users of a shared clock need.
+ */
+static void csid_release_clock_rates(struct csid_device *csid)
+{
+ int i;
+
+ for (i = 0; i < csid->nclocks; i++) {
+ struct camss_clock *clock = &csid->clock[i];
+ long rate;
+
+ if (!clock->nfreqs || !csid_match_scaled_clock_name(clock))
+ continue;
+
+ clk_drop_range(clock->clk);
+
+ /* Round first, so that the rate respects the other votes */
+ rate = clk_round_rate(clock->clk, clock->freq[0]);
+ if (rate > 0)
+ clk_set_rate(clock->clk, rate);
+ }
+}
+
/*
* csid_hw_version - CSID hardware version query
* @csid: CSID device
@@ -707,6 +833,7 @@ static int csid_set_power(struct v4l2_subdev *sd, int on)
ret = csid_set_clock_rates(csid);
if (ret < 0) {
+ csid_release_clock_rates(csid);
regulator_bulk_disable(csid->num_supplies,
csid->supplies);
pm_runtime_put_sync(dev);
@@ -715,6 +842,7 @@ static int csid_set_power(struct v4l2_subdev *sd, int on)
ret = camss_enable_clocks(csid->nclocks, csid->clock, dev);
if (ret < 0) {
+ csid_release_clock_rates(csid);
regulator_bulk_disable(csid->num_supplies,
csid->supplies);
pm_runtime_put_sync(dev);
@@ -729,6 +857,7 @@ static int csid_set_power(struct v4l2_subdev *sd, int on)
if (ret < 0) {
disable_irq(csid->irq);
camss_disable_clocks(csid->nclocks, csid->clock);
+ csid_release_clock_rates(csid);
regulator_bulk_disable(csid->num_supplies,
csid->supplies);
pm_runtime_put_sync(dev);
@@ -739,6 +868,7 @@ static int csid_set_power(struct v4l2_subdev *sd, int on)
} else {
disable_irq(csid->irq);
camss_disable_clocks(csid->nclocks, csid->clock);
+ csid_release_clock_rates(csid);
regulator_bulk_disable(csid->num_supplies,
csid->supplies);
pm_runtime_put_sync(dev);
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 09/23] media: qcom: camss: csid: Scale the clocks with the CSI-2 link rate
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
From: Loic Poulain <loic.poulain@oss.qualcomm.com>
Only the gen1 "csiN" clocks are scaled with the link rate of the sensor,
the CSID core and CSIPHY receive clocks of all the other SoCs are set to
the first rate of the resource table. A SoC can therefore only be
described for one sensor bandwidth: the lowest rate first breaks fast
sensors, the highest one burns power with the slow ones.
Compute the minimum rate from the link frequency for all generations.
The CSIPHY passes each D-PHY lane to the CSID over an 8 bit wide
interface clocked by the receive clock, so that clock has to run at the
per lane bit rate divided by 8, which is link_freq / 4. The core clock
must not be slower, hence the same minimum for it and the cap of the
receive clock at the core rate. The clocks are matched by suffix and
voted for with clk_set_rate_range(), as the CSIDs of the recent SoCs
share them.
Up to 1.8 Gbps/lane the selected rates are unchanged on every supported
SoC.
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/camss-csid.c | 208 ++++++++++++++++++++-----
1 file changed, 169 insertions(+), 39 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c
index 51f20907ffde6ad2a40b787fdee6d6525e7603a2..714cea6883a78664e76109d11094f7b6c2b0729e 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.c
+++ b/drivers/media/platform/qcom/camss/camss-csid.c
@@ -16,6 +16,7 @@
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
+#include <linux/string.h>
#include <media/media-entity.h>
#include <media/mipi-csi2.h>
#include <media/v4l2-device.h>
@@ -532,72 +533,197 @@ const struct csid_format_info *csid_get_fmt_entry(const struct csid_format_info
return &formats[0];
}
+/* Match the core clock of the CSID */
+static bool csid_match_core_clock_name(struct camss_clock *clock)
+{
+ /* "csid", "vfe0_csid", "vfe_lite_csid", ... */
+ if (strends(clock->name, "csid"))
+ return true;
+
+ /* Named after the CSI port on the SoCs with a gen1 CSID */
+ return !strcmp(clock->name, "csi0") || !strcmp(clock->name, "csi1") ||
+ !strcmp(clock->name, "csi2") || !strcmp(clock->name, "csi3");
+}
+
+/* Match the clock of the CSIPHY to CSID interface */
+static bool csid_match_phy_rx_clock_name(struct camss_clock *clock)
+{
+ /* "csiphy_rx", "csid_csiphy_rx", "vfe0_cphy_rx", ... */
+ return strends(clock->name, "phy_rx");
+}
+
+/* Match a clock whose rate depends on the CSI-2 link rate */
+static bool csid_match_scaled_clock_name(struct camss_clock *clock)
+{
+ return csid_match_core_clock_name(clock) ||
+ csid_match_phy_rx_clock_name(clock);
+}
+
/*
- * csid_set_clock_rates - Calculate and set clock rates on CSID module
- * @csiphy: CSID device
+ * csid_get_min_clock_rate - Get the rate the CSI-2 link requires
+ * @csid: CSID device
+ *
+ * The CSIPHY deserialises every D-PHY data lane into bytes and passes them to
+ * the CSID over an interface which is, as per the CSID HPG, 8 bits wide per
+ * lane and clocked by the CSIPHY receive clock. That clock has to run at the
+ * per lane bit rate divided by 8 at the very least. The link frequency is the
+ * DDR clock of the link, i.e. half the per lane bit rate, which makes the
+ * minimum rate link_freq / 4.
+ *
+ * Qualcomm recommends clocking the CSID core at least as fast as the CSIPHY
+ * receive clock feeding it, so the same minimum applies to the core clock.
+ *
+ * C-PHY maps 16 bits onto 7 symbols and needs a different ratio, but CAMSS
+ * does not support it so far.
+ *
+ * Return the minimum rate in Hz, clock margin included, or 0 if the link
+ * frequency of the sensor is not known
*/
-static int csid_set_clock_rates(struct csid_device *csid)
+static u64 csid_get_min_clock_rate(struct csid_device *csid)
{
- struct device *dev = csid->camss->dev;
const struct csid_format_info *fmt;
s64 link_freq;
- int i, j;
- int ret;
+ u64 min_rate;
fmt = csid_get_fmt_entry(csid->res->formats->formats, csid->res->formats->nformats,
- csid->fmt[MSM_CSIPHY_PAD_SINK].code);
+ csid->fmt[MSM_CSID_PAD_SINK].code);
link_freq = camss_get_link_freq(&csid->subdev.entity, fmt->bpp,
csid->phy.lane_cnt);
if (link_freq < 0)
- link_freq = 0;
+ return 0;
+
+ min_rate = link_freq / 4;
+ camss_add_clock_margin(&min_rate);
+
+ return min_rate;
+}
+
+/* Get the lowest level of a clock above min_rate, or -EINVAL if there is none */
+static int csid_find_clock_level(struct camss_clock *clock, u64 min_rate)
+{
+ int i;
+
+ /* Play safe with the highest level if the link rate is not known */
+ if (!min_rate)
+ return clock->nfreqs - 1;
+
+ for (i = 0; i < clock->nfreqs; i++)
+ if (clock->freq[i] > min_rate)
+ return i;
+
+ return -EINVAL;
+}
+
+/* Lower a level down to max_rate, but never below what min_rate needs */
+static int csid_cap_clock_level(struct camss_clock *clock, int level,
+ u64 min_rate, u64 max_rate)
+{
+ while (level > 0 && clock->freq[level] > max_rate &&
+ clock->freq[level - 1] > min_rate)
+ level--;
+
+ return level;
+}
+
+/*
+ * csid_set_clock_rates - Calculate and set clock rates on CSID module
+ * @csid: CSID device
+ */
+static int csid_set_clock_rates(struct csid_device *csid)
+{
+ struct device *dev = csid->camss->dev;
+ u64 min_rate = csid_get_min_clock_rate(csid);
+ u64 core_rate = 0;
+ int i, j;
+ int ret;
+
+ /*
+ * Settle the rate of the core clock first, as the receive clock must
+ * not outrun it and the clocks are not listed in a fixed order.
+ */
for (i = 0; i < csid->nclocks; i++) {
struct camss_clock *clock = &csid->clock[i];
- if (!strcmp(clock->name, "csi0") ||
- !strcmp(clock->name, "csi1") ||
- !strcmp(clock->name, "csi2") ||
- !strcmp(clock->name, "csi3")) {
- u64 min_rate = link_freq / 4;
- long rate;
+ if (!clock->nfreqs || !csid_match_core_clock_name(clock))
+ continue;
- camss_add_clock_margin(&min_rate);
+ j = csid_find_clock_level(clock, min_rate);
+ if (j < 0) {
+ dev_err(dev, "Link rate is too high for the %s clock\n",
+ clock->name);
+ return j;
+ }
- for (j = 0; j < clock->nfreqs; j++)
- if (min_rate < clock->freq[j])
- break;
+ core_rate = max_t(u64, core_rate, clock->freq[j]);
+ }
- if (j == clock->nfreqs) {
- dev_err(dev,
- "Pixel clock is too high for CSID\n");
- return -EINVAL;
- }
+ for (i = 0; i < csid->nclocks; i++) {
+ struct camss_clock *clock = &csid->clock[i];
- /* if sensor pixel clock is not available */
- /* set highest possible CSID clock rate */
- if (min_rate == 0)
- j = clock->nfreqs - 1;
+ if (!clock->nfreqs)
+ continue;
- rate = clk_round_rate(clock->clk, clock->freq[j]);
- if (rate < 0) {
- dev_err(dev, "clk round rate failed: %ld\n",
- rate);
- return -EINVAL;
- }
+ if (!csid_match_scaled_clock_name(clock)) {
+ /* The remaining clocks run at their lowest level */
- ret = clk_set_rate(clock->clk, rate);
- if (ret < 0) {
- dev_err(dev, "clk set rate failed: %d\n", ret);
- return ret;
- }
- } else if (clock->nfreqs) {
clk_set_rate(clock->clk, clock->freq[0]);
+ continue;
+ }
+
+ j = csid_find_clock_level(clock, min_rate);
+ if (j < 0) {
+ dev_err(dev, "Link rate is too high for the %s clock\n",
+ clock->name);
+ return j;
+ }
+
+ /*
+ * There is nothing to gain from running the receive clock
+ * faster than the core clock, as long as the link rate is
+ * still covered.
+ */
+ if (core_rate && csid_match_phy_rx_clock_name(clock))
+ j = csid_cap_clock_level(clock, j, min_rate, core_rate);
+
+ /*
+ * Vote for the rate as a minimum, as the clock may be shared
+ * with another CSID which needs it to run faster.
+ */
+ ret = clk_set_rate_range(clock->clk, clock->freq[j], ULONG_MAX);
+ if (ret < 0) {
+ dev_err(dev, "clk set rate range failed: %d\n", ret);
+ return ret;
}
}
return 0;
}
+/*
+ * Drop the minimum rates the CSID votes for and take its clocks back to their
+ * lowest level, or to the lowest level the other users of a shared clock need.
+ */
+static void csid_release_clock_rates(struct csid_device *csid)
+{
+ int i;
+
+ for (i = 0; i < csid->nclocks; i++) {
+ struct camss_clock *clock = &csid->clock[i];
+ long rate;
+
+ if (!clock->nfreqs || !csid_match_scaled_clock_name(clock))
+ continue;
+
+ clk_drop_range(clock->clk);
+
+ /* Round first, so that the rate respects the other votes */
+ rate = clk_round_rate(clock->clk, clock->freq[0]);
+ if (rate > 0)
+ clk_set_rate(clock->clk, rate);
+ }
+}
+
/*
* csid_hw_version - CSID hardware version query
* @csid: CSID device
@@ -707,6 +833,7 @@ static int csid_set_power(struct v4l2_subdev *sd, int on)
ret = csid_set_clock_rates(csid);
if (ret < 0) {
+ csid_release_clock_rates(csid);
regulator_bulk_disable(csid->num_supplies,
csid->supplies);
pm_runtime_put_sync(dev);
@@ -715,6 +842,7 @@ static int csid_set_power(struct v4l2_subdev *sd, int on)
ret = camss_enable_clocks(csid->nclocks, csid->clock, dev);
if (ret < 0) {
+ csid_release_clock_rates(csid);
regulator_bulk_disable(csid->num_supplies,
csid->supplies);
pm_runtime_put_sync(dev);
@@ -729,6 +857,7 @@ static int csid_set_power(struct v4l2_subdev *sd, int on)
if (ret < 0) {
disable_irq(csid->irq);
camss_disable_clocks(csid->nclocks, csid->clock);
+ csid_release_clock_rates(csid);
regulator_bulk_disable(csid->num_supplies,
csid->supplies);
pm_runtime_put_sync(dev);
@@ -739,6 +868,7 @@ static int csid_set_power(struct v4l2_subdev *sd, int on)
} else {
disable_irq(csid->irq);
camss_disable_clocks(csid->nclocks, csid->clock);
+ csid_release_clock_rates(csid);
regulator_bulk_disable(csid->num_supplies,
csid->supplies);
pm_runtime_put_sync(dev);
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 10/23] media: qcom: camss: csid: Add support for CSID 980
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu, Atiya Kailany
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add resource information for CSID devices and the driver for CSID 980,
which handles CSID register configuration, module reset and IRQ handling
for BUF_DONE events.
In SM8750, the RUP and AUP updates of the Full CSIDs are split into two
registers with a SET register, while Lite CSIDs still use a single
register. The driver handles these differences.
Also define the SOF and EOF event bits for the CSI2 input and CAMIF, and
the RDIn IRQ mask register. These are definitions only; frame event IRQs
are not handled yet.
Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/Makefile | 1 +
drivers/media/platform/qcom/camss/camss-csid-980.c | 466 +++++++++++++++++++++
drivers/media/platform/qcom/camss/camss-csid.h | 1 +
drivers/media/platform/qcom/camss/camss.c | 72 ++++
4 files changed, 540 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
index 42a14e8fe1b7f28ba5ffcbe59769093b08db4d6b..1aef4267543dfa1c25dbbf351252862bf94a847d 100644
--- a/drivers/media/platform/qcom/camss/Makefile
+++ b/drivers/media/platform/qcom/camss/Makefile
@@ -8,6 +8,7 @@ qcom-camss-objs += \
camss-csid-4-7.o \
camss-csid-340.o \
camss-csid-680.o \
+ camss-csid-980.o \
camss-csid-1080.o \
camss-csid-gen2.o \
camss-csid-gen3.o \
diff --git a/drivers/media/platform/qcom/camss/camss-csid-980.c b/drivers/media/platform/qcom/camss/camss-csid-980.c
new file mode 100644
index 0000000000000000000000000000000000000000..713db25cd8c65ed7e991bffbb8b19d66c662e708
--- /dev/null
+++ b/drivers/media/platform/qcom/camss/camss-csid-980.c
@@ -0,0 +1,466 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * camss-csid-980.c
+ *
+ * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include "camss.h"
+#include "camss-csid.h"
+#include "camss-csid-gen3.h"
+
+/* Reset and Command Registers */
+#define CSID_RST_CFG 0xC
+#define RST_MODE BIT(0)
+#define RST_LOCATION BIT(4)
+
+/* Reset and Command Registers */
+#define CSID_RST_CMD 0x10
+#define SELECT_HW_RST BIT(0)
+#define SELECT_IRQ_RST BIT(2)
+#define CSID_IRQ_CMD 0x14
+#define IRQ_CMD_CLEAR BIT(0)
+
+/* Register Update Commands, RUP/AUP */
+#define CSID_RUP_CMD 0x18
+#define CSID_AUP_CMD 0x1C
+#define CSID_RUP_AUP_RDI(rdi) (BIT(8) << (rdi))
+#define CSID_RUP_AUP_CMD 0x20
+#define RUP_SET BIT(0)
+#define MUP BIT(4)
+
+#define CSID_LITE_RUP_AUP_CMD 0x18
+#define CSID_LITE_RUP_RDI(rdi) (BIT(4) << (rdi))
+#define CSID_LITE_AUP_RDI(rdi) (BIT(20) << (rdi))
+
+/* Top level interrupt registers */
+#define CSID_TOP_IRQ_STATUS (csid_is_lite(csid) ? 0x7C : 0x84)
+#define CSID_TOP_IRQ_MASK (csid_is_lite(csid) ? 0x80 : 0x88)
+#define CSID_TOP_IRQ_CLEAR (csid_is_lite(csid) ? 0x84 : 0x8C)
+#define CSID_TOP_IRQ_SET (csid_is_lite(csid) ? 0x88 : 0x90)
+#define INFO_RST_DONE BIT(0)
+#define CSI2_RX_IRQ_STATUS BIT(2)
+#define BUF_DONE_IRQ_STATUS BIT(csid_is_lite(csid) ? 13 : 3)
+
+/* Buffer done interrupt registers */
+#define CSID_BUF_DONE_IRQ_STATUS (csid_is_lite(csid) ? 0x8C : 0xA4)
+#define BUF_DONE_IRQ_STATUS_RDI_OFFSET (csid_is_lite(csid) ? 1 : 16)
+#define CSID_BUF_DONE_IRQ_MASK (csid_is_lite(csid) ? 0x90 : 0xA8)
+#define CSID_BUF_DONE_IRQ_CLEAR (csid_is_lite(csid) ? 0x94 : 0xAC)
+#define CSID_BUF_DONE_IRQ_SET (csid_is_lite(csid) ? 0x98 : 0xB0)
+
+/* CSI2 RX interrupt registers */
+#define CSID_CSI2_RX_IRQ_STATUS (csid_is_lite(csid) ? 0x9C : 0xB4)
+#define CSID_CSI2_RX_IRQ_MASK (csid_is_lite(csid) ? 0xA0 : 0xB8)
+#define CSID_CSI2_RX_IRQ_CLEAR (csid_is_lite(csid) ? 0xA4 : 0xBC)
+#define CSID_CSI2_RX_IRQ_SET (csid_is_lite(csid) ? 0xA8 : 0xC0)
+
+/* CSI2 RX Configuration */
+#define CSID_CSI2_RX_CFG0 (csid_is_lite(csid) ? 0x200 : 0x400)
+#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0
+#define CSI2_RX_CFG0_DL0_INPUT_SEL 4
+#define CSI2_RX_CFG0_PHY_NUM_SEL 20
+#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1
+#define CSID_CSI2_RX_CFG1 (csid_is_lite(csid) ? 0x204 : 0x404)
+#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0)
+#define CSI2_RX_CFG1_VC_MODE BIT(2)
+
+#define MSM_CSID_MAX_SRC_STREAMS_980 (csid_is_lite(csid) ? 4 : 5)
+
+#define CSID_RDI_CFG0(rdi) \
+ ({ \
+ __typeof__(rdi) _rdi = (rdi); \
+ csid_is_lite(csid) ? 0x500 + 0x100 * _rdi : \
+ 0xE00 + 0x200 * _rdi; \
+ })
+#define RDI_CFG0_RETIME_BS BIT(5)
+#define RDI_CFG0_TIMESTAMP_EN BIT(6)
+#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8)
+#define RDI_CFG0_DECODE_FORMAT 12
+#define RDI_CFG0_DT 16
+#define RDI_CFG0_VC 22
+#define RDI_CFG0_DT_ID 27
+#define RDI_CFG0_EN BIT(31)
+
+/* RDI Control and Configuration */
+#define CSID_RDI_CTRL(rdi) \
+ ({ \
+ __typeof__(rdi) _rdi = (rdi); \
+ csid_is_lite(csid) ? 0x504 + 0x100 * _rdi : \
+ 0xE04 + 0x200 * _rdi; \
+ })
+#define RDI_CTRL_START_CMD BIT(0)
+
+#define CSID_RDI_CFG1(rdi) \
+ ({ \
+ __typeof__(rdi) _rdi = (rdi); \
+ csid_is_lite(csid) ? 0x510 + 0x100 * _rdi : \
+ 0xE10 + 0x200 * _rdi; \
+ })
+#define RDI_CFG1_DROP_H_EN BIT(5)
+#define RDI_CFG1_DROP_V_EN BIT(6)
+#define RDI_CFG1_CROP_H_EN BIT(7)
+#define RDI_CFG1_CROP_V_EN BIT(8)
+#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15)
+
+/* RDI Pixel Store Configuration */
+#define CSID_RDI_PIX_STORE_CFG0(rdi) (0xE14 + 0x200 * (rdi))
+#define RDI_PIX_STORE_CFG0_EN BIT(0)
+#define RDI_PIX_STORE_CFG0_MIN_HBI 1
+
+/* RDI IRQ Status in wrapper */
+#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) \
+ ((csid_is_lite(csid) ? 0xEC : 0x114) + 0x10 * (rdi))
+#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) \
+ ((csid_is_lite(csid) ? 0xF4 : 0x11C) + 0x10 * (rdi))
+#define CSID_CSI2_RDIN_IRQ_MASK(rdi) \
+ ((csid_is_lite(csid) ? 0xF0 : 0x118) + 0x10 * (rdi))
+#define INFO_RUP_DONE BIT(23)
+#define INFO_INPUT_SOF BIT(12)
+#define INFO_INPUT_EOF BIT(9)
+#define INFO_CAMIF_SOF BIT(4)
+#define INFO_CAMIF_EOF BIT(3)
+
+static void __csid_full_aup_rup_trigger(struct csid_device *csid)
+{
+ /* trigger SET in combined register */
+ writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD);
+}
+
+static void __csid_addr_update(struct csid_device *csid, int port_id)
+{
+ if (csid_is_lite(csid)) {
+ /* CSID Lites in v980 follow the legacy way of a combined RUP
+ * and AUP commands without an explicit SET register.
+ */
+ csid->reg_update |= CSID_LITE_AUP_RDI(port_id);
+ writel(csid->reg_update, csid->base + CSID_LITE_RUP_AUP_CMD);
+ } else {
+ csid->addr_update |= CSID_RUP_AUP_RDI(port_id);
+ writel(csid->addr_update, csid->base + CSID_AUP_CMD);
+
+ /* CSID Fulls in v980 split AUP and RUP commands, which requires
+ * additional SET operation to make registers modification take
+ * effect.
+ */
+ __csid_full_aup_rup_trigger(csid);
+ }
+}
+
+static void __csid_reg_update(struct csid_device *csid, int port_id)
+{
+ if (csid_is_lite(csid)) {
+ /* CSID Lites in v980 follow the legacy way of a combined RUP
+ * and AUP commands without an explicit SET register.
+ */
+ csid->reg_update |= CSID_LITE_RUP_RDI(port_id);
+ writel(csid->reg_update, csid->base + CSID_LITE_RUP_AUP_CMD);
+ } else {
+ csid->reg_update |= CSID_RUP_AUP_RDI(port_id);
+ writel(csid->reg_update, csid->base + CSID_RUP_CMD);
+
+ /* CSID Fulls in v980 split AUP and RUP commands, which requires
+ * additional SET operation to make registers modification take
+ * effect.
+ */
+ __csid_full_aup_rup_trigger(csid);
+ }
+}
+
+static void __csid_addr_update_clear(struct csid_device *csid, int port_id)
+{
+ /* Hardware clears the registers upon consuming the settings */
+ if (csid_is_lite(csid))
+ csid->reg_update &= ~CSID_LITE_AUP_RDI(port_id);
+ else
+ csid->addr_update &= ~CSID_RUP_AUP_RDI(port_id);
+}
+
+static void __csid_reg_update_clear(struct csid_device *csid, int port_id)
+{
+ /* Hardware clears the registers upon consuming the settings */
+ if (csid_is_lite(csid))
+ csid->reg_update &= ~CSID_LITE_RUP_RDI(port_id);
+ else
+ csid->reg_update &= ~CSID_RUP_AUP_RDI(port_id);
+}
+
+static void __csid_configure_rx(struct csid_device *csid,
+ struct csid_phy_config *phy)
+{
+ int val;
+
+ val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
+ val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
+ val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX)
+ << CSI2_RX_CFG0_PHY_NUM_SEL;
+ writel(val, csid->base + CSID_CSI2_RX_CFG0);
+
+ val = CSI2_RX_CFG1_ECC_CORRECTION_EN;
+ writel(val, csid->base + CSID_CSI2_RX_CFG1);
+}
+
+static void __csid_configure_rx_vc(struct csid_device *csid, int vc)
+{
+ int val;
+
+ if (vc > 3) {
+ val = readl(csid->base + CSID_CSI2_RX_CFG1);
+ val |= CSI2_RX_CFG1_VC_MODE;
+ writel(val, csid->base + CSID_CSI2_RX_CFG1);
+ }
+}
+
+static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi)
+{
+ u32 rdi_ctrl_offset = CSID_RDI_CTRL(rdi);
+ int val = 0;
+
+ if (enable)
+ val = RDI_CTRL_START_CMD;
+
+ writel(val, csid->base + rdi_ctrl_offset);
+}
+
+static void __csid_configure_rdi_pix_store(struct csid_device *csid, u8 rdi)
+{
+ u32 val;
+
+ /*
+ * Configure pixel store to allow absorption of hblanking or idle time.
+ * This helps with horizontal crop and prevents line buffer conflicts.
+ * Reset state is 0x8 which has MIN_HBI=4, we keep the default MIN_HBI
+ * and just enable the pixel store functionality.
+ */
+ val = (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN;
+ writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi));
+}
+
+static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 port, u8 vc)
+{
+ u8 lane_cnt = csid->phy.lane_cnt;
+ u32 val;
+
+ /* Source pads matching RDI channels on hardware.
+ * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc.
+ */
+ struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + port];
+ const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
+ csid->res->formats->nformats,
+ input_format->code);
+
+ if (!lane_cnt)
+ lane_cnt = 4;
+
+ /*
+ * DT_ID is a two bit bitfield that is concatenated with
+ * the four least significant bits of the five bit VC
+ * bitfield to generate an internal CID value.
+ *
+ * CSID_RDI_CFG0(vc)
+ * DT_ID : 28:27
+ * VC : 26:22
+ * DT : 21:16
+ *
+ * CID : VC 3:0 << 2 | DT_ID 1:0
+ */
+ u8 dt_id = vc & 0x03;
+ u32 rdi_cfg0_offset = CSID_RDI_CFG0(port);
+ u32 rdi_cfg1_offset = CSID_RDI_CFG1(port);
+ u32 rdi_ctrl_offset = CSID_RDI_CTRL(port);
+
+ val = RDI_CFG0_TIMESTAMP_EN;
+ val |= RDI_CFG0_TIMESTAMP_STB_SEL;
+ val |= RDI_CFG0_RETIME_BS;
+
+ /* note: for non-RDI path, this should be format->decode_format */
+ val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
+ val |= vc << RDI_CFG0_VC;
+ val |= format->data_type << RDI_CFG0_DT;
+ val |= dt_id << RDI_CFG0_DT_ID;
+ writel(val, csid->base + rdi_cfg0_offset);
+
+ val = RDI_CFG1_PACKING_FORMAT_MIPI;
+ writel(val, csid->base + rdi_cfg1_offset);
+
+ /* Configure pixel store using dedicated register in 980 */
+ if (!csid_is_lite(csid))
+ __csid_configure_rdi_pix_store(csid, port);
+
+ val = 0;
+ writel(val, csid->base + rdi_ctrl_offset);
+
+ val = readl(csid->base + rdi_cfg0_offset);
+
+ if (enable)
+ val |= RDI_CFG0_EN;
+
+ writel(val, csid->base + rdi_cfg0_offset);
+}
+
+static void csid_configure_stream(struct csid_device *csid, u8 enable)
+{
+ u8 i, k;
+
+ __csid_configure_rx(csid, &csid->phy);
+
+ for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) {
+ if (csid->phy.en_vc & BIT(i)) {
+ __csid_configure_rdi_stream(csid, enable, i, 0);
+ __csid_configure_rx_vc(csid, 0);
+
+ for (k = 0; k < CAMSS_INIT_BUF_COUNT; k++) {
+ __csid_addr_update(csid, i);
+ __csid_reg_update(csid, i);
+ }
+
+ __csid_ctrl_rdi(csid, enable, i);
+ }
+ }
+}
+
+static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val)
+{
+ return 0;
+}
+
+static void csid_subdev_reg_update(struct csid_device *csid, int port_id,
+ bool clear)
+{
+ if (clear)
+ __csid_reg_update_clear(csid, port_id);
+ else
+ __csid_reg_update(csid, port_id);
+}
+
+static void csid_subdev_addr_update(struct csid_device *csid, int port_id,
+ bool clear)
+{
+ if (clear)
+ __csid_addr_update_clear(csid, port_id);
+ else
+ __csid_addr_update(csid, port_id);
+}
+
+/**
+ * csid_isr - CSID module interrupt service routine
+ * @irq: Interrupt line
+ * @dev: CSID device
+ *
+ * Return IRQ_HANDLED on success
+ */
+static irqreturn_t csid_isr(int irq, void *dev)
+{
+ struct csid_device *csid = dev;
+ u32 val, buf_done_val;
+ u8 reset_done;
+ int i;
+
+ val = readl(csid->base + CSID_TOP_IRQ_STATUS);
+ writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
+
+ reset_done = val & INFO_RST_DONE;
+
+ buf_done_val = readl(csid->base + CSID_BUF_DONE_IRQ_STATUS);
+ writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
+
+ for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) {
+ if (csid->phy.en_vc & BIT(i)) {
+ val = readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i));
+ writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i));
+
+ if (val & INFO_RUP_DONE) {
+ __csid_addr_update_clear(csid, i);
+ __csid_reg_update_clear(csid, i);
+ }
+
+ if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i))
+ camss_buf_done(csid->camss, csid->id, i);
+ }
+ }
+
+ val = IRQ_CMD_CLEAR;
+ writel(val, csid->base + CSID_IRQ_CMD);
+
+ if (reset_done)
+ complete(&csid->reset_complete);
+
+ return IRQ_HANDLED;
+}
+
+/**
+ * csid_reset - Trigger reset on CSID module and wait to complete
+ * @csid: CSID device
+ *
+ * Return 0 on success or a negative error code otherwise
+ */
+static int csid_reset(struct csid_device *csid)
+{
+ unsigned long time;
+ u32 val;
+ int i;
+
+ reinit_completion(&csid->reset_complete);
+
+ val = INFO_RST_DONE | BUF_DONE_IRQ_STATUS;
+ writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
+ writel(val, csid->base + CSID_TOP_IRQ_MASK);
+
+ val = 0;
+ for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) {
+ if (csid->phy.en_vc & BIT(i)) {
+ /*
+ * Only need to clear buf done IRQ status here,
+ * RUP done IRQ status will be cleared once isr
+ * strobe generated by CSID_RST_CMD
+ */
+ val |= BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i);
+ }
+ }
+ writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
+ writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK);
+
+ /* Clear all IRQ status with CLEAR bits set */
+ val = IRQ_CMD_CLEAR;
+ writel(val, csid->base + CSID_IRQ_CMD);
+
+ val = RST_LOCATION | RST_MODE;
+ writel(val, csid->base + CSID_RST_CFG);
+
+ val = SELECT_HW_RST | SELECT_IRQ_RST;
+ writel(val, csid->base + CSID_RST_CMD);
+
+ time = wait_for_completion_timeout(&csid->reset_complete,
+ msecs_to_jiffies(CSID_RESET_TIMEOUT_MS));
+
+ if (!time) {
+ dev_err(csid->camss->dev, "CSID reset timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static void csid_subdev_init(struct csid_device *csid)
+{
+ csid->testgen.nmodes = CSID_PAYLOAD_MODE_DISABLED;
+}
+
+const struct csid_hw_ops csid_ops_980 = {
+ .configure_stream = csid_configure_stream,
+ .configure_testgen_pattern = csid_configure_testgen_pattern,
+ .hw_version = csid_hw_version,
+ .isr = csid_isr,
+ .reset = csid_reset,
+ .src_pad_code = csid_src_pad_code,
+ .subdev_init = csid_subdev_init,
+ .reg_update = csid_subdev_reg_update,
+ .addr_update = csid_subdev_addr_update,
+};
diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h
index a3ab2a384bb49ac24955e86c8452a8ce36ce71b2..c0aa3ef054588a1a434932ce8e38ad0d84690858 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.h
+++ b/drivers/media/platform/qcom/camss/camss-csid.h
@@ -225,6 +225,7 @@ extern const struct csid_hw_ops csid_ops_4_1;
extern const struct csid_hw_ops csid_ops_4_7;
extern const struct csid_hw_ops csid_ops_340;
extern const struct csid_hw_ops csid_ops_680;
+extern const struct csid_hw_ops csid_ops_980;
extern const struct csid_hw_ops csid_ops_1080;
extern const struct csid_hw_ops csid_ops_gen2;
extern const struct csid_hw_ops csid_ops_gen3;
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 196eebc2d7d118040319bcf967b91c4ca98a4833..9f7b2948b3aa4d9d401aa5ad76b6133101c95278 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -4308,6 +4308,76 @@ static const struct resources_icc icc_res_sa8775p[] = {
},
};
+static const struct camss_subdev_resources csid_res_sm8750[] = {
+ /* CSID0 */
+ {
+ .clock = { "csid", "csiphy_rx" },
+ .clock_rate = { { 266666667, 400000000, 480000000 },
+ { 266666667, 400000000, 480000000 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_980,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID1 */
+ {
+ .clock = { "csid", "csiphy_rx" },
+ .clock_rate = { { 266666667, 400000000, 480000000 },
+ { 266666667, 400000000, 480000000 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_980,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID2 */
+ {
+ .clock = { "csid", "csiphy_rx" },
+ .clock_rate = { { 266666667, 400000000, 480000000 },
+ { 266666667, 400000000, 480000000 } },
+ .reg = { "csid2" },
+ .interrupt = { "csid2" },
+ .csid = {
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_980,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE0 */
+ {
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 266666667, 400000000, 480000000 },
+ { 266666667, 400000000, 480000000 } },
+ .reg = { "csid_lite0" },
+ .interrupt = { "csid_lite0" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_980,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE1 */
+ {
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 266666667, 400000000, 480000000 },
+ { 266666667, 400000000, 480000000 } },
+ .reg = { "csid_lite1" },
+ .interrupt = { "csid_lite1" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_980,
+ .formats = &csid_formats_gen2
+ }
+ }
+};
+
static const struct resources_icc icc_res_sm8750[] = {
{
.name = "ahb",
@@ -6044,9 +6114,11 @@ static const struct camss_resources sm8750_resources = {
.version = CAMSS_8750,
.pd_name = "top",
.pm_clks = { "cpas_fast_ahb", "cpas_ahb", "gcc_axi_hf" },
+ .csid_res = csid_res_sm8750,
.icc_res = icc_res_sm8750,
.icc_path_num = ARRAY_SIZE(icc_res_sm8750),
.csiphy_num = 6,
+ .csid_num = ARRAY_SIZE(csid_res_sm8750),
};
static const struct camss_resources x1e80100_resources = {
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 10/23] media: qcom: camss: csid: Add support for CSID 980
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu, Atiya Kailany
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add resource information for CSID devices and the driver for CSID 980,
which handles CSID register configuration, module reset and IRQ handling
for BUF_DONE events.
In SM8750, the RUP and AUP updates of the Full CSIDs are split into two
registers with a SET register, while Lite CSIDs still use a single
register. The driver handles these differences.
Also define the SOF and EOF event bits for the CSI2 input and CAMIF, and
the RDIn IRQ mask register. These are definitions only; frame event IRQs
are not handled yet.
Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/Makefile | 1 +
drivers/media/platform/qcom/camss/camss-csid-980.c | 466 +++++++++++++++++++++
drivers/media/platform/qcom/camss/camss-csid.h | 1 +
drivers/media/platform/qcom/camss/camss.c | 72 ++++
4 files changed, 540 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
index 42a14e8fe1b7f28ba5ffcbe59769093b08db4d6b..1aef4267543dfa1c25dbbf351252862bf94a847d 100644
--- a/drivers/media/platform/qcom/camss/Makefile
+++ b/drivers/media/platform/qcom/camss/Makefile
@@ -8,6 +8,7 @@ qcom-camss-objs += \
camss-csid-4-7.o \
camss-csid-340.o \
camss-csid-680.o \
+ camss-csid-980.o \
camss-csid-1080.o \
camss-csid-gen2.o \
camss-csid-gen3.o \
diff --git a/drivers/media/platform/qcom/camss/camss-csid-980.c b/drivers/media/platform/qcom/camss/camss-csid-980.c
new file mode 100644
index 0000000000000000000000000000000000000000..713db25cd8c65ed7e991bffbb8b19d66c662e708
--- /dev/null
+++ b/drivers/media/platform/qcom/camss/camss-csid-980.c
@@ -0,0 +1,466 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * camss-csid-980.c
+ *
+ * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include "camss.h"
+#include "camss-csid.h"
+#include "camss-csid-gen3.h"
+
+/* Reset and Command Registers */
+#define CSID_RST_CFG 0xC
+#define RST_MODE BIT(0)
+#define RST_LOCATION BIT(4)
+
+/* Reset and Command Registers */
+#define CSID_RST_CMD 0x10
+#define SELECT_HW_RST BIT(0)
+#define SELECT_IRQ_RST BIT(2)
+#define CSID_IRQ_CMD 0x14
+#define IRQ_CMD_CLEAR BIT(0)
+
+/* Register Update Commands, RUP/AUP */
+#define CSID_RUP_CMD 0x18
+#define CSID_AUP_CMD 0x1C
+#define CSID_RUP_AUP_RDI(rdi) (BIT(8) << (rdi))
+#define CSID_RUP_AUP_CMD 0x20
+#define RUP_SET BIT(0)
+#define MUP BIT(4)
+
+#define CSID_LITE_RUP_AUP_CMD 0x18
+#define CSID_LITE_RUP_RDI(rdi) (BIT(4) << (rdi))
+#define CSID_LITE_AUP_RDI(rdi) (BIT(20) << (rdi))
+
+/* Top level interrupt registers */
+#define CSID_TOP_IRQ_STATUS (csid_is_lite(csid) ? 0x7C : 0x84)
+#define CSID_TOP_IRQ_MASK (csid_is_lite(csid) ? 0x80 : 0x88)
+#define CSID_TOP_IRQ_CLEAR (csid_is_lite(csid) ? 0x84 : 0x8C)
+#define CSID_TOP_IRQ_SET (csid_is_lite(csid) ? 0x88 : 0x90)
+#define INFO_RST_DONE BIT(0)
+#define CSI2_RX_IRQ_STATUS BIT(2)
+#define BUF_DONE_IRQ_STATUS BIT(csid_is_lite(csid) ? 13 : 3)
+
+/* Buffer done interrupt registers */
+#define CSID_BUF_DONE_IRQ_STATUS (csid_is_lite(csid) ? 0x8C : 0xA4)
+#define BUF_DONE_IRQ_STATUS_RDI_OFFSET (csid_is_lite(csid) ? 1 : 16)
+#define CSID_BUF_DONE_IRQ_MASK (csid_is_lite(csid) ? 0x90 : 0xA8)
+#define CSID_BUF_DONE_IRQ_CLEAR (csid_is_lite(csid) ? 0x94 : 0xAC)
+#define CSID_BUF_DONE_IRQ_SET (csid_is_lite(csid) ? 0x98 : 0xB0)
+
+/* CSI2 RX interrupt registers */
+#define CSID_CSI2_RX_IRQ_STATUS (csid_is_lite(csid) ? 0x9C : 0xB4)
+#define CSID_CSI2_RX_IRQ_MASK (csid_is_lite(csid) ? 0xA0 : 0xB8)
+#define CSID_CSI2_RX_IRQ_CLEAR (csid_is_lite(csid) ? 0xA4 : 0xBC)
+#define CSID_CSI2_RX_IRQ_SET (csid_is_lite(csid) ? 0xA8 : 0xC0)
+
+/* CSI2 RX Configuration */
+#define CSID_CSI2_RX_CFG0 (csid_is_lite(csid) ? 0x200 : 0x400)
+#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0
+#define CSI2_RX_CFG0_DL0_INPUT_SEL 4
+#define CSI2_RX_CFG0_PHY_NUM_SEL 20
+#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1
+#define CSID_CSI2_RX_CFG1 (csid_is_lite(csid) ? 0x204 : 0x404)
+#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0)
+#define CSI2_RX_CFG1_VC_MODE BIT(2)
+
+#define MSM_CSID_MAX_SRC_STREAMS_980 (csid_is_lite(csid) ? 4 : 5)
+
+#define CSID_RDI_CFG0(rdi) \
+ ({ \
+ __typeof__(rdi) _rdi = (rdi); \
+ csid_is_lite(csid) ? 0x500 + 0x100 * _rdi : \
+ 0xE00 + 0x200 * _rdi; \
+ })
+#define RDI_CFG0_RETIME_BS BIT(5)
+#define RDI_CFG0_TIMESTAMP_EN BIT(6)
+#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8)
+#define RDI_CFG0_DECODE_FORMAT 12
+#define RDI_CFG0_DT 16
+#define RDI_CFG0_VC 22
+#define RDI_CFG0_DT_ID 27
+#define RDI_CFG0_EN BIT(31)
+
+/* RDI Control and Configuration */
+#define CSID_RDI_CTRL(rdi) \
+ ({ \
+ __typeof__(rdi) _rdi = (rdi); \
+ csid_is_lite(csid) ? 0x504 + 0x100 * _rdi : \
+ 0xE04 + 0x200 * _rdi; \
+ })
+#define RDI_CTRL_START_CMD BIT(0)
+
+#define CSID_RDI_CFG1(rdi) \
+ ({ \
+ __typeof__(rdi) _rdi = (rdi); \
+ csid_is_lite(csid) ? 0x510 + 0x100 * _rdi : \
+ 0xE10 + 0x200 * _rdi; \
+ })
+#define RDI_CFG1_DROP_H_EN BIT(5)
+#define RDI_CFG1_DROP_V_EN BIT(6)
+#define RDI_CFG1_CROP_H_EN BIT(7)
+#define RDI_CFG1_CROP_V_EN BIT(8)
+#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15)
+
+/* RDI Pixel Store Configuration */
+#define CSID_RDI_PIX_STORE_CFG0(rdi) (0xE14 + 0x200 * (rdi))
+#define RDI_PIX_STORE_CFG0_EN BIT(0)
+#define RDI_PIX_STORE_CFG0_MIN_HBI 1
+
+/* RDI IRQ Status in wrapper */
+#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) \
+ ((csid_is_lite(csid) ? 0xEC : 0x114) + 0x10 * (rdi))
+#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) \
+ ((csid_is_lite(csid) ? 0xF4 : 0x11C) + 0x10 * (rdi))
+#define CSID_CSI2_RDIN_IRQ_MASK(rdi) \
+ ((csid_is_lite(csid) ? 0xF0 : 0x118) + 0x10 * (rdi))
+#define INFO_RUP_DONE BIT(23)
+#define INFO_INPUT_SOF BIT(12)
+#define INFO_INPUT_EOF BIT(9)
+#define INFO_CAMIF_SOF BIT(4)
+#define INFO_CAMIF_EOF BIT(3)
+
+static void __csid_full_aup_rup_trigger(struct csid_device *csid)
+{
+ /* trigger SET in combined register */
+ writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD);
+}
+
+static void __csid_addr_update(struct csid_device *csid, int port_id)
+{
+ if (csid_is_lite(csid)) {
+ /* CSID Lites in v980 follow the legacy way of a combined RUP
+ * and AUP commands without an explicit SET register.
+ */
+ csid->reg_update |= CSID_LITE_AUP_RDI(port_id);
+ writel(csid->reg_update, csid->base + CSID_LITE_RUP_AUP_CMD);
+ } else {
+ csid->addr_update |= CSID_RUP_AUP_RDI(port_id);
+ writel(csid->addr_update, csid->base + CSID_AUP_CMD);
+
+ /* CSID Fulls in v980 split AUP and RUP commands, which requires
+ * additional SET operation to make registers modification take
+ * effect.
+ */
+ __csid_full_aup_rup_trigger(csid);
+ }
+}
+
+static void __csid_reg_update(struct csid_device *csid, int port_id)
+{
+ if (csid_is_lite(csid)) {
+ /* CSID Lites in v980 follow the legacy way of a combined RUP
+ * and AUP commands without an explicit SET register.
+ */
+ csid->reg_update |= CSID_LITE_RUP_RDI(port_id);
+ writel(csid->reg_update, csid->base + CSID_LITE_RUP_AUP_CMD);
+ } else {
+ csid->reg_update |= CSID_RUP_AUP_RDI(port_id);
+ writel(csid->reg_update, csid->base + CSID_RUP_CMD);
+
+ /* CSID Fulls in v980 split AUP and RUP commands, which requires
+ * additional SET operation to make registers modification take
+ * effect.
+ */
+ __csid_full_aup_rup_trigger(csid);
+ }
+}
+
+static void __csid_addr_update_clear(struct csid_device *csid, int port_id)
+{
+ /* Hardware clears the registers upon consuming the settings */
+ if (csid_is_lite(csid))
+ csid->reg_update &= ~CSID_LITE_AUP_RDI(port_id);
+ else
+ csid->addr_update &= ~CSID_RUP_AUP_RDI(port_id);
+}
+
+static void __csid_reg_update_clear(struct csid_device *csid, int port_id)
+{
+ /* Hardware clears the registers upon consuming the settings */
+ if (csid_is_lite(csid))
+ csid->reg_update &= ~CSID_LITE_RUP_RDI(port_id);
+ else
+ csid->reg_update &= ~CSID_RUP_AUP_RDI(port_id);
+}
+
+static void __csid_configure_rx(struct csid_device *csid,
+ struct csid_phy_config *phy)
+{
+ int val;
+
+ val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
+ val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
+ val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX)
+ << CSI2_RX_CFG0_PHY_NUM_SEL;
+ writel(val, csid->base + CSID_CSI2_RX_CFG0);
+
+ val = CSI2_RX_CFG1_ECC_CORRECTION_EN;
+ writel(val, csid->base + CSID_CSI2_RX_CFG1);
+}
+
+static void __csid_configure_rx_vc(struct csid_device *csid, int vc)
+{
+ int val;
+
+ if (vc > 3) {
+ val = readl(csid->base + CSID_CSI2_RX_CFG1);
+ val |= CSI2_RX_CFG1_VC_MODE;
+ writel(val, csid->base + CSID_CSI2_RX_CFG1);
+ }
+}
+
+static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi)
+{
+ u32 rdi_ctrl_offset = CSID_RDI_CTRL(rdi);
+ int val = 0;
+
+ if (enable)
+ val = RDI_CTRL_START_CMD;
+
+ writel(val, csid->base + rdi_ctrl_offset);
+}
+
+static void __csid_configure_rdi_pix_store(struct csid_device *csid, u8 rdi)
+{
+ u32 val;
+
+ /*
+ * Configure pixel store to allow absorption of hblanking or idle time.
+ * This helps with horizontal crop and prevents line buffer conflicts.
+ * Reset state is 0x8 which has MIN_HBI=4, we keep the default MIN_HBI
+ * and just enable the pixel store functionality.
+ */
+ val = (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN;
+ writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi));
+}
+
+static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 port, u8 vc)
+{
+ u8 lane_cnt = csid->phy.lane_cnt;
+ u32 val;
+
+ /* Source pads matching RDI channels on hardware.
+ * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc.
+ */
+ struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + port];
+ const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
+ csid->res->formats->nformats,
+ input_format->code);
+
+ if (!lane_cnt)
+ lane_cnt = 4;
+
+ /*
+ * DT_ID is a two bit bitfield that is concatenated with
+ * the four least significant bits of the five bit VC
+ * bitfield to generate an internal CID value.
+ *
+ * CSID_RDI_CFG0(vc)
+ * DT_ID : 28:27
+ * VC : 26:22
+ * DT : 21:16
+ *
+ * CID : VC 3:0 << 2 | DT_ID 1:0
+ */
+ u8 dt_id = vc & 0x03;
+ u32 rdi_cfg0_offset = CSID_RDI_CFG0(port);
+ u32 rdi_cfg1_offset = CSID_RDI_CFG1(port);
+ u32 rdi_ctrl_offset = CSID_RDI_CTRL(port);
+
+ val = RDI_CFG0_TIMESTAMP_EN;
+ val |= RDI_CFG0_TIMESTAMP_STB_SEL;
+ val |= RDI_CFG0_RETIME_BS;
+
+ /* note: for non-RDI path, this should be format->decode_format */
+ val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
+ val |= vc << RDI_CFG0_VC;
+ val |= format->data_type << RDI_CFG0_DT;
+ val |= dt_id << RDI_CFG0_DT_ID;
+ writel(val, csid->base + rdi_cfg0_offset);
+
+ val = RDI_CFG1_PACKING_FORMAT_MIPI;
+ writel(val, csid->base + rdi_cfg1_offset);
+
+ /* Configure pixel store using dedicated register in 980 */
+ if (!csid_is_lite(csid))
+ __csid_configure_rdi_pix_store(csid, port);
+
+ val = 0;
+ writel(val, csid->base + rdi_ctrl_offset);
+
+ val = readl(csid->base + rdi_cfg0_offset);
+
+ if (enable)
+ val |= RDI_CFG0_EN;
+
+ writel(val, csid->base + rdi_cfg0_offset);
+}
+
+static void csid_configure_stream(struct csid_device *csid, u8 enable)
+{
+ u8 i, k;
+
+ __csid_configure_rx(csid, &csid->phy);
+
+ for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) {
+ if (csid->phy.en_vc & BIT(i)) {
+ __csid_configure_rdi_stream(csid, enable, i, 0);
+ __csid_configure_rx_vc(csid, 0);
+
+ for (k = 0; k < CAMSS_INIT_BUF_COUNT; k++) {
+ __csid_addr_update(csid, i);
+ __csid_reg_update(csid, i);
+ }
+
+ __csid_ctrl_rdi(csid, enable, i);
+ }
+ }
+}
+
+static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val)
+{
+ return 0;
+}
+
+static void csid_subdev_reg_update(struct csid_device *csid, int port_id,
+ bool clear)
+{
+ if (clear)
+ __csid_reg_update_clear(csid, port_id);
+ else
+ __csid_reg_update(csid, port_id);
+}
+
+static void csid_subdev_addr_update(struct csid_device *csid, int port_id,
+ bool clear)
+{
+ if (clear)
+ __csid_addr_update_clear(csid, port_id);
+ else
+ __csid_addr_update(csid, port_id);
+}
+
+/**
+ * csid_isr - CSID module interrupt service routine
+ * @irq: Interrupt line
+ * @dev: CSID device
+ *
+ * Return IRQ_HANDLED on success
+ */
+static irqreturn_t csid_isr(int irq, void *dev)
+{
+ struct csid_device *csid = dev;
+ u32 val, buf_done_val;
+ u8 reset_done;
+ int i;
+
+ val = readl(csid->base + CSID_TOP_IRQ_STATUS);
+ writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
+
+ reset_done = val & INFO_RST_DONE;
+
+ buf_done_val = readl(csid->base + CSID_BUF_DONE_IRQ_STATUS);
+ writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
+
+ for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) {
+ if (csid->phy.en_vc & BIT(i)) {
+ val = readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i));
+ writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i));
+
+ if (val & INFO_RUP_DONE) {
+ __csid_addr_update_clear(csid, i);
+ __csid_reg_update_clear(csid, i);
+ }
+
+ if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i))
+ camss_buf_done(csid->camss, csid->id, i);
+ }
+ }
+
+ val = IRQ_CMD_CLEAR;
+ writel(val, csid->base + CSID_IRQ_CMD);
+
+ if (reset_done)
+ complete(&csid->reset_complete);
+
+ return IRQ_HANDLED;
+}
+
+/**
+ * csid_reset - Trigger reset on CSID module and wait to complete
+ * @csid: CSID device
+ *
+ * Return 0 on success or a negative error code otherwise
+ */
+static int csid_reset(struct csid_device *csid)
+{
+ unsigned long time;
+ u32 val;
+ int i;
+
+ reinit_completion(&csid->reset_complete);
+
+ val = INFO_RST_DONE | BUF_DONE_IRQ_STATUS;
+ writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
+ writel(val, csid->base + CSID_TOP_IRQ_MASK);
+
+ val = 0;
+ for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) {
+ if (csid->phy.en_vc & BIT(i)) {
+ /*
+ * Only need to clear buf done IRQ status here,
+ * RUP done IRQ status will be cleared once isr
+ * strobe generated by CSID_RST_CMD
+ */
+ val |= BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i);
+ }
+ }
+ writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
+ writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK);
+
+ /* Clear all IRQ status with CLEAR bits set */
+ val = IRQ_CMD_CLEAR;
+ writel(val, csid->base + CSID_IRQ_CMD);
+
+ val = RST_LOCATION | RST_MODE;
+ writel(val, csid->base + CSID_RST_CFG);
+
+ val = SELECT_HW_RST | SELECT_IRQ_RST;
+ writel(val, csid->base + CSID_RST_CMD);
+
+ time = wait_for_completion_timeout(&csid->reset_complete,
+ msecs_to_jiffies(CSID_RESET_TIMEOUT_MS));
+
+ if (!time) {
+ dev_err(csid->camss->dev, "CSID reset timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static void csid_subdev_init(struct csid_device *csid)
+{
+ csid->testgen.nmodes = CSID_PAYLOAD_MODE_DISABLED;
+}
+
+const struct csid_hw_ops csid_ops_980 = {
+ .configure_stream = csid_configure_stream,
+ .configure_testgen_pattern = csid_configure_testgen_pattern,
+ .hw_version = csid_hw_version,
+ .isr = csid_isr,
+ .reset = csid_reset,
+ .src_pad_code = csid_src_pad_code,
+ .subdev_init = csid_subdev_init,
+ .reg_update = csid_subdev_reg_update,
+ .addr_update = csid_subdev_addr_update,
+};
diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h
index a3ab2a384bb49ac24955e86c8452a8ce36ce71b2..c0aa3ef054588a1a434932ce8e38ad0d84690858 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.h
+++ b/drivers/media/platform/qcom/camss/camss-csid.h
@@ -225,6 +225,7 @@ extern const struct csid_hw_ops csid_ops_4_1;
extern const struct csid_hw_ops csid_ops_4_7;
extern const struct csid_hw_ops csid_ops_340;
extern const struct csid_hw_ops csid_ops_680;
+extern const struct csid_hw_ops csid_ops_980;
extern const struct csid_hw_ops csid_ops_1080;
extern const struct csid_hw_ops csid_ops_gen2;
extern const struct csid_hw_ops csid_ops_gen3;
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 196eebc2d7d118040319bcf967b91c4ca98a4833..9f7b2948b3aa4d9d401aa5ad76b6133101c95278 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -4308,6 +4308,76 @@ static const struct resources_icc icc_res_sa8775p[] = {
},
};
+static const struct camss_subdev_resources csid_res_sm8750[] = {
+ /* CSID0 */
+ {
+ .clock = { "csid", "csiphy_rx" },
+ .clock_rate = { { 266666667, 400000000, 480000000 },
+ { 266666667, 400000000, 480000000 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_980,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID1 */
+ {
+ .clock = { "csid", "csiphy_rx" },
+ .clock_rate = { { 266666667, 400000000, 480000000 },
+ { 266666667, 400000000, 480000000 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_980,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID2 */
+ {
+ .clock = { "csid", "csiphy_rx" },
+ .clock_rate = { { 266666667, 400000000, 480000000 },
+ { 266666667, 400000000, 480000000 } },
+ .reg = { "csid2" },
+ .interrupt = { "csid2" },
+ .csid = {
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_980,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE0 */
+ {
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 266666667, 400000000, 480000000 },
+ { 266666667, 400000000, 480000000 } },
+ .reg = { "csid_lite0" },
+ .interrupt = { "csid_lite0" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_980,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE1 */
+ {
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 266666667, 400000000, 480000000 },
+ { 266666667, 400000000, 480000000 } },
+ .reg = { "csid_lite1" },
+ .interrupt = { "csid_lite1" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_980,
+ .formats = &csid_formats_gen2
+ }
+ }
+};
+
static const struct resources_icc icc_res_sm8750[] = {
{
.name = "ahb",
@@ -6044,9 +6114,11 @@ static const struct camss_resources sm8750_resources = {
.version = CAMSS_8750,
.pd_name = "top",
.pm_clks = { "cpas_fast_ahb", "cpas_ahb", "gcc_axi_hf" },
+ .csid_res = csid_res_sm8750,
.icc_res = icc_res_sm8750,
.icc_path_num = ARRAY_SIZE(icc_res_sm8750),
.csiphy_num = 6,
+ .csid_num = ARRAY_SIZE(csid_res_sm8750),
};
static const struct camss_resources x1e80100_resources = {
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 11/23] media: qcom: camss: vfe: Add support for VFE 980
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add support for the VFE (Video Front End) 980 found on SM8750 SoC.
The bus register base of the lite VFEs starts at 0x200 and that of the
full VFEs at 0x800.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/Makefile | 1 +
drivers/media/platform/qcom/camss/camss-vfe-980.c | 213 ++++++++++++++++++++++
drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
drivers/media/platform/qcom/camss/camss-vfe.h | 1 +
drivers/media/platform/qcom/camss/camss.c | 115 ++++++++++++
5 files changed, 332 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
index 1aef4267543dfa1c25dbbf351252862bf94a847d..b955b3c735ddcd0f8c733553188cef8b48fe4e9f 100644
--- a/drivers/media/platform/qcom/camss/Makefile
+++ b/drivers/media/platform/qcom/camss/Makefile
@@ -27,6 +27,7 @@ qcom-camss-objs += \
camss-vfe-340.o \
camss-vfe-480.o \
camss-vfe-680.o \
+ camss-vfe-980.o \
camss-vfe-1080.o \
camss-vfe-gen1.o \
camss-vfe-gen3.o \
diff --git a/drivers/media/platform/qcom/camss/camss-vfe-980.c b/drivers/media/platform/qcom/camss/camss-vfe-980.c
new file mode 100644
index 0000000000000000000000000000000000000000..47f6c18190acfbf3c6ab49186fc73fde6a0ac799
--- /dev/null
+++ b/drivers/media/platform/qcom/camss/camss-vfe-980.c
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * camss-vfe-980.c
+ *
+ * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module 980
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+
+#include "camss.h"
+#include "camss-vfe.h"
+
+/* VFE-980 Bus Register Base Addresses */
+#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x200 : 0x800)
+
+#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08)
+#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF)
+
+#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0x128)
+
+#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x500 + (n) * 0x100)
+#define WM_CFG_EN BIT(0)
+#define WM_VIR_FRM_EN BIT(1)
+#define WM_CFG_MODE BIT(16)
+#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x504 + (n) * 0x100)
+#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x508 + (n) * 0x100)
+#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x50C + (n) * 0x100)
+#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF)
+#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x514 + (n) * 0x100)
+#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF)
+#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x518 + (n) * 0x100)
+
+#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x530 + (n) * 0x100)
+#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x534 + (n) * 0x100)
+
+/* VFE lite has no such registers */
+#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x538 + (n) * 0x100)
+#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x53C + (n) * 0x100)
+
+#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x560 + (n) * 0x100)
+#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x564 + (n) * 0x100)
+
+/*
+ * IFE write master client IDs
+ *
+ * VIDEO_FULL 0
+ * VIDEO_DC4_Y 1
+ * VIDEO_DC4_C 2
+ * VIDEO_DC16_Y 3
+ * VIDEO_DC16_C 4
+ * DISPLAY_DS2_Y 5
+ * DISPLAY_DS2_C 6
+ * FD_Y 7
+ * FD_C 8
+ * IR_OUT 9
+ * STATS_AEC_BG 10
+ * STATS_AEC_BHIST 11
+ * STATS_TINTLESS_BG 12
+ * STATS_AWB_BG 13
+ * STATS_AWB_BFW 14
+ * STATS_AF_BHIST 15
+ * STATS_ALSC_BG 16
+ * STATS_FLICKER_BAYERRS 17
+ * STATS_TMC_BHIST 18
+ * PDAF_0 19
+ * PDAF_1 20
+ * PDAF_2 21
+ * PDAF_3 22
+ * RDI0 23
+ * RDI1 24
+ * RDI2 25
+ * RDI3 26
+ * RDI4 27
+ *
+ * IFE Lite write master client IDs
+ *
+ * RDI0 0
+ * RDI1 1
+ * RDI2 2
+ * RDI3 3
+ * GAMMA 4
+ * STATES_BE 5
+ */
+#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n))
+
+static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
+{
+ struct v4l2_pix_format_mplane *pix =
+ &line->video_out.active_fmt.fmt.pix_mp;
+
+ wm = RDI_WM(wm);
+
+ /* no clock gating at bus input */
+ writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);
+
+ writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
+
+ writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8,
+ vfe->base + VFE_BUS_WM_FRAME_INCR(wm));
+ writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF),
+ vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm));
+ writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE,
+ vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm));
+ writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm));
+
+ /* no dropped frames, one irq per frame */
+ if (!vfe_is_lite(vfe)) {
+ writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm));
+ writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm));
+ }
+
+ writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm));
+ writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm));
+
+ writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm));
+ writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm));
+
+ writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm));
+}
+
+static void vfe_wm_stop(struct vfe_device *vfe, u8 wm)
+{
+ wm = RDI_WM(wm);
+ writel(0, vfe->base + VFE_BUS_WM_CFG(wm));
+}
+
+static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr,
+ struct vfe_line *line)
+{
+ wm = RDI_WM(wm);
+ writel(addr >> 8, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
+
+ dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", wm, addr);
+}
+
+static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
+{
+ int port_id = line_id;
+
+ camss_reg_update(vfe->camss, vfe->id, port_id, false);
+}
+
+static void vfe_reg_update_clear(struct vfe_device *vfe,
+ enum vfe_line_id line_id)
+{
+ int port_id = line_id;
+
+ camss_reg_update(vfe->camss, vfe->id, port_id, true);
+}
+
+static void vfe_addr_update(struct vfe_device *vfe, enum vfe_line_id line_id)
+{
+ int port_id = line_id;
+
+ camss_addr_update(vfe->camss, vfe->id, port_id, false);
+}
+
+static void vfe_addr_update_clear(struct vfe_device *vfe, enum vfe_line_id line_id)
+{
+ int port_id = line_id;
+
+ camss_addr_update(vfe->camss, vfe->id, port_id, true);
+}
+
+static const struct camss_video_ops vfe_video_ops_980 = {
+ .queue_buffer = vfe_queue_buffer_v2,
+ .flush_buffers = vfe_flush_buffers,
+};
+
+static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe)
+{
+ vfe->video_ops = vfe_video_ops_980;
+}
+
+static void vfe_global_reset(struct vfe_device *vfe)
+{
+ vfe_isr_reset_ack(vfe);
+}
+
+static irqreturn_t vfe_isr(int irq, void *dev)
+{
+ /* nop */
+ return IRQ_HANDLED;
+}
+
+static int vfe_halt(struct vfe_device *vfe)
+{
+ /* rely on vfe_disable_output() to stop the VFE */
+ return 0;
+}
+
+const struct vfe_hw_ops vfe_ops_980 = {
+ .addr_update = vfe_addr_update,
+ .addr_update_clear = vfe_addr_update_clear,
+ .global_reset = vfe_global_reset,
+ .hw_version = vfe_hw_version,
+ .isr = vfe_isr,
+ .pm_domain_off = vfe_pm_domain_off,
+ .pm_domain_on = vfe_pm_domain_on,
+ .reg_update = vfe_reg_update,
+ .reg_update_clear = vfe_reg_update_clear,
+ .subdev_init = vfe_subdev_init,
+ .vfe_disable = vfe_disable,
+ .vfe_enable = vfe_enable_v2,
+ .vfe_halt = vfe_halt,
+ .vfe_wm_start = vfe_wm_start,
+ .vfe_wm_stop = vfe_wm_stop,
+ .vfe_buf_done = vfe_buf_done,
+ .vfe_wm_update = vfe_wm_update,
+};
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 7a7d7fbc4e825ba980312e3079ab1ccb2ff0b62b..7a20d9c1a350da183959f9ae024ef6f53cbd0c1c 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -352,6 +352,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
case CAMSS_845:
case CAMSS_8550:
case CAMSS_8650:
+ case CAMSS_8750:
case CAMSS_8775P:
case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
@@ -2017,6 +2018,7 @@ static int vfe_bpl_align_rdi(struct vfe_device *vfe)
case CAMSS_845:
case CAMSS_8550:
case CAMSS_8650:
+ case CAMSS_8750:
case CAMSS_8775P:
case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h
index 0a91440cfe438625f7f1b71b60186491b3d24d5d..c8afa0dc9660d4b8cb0891ad2bbd9fdc92126e48 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.h
+++ b/drivers/media/platform/qcom/camss/camss-vfe.h
@@ -251,6 +251,7 @@ extern const struct vfe_hw_ops vfe_ops_170;
extern const struct vfe_hw_ops vfe_ops_340;
extern const struct vfe_hw_ops vfe_ops_480;
extern const struct vfe_hw_ops vfe_ops_680;
+extern const struct vfe_hw_ops vfe_ops_980;
extern const struct vfe_hw_ops vfe_ops_1080;
extern const struct vfe_hw_ops vfe_ops_gen3;
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 9f7b2948b3aa4d9d401aa5ad76b6133101c95278..d05c0f965f01ce02a91b5f8dbd58a43ad9691019 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -229,6 +229,119 @@ static const struct camss_subdev_resources vfe_res_kaanapali[] = {
},
};
+static const struct camss_subdev_resources vfe_res_sm8750[] = {
+ /* VFE0 - TFE Full */
+ {
+ .clock = { "vfe0_fast_ahb", "vfe0",
+ "cpas_vfe0", "cpas_vfe1", "cpas_vfe2",
+ "camnoc_rt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 360280000, 480000000, 630000000, 716000000,
+ 833000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000 },
+ { 0 } },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 3,
+ .has_pd = true,
+ .pd_name = "ife0",
+ .hw_ops = &vfe_ops_980,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE1 - TFE Full */
+ {
+ .clock = { "vfe1_fast_ahb", "vfe1",
+ "cpas_vfe0", "cpas_vfe1", "cpas_vfe2",
+ "camnoc_rt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 360280000, 480000000, 630000000, 716000000,
+ 833000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000 },
+ { 0 } },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 3,
+ .has_pd = true,
+ .pd_name = "ife1",
+ .hw_ops = &vfe_ops_980,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE2 - TFE Full */
+ {
+ .clock = { "vfe2_fast_ahb", "vfe2",
+ "cpas_vfe0", "cpas_vfe1", "cpas_vfe2",
+ "camnoc_rt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 360280000, 480000000, 630000000, 716000000,
+ 833000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000 },
+ { 0 } },
+ .reg = { "vfe2" },
+ .interrupt = { "vfe2" },
+ .vfe = {
+ .line_num = 3,
+ .has_pd = true,
+ .pd_name = "ife2",
+ .hw_ops = &vfe_ops_980,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE3 - IFE Lite */
+ {
+ .clock = { "vfe_lite_ahb", "vfe_lite", "cpas_vfe_lite",
+ "camnoc_rt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 0 },
+ { 200000000, 300000000, 400000000 },
+ { 0 } },
+ .reg = { "vfe_lite0" },
+ .interrupt = { "vfe_lite0" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_980,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE4 - IFE Lite */
+ {
+ .clock = { "vfe_lite_ahb", "vfe_lite", "cpas_vfe_lite",
+ "camnoc_rt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 0 },
+ { 200000000, 300000000, 400000000 },
+ { 0 } },
+ .reg = { "vfe_lite1" },
+ .interrupt = { "vfe_lite1" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_980,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+};
+
static const struct resources_icc icc_res_kaanapali[] = {
{
.name = "ahb",
@@ -6115,10 +6228,12 @@ static const struct camss_resources sm8750_resources = {
.pd_name = "top",
.pm_clks = { "cpas_fast_ahb", "cpas_ahb", "gcc_axi_hf" },
.csid_res = csid_res_sm8750,
+ .vfe_res = vfe_res_sm8750,
.icc_res = icc_res_sm8750,
.icc_path_num = ARRAY_SIZE(icc_res_sm8750),
.csiphy_num = 6,
.csid_num = ARRAY_SIZE(csid_res_sm8750),
+ .vfe_num = ARRAY_SIZE(vfe_res_sm8750),
};
static const struct camss_resources x1e80100_resources = {
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 11/23] media: qcom: camss: vfe: Add support for VFE 980
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add support for the VFE (Video Front End) 980 found on SM8750 SoC.
The bus register base of the lite VFEs starts at 0x200 and that of the
full VFEs at 0x800.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/Makefile | 1 +
drivers/media/platform/qcom/camss/camss-vfe-980.c | 213 ++++++++++++++++++++++
drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
drivers/media/platform/qcom/camss/camss-vfe.h | 1 +
drivers/media/platform/qcom/camss/camss.c | 115 ++++++++++++
5 files changed, 332 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
index 1aef4267543dfa1c25dbbf351252862bf94a847d..b955b3c735ddcd0f8c733553188cef8b48fe4e9f 100644
--- a/drivers/media/platform/qcom/camss/Makefile
+++ b/drivers/media/platform/qcom/camss/Makefile
@@ -27,6 +27,7 @@ qcom-camss-objs += \
camss-vfe-340.o \
camss-vfe-480.o \
camss-vfe-680.o \
+ camss-vfe-980.o \
camss-vfe-1080.o \
camss-vfe-gen1.o \
camss-vfe-gen3.o \
diff --git a/drivers/media/platform/qcom/camss/camss-vfe-980.c b/drivers/media/platform/qcom/camss/camss-vfe-980.c
new file mode 100644
index 0000000000000000000000000000000000000000..47f6c18190acfbf3c6ab49186fc73fde6a0ac799
--- /dev/null
+++ b/drivers/media/platform/qcom/camss/camss-vfe-980.c
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * camss-vfe-980.c
+ *
+ * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module 980
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+
+#include "camss.h"
+#include "camss-vfe.h"
+
+/* VFE-980 Bus Register Base Addresses */
+#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x200 : 0x800)
+
+#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08)
+#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF)
+
+#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0x128)
+
+#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x500 + (n) * 0x100)
+#define WM_CFG_EN BIT(0)
+#define WM_VIR_FRM_EN BIT(1)
+#define WM_CFG_MODE BIT(16)
+#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x504 + (n) * 0x100)
+#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x508 + (n) * 0x100)
+#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x50C + (n) * 0x100)
+#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF)
+#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x514 + (n) * 0x100)
+#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF)
+#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x518 + (n) * 0x100)
+
+#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x530 + (n) * 0x100)
+#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x534 + (n) * 0x100)
+
+/* VFE lite has no such registers */
+#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x538 + (n) * 0x100)
+#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x53C + (n) * 0x100)
+
+#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x560 + (n) * 0x100)
+#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x564 + (n) * 0x100)
+
+/*
+ * IFE write master client IDs
+ *
+ * VIDEO_FULL 0
+ * VIDEO_DC4_Y 1
+ * VIDEO_DC4_C 2
+ * VIDEO_DC16_Y 3
+ * VIDEO_DC16_C 4
+ * DISPLAY_DS2_Y 5
+ * DISPLAY_DS2_C 6
+ * FD_Y 7
+ * FD_C 8
+ * IR_OUT 9
+ * STATS_AEC_BG 10
+ * STATS_AEC_BHIST 11
+ * STATS_TINTLESS_BG 12
+ * STATS_AWB_BG 13
+ * STATS_AWB_BFW 14
+ * STATS_AF_BHIST 15
+ * STATS_ALSC_BG 16
+ * STATS_FLICKER_BAYERRS 17
+ * STATS_TMC_BHIST 18
+ * PDAF_0 19
+ * PDAF_1 20
+ * PDAF_2 21
+ * PDAF_3 22
+ * RDI0 23
+ * RDI1 24
+ * RDI2 25
+ * RDI3 26
+ * RDI4 27
+ *
+ * IFE Lite write master client IDs
+ *
+ * RDI0 0
+ * RDI1 1
+ * RDI2 2
+ * RDI3 3
+ * GAMMA 4
+ * STATES_BE 5
+ */
+#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n))
+
+static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
+{
+ struct v4l2_pix_format_mplane *pix =
+ &line->video_out.active_fmt.fmt.pix_mp;
+
+ wm = RDI_WM(wm);
+
+ /* no clock gating at bus input */
+ writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);
+
+ writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
+
+ writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8,
+ vfe->base + VFE_BUS_WM_FRAME_INCR(wm));
+ writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF),
+ vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm));
+ writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE,
+ vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm));
+ writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm));
+
+ /* no dropped frames, one irq per frame */
+ if (!vfe_is_lite(vfe)) {
+ writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm));
+ writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm));
+ }
+
+ writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm));
+ writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm));
+
+ writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm));
+ writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm));
+
+ writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm));
+}
+
+static void vfe_wm_stop(struct vfe_device *vfe, u8 wm)
+{
+ wm = RDI_WM(wm);
+ writel(0, vfe->base + VFE_BUS_WM_CFG(wm));
+}
+
+static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr,
+ struct vfe_line *line)
+{
+ wm = RDI_WM(wm);
+ writel(addr >> 8, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
+
+ dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", wm, addr);
+}
+
+static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
+{
+ int port_id = line_id;
+
+ camss_reg_update(vfe->camss, vfe->id, port_id, false);
+}
+
+static void vfe_reg_update_clear(struct vfe_device *vfe,
+ enum vfe_line_id line_id)
+{
+ int port_id = line_id;
+
+ camss_reg_update(vfe->camss, vfe->id, port_id, true);
+}
+
+static void vfe_addr_update(struct vfe_device *vfe, enum vfe_line_id line_id)
+{
+ int port_id = line_id;
+
+ camss_addr_update(vfe->camss, vfe->id, port_id, false);
+}
+
+static void vfe_addr_update_clear(struct vfe_device *vfe, enum vfe_line_id line_id)
+{
+ int port_id = line_id;
+
+ camss_addr_update(vfe->camss, vfe->id, port_id, true);
+}
+
+static const struct camss_video_ops vfe_video_ops_980 = {
+ .queue_buffer = vfe_queue_buffer_v2,
+ .flush_buffers = vfe_flush_buffers,
+};
+
+static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe)
+{
+ vfe->video_ops = vfe_video_ops_980;
+}
+
+static void vfe_global_reset(struct vfe_device *vfe)
+{
+ vfe_isr_reset_ack(vfe);
+}
+
+static irqreturn_t vfe_isr(int irq, void *dev)
+{
+ /* nop */
+ return IRQ_HANDLED;
+}
+
+static int vfe_halt(struct vfe_device *vfe)
+{
+ /* rely on vfe_disable_output() to stop the VFE */
+ return 0;
+}
+
+const struct vfe_hw_ops vfe_ops_980 = {
+ .addr_update = vfe_addr_update,
+ .addr_update_clear = vfe_addr_update_clear,
+ .global_reset = vfe_global_reset,
+ .hw_version = vfe_hw_version,
+ .isr = vfe_isr,
+ .pm_domain_off = vfe_pm_domain_off,
+ .pm_domain_on = vfe_pm_domain_on,
+ .reg_update = vfe_reg_update,
+ .reg_update_clear = vfe_reg_update_clear,
+ .subdev_init = vfe_subdev_init,
+ .vfe_disable = vfe_disable,
+ .vfe_enable = vfe_enable_v2,
+ .vfe_halt = vfe_halt,
+ .vfe_wm_start = vfe_wm_start,
+ .vfe_wm_stop = vfe_wm_stop,
+ .vfe_buf_done = vfe_buf_done,
+ .vfe_wm_update = vfe_wm_update,
+};
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 7a7d7fbc4e825ba980312e3079ab1ccb2ff0b62b..7a20d9c1a350da183959f9ae024ef6f53cbd0c1c 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -352,6 +352,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
case CAMSS_845:
case CAMSS_8550:
case CAMSS_8650:
+ case CAMSS_8750:
case CAMSS_8775P:
case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
@@ -2017,6 +2018,7 @@ static int vfe_bpl_align_rdi(struct vfe_device *vfe)
case CAMSS_845:
case CAMSS_8550:
case CAMSS_8650:
+ case CAMSS_8750:
case CAMSS_8775P:
case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h
index 0a91440cfe438625f7f1b71b60186491b3d24d5d..c8afa0dc9660d4b8cb0891ad2bbd9fdc92126e48 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.h
+++ b/drivers/media/platform/qcom/camss/camss-vfe.h
@@ -251,6 +251,7 @@ extern const struct vfe_hw_ops vfe_ops_170;
extern const struct vfe_hw_ops vfe_ops_340;
extern const struct vfe_hw_ops vfe_ops_480;
extern const struct vfe_hw_ops vfe_ops_680;
+extern const struct vfe_hw_ops vfe_ops_980;
extern const struct vfe_hw_ops vfe_ops_1080;
extern const struct vfe_hw_ops vfe_ops_gen3;
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 9f7b2948b3aa4d9d401aa5ad76b6133101c95278..d05c0f965f01ce02a91b5f8dbd58a43ad9691019 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -229,6 +229,119 @@ static const struct camss_subdev_resources vfe_res_kaanapali[] = {
},
};
+static const struct camss_subdev_resources vfe_res_sm8750[] = {
+ /* VFE0 - TFE Full */
+ {
+ .clock = { "vfe0_fast_ahb", "vfe0",
+ "cpas_vfe0", "cpas_vfe1", "cpas_vfe2",
+ "camnoc_rt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 360280000, 480000000, 630000000, 716000000,
+ 833000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000 },
+ { 0 } },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 3,
+ .has_pd = true,
+ .pd_name = "ife0",
+ .hw_ops = &vfe_ops_980,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE1 - TFE Full */
+ {
+ .clock = { "vfe1_fast_ahb", "vfe1",
+ "cpas_vfe0", "cpas_vfe1", "cpas_vfe2",
+ "camnoc_rt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 360280000, 480000000, 630000000, 716000000,
+ 833000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000 },
+ { 0 } },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 3,
+ .has_pd = true,
+ .pd_name = "ife1",
+ .hw_ops = &vfe_ops_980,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE2 - TFE Full */
+ {
+ .clock = { "vfe2_fast_ahb", "vfe2",
+ "cpas_vfe0", "cpas_vfe1", "cpas_vfe2",
+ "camnoc_rt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 360280000, 480000000, 630000000, 716000000,
+ 833000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000 },
+ { 0 } },
+ .reg = { "vfe2" },
+ .interrupt = { "vfe2" },
+ .vfe = {
+ .line_num = 3,
+ .has_pd = true,
+ .pd_name = "ife2",
+ .hw_ops = &vfe_ops_980,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE3 - IFE Lite */
+ {
+ .clock = { "vfe_lite_ahb", "vfe_lite", "cpas_vfe_lite",
+ "camnoc_rt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 0 },
+ { 200000000, 300000000, 400000000 },
+ { 0 } },
+ .reg = { "vfe_lite0" },
+ .interrupt = { "vfe_lite0" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_980,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE4 - IFE Lite */
+ {
+ .clock = { "vfe_lite_ahb", "vfe_lite", "cpas_vfe_lite",
+ "camnoc_rt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 0 },
+ { 200000000, 300000000, 400000000 },
+ { 0 } },
+ .reg = { "vfe_lite1" },
+ .interrupt = { "vfe_lite1" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_980,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+};
+
static const struct resources_icc icc_res_kaanapali[] = {
{
.name = "ahb",
@@ -6115,10 +6228,12 @@ static const struct camss_resources sm8750_resources = {
.pd_name = "top",
.pm_clks = { "cpas_fast_ahb", "cpas_ahb", "gcc_axi_hf" },
.csid_res = csid_res_sm8750,
+ .vfe_res = vfe_res_sm8750,
.icc_res = icc_res_sm8750,
.icc_path_num = ARRAY_SIZE(icc_res_sm8750),
.csiphy_num = 6,
.csid_num = ARRAY_SIZE(csid_res_sm8750),
+ .vfe_num = ARRAY_SIZE(vfe_res_sm8750),
};
static const struct camss_resources x1e80100_resources = {
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 12/23] media: qcom: camss: tpg: Add support for v2.3.0 TPG
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add support for the TPG on SM8750, which uses hardware version 2.3.0.
Its test enable and reset go through TPG_CTRL_CMD, so lower the hardware
version gate in the TPG gen1 driver from 2.4.0 to 2.3.0. Older TPGs keep
the TPG_CTRL test enable path.
Reuse the SA8775P TPG resource table for SM8750, since SM8750 uses the same
TPG register and clock names. When a TPG is linked to a CSID 980, route its
output into the CSID RX through the CSI2 TPG mux.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/camss-csid-980.c | 16 ++++++++++++++--
drivers/media/platform/qcom/camss/camss-tpg-gen1.c | 5 +++--
drivers/media/platform/qcom/camss/camss.c | 2 ++
3 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-csid-980.c b/drivers/media/platform/qcom/camss/camss-csid-980.c
index 713db25cd8c65ed7e991bffbb8b19d66c662e708..38cbd67d355d0e7bc683cf5a9e521d082c479d58 100644
--- a/drivers/media/platform/qcom/camss/camss-csid-980.c
+++ b/drivers/media/platform/qcom/camss/camss-csid-980.c
@@ -6,6 +6,7 @@
*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
+#include <linux/bitfield.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
@@ -67,6 +68,8 @@
#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0
#define CSI2_RX_CFG0_DL0_INPUT_SEL 4
#define CSI2_RX_CFG0_PHY_NUM_SEL 20
+#define CSI2_RX_CFG0_TPG_MUX_EN BIT(27)
+#define CSI2_RX_CFG0_TPG_MUX_SEL GENMASK(29, 28)
#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1
#define CSID_CSI2_RX_CFG1 (csid_is_lite(csid) ? 0x204 : 0x404)
#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0)
@@ -195,12 +198,21 @@ static void __csid_reg_update_clear(struct csid_device *csid, int port_id)
static void __csid_configure_rx(struct csid_device *csid,
struct csid_phy_config *phy)
{
+ struct camss *camss = csid->camss;
int val;
val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
- val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX)
- << CSI2_RX_CFG0_PHY_NUM_SEL;
+
+ if (camss->tpg && csid->tpg_linked &&
+ camss->tpg[phy->csiphy_id].testgen.mode != TPG_PAYLOAD_MODE_DISABLED) {
+ val |= FIELD_PREP(CSI2_RX_CFG0_TPG_MUX_SEL, phy->csiphy_id + 1);
+ val |= CSI2_RX_CFG0_TPG_MUX_EN;
+ } else {
+ val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX)
+ << CSI2_RX_CFG0_PHY_NUM_SEL;
+ }
+
writel(val, csid->base + CSID_CSI2_RX_CFG0);
val = CSI2_RX_CFG1_ECC_CORRECTION_EN;
diff --git a/drivers/media/platform/qcom/camss/camss-tpg-gen1.c b/drivers/media/platform/qcom/camss/camss-tpg-gen1.c
index cabbb2638cf38ddfd333d2c2c6a04984f223d66b..1972423ba41d9d30f5b00a08c1b4a07ed2a0e51f 100644
--- a/drivers/media/platform/qcom/camss/camss-tpg-gen1.c
+++ b/drivers/media/platform/qcom/camss/camss-tpg-gen1.c
@@ -22,6 +22,7 @@
#define TPG_HW_VER_2_0_0 TPG_HW_VER(2, 0, 0)
#define TPG_HW_VER_2_1_0 TPG_HW_VER(2, 1, 0)
+#define TPG_HW_VER_2_3_0 TPG_HW_VER(2, 3, 0)
#define TPG_HW_VER_2_4_0 TPG_HW_VER(2, 4, 0)
#define TPG_HW_STATUS 0x4
@@ -170,7 +171,7 @@ static int tpg_stream_on(struct tpg_device *tpg)
val = FIELD_PREP(TPG_CTRL_NUM_ACTIVE_LANES, lane_cnt - 1) |
FIELD_PREP(TPG_CTRL_NUM_ACTIVE_VC, last_vc);
- if (tpg->hw_version < TPG_HW_VER_2_4_0) {
+ if (tpg->hw_version < TPG_HW_VER_2_3_0) {
val |= FIELD_PREP(TPG_CTRL_TEST_EN, 1);
writel(val, tpg->base + TPG_CTRL);
} else {
@@ -183,7 +184,7 @@ static int tpg_stream_on(struct tpg_device *tpg)
static int tpg_reset(struct tpg_device *tpg)
{
- if (tpg->hw_version < TPG_HW_VER_2_4_0)
+ if (tpg->hw_version < TPG_HW_VER_2_3_0)
writel(0, tpg->base + TPG_CTRL);
writel(TPG_CTRL_CMD_HW_RESET, tpg->base + TPG_CTRL_CMD);
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index d05c0f965f01ce02a91b5f8dbd58a43ad9691019..de22ff74c7acfe912afea31dabc1ecc250b022b0 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -6230,8 +6230,10 @@ static const struct camss_resources sm8750_resources = {
.csid_res = csid_res_sm8750,
.vfe_res = vfe_res_sm8750,
.icc_res = icc_res_sm8750,
+ .tpg_res = tpg_res_8775p,
.icc_path_num = ARRAY_SIZE(icc_res_sm8750),
.csiphy_num = 6,
+ .tpg_num = ARRAY_SIZE(tpg_res_8775p),
.csid_num = ARRAY_SIZE(csid_res_sm8750),
.vfe_num = ARRAY_SIZE(vfe_res_sm8750),
};
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 12/23] media: qcom: camss: tpg: Add support for v2.3.0 TPG
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add support for the TPG on SM8750, which uses hardware version 2.3.0.
Its test enable and reset go through TPG_CTRL_CMD, so lower the hardware
version gate in the TPG gen1 driver from 2.4.0 to 2.3.0. Older TPGs keep
the TPG_CTRL test enable path.
Reuse the SA8775P TPG resource table for SM8750, since SM8750 uses the same
TPG register and clock names. When a TPG is linked to a CSID 980, route its
output into the CSID RX through the CSI2 TPG mux.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/camss-csid-980.c | 16 ++++++++++++++--
drivers/media/platform/qcom/camss/camss-tpg-gen1.c | 5 +++--
drivers/media/platform/qcom/camss/camss.c | 2 ++
3 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-csid-980.c b/drivers/media/platform/qcom/camss/camss-csid-980.c
index 713db25cd8c65ed7e991bffbb8b19d66c662e708..38cbd67d355d0e7bc683cf5a9e521d082c479d58 100644
--- a/drivers/media/platform/qcom/camss/camss-csid-980.c
+++ b/drivers/media/platform/qcom/camss/camss-csid-980.c
@@ -6,6 +6,7 @@
*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
+#include <linux/bitfield.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
@@ -67,6 +68,8 @@
#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0
#define CSI2_RX_CFG0_DL0_INPUT_SEL 4
#define CSI2_RX_CFG0_PHY_NUM_SEL 20
+#define CSI2_RX_CFG0_TPG_MUX_EN BIT(27)
+#define CSI2_RX_CFG0_TPG_MUX_SEL GENMASK(29, 28)
#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1
#define CSID_CSI2_RX_CFG1 (csid_is_lite(csid) ? 0x204 : 0x404)
#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0)
@@ -195,12 +198,21 @@ static void __csid_reg_update_clear(struct csid_device *csid, int port_id)
static void __csid_configure_rx(struct csid_device *csid,
struct csid_phy_config *phy)
{
+ struct camss *camss = csid->camss;
int val;
val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
- val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX)
- << CSI2_RX_CFG0_PHY_NUM_SEL;
+
+ if (camss->tpg && csid->tpg_linked &&
+ camss->tpg[phy->csiphy_id].testgen.mode != TPG_PAYLOAD_MODE_DISABLED) {
+ val |= FIELD_PREP(CSI2_RX_CFG0_TPG_MUX_SEL, phy->csiphy_id + 1);
+ val |= CSI2_RX_CFG0_TPG_MUX_EN;
+ } else {
+ val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX)
+ << CSI2_RX_CFG0_PHY_NUM_SEL;
+ }
+
writel(val, csid->base + CSID_CSI2_RX_CFG0);
val = CSI2_RX_CFG1_ECC_CORRECTION_EN;
diff --git a/drivers/media/platform/qcom/camss/camss-tpg-gen1.c b/drivers/media/platform/qcom/camss/camss-tpg-gen1.c
index cabbb2638cf38ddfd333d2c2c6a04984f223d66b..1972423ba41d9d30f5b00a08c1b4a07ed2a0e51f 100644
--- a/drivers/media/platform/qcom/camss/camss-tpg-gen1.c
+++ b/drivers/media/platform/qcom/camss/camss-tpg-gen1.c
@@ -22,6 +22,7 @@
#define TPG_HW_VER_2_0_0 TPG_HW_VER(2, 0, 0)
#define TPG_HW_VER_2_1_0 TPG_HW_VER(2, 1, 0)
+#define TPG_HW_VER_2_3_0 TPG_HW_VER(2, 3, 0)
#define TPG_HW_VER_2_4_0 TPG_HW_VER(2, 4, 0)
#define TPG_HW_STATUS 0x4
@@ -170,7 +171,7 @@ static int tpg_stream_on(struct tpg_device *tpg)
val = FIELD_PREP(TPG_CTRL_NUM_ACTIVE_LANES, lane_cnt - 1) |
FIELD_PREP(TPG_CTRL_NUM_ACTIVE_VC, last_vc);
- if (tpg->hw_version < TPG_HW_VER_2_4_0) {
+ if (tpg->hw_version < TPG_HW_VER_2_3_0) {
val |= FIELD_PREP(TPG_CTRL_TEST_EN, 1);
writel(val, tpg->base + TPG_CTRL);
} else {
@@ -183,7 +184,7 @@ static int tpg_stream_on(struct tpg_device *tpg)
static int tpg_reset(struct tpg_device *tpg)
{
- if (tpg->hw_version < TPG_HW_VER_2_4_0)
+ if (tpg->hw_version < TPG_HW_VER_2_3_0)
writel(0, tpg->base + TPG_CTRL);
writel(TPG_CTRL_CMD_HW_RESET, tpg->base + TPG_CTRL_CMD);
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index d05c0f965f01ce02a91b5f8dbd58a43ad9691019..de22ff74c7acfe912afea31dabc1ecc250b022b0 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -6230,8 +6230,10 @@ static const struct camss_resources sm8750_resources = {
.csid_res = csid_res_sm8750,
.vfe_res = vfe_res_sm8750,
.icc_res = icc_res_sm8750,
+ .tpg_res = tpg_res_8775p,
.icc_path_num = ARRAY_SIZE(icc_res_sm8750),
.csiphy_num = 6,
+ .tpg_num = ARRAY_SIZE(tpg_res_8775p),
.csid_num = ARRAY_SIZE(csid_res_sm8750),
.vfe_num = ARRAY_SIZE(vfe_res_sm8750),
};
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 13/23] media: qcom: camss: Add Eliza compatible
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
Add CAMSS_ELIZA enum, Eliza compatible and Eliza CAMSS driver private
data. Eliza has 3 CSID + 1 CSID Lite, 3 VFE + 1 VFE Lite and 2 TPG
instances. CSIPHY resources are not listed because the PHYs are probed
standalone.
Eliza's CSID 970 and VFE 970 are register compatible with the SM8750
CSID 980 and VFE 980, so reuse the SM8750 CSID, VFE and TPG resources.
The only difference is that the VFE RDI write master client IDs start at
20 instead of 23.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/camss-vfe-980.c | 5 ++++-
drivers/media/platform/qcom/camss/camss-vfe.c | 2 ++
drivers/media/platform/qcom/camss/camss.c | 16 ++++++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
4 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/qcom/camss/camss-vfe-980.c b/drivers/media/platform/qcom/camss/camss-vfe-980.c
index 47f6c18190acfbf3c6ab49186fc73fde6a0ac799..ecdfaa4d528aaacd97aae6335c6488de09cf6e12 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe-980.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe-980.c
@@ -83,8 +83,11 @@
* RDI3 3
* GAMMA 4
* STATES_BE 5
+ *
+ * On Eliza (VFE 970) the RDI0..3 write master client IDs are 20..23.
*/
-#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n))
+#define RDI_WM_BASE(vfe) ((vfe)->camss->res->version == CAMSS_ELIZA ? 0x14 : 0x17)
+#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : RDI_WM_BASE(vfe)) + (n))
static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
{
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 7a20d9c1a350da183959f9ae024ef6f53cbd0c1c..3992516d672ebd43184c2a82e238581bf693cbe2 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -354,6 +354,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
case CAMSS_8650:
case CAMSS_8750:
case CAMSS_8775P:
+ case CAMSS_ELIZA:
case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
switch (sink_code) {
@@ -2020,6 +2021,7 @@ static int vfe_bpl_align_rdi(struct vfe_device *vfe)
case CAMSS_8650:
case CAMSS_8750:
case CAMSS_8775P:
+ case CAMSS_ELIZA:
case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
ret = 16;
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index de22ff74c7acfe912afea31dabc1ecc250b022b0..a6a0313eeabca5f2c8f8c7b569030ea5b0a5a848 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -6238,6 +6238,21 @@ static const struct camss_resources sm8750_resources = {
.vfe_num = ARRAY_SIZE(vfe_res_sm8750),
};
+static const struct camss_resources eliza_resources = {
+ .version = CAMSS_ELIZA,
+ .pd_name = "top",
+ .pm_clks = { "cpas_fast_ahb", "cpas_ahb", "gcc_axi_hf" },
+ .csid_res = csid_res_sm8750,
+ .vfe_res = vfe_res_sm8750,
+ .icc_res = icc_res_sm8750,
+ .tpg_res = tpg_res_8775p,
+ .icc_path_num = ARRAY_SIZE(icc_res_sm8750),
+ .csiphy_num = 4,
+ .tpg_num = 2,
+ .csid_num = 4,
+ .vfe_num = 4,
+};
+
static const struct camss_resources x1e80100_resources = {
.version = CAMSS_X1E80100,
.pd_name = "top",
@@ -6255,6 +6270,7 @@ static const struct camss_resources x1e80100_resources = {
};
static const struct of_device_id camss_dt_match[] = {
+ { .compatible = "qcom,eliza-camss", .data = &eliza_resources },
{ .compatible = "qcom,kaanapali-camss", .data = &kaanapali_resources },
{ .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
{ .compatible = "qcom,msm8939-camss", .data = &msm8939_resources },
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index 3da970d251e728d339d13fdaef23ea5dfa46dd3b..0f909a4a409b7d1476966aecfaebb4cd60871974 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -97,6 +97,7 @@ enum camss_version {
CAMSS_8650,
CAMSS_8750,
CAMSS_8775P,
+ CAMSS_ELIZA,
CAMSS_KAANAPALI,
CAMSS_X1E80100,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 13/23] media: qcom: camss: Add Eliza compatible
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
Add CAMSS_ELIZA enum, Eliza compatible and Eliza CAMSS driver private
data. Eliza has 3 CSID + 1 CSID Lite, 3 VFE + 1 VFE Lite and 2 TPG
instances. CSIPHY resources are not listed because the PHYs are probed
standalone.
Eliza's CSID 970 and VFE 970 are register compatible with the SM8750
CSID 980 and VFE 980, so reuse the SM8750 CSID, VFE and TPG resources.
The only difference is that the VFE RDI write master client IDs start at
20 instead of 23.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/camss-vfe-980.c | 5 ++++-
drivers/media/platform/qcom/camss/camss-vfe.c | 2 ++
drivers/media/platform/qcom/camss/camss.c | 16 ++++++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
4 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/qcom/camss/camss-vfe-980.c b/drivers/media/platform/qcom/camss/camss-vfe-980.c
index 47f6c18190acfbf3c6ab49186fc73fde6a0ac799..ecdfaa4d528aaacd97aae6335c6488de09cf6e12 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe-980.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe-980.c
@@ -83,8 +83,11 @@
* RDI3 3
* GAMMA 4
* STATES_BE 5
+ *
+ * On Eliza (VFE 970) the RDI0..3 write master client IDs are 20..23.
*/
-#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n))
+#define RDI_WM_BASE(vfe) ((vfe)->camss->res->version == CAMSS_ELIZA ? 0x14 : 0x17)
+#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : RDI_WM_BASE(vfe)) + (n))
static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
{
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 7a20d9c1a350da183959f9ae024ef6f53cbd0c1c..3992516d672ebd43184c2a82e238581bf693cbe2 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -354,6 +354,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
case CAMSS_8650:
case CAMSS_8750:
case CAMSS_8775P:
+ case CAMSS_ELIZA:
case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
switch (sink_code) {
@@ -2020,6 +2021,7 @@ static int vfe_bpl_align_rdi(struct vfe_device *vfe)
case CAMSS_8650:
case CAMSS_8750:
case CAMSS_8775P:
+ case CAMSS_ELIZA:
case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
ret = 16;
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index de22ff74c7acfe912afea31dabc1ecc250b022b0..a6a0313eeabca5f2c8f8c7b569030ea5b0a5a848 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -6238,6 +6238,21 @@ static const struct camss_resources sm8750_resources = {
.vfe_num = ARRAY_SIZE(vfe_res_sm8750),
};
+static const struct camss_resources eliza_resources = {
+ .version = CAMSS_ELIZA,
+ .pd_name = "top",
+ .pm_clks = { "cpas_fast_ahb", "cpas_ahb", "gcc_axi_hf" },
+ .csid_res = csid_res_sm8750,
+ .vfe_res = vfe_res_sm8750,
+ .icc_res = icc_res_sm8750,
+ .tpg_res = tpg_res_8775p,
+ .icc_path_num = ARRAY_SIZE(icc_res_sm8750),
+ .csiphy_num = 4,
+ .tpg_num = 2,
+ .csid_num = 4,
+ .vfe_num = 4,
+};
+
static const struct camss_resources x1e80100_resources = {
.version = CAMSS_X1E80100,
.pd_name = "top",
@@ -6255,6 +6270,7 @@ static const struct camss_resources x1e80100_resources = {
};
static const struct of_device_id camss_dt_match[] = {
+ { .compatible = "qcom,eliza-camss", .data = &eliza_resources },
{ .compatible = "qcom,kaanapali-camss", .data = &kaanapali_resources },
{ .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
{ .compatible = "qcom,msm8939-camss", .data = &msm8939_resources },
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index 3da970d251e728d339d13fdaef23ea5dfa46dd3b..0f909a4a409b7d1476966aecfaebb4cd60871974 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -97,6 +97,7 @@ enum camss_version {
CAMSS_8650,
CAMSS_8750,
CAMSS_8775P,
+ CAMSS_ELIZA,
CAMSS_KAANAPALI,
CAMSS_X1E80100,
};
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 14/23] arm64: dts: qcom: sm8750: Add CAMSS and CSIPHY block definitions
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Describe the CAMSS and CSIPHY blocks on SM8750 so that camera pipelines
can be enabled by board device trees.
The camera subsystem contains:
- 6 x CSIPHY (CSI Physical Layer)
- 3 x TPG (Test Pattern Generator)
- 3 x CSID (CSI Decoder)
- 2 x CSID Lite
- 3 x VFE (Video Front End), 5 RDI per VFE
- 2 x VFE Lite, 4 RDI per VFE Lite
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8750.dtsi | 397 +++++++++++++++++++++++++++++++++++
1 file changed, 397 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 401f9eceb38cb1a4a27f95bce08126e73ffe501b..e91f7f8377c0c37cd54e5e91585ef58a4f8a65a0 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -20,6 +20,7 @@
#include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/soc/qcom,gpr.h>
@@ -3349,6 +3350,380 @@ videocc: clock-controller@aaf0000 {
#power-domain-cells = <1>;
};
+ camss: isp@ac04000 {
+ compatible = "qcom,sm8750-camss";
+
+ reg = <0x0 0x0ac04000 0x0 0x1000>,
+ <0x0 0x0ad27000 0x0 0x2b00>,
+ <0x0 0x0ad2a000 0x0 0x2b00>,
+ <0x0 0x0ad2d000 0x0 0x2b00>,
+ <0x0 0x0ad6d000 0x0 0xa00>,
+ <0x0 0x0ad72000 0x0 0xa00>,
+ <0x0 0x0ad8b000 0x0 0x400>,
+ <0x0 0x0ad8c000 0x0 0x400>,
+ <0x0 0x0ad8d000 0x0 0x400>,
+ <0x0 0x0ac86000 0x0 0x10000>,
+ <0x0 0x0ac96000 0x0 0x10000>,
+ <0x0 0x0aca6000 0x0 0x10000>,
+ <0x0 0x0ad6e000 0x0 0x3000>,
+ <0x0 0x0ad73000 0x0 0x3000>;
+ reg-names = "top",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "tpg0",
+ "tpg1",
+ "tpg2",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
+ <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>;
+ clock-names = "camnoc_rt_axi",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe2",
+ "cpas_vfe_lite",
+ "csid",
+ "csiphy_rx",
+ "gcc_axi_hf",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "qdss_debug_xo";
+
+ interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc";
+
+ iommus = <&apps_smmu 0x1c00 0x00>;
+
+ power-domains = <&camcc CAM_CC_TFE_0_GDSC>,
+ <&camcc CAM_CC_TFE_1_GDSC>,
+ <&camcc CAM_CC_TFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "ife2",
+ "top";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camss_csiphy0_in_port: port@0 {
+ reg = <0>;
+ };
+
+ camss_csiphy1_in_port: port@1 {
+ reg = <1>;
+ };
+
+ camss_csiphy2_in_port: port@2 {
+ reg = <2>;
+ };
+
+ camss_csiphy3_in_port: port@3 {
+ reg = <3>;
+ };
+
+ camss_csiphy4_in_port: port@4 {
+ reg = <4>;
+ };
+
+ camss_csiphy5_in_port: port@5 {
+ reg = <5>;
+ };
+ };
+ };
+
+ csiphy0: phy@ada9000 {
+ compatible = "qcom,sm8750-csi2-phy";
+ reg = <0x0 0x0ada9000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy0_in_port: port@0 {
+ reg = <0>;
+ };
+
+ csiphy0_out_port: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ csiphy1: phy@adab000 {
+ compatible = "qcom,sm8750-csi2-phy";
+ reg = <0x0 0x0adab000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy1_in_port: port@0 {
+ reg = <0>;
+ };
+
+ csiphy1_out_port: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ csiphy2: phy@adad000 {
+ compatible = "qcom,sm8750-csi2-phy";
+ reg = <0x0 0x0adad000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy2_in_port: port@0 {
+ reg = <0>;
+ };
+
+ csiphy2_out_port: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ csiphy3: phy@adaf000 {
+ compatible = "qcom,sm8750-csi2-phy";
+ reg = <0x0 0x0adaf000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy3_in_port: port@0 {
+ reg = <0>;
+ };
+
+ csiphy3_out_port: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ csiphy4: phy@adb1000 {
+ compatible = "qcom,sm8750-csi2-phy";
+ reg = <0x0 0x0adb1000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy4_in_port: port@0 {
+ reg = <0>;
+ };
+
+ csiphy4_out_port: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ csiphy5: phy@adb3000 {
+ compatible = "qcom,sm8750-csi2-phy";
+ reg = <0x0 0x0adb3000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY5_CLK>,
+ <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy5_in_port: port@0 {
+ reg = <0>;
+ };
+
+ csiphy5_out_port: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
mdss: display-subsystem@ae00000 {
compatible = "qcom,sm8750-mdss";
reg = <0x0 0x0ae00000 0x0 0x1000>;
@@ -6535,6 +6910,28 @@ compute-cb@14 {
};
};
+ csiphy_mxc_opp_table: opp-table-mxc {
+ compatible = "operating-points-v2";
+
+ opp-266666667 {
+ opp-hz = /bits/ 64 <266666667>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>,
+ <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+ };
+
thermal-zones {
aoss0-thermal {
thermal-sensors = <&tsens0 0>;
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 14/23] arm64: dts: qcom: sm8750: Add CAMSS and CSIPHY block definitions
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Describe the CAMSS and CSIPHY blocks on SM8750 so that camera pipelines
can be enabled by board device trees.
The camera subsystem contains:
- 6 x CSIPHY (CSI Physical Layer)
- 3 x TPG (Test Pattern Generator)
- 3 x CSID (CSI Decoder)
- 2 x CSID Lite
- 3 x VFE (Video Front End), 5 RDI per VFE
- 2 x VFE Lite, 4 RDI per VFE Lite
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8750.dtsi | 397 +++++++++++++++++++++++++++++++++++
1 file changed, 397 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 401f9eceb38cb1a4a27f95bce08126e73ffe501b..e91f7f8377c0c37cd54e5e91585ef58a4f8a65a0 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -20,6 +20,7 @@
#include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/soc/qcom,gpr.h>
@@ -3349,6 +3350,380 @@ videocc: clock-controller@aaf0000 {
#power-domain-cells = <1>;
};
+ camss: isp@ac04000 {
+ compatible = "qcom,sm8750-camss";
+
+ reg = <0x0 0x0ac04000 0x0 0x1000>,
+ <0x0 0x0ad27000 0x0 0x2b00>,
+ <0x0 0x0ad2a000 0x0 0x2b00>,
+ <0x0 0x0ad2d000 0x0 0x2b00>,
+ <0x0 0x0ad6d000 0x0 0xa00>,
+ <0x0 0x0ad72000 0x0 0xa00>,
+ <0x0 0x0ad8b000 0x0 0x400>,
+ <0x0 0x0ad8c000 0x0 0x400>,
+ <0x0 0x0ad8d000 0x0 0x400>,
+ <0x0 0x0ac86000 0x0 0x10000>,
+ <0x0 0x0ac96000 0x0 0x10000>,
+ <0x0 0x0aca6000 0x0 0x10000>,
+ <0x0 0x0ad6e000 0x0 0x3000>,
+ <0x0 0x0ad73000 0x0 0x3000>;
+ reg-names = "top",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "tpg0",
+ "tpg1",
+ "tpg2",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
+ <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>;
+ clock-names = "camnoc_rt_axi",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe2",
+ "cpas_vfe_lite",
+ "csid",
+ "csiphy_rx",
+ "gcc_axi_hf",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "qdss_debug_xo";
+
+ interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc";
+
+ iommus = <&apps_smmu 0x1c00 0x00>;
+
+ power-domains = <&camcc CAM_CC_TFE_0_GDSC>,
+ <&camcc CAM_CC_TFE_1_GDSC>,
+ <&camcc CAM_CC_TFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "ife2",
+ "top";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camss_csiphy0_in_port: port@0 {
+ reg = <0>;
+ };
+
+ camss_csiphy1_in_port: port@1 {
+ reg = <1>;
+ };
+
+ camss_csiphy2_in_port: port@2 {
+ reg = <2>;
+ };
+
+ camss_csiphy3_in_port: port@3 {
+ reg = <3>;
+ };
+
+ camss_csiphy4_in_port: port@4 {
+ reg = <4>;
+ };
+
+ camss_csiphy5_in_port: port@5 {
+ reg = <5>;
+ };
+ };
+ };
+
+ csiphy0: phy@ada9000 {
+ compatible = "qcom,sm8750-csi2-phy";
+ reg = <0x0 0x0ada9000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy0_in_port: port@0 {
+ reg = <0>;
+ };
+
+ csiphy0_out_port: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ csiphy1: phy@adab000 {
+ compatible = "qcom,sm8750-csi2-phy";
+ reg = <0x0 0x0adab000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy1_in_port: port@0 {
+ reg = <0>;
+ };
+
+ csiphy1_out_port: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ csiphy2: phy@adad000 {
+ compatible = "qcom,sm8750-csi2-phy";
+ reg = <0x0 0x0adad000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy2_in_port: port@0 {
+ reg = <0>;
+ };
+
+ csiphy2_out_port: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ csiphy3: phy@adaf000 {
+ compatible = "qcom,sm8750-csi2-phy";
+ reg = <0x0 0x0adaf000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy3_in_port: port@0 {
+ reg = <0>;
+ };
+
+ csiphy3_out_port: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ csiphy4: phy@adb1000 {
+ compatible = "qcom,sm8750-csi2-phy";
+ reg = <0x0 0x0adb1000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy4_in_port: port@0 {
+ reg = <0>;
+ };
+
+ csiphy4_out_port: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ csiphy5: phy@adb3000 {
+ compatible = "qcom,sm8750-csi2-phy";
+ reg = <0x0 0x0adb3000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY5_CLK>,
+ <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy5_in_port: port@0 {
+ reg = <0>;
+ };
+
+ csiphy5_out_port: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
mdss: display-subsystem@ae00000 {
compatible = "qcom,sm8750-mdss";
reg = <0x0 0x0ae00000 0x0 0x1000>;
@@ -6535,6 +6910,28 @@ compute-cb@14 {
};
};
+ csiphy_mxc_opp_table: opp-table-mxc {
+ compatible = "operating-points-v2";
+
+ opp-266666667 {
+ opp-hz = /bits/ 64 <266666667>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>,
+ <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+ };
+
thermal-zones {
aoss0-thermal {
thermal-sensors = <&tsens0 0>;
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 15/23] arm64: dts: qcom: sm8750: Add CCI definitions
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Qualcomm SM8750 SoC has three Camera Control Interface (CCI). Each
controller contains two I2C hosts.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8750.dtsi | 282 +++++++++++++++++++++++++++++++++++
1 file changed, 282 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index e91f7f8377c0c37cd54e5e91585ef58a4f8a65a0..b1fe1c2f5ae9c5b6107729fbdf31c2577ee3ebd3 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -3496,6 +3496,96 @@ camss_csiphy5_in_port: port@5 {
};
};
+ cci0: cci@ac7b000 {
+ compatible = "qcom,sm8750-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0ac7b000 0x0 0x1000>;
+ interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK>;
+ clock-names = "ahb", "cci";
+ pinctrl-0 = <&cci0_0_default &cci0_1_default>;
+ pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@ac7c000 {
+ compatible = "qcom,sm8750-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0ac7c000 0x0 0x1000>;
+ interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK>;
+ clock-names = "ahb", "cci";
+ pinctrl-0 = <&cci1_0_default &cci1_1_default>;
+ pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci2: cci@ac7d000 {
+ compatible = "qcom,sm8750-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0ac7d000 0x0 0x1000>;
+ interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CCI_2_CLK>;
+ clock-names = "ahb", "cci";
+ pinctrl-0 = <&cci2_0_default &cci2_1_default>;
+ pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci2_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci2_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
csiphy0: phy@ada9000 {
compatible = "qcom,sm8750-csi2-phy";
reg = <0x0 0x0ada9000 0x0 0x2000>;
@@ -4296,6 +4386,198 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 216>;
wakeup-parent = <&pdc>;
+ cci0_0_default: cci0-0-default-state {
+ sda-pins {
+ pins = "gpio113";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio114";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci0_0_sleep: cci0-0-sleep-state {
+ sda-pins {
+ pins = "gpio113";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio114";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci0_1_default: cci0-1-default-state {
+ sda-pins {
+ pins = "gpio115";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio116";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci0_1_sleep: cci0-1-sleep-state {
+ sda-pins {
+ pins = "gpio115";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio116";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_0_default: cci1-0-default-state {
+ sda-pins {
+ pins = "gpio117";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio118";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci1_0_sleep: cci1-0-sleep-state {
+ sda-pins {
+ pins = "gpio117";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio118";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_1_default: cci1-1-default-state {
+ sda-pins {
+ pins = "gpio111";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio164";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci1_1_sleep: cci1-1-sleep-state {
+ sda-pins {
+ pins = "gpio111";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio164";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci2_0_default: cci2-0-default-state {
+ sda-pins {
+ pins = "gpio112";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio153";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci2_0_sleep: cci2-0-sleep-state {
+ sda-pins {
+ pins = "gpio112";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio153";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci2_1_default: cci2-1-default-state {
+ sda-pins {
+ pins = "gpio119";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio120";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci2_1_sleep: cci2-1-sleep-state {
+ sda-pins {
+ pins = "gpio119";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio120";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
hub_i2c0_data_clk: hub-i2c0-data-clk-state {
/* SDA, SCL */
pins = "gpio64", "gpio65";
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 15/23] arm64: dts: qcom: sm8750: Add CCI definitions
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Qualcomm SM8750 SoC has three Camera Control Interface (CCI). Each
controller contains two I2C hosts.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8750.dtsi | 282 +++++++++++++++++++++++++++++++++++
1 file changed, 282 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index e91f7f8377c0c37cd54e5e91585ef58a4f8a65a0..b1fe1c2f5ae9c5b6107729fbdf31c2577ee3ebd3 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -3496,6 +3496,96 @@ camss_csiphy5_in_port: port@5 {
};
};
+ cci0: cci@ac7b000 {
+ compatible = "qcom,sm8750-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0ac7b000 0x0 0x1000>;
+ interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK>;
+ clock-names = "ahb", "cci";
+ pinctrl-0 = <&cci0_0_default &cci0_1_default>;
+ pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@ac7c000 {
+ compatible = "qcom,sm8750-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0ac7c000 0x0 0x1000>;
+ interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK>;
+ clock-names = "ahb", "cci";
+ pinctrl-0 = <&cci1_0_default &cci1_1_default>;
+ pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci2: cci@ac7d000 {
+ compatible = "qcom,sm8750-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0ac7d000 0x0 0x1000>;
+ interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CCI_2_CLK>;
+ clock-names = "ahb", "cci";
+ pinctrl-0 = <&cci2_0_default &cci2_1_default>;
+ pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci2_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci2_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
csiphy0: phy@ada9000 {
compatible = "qcom,sm8750-csi2-phy";
reg = <0x0 0x0ada9000 0x0 0x2000>;
@@ -4296,6 +4386,198 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 216>;
wakeup-parent = <&pdc>;
+ cci0_0_default: cci0-0-default-state {
+ sda-pins {
+ pins = "gpio113";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio114";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci0_0_sleep: cci0-0-sleep-state {
+ sda-pins {
+ pins = "gpio113";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio114";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci0_1_default: cci0-1-default-state {
+ sda-pins {
+ pins = "gpio115";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio116";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci0_1_sleep: cci0-1-sleep-state {
+ sda-pins {
+ pins = "gpio115";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio116";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_0_default: cci1-0-default-state {
+ sda-pins {
+ pins = "gpio117";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio118";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci1_0_sleep: cci1-0-sleep-state {
+ sda-pins {
+ pins = "gpio117";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio118";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_1_default: cci1-1-default-state {
+ sda-pins {
+ pins = "gpio111";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio164";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci1_1_sleep: cci1-1-sleep-state {
+ sda-pins {
+ pins = "gpio111";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio164";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci2_0_default: cci2-0-default-state {
+ sda-pins {
+ pins = "gpio112";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio153";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci2_0_sleep: cci2-0-sleep-state {
+ sda-pins {
+ pins = "gpio112";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio153";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci2_1_default: cci2-1-default-state {
+ sda-pins {
+ pins = "gpio119";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio120";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci2_1_sleep: cci2-1-sleep-state {
+ sda-pins {
+ pins = "gpio119";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio120";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
hub_i2c0_data_clk: hub-i2c0-data-clk-state {
/* SDA, SCL */
pins = "gpio64", "gpio65";
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 16/23] arm64: dts: qcom: sm8750: Add camera MCLK pinctrl
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu, Konrad Dybcio
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Define pinctrl definitions to enable camera master clocks on SM8750.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8750.dtsi | 56 ++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index b1fe1c2f5ae9c5b6107729fbdf31c2577ee3ebd3..522d2c0c374cba48de1420be5357db65864bd3cc 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -4386,6 +4386,62 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 216>;
wakeup-parent = <&pdc>;
+ cam_mclk0_default: cam-mclk0-default-state {
+ pins = "gpio89";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk1_default: cam-mclk1-default-state {
+ pins = "gpio90";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk2_default: cam-mclk2-default-state {
+ pins = "gpio91";
+ function = "cam_aon_mclk2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk3_default: cam-mclk3-default-state {
+ pins = "gpio92";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk4_default: cam-mclk4-default-state {
+ pins = "gpio93";
+ function = "cam_aon_mclk4";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk5_default: cam-mclk5-default-state {
+ pins = "gpio94";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk6_default: cam-mclk6-default-state {
+ pins = "gpio95";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk7_default: cam-mclk7-default-state {
+ pins = "gpio96";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
cci0_0_default: cci0-0-default-state {
sda-pins {
pins = "gpio113";
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 16/23] arm64: dts: qcom: sm8750: Add camera MCLK pinctrl
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu, Konrad Dybcio
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Define pinctrl definitions to enable camera master clocks on SM8750.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8750.dtsi | 56 ++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index b1fe1c2f5ae9c5b6107729fbdf31c2577ee3ebd3..522d2c0c374cba48de1420be5357db65864bd3cc 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -4386,6 +4386,62 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 216>;
wakeup-parent = <&pdc>;
+ cam_mclk0_default: cam-mclk0-default-state {
+ pins = "gpio89";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk1_default: cam-mclk1-default-state {
+ pins = "gpio90";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk2_default: cam-mclk2-default-state {
+ pins = "gpio91";
+ function = "cam_aon_mclk2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk3_default: cam-mclk3-default-state {
+ pins = "gpio92";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk4_default: cam-mclk4-default-state {
+ pins = "gpio93";
+ function = "cam_aon_mclk4";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk5_default: cam-mclk5-default-state {
+ pins = "gpio94";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk6_default: cam-mclk6-default-state {
+ pins = "gpio95";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk7_default: cam-mclk7-default-state {
+ pins = "gpio96";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
cci0_0_default: cci0-0-default-state {
sda-pins {
pins = "gpio113";
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 17/23] arm64: dts: qcom: sm8750-qrd: Enable S5KJN1 camera sensor
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
Enable CAMSS, CCI1 and CSIPHY3 on the SM8750 QRD board. The S5KJN1
camera sensor is connected to CCI1 I2C bus 0, uses MCLK3 at 24 MHz and
connects to CSIPHY3 over a 4-lane D-PHY link.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 72 +++++++++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
index 75927e1f7b9ab0316781c64dbcc82d3394c414f6..c92a1f3c47bd5cbae26854614682c3bc7daa0398 100644
--- a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/media/video-interfaces.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sm8750.dtsi"
#include "pm8010.dtsi"
@@ -858,6 +859,70 @@ vreg_l7n_3p3: ldo7 {
};
};
+&camss {
+ status = "okay";
+};
+
+&camss_csiphy3_in_port {
+ camss_csiphy3_inep: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&csiphy3_out_ep>;
+ };
+};
+
+&cci1 {
+ status = "okay";
+};
+
+&cci1_i2c0 {
+ camera@56 {
+ compatible = "samsung,s5kjn1";
+ reg = <0x56>;
+
+ reset-gpios = <&tlmm 109 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&cam_mclk3_default &cam3_reset_default>;
+ pinctrl-names = "default";
+
+ clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>;
+ assigned-clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>;
+ assigned-clock-rates = <24000000>;
+
+ vdda-supply = <&vreg_l4m_2p8>;
+ vddd-supply = <&vreg_l2m_1p056>;
+ vddio-supply = <&vreg_l5m_1p8>;
+
+ port {
+ s5kjn1_out_ep: endpoint {
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <700000000>;
+ remote-endpoint = <&csiphy3_in_ep>;
+ };
+ };
+ };
+};
+
+&csiphy3 {
+ vdda-0p9-supply = <&vreg_l1f_0p88>;
+ vdda-1p2-supply = <&vreg_l3g_1p2>;
+
+ status = "okay";
+};
+
+&csiphy3_in_port {
+ csiphy3_in_ep: endpoint {
+ bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&s5kjn1_out_ep>;
+ };
+};
+
+&csiphy3_out_port {
+ csiphy3_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy3_inep>;
+ };
+};
+
&gpu {
status = "okay";
};
@@ -1081,6 +1146,13 @@ &tlmm {
/* reserved for secure world */
gpio-reserved-ranges = <36 4>, <74 1>;
+ cam3_reset_default: cam3-reset-default-state {
+ pins = "gpio109";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
sdc2_card_det_n: sd-card-det-n-state {
pins = "gpio55";
function = "gpio";
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 17/23] arm64: dts: qcom: sm8750-qrd: Enable S5KJN1 camera sensor
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
Enable CAMSS, CCI1 and CSIPHY3 on the SM8750 QRD board. The S5KJN1
camera sensor is connected to CCI1 I2C bus 0, uses MCLK3 at 24 MHz and
connects to CSIPHY3 over a 4-lane D-PHY link.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 72 +++++++++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
index 75927e1f7b9ab0316781c64dbcc82d3394c414f6..c92a1f3c47bd5cbae26854614682c3bc7daa0398 100644
--- a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/media/video-interfaces.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sm8750.dtsi"
#include "pm8010.dtsi"
@@ -858,6 +859,70 @@ vreg_l7n_3p3: ldo7 {
};
};
+&camss {
+ status = "okay";
+};
+
+&camss_csiphy3_in_port {
+ camss_csiphy3_inep: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&csiphy3_out_ep>;
+ };
+};
+
+&cci1 {
+ status = "okay";
+};
+
+&cci1_i2c0 {
+ camera@56 {
+ compatible = "samsung,s5kjn1";
+ reg = <0x56>;
+
+ reset-gpios = <&tlmm 109 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&cam_mclk3_default &cam3_reset_default>;
+ pinctrl-names = "default";
+
+ clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>;
+ assigned-clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK3_CLK>;
+ assigned-clock-rates = <24000000>;
+
+ vdda-supply = <&vreg_l4m_2p8>;
+ vddd-supply = <&vreg_l2m_1p056>;
+ vddio-supply = <&vreg_l5m_1p8>;
+
+ port {
+ s5kjn1_out_ep: endpoint {
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <700000000>;
+ remote-endpoint = <&csiphy3_in_ep>;
+ };
+ };
+ };
+};
+
+&csiphy3 {
+ vdda-0p9-supply = <&vreg_l1f_0p88>;
+ vdda-1p2-supply = <&vreg_l3g_1p2>;
+
+ status = "okay";
+};
+
+&csiphy3_in_port {
+ csiphy3_in_ep: endpoint {
+ bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&s5kjn1_out_ep>;
+ };
+};
+
+&csiphy3_out_port {
+ csiphy3_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy3_inep>;
+ };
+};
+
&gpu {
status = "okay";
};
@@ -1081,6 +1146,13 @@ &tlmm {
/* reserved for secure world */
gpio-reserved-ranges = <36 4>, <74 1>;
+ cam3_reset_default: cam3-reset-default-state {
+ pins = "gpio109";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
sdc2_card_det_n: sd-card-det-n-state {
pins = "gpio55";
function = "gpio";
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 18/23] arm64: dts: qcom: eliza: Add CAMSS and CSIPHY block definitions
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
Describe the CAMSS and CSIPHY blocks on Eliza so that camera pipelines
can be enabled by board device trees.
The camera subsystem contains:
- 4 x CSIPHY (CSI Physical Layer)
- 2 x TPG (Test Pattern Generator)
- 3 x CSID (CSI Decoder)
- 1 x CSID Lite
- 3 x VFE (Video Front End), 4 RDI per VFE
- 1 x VFE Lite, 4 RDI per VFE Lite
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/eliza.dtsi | 296 ++++++++++++++++++++++++++++++++++++
1 file changed, 296 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi
index 4a125ef386c025fe6ecdbf4d17a785d1532ba09e..dd21cc4d267787db3d8741f8a8970629bd20d0c4 100644
--- a/arch/arm64/boot/dts/qcom/eliza.dtsi
+++ b/arch/arm64/boot/dts/qcom/eliza.dtsi
@@ -357,6 +357,22 @@ memory@a0000000 {
reg = <0x0 0xa0000000 0x0 0x0>;
};
+ csiphy_opp_table: opp-table-csiphy {
+ compatible = "operating-points-v2";
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -3448,6 +3464,286 @@ videocc: clock-controller@aaf0000 {
#power-domain-cells = <1>;
};
+ camss: isp@ac04000 {
+ compatible = "qcom,eliza-camss";
+
+ reg = <0x0 0x0ac04000 0x0 0x1000>,
+ <0x0 0x0ad27000 0x0 0x2b00>,
+ <0x0 0x0ad2a000 0x0 0x2b00>,
+ <0x0 0x0ad2d000 0x0 0x2b00>,
+ <0x0 0x0ad6d000 0x0 0xa00>,
+ <0x0 0x0ad8b000 0x0 0x400>,
+ <0x0 0x0ad8c000 0x0 0x400>,
+ <0x0 0x0ac86000 0x0 0x10000>,
+ <0x0 0x0ac96000 0x0 0x10000>,
+ <0x0 0x0aca6000 0x0 0x10000>,
+ <0x0 0x0ad6e000 0x0 0x3000>;
+ reg-names = "top",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "tpg0",
+ "tpg1",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0";
+
+ clocks = <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
+ <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>;
+ clock-names = "camnoc_rt_axi",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe2",
+ "cpas_vfe_lite",
+ "csid",
+ "csiphy_rx",
+ "gcc_axi_hf",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "qdss_debug_xo";
+
+ interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc";
+
+ iommus = <&apps_smmu 0x1c00 0x00>;
+
+ power-domains = <&camcc CAM_CC_TFE_0_GDSC>,
+ <&camcc CAM_CC_TFE_1_GDSC>,
+ <&camcc CAM_CC_TFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "ife2",
+ "top";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camss_csiphy0_in_port: port@0 {
+ reg = <0>;
+ };
+
+ camss_csiphy1_in_port: port@1 {
+ reg = <1>;
+ };
+
+ camss_csiphy2_in_port: port@2 {
+ reg = <2>;
+ };
+
+ camss_csiphy3_in_port: port@3 {
+ reg = <3>;
+ };
+ };
+ };
+
+ csiphy0: phy@ada9000 {
+ compatible = "qcom,eliza-csi2-phy", "qcom,x1e80100-csi2-phy";
+ reg = <0x0 0x0ada9000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 568 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy0_in_port: port@0 {
+ reg = <0>;
+ };
+
+ csiphy0_out_port: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ csiphy1: phy@adab000 {
+ compatible = "qcom,eliza-csi2-phy", "qcom,x1e80100-csi2-phy";
+ reg = <0x0 0x0adab000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 569 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy1_in_port: port@0 {
+ reg = <0>;
+ };
+
+ csiphy1_out_port: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ csiphy2: phy@adad000 {
+ compatible = "qcom,eliza-csi2-phy", "qcom,x1e80100-csi2-phy";
+ reg = <0x0 0x0adad000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 570 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy2_in_port: port@0 {
+ reg = <0>;
+ };
+
+ csiphy2_out_port: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ csiphy3: phy@adaf000 {
+ compatible = "qcom,eliza-csi2-phy", "qcom,x1e80100-csi2-phy";
+ reg = <0x0 0x0adaf000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 571 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy3_in_port: port@0 {
+ reg = <0>;
+ };
+
+ csiphy3_out_port: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
camcc: clock-controller@ade0000 {
compatible = "qcom,eliza-camcc";
reg = <0x0 0x0ade0000 0x0 0x20000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 18/23] arm64: dts: qcom: eliza: Add CAMSS and CSIPHY block definitions
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
Describe the CAMSS and CSIPHY blocks on Eliza so that camera pipelines
can be enabled by board device trees.
The camera subsystem contains:
- 4 x CSIPHY (CSI Physical Layer)
- 2 x TPG (Test Pattern Generator)
- 3 x CSID (CSI Decoder)
- 1 x CSID Lite
- 3 x VFE (Video Front End), 4 RDI per VFE
- 1 x VFE Lite, 4 RDI per VFE Lite
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/eliza.dtsi | 296 ++++++++++++++++++++++++++++++++++++
1 file changed, 296 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi
index 4a125ef386c025fe6ecdbf4d17a785d1532ba09e..dd21cc4d267787db3d8741f8a8970629bd20d0c4 100644
--- a/arch/arm64/boot/dts/qcom/eliza.dtsi
+++ b/arch/arm64/boot/dts/qcom/eliza.dtsi
@@ -357,6 +357,22 @@ memory@a0000000 {
reg = <0x0 0xa0000000 0x0 0x0>;
};
+ csiphy_opp_table: opp-table-csiphy {
+ compatible = "operating-points-v2";
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -3448,6 +3464,286 @@ videocc: clock-controller@aaf0000 {
#power-domain-cells = <1>;
};
+ camss: isp@ac04000 {
+ compatible = "qcom,eliza-camss";
+
+ reg = <0x0 0x0ac04000 0x0 0x1000>,
+ <0x0 0x0ad27000 0x0 0x2b00>,
+ <0x0 0x0ad2a000 0x0 0x2b00>,
+ <0x0 0x0ad2d000 0x0 0x2b00>,
+ <0x0 0x0ad6d000 0x0 0xa00>,
+ <0x0 0x0ad8b000 0x0 0x400>,
+ <0x0 0x0ad8c000 0x0 0x400>,
+ <0x0 0x0ac86000 0x0 0x10000>,
+ <0x0 0x0ac96000 0x0 0x10000>,
+ <0x0 0x0aca6000 0x0 0x10000>,
+ <0x0 0x0ad6e000 0x0 0x3000>;
+ reg-names = "top",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "tpg0",
+ "tpg1",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0";
+
+ clocks = <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
+ <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>;
+ clock-names = "camnoc_rt_axi",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe2",
+ "cpas_vfe_lite",
+ "csid",
+ "csiphy_rx",
+ "gcc_axi_hf",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "qdss_debug_xo";
+
+ interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc";
+
+ iommus = <&apps_smmu 0x1c00 0x00>;
+
+ power-domains = <&camcc CAM_CC_TFE_0_GDSC>,
+ <&camcc CAM_CC_TFE_1_GDSC>,
+ <&camcc CAM_CC_TFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "ife2",
+ "top";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camss_csiphy0_in_port: port@0 {
+ reg = <0>;
+ };
+
+ camss_csiphy1_in_port: port@1 {
+ reg = <1>;
+ };
+
+ camss_csiphy2_in_port: port@2 {
+ reg = <2>;
+ };
+
+ camss_csiphy3_in_port: port@3 {
+ reg = <3>;
+ };
+ };
+ };
+
+ csiphy0: phy@ada9000 {
+ compatible = "qcom,eliza-csi2-phy", "qcom,x1e80100-csi2-phy";
+ reg = <0x0 0x0ada9000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 568 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy0_in_port: port@0 {
+ reg = <0>;
+ };
+
+ csiphy0_out_port: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ csiphy1: phy@adab000 {
+ compatible = "qcom,eliza-csi2-phy", "qcom,x1e80100-csi2-phy";
+ reg = <0x0 0x0adab000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 569 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy1_in_port: port@0 {
+ reg = <0>;
+ };
+
+ csiphy1_out_port: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ csiphy2: phy@adad000 {
+ compatible = "qcom,eliza-csi2-phy", "qcom,x1e80100-csi2-phy";
+ reg = <0x0 0x0adad000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 570 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy2_in_port: port@0 {
+ reg = <0>;
+ };
+
+ csiphy2_out_port: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ csiphy3: phy@adaf000 {
+ compatible = "qcom,eliza-csi2-phy", "qcom,x1e80100-csi2-phy";
+ reg = <0x0 0x0adaf000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 571 IRQ_TYPE_EDGE_RISING>;
+
+ operating-points-v2 = <&csiphy_opp_table>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy3_in_port: port@0 {
+ reg = <0>;
+ };
+
+ csiphy3_out_port: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
camcc: clock-controller@ade0000 {
compatible = "qcom,eliza-camcc";
reg = <0x0 0x0ade0000 0x0 0x20000>;
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 19/23] arm64: dts: qcom: eliza: Add CCI definitions
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
Eliza has two Camera Control Interface (CCI) controllers, each with two
I2C hosts. Add the CCI nodes and their pinctrl states. The nodes are
left disabled; boards enable the CCI instances their camera sensors are
attached to.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/eliza.dtsi | 188 ++++++++++++++++++++++++++++++++++++
1 file changed, 188 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi
index dd21cc4d267787db3d8741f8a8970629bd20d0c4..0b759bf5b91e412743c12982b79ab4506b9a50b9 100644
--- a/arch/arm64/boot/dts/qcom/eliza.dtsi
+++ b/arch/arm64/boot/dts/qcom/eliza.dtsi
@@ -3592,6 +3592,66 @@ camss_csiphy3_in_port: port@3 {
};
};
+ cci0: cci@ac7b000 {
+ compatible = "qcom,eliza-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0ac7b000 0x0 0x1000>;
+ interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK>;
+ clock-names = "ahb", "cci";
+ pinctrl-0 = <&cci0_0_default &cci0_1_default>;
+ pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@ac7c000 {
+ compatible = "qcom,eliza-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0ac7c000 0x0 0x1000>;
+ interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK>;
+ clock-names = "ahb", "cci";
+ pinctrl-0 = <&cci1_0_default &cci1_1_default>;
+ pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
csiphy0: phy@ada9000 {
compatible = "qcom,eliza-csi2-phy", "qcom,x1e80100-csi2-phy";
reg = <0x0 0x0ada9000 0x0 0x2000>;
@@ -3953,6 +4013,134 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 186>;
wakeup-parent = <&pdc>;
+ cci0_0_default: cci0-0-default-state {
+ sda-pins {
+ pins = "gpio70";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio71";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci0_0_sleep: cci0-0-sleep-state {
+ sda-pins {
+ pins = "gpio70";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio71";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci0_1_default: cci0-1-default-state {
+ sda-pins {
+ pins = "gpio72";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio73";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci0_1_sleep: cci0-1-sleep-state {
+ sda-pins {
+ pins = "gpio72";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio73";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_0_default: cci1-0-default-state {
+ sda-pins {
+ pins = "gpio74";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio75";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci1_0_sleep: cci1-0-sleep-state {
+ sda-pins {
+ pins = "gpio74";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio75";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_1_default: cci1-1-default-state {
+ sda-pins {
+ pins = "gpio76";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio77";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci1_1_sleep: cci1-1-sleep-state {
+ sda-pins {
+ pins = "gpio76";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio77";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
pcie0_default_state: pcie0-default-state {
perst-pins {
pins = "gpio78";
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 19/23] arm64: dts: qcom: eliza: Add CCI definitions
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
Eliza has two Camera Control Interface (CCI) controllers, each with two
I2C hosts. Add the CCI nodes and their pinctrl states. The nodes are
left disabled; boards enable the CCI instances their camera sensors are
attached to.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/eliza.dtsi | 188 ++++++++++++++++++++++++++++++++++++
1 file changed, 188 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi
index dd21cc4d267787db3d8741f8a8970629bd20d0c4..0b759bf5b91e412743c12982b79ab4506b9a50b9 100644
--- a/arch/arm64/boot/dts/qcom/eliza.dtsi
+++ b/arch/arm64/boot/dts/qcom/eliza.dtsi
@@ -3592,6 +3592,66 @@ camss_csiphy3_in_port: port@3 {
};
};
+ cci0: cci@ac7b000 {
+ compatible = "qcom,eliza-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0ac7b000 0x0 0x1000>;
+ interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK>;
+ clock-names = "ahb", "cci";
+ pinctrl-0 = <&cci0_0_default &cci0_1_default>;
+ pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@ac7c000 {
+ compatible = "qcom,eliza-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0ac7c000 0x0 0x1000>;
+ interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK>;
+ clock-names = "ahb", "cci";
+ pinctrl-0 = <&cci1_0_default &cci1_1_default>;
+ pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
csiphy0: phy@ada9000 {
compatible = "qcom,eliza-csi2-phy", "qcom,x1e80100-csi2-phy";
reg = <0x0 0x0ada9000 0x0 0x2000>;
@@ -3953,6 +4013,134 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 186>;
wakeup-parent = <&pdc>;
+ cci0_0_default: cci0-0-default-state {
+ sda-pins {
+ pins = "gpio70";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio71";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci0_0_sleep: cci0-0-sleep-state {
+ sda-pins {
+ pins = "gpio70";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio71";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci0_1_default: cci0-1-default-state {
+ sda-pins {
+ pins = "gpio72";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio73";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci0_1_sleep: cci0-1-sleep-state {
+ sda-pins {
+ pins = "gpio72";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio73";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_0_default: cci1-0-default-state {
+ sda-pins {
+ pins = "gpio74";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio75";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci1_0_sleep: cci1-0-sleep-state {
+ sda-pins {
+ pins = "gpio74";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio75";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_1_default: cci1-1-default-state {
+ sda-pins {
+ pins = "gpio76";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio77";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci1_1_sleep: cci1-1-sleep-state {
+ sda-pins {
+ pins = "gpio76";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio77";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
pcie0_default_state: pcie0-default-state {
perst-pins {
pins = "gpio78";
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 20/23] arm64: dts: qcom: eliza: Add camera MCLK pinctrl
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
Add TLMM pinctrl states for the camera master clocks MCLK0 to MCLK3 on
Eliza so camera sensor nodes can select the MCLK pin functions when
enabled.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/eliza.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi
index 0b759bf5b91e412743c12982b79ab4506b9a50b9..f22a8b031e7c56e4ae7311c34ee6ca48359ce8fe 100644
--- a/arch/arm64/boot/dts/qcom/eliza.dtsi
+++ b/arch/arm64/boot/dts/qcom/eliza.dtsi
@@ -4013,6 +4013,34 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 186>;
wakeup-parent = <&pdc>;
+ cam_mclk0_default: cam-mclk0-default-state {
+ pins = "gpio65";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk1_default: cam-mclk1-default-state {
+ pins = "gpio66";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk2_default: cam-mclk2-default-state {
+ pins = "gpio67";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk3_default: cam-mclk3-default-state {
+ pins = "gpio68";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
cci0_0_default: cci0-0-default-state {
sda-pins {
pins = "gpio70";
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 20/23] arm64: dts: qcom: eliza: Add camera MCLK pinctrl
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
Add TLMM pinctrl states for the camera master clocks MCLK0 to MCLK3 on
Eliza so camera sensor nodes can select the MCLK pin functions when
enabled.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/eliza.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi
index 0b759bf5b91e412743c12982b79ab4506b9a50b9..f22a8b031e7c56e4ae7311c34ee6ca48359ce8fe 100644
--- a/arch/arm64/boot/dts/qcom/eliza.dtsi
+++ b/arch/arm64/boot/dts/qcom/eliza.dtsi
@@ -4013,6 +4013,34 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 186>;
wakeup-parent = <&pdc>;
+ cam_mclk0_default: cam-mclk0-default-state {
+ pins = "gpio65";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk1_default: cam-mclk1-default-state {
+ pins = "gpio66";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk2_default: cam-mclk2-default-state {
+ pins = "gpio67";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk3_default: cam-mclk3-default-state {
+ pins = "gpio68";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
cci0_0_default: cci0-0-default-state {
sda-pins {
pins = "gpio70";
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 21/23] arm64: dts: qcom: eliza-mtp: Add PM8010 PMICs
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
The Eliza MTP carries two PM8010 PMICs (IDs "m" and "n") that supply the
camera rails. Add the pm8010-eliza.dtsi describing both PMICs and their
thermal zones, and instantiate their RPMh regulators on the MTP.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/eliza-mtp.dts | 116 +++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/pm8010-eliza.dtsi | 81 ++++++++++++++++++++
2 files changed, 197 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/qcom/eliza-mtp.dts
index ee05192adcfb9f79cba59f11001b640a8572cc91..af7450fa2020d29a4ce98eb958dabd0cd8c61860 100644
--- a/arch/arm64/boot/dts/qcom/eliza-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts
@@ -12,6 +12,7 @@
#include "pm7550ba-eliza.dtsi"
#include "pm7550-eliza.dtsi"
+#include "pm8010-eliza.dtsi"
#include "pm8550vs-d-eliza.dtsi"
#include "pm8550vs-g-eliza.dtsi"
#include "pmr735d-eliza.dtsi"
@@ -420,6 +421,121 @@ vreg_l7k: ldo7 {
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
+
+ regulators-4 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+
+ vdd-l1-l2-supply = <&vreg_s2b>;
+ vdd-l3-l4-supply = <&vreg_bob>;
+ vdd-l5-supply = <&vreg_s1b>;
+ vdd-l6-supply = <&vreg_bob>;
+ vdd-l7-supply = <&vreg_bob>;
+
+ qcom,pmic-id = "m";
+
+ vreg_l1m: ldo1 {
+ regulator-name = "vreg_l1m";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m: ldo2 {
+ regulator-name = "vreg_l2m";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m: ldo3 {
+ regulator-name = "vreg_l3m";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m: ldo4 {
+ regulator-name = "vreg_l4m";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m: ldo6 {
+ regulator-name = "vreg_l6m";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m: ldo7 {
+ regulator-name = "vreg_l7m";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+
+ vdd-l1-l2-supply = <&vreg_s2b>;
+ vdd-l3-l4-supply = <&vreg_s1b>;
+ vdd-l5-supply = <&vreg_s1b>;
+ vdd-l6-supply = <&vreg_bob>;
+ vdd-l7-supply = <&vreg_bob>;
+
+ qcom,pmic-id = "n";
+
+ vreg_l1n: ldo1 {
+ regulator-name = "vreg_l1n";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n: ldo2 {
+ regulator-name = "vreg_l2n";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n: ldo3 {
+ regulator-name = "vreg_l3n";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n: ldo4 {
+ regulator-name = "vreg_l4n";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n: ldo5 {
+ regulator-name = "vreg_l5n";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n: ldo6 {
+ regulator-name = "vreg_l6n";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n: ldo7 {
+ regulator-name = "vreg_l7n";
+ regulator-min-microvolt = <3304000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
};
&gpu {
diff --git a/arch/arm64/boot/dts/qcom/pm8010-eliza.dtsi b/arch/arm64/boot/dts/qcom/pm8010-eliza.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..7fe414970b27c483706c86491c4db124bdeed43e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm8010-eliza.dtsi
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+ thermal-zones {
+ pm8010-m-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8010_m_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pm8010-n-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8010_n_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+ };
+};
+
+&spmi_bus0 {
+ pm8010_m: pmic@c {
+ compatible = "qcom,pm8010", "qcom,spmi-pmic";
+ reg = <0xc SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8010_m_temp_alarm: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+ };
+
+ pm8010_n: pmic@d {
+ compatible = "qcom,pm8010", "qcom,spmi-pmic";
+ reg = <0xd SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8010_n_temp_alarm: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0xd 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 21/23] arm64: dts: qcom: eliza-mtp: Add PM8010 PMICs
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
The Eliza MTP carries two PM8010 PMICs (IDs "m" and "n") that supply the
camera rails. Add the pm8010-eliza.dtsi describing both PMICs and their
thermal zones, and instantiate their RPMh regulators on the MTP.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/eliza-mtp.dts | 116 +++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/pm8010-eliza.dtsi | 81 ++++++++++++++++++++
2 files changed, 197 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/qcom/eliza-mtp.dts
index ee05192adcfb9f79cba59f11001b640a8572cc91..af7450fa2020d29a4ce98eb958dabd0cd8c61860 100644
--- a/arch/arm64/boot/dts/qcom/eliza-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts
@@ -12,6 +12,7 @@
#include "pm7550ba-eliza.dtsi"
#include "pm7550-eliza.dtsi"
+#include "pm8010-eliza.dtsi"
#include "pm8550vs-d-eliza.dtsi"
#include "pm8550vs-g-eliza.dtsi"
#include "pmr735d-eliza.dtsi"
@@ -420,6 +421,121 @@ vreg_l7k: ldo7 {
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
+
+ regulators-4 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+
+ vdd-l1-l2-supply = <&vreg_s2b>;
+ vdd-l3-l4-supply = <&vreg_bob>;
+ vdd-l5-supply = <&vreg_s1b>;
+ vdd-l6-supply = <&vreg_bob>;
+ vdd-l7-supply = <&vreg_bob>;
+
+ qcom,pmic-id = "m";
+
+ vreg_l1m: ldo1 {
+ regulator-name = "vreg_l1m";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m: ldo2 {
+ regulator-name = "vreg_l2m";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m: ldo3 {
+ regulator-name = "vreg_l3m";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m: ldo4 {
+ regulator-name = "vreg_l4m";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m: ldo6 {
+ regulator-name = "vreg_l6m";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m: ldo7 {
+ regulator-name = "vreg_l7m";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+
+ vdd-l1-l2-supply = <&vreg_s2b>;
+ vdd-l3-l4-supply = <&vreg_s1b>;
+ vdd-l5-supply = <&vreg_s1b>;
+ vdd-l6-supply = <&vreg_bob>;
+ vdd-l7-supply = <&vreg_bob>;
+
+ qcom,pmic-id = "n";
+
+ vreg_l1n: ldo1 {
+ regulator-name = "vreg_l1n";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n: ldo2 {
+ regulator-name = "vreg_l2n";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n: ldo3 {
+ regulator-name = "vreg_l3n";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n: ldo4 {
+ regulator-name = "vreg_l4n";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n: ldo5 {
+ regulator-name = "vreg_l5n";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n: ldo6 {
+ regulator-name = "vreg_l6n";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n: ldo7 {
+ regulator-name = "vreg_l7n";
+ regulator-min-microvolt = <3304000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
};
&gpu {
diff --git a/arch/arm64/boot/dts/qcom/pm8010-eliza.dtsi b/arch/arm64/boot/dts/qcom/pm8010-eliza.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..7fe414970b27c483706c86491c4db124bdeed43e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm8010-eliza.dtsi
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+ thermal-zones {
+ pm8010-m-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8010_m_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pm8010-n-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8010_n_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+ };
+};
+
+&spmi_bus0 {
+ pm8010_m: pmic@c {
+ compatible = "qcom,pm8010", "qcom,spmi-pmic";
+ reg = <0xc SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8010_m_temp_alarm: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+ };
+
+ pm8010_n: pmic@d {
+ compatible = "qcom,pm8010", "qcom,spmi-pmic";
+ reg = <0xd SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8010_n_temp_alarm: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0xd 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+ };
+};
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 22/23] arm64: dts: qcom: eliza-mtp: Enable rear camera
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
Enable the rear camera on the Eliza MTP: a Samsung S5KJN1 on CCI1 I2C
bus 0, connected to CSIPHY2 over four data lanes. The sensor takes MCLK2
at 24 MHz, is powered from the PM8010 regulators added in the previous
patch and is reset through GPIO125.
Also enable CAMSS, CSIPHY2 and CCI1.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/eliza-mtp.dts | 72 ++++++++++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/qcom/eliza-mtp.dts
index af7450fa2020d29a4ce98eb958dabd0cd8c61860..cd14b44cf0aef33a7939075949916d054cd77659 100644
--- a/arch/arm64/boot/dts/qcom/eliza-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/media/video-interfaces.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "eliza.dtsi"
@@ -538,6 +539,70 @@ vreg_l7n: ldo7 {
};
};
+&camss {
+ status = "okay";
+};
+
+&camss_csiphy2_in_port {
+ camss_csiphy2_inep: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&csiphy2_out_ep>;
+ };
+};
+
+&cci1 {
+ status = "okay";
+};
+
+&cci1_i2c0 {
+ camera@56 {
+ compatible = "samsung,s5kjn1";
+ reg = <0x56>;
+
+ reset-gpios = <&tlmm 125 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&cam_mclk2_default &cam2_reset_default>;
+ pinctrl-names = "default";
+
+ clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
+ assigned-clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
+ assigned-clock-rates = <24000000>;
+
+ vdda-supply = <&vreg_l4m>;
+ vddd-supply = <&vreg_l2m>;
+ vddio-supply = <&vreg_l5n>;
+
+ port {
+ s5kjn1_out_ep: endpoint {
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <700000000>;
+ remote-endpoint = <&csiphy2_in_ep>;
+ };
+ };
+ };
+};
+
+&csiphy2 {
+ vdda-0p9-supply = <&vreg_l2b>;
+ vdda-1p2-supply = <&vreg_l4b>;
+
+ status = "okay";
+};
+
+&csiphy2_in_port {
+ csiphy2_in_ep: endpoint {
+ bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&s5kjn1_out_ep>;
+ };
+};
+
+&csiphy2_out_port {
+ csiphy2_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy2_inep>;
+ };
+};
+
&gpu {
status = "okay";
};
@@ -657,6 +722,13 @@ &tlmm {
<111 2>, /* WCN UART1 */
<118 1>; /* NFC Secure I/O */
+ cam2_reset_default: cam2-reset-default-state {
+ pins = "gpio125";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
disp0_reset_n_active: disp0-reset-n-active-state {
pins = "gpio12";
function = "gpio";
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 22/23] arm64: dts: qcom: eliza-mtp: Enable rear camera
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
Enable the rear camera on the Eliza MTP: a Samsung S5KJN1 on CCI1 I2C
bus 0, connected to CSIPHY2 over four data lanes. The sensor takes MCLK2
at 24 MHz, is powered from the PM8010 regulators added in the previous
patch and is reset through GPIO125.
Also enable CAMSS, CSIPHY2 and CCI1.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/eliza-mtp.dts | 72 ++++++++++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/qcom/eliza-mtp.dts
index af7450fa2020d29a4ce98eb958dabd0cd8c61860..cd14b44cf0aef33a7939075949916d054cd77659 100644
--- a/arch/arm64/boot/dts/qcom/eliza-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/media/video-interfaces.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "eliza.dtsi"
@@ -538,6 +539,70 @@ vreg_l7n: ldo7 {
};
};
+&camss {
+ status = "okay";
+};
+
+&camss_csiphy2_in_port {
+ camss_csiphy2_inep: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&csiphy2_out_ep>;
+ };
+};
+
+&cci1 {
+ status = "okay";
+};
+
+&cci1_i2c0 {
+ camera@56 {
+ compatible = "samsung,s5kjn1";
+ reg = <0x56>;
+
+ reset-gpios = <&tlmm 125 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&cam_mclk2_default &cam2_reset_default>;
+ pinctrl-names = "default";
+
+ clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
+ assigned-clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>;
+ assigned-clock-rates = <24000000>;
+
+ vdda-supply = <&vreg_l4m>;
+ vddd-supply = <&vreg_l2m>;
+ vddio-supply = <&vreg_l5n>;
+
+ port {
+ s5kjn1_out_ep: endpoint {
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <700000000>;
+ remote-endpoint = <&csiphy2_in_ep>;
+ };
+ };
+ };
+};
+
+&csiphy2 {
+ vdda-0p9-supply = <&vreg_l2b>;
+ vdda-1p2-supply = <&vreg_l4b>;
+
+ status = "okay";
+};
+
+&csiphy2_in_port {
+ csiphy2_in_ep: endpoint {
+ bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&s5kjn1_out_ep>;
+ };
+};
+
+&csiphy2_out_port {
+ csiphy2_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy2_inep>;
+ };
+};
+
&gpu {
status = "okay";
};
@@ -657,6 +722,13 @@ &tlmm {
<111 2>, /* WCN UART1 */
<118 1>; /* NFC Secure I/O */
+ cam2_reset_default: cam2-reset-default-state {
+ pins = "gpio125";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
disp0_reset_n_active: disp0-reset-n-active-state {
pins = "gpio12";
function = "gpio";
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 23/23] arm64: dts: qcom: eliza-evk-imx577-camera: Add DT overlay
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:29 ` Wenmeng Liu
-1 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
Add an overlay for optional IMX577 integration on the Eliza CQS EVK,
shared by the eMMC and UFS variants. The sensor is on CCI0 I2C bus 0,
uses MCLK0 with its reset on GPIO8 and connects to CSIPHY0 over CSI-2.
The overlay enables CAMSS, CSIPHY0 and CCI0.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/Makefile | 4 +
.../boot/dts/qcom/eliza-evk-imx577-camera.dtso | 85 ++++++++++++++++++++++
2 files changed, 89 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 64d2cfdb89c89f1c6eb0085e2bf5877ff980dbc4..a9374c54dd514f53b7aa97f5581c99cb6e75697d 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -16,6 +16,10 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8096sg-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
dtb-$(CONFIG_ARCH_QCOM) += eliza-cqs-evk-emmc.dtb
dtb-$(CONFIG_ARCH_QCOM) += eliza-cqs-evk-ufs.dtb
+eliza-cqs-evk-emmc-imx577-camera-dtbs := eliza-cqs-evk-emmc.dtb eliza-evk-imx577-camera.dtbo
+eliza-cqs-evk-ufs-imx577-camera-dtbs := eliza-cqs-evk-ufs.dtb eliza-evk-imx577-camera.dtbo
+dtb-$(CONFIG_ARCH_QCOM) += eliza-cqs-evk-emmc-imx577-camera.dtb
+dtb-$(CONFIG_ARCH_QCOM) += eliza-cqs-evk-ufs-imx577-camera.dtb
dtb-$(CONFIG_ARCH_QCOM) += eliza-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += glymur-asus-zenbook-a14-ux3407na.dtb
dtb-$(CONFIG_ARCH_QCOM) += glymur-asus-zenbook-a16-ux3607oa.dtb
diff --git a/arch/arm64/boot/dts/qcom/eliza-evk-imx577-camera.dtso b/arch/arm64/boot/dts/qcom/eliza-evk-imx577-camera.dtso
new file mode 100644
index 0000000000000000000000000000000000000000..08f2e3c62dbdaf23a2f6ca69a5c392054cb1c225
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/eliza-evk-imx577-camera.dtso
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,eliza-cambistmclkcc.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/media/video-interfaces.h>
+
+&camss {
+ status = "okay";
+};
+
+&camss_csiphy0_in_port {
+ camss_csiphy0_inep: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&csiphy0_out_ep>;
+ };
+};
+
+&cci0 {
+ status = "okay";
+};
+
+&cci0_i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera@1a {
+ compatible = "sony,imx577";
+ reg = <0x1a>;
+
+ reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&cam_mclk0_default &cam0_reset_default>;
+ pinctrl-names = "default";
+
+ clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
+ assigned-clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
+ assigned-clock-rates = <24000000>;
+
+ dovdd-supply = <&vreg_l7b>;
+
+ port {
+ imx577_out_ep: endpoint {
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <600000000>;
+ remote-endpoint = <&csiphy0_in_ep>;
+ };
+ };
+ };
+};
+
+&csiphy0 {
+ vdda-0p9-supply = <&vreg_l2b>;
+ vdda-1p2-supply = <&vreg_l4b>;
+
+ status = "okay";
+};
+
+&csiphy0_in_port {
+ csiphy0_in_ep: endpoint {
+ bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&imx577_out_ep>;
+ };
+};
+
+&csiphy0_out_port {
+ csiphy0_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy0_inep>;
+ };
+};
+
+&tlmm {
+ cam0_reset_default: cam0-reset-default-state {
+ pins = "gpio8";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v7 23/23] arm64: dts: qcom: eliza-evk-imx577-camera: Add DT overlay
@ 2026-11-14 11:29 ` Wenmeng Liu
0 siblings, 0 replies; 56+ messages in thread
From: Wenmeng Liu @ 2026-11-14 11:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Hangxiang Ma, Bryan O'Donoghue,
Robert Foss, Andi Shyti, Bjorn Andersson, Konrad Dybcio,
Abel Vesa, Frank Li
Cc: linux-phy, linux-media, linux-arm-msm, devicetree, linux-kernel,
linux-i2c, Wenmeng Liu
Add an overlay for optional IMX577 integration on the Eliza CQS EVK,
shared by the eMMC and UFS variants. The sensor is on CCI0 I2C bus 0,
uses MCLK0 with its reset on GPIO8 and connects to CSIPHY0 over CSI-2.
The overlay enables CAMSS, CSIPHY0 and CCI0.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/Makefile | 4 +
.../boot/dts/qcom/eliza-evk-imx577-camera.dtso | 85 ++++++++++++++++++++++
2 files changed, 89 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 64d2cfdb89c89f1c6eb0085e2bf5877ff980dbc4..a9374c54dd514f53b7aa97f5581c99cb6e75697d 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -16,6 +16,10 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8096sg-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
dtb-$(CONFIG_ARCH_QCOM) += eliza-cqs-evk-emmc.dtb
dtb-$(CONFIG_ARCH_QCOM) += eliza-cqs-evk-ufs.dtb
+eliza-cqs-evk-emmc-imx577-camera-dtbs := eliza-cqs-evk-emmc.dtb eliza-evk-imx577-camera.dtbo
+eliza-cqs-evk-ufs-imx577-camera-dtbs := eliza-cqs-evk-ufs.dtb eliza-evk-imx577-camera.dtbo
+dtb-$(CONFIG_ARCH_QCOM) += eliza-cqs-evk-emmc-imx577-camera.dtb
+dtb-$(CONFIG_ARCH_QCOM) += eliza-cqs-evk-ufs-imx577-camera.dtb
dtb-$(CONFIG_ARCH_QCOM) += eliza-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += glymur-asus-zenbook-a14-ux3407na.dtb
dtb-$(CONFIG_ARCH_QCOM) += glymur-asus-zenbook-a16-ux3607oa.dtb
diff --git a/arch/arm64/boot/dts/qcom/eliza-evk-imx577-camera.dtso b/arch/arm64/boot/dts/qcom/eliza-evk-imx577-camera.dtso
new file mode 100644
index 0000000000000000000000000000000000000000..08f2e3c62dbdaf23a2f6ca69a5c392054cb1c225
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/eliza-evk-imx577-camera.dtso
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,eliza-cambistmclkcc.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/media/video-interfaces.h>
+
+&camss {
+ status = "okay";
+};
+
+&camss_csiphy0_in_port {
+ camss_csiphy0_inep: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&csiphy0_out_ep>;
+ };
+};
+
+&cci0 {
+ status = "okay";
+};
+
+&cci0_i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera@1a {
+ compatible = "sony,imx577";
+ reg = <0x1a>;
+
+ reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&cam_mclk0_default &cam0_reset_default>;
+ pinctrl-names = "default";
+
+ clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
+ assigned-clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK0_CLK>;
+ assigned-clock-rates = <24000000>;
+
+ dovdd-supply = <&vreg_l7b>;
+
+ port {
+ imx577_out_ep: endpoint {
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <600000000>;
+ remote-endpoint = <&csiphy0_in_ep>;
+ };
+ };
+ };
+};
+
+&csiphy0 {
+ vdda-0p9-supply = <&vreg_l2b>;
+ vdda-1p2-supply = <&vreg_l4b>;
+
+ status = "okay";
+};
+
+&csiphy0_in_port {
+ csiphy0_in_ep: endpoint {
+ bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&imx577_out_ep>;
+ };
+};
+
+&csiphy0_out_port {
+ csiphy0_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy0_inep>;
+ };
+};
+
+&tlmm {
+ cam0_reset_default: cam0-reset-default-state {
+ pins = "gpio8";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 56+ messages in thread
* Re: [PATCH v7 03/23] dt-bindings: media: qcom,sm8750-camss: Add SM8750 CAMSS
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:42 ` sashiko-bot
-1 siblings, 0 replies; 56+ messages in thread
From: sashiko-bot @ 2026-11-14 11:42 UTC (permalink / raw)
To: Wenmeng Liu
Cc: linux-phy, devicetree, robh, conor+dt, media-ci, vkoul,
neil.armstrong, olteanv
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] dt-bindings: media: qcom,sm8750-camss: invalid 0-based
data-lanes in example
--
commit cfe5f0b3c8e80533b908dd73b55a048664a6ed2e
Author: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
dt-bindings: media: qcom,sm8750-camss: Add SM8750 CAMSS
This commit adds the Device Tree binding schema for the Qualcomm SM8750
Camera Subsystem (CAMSS).
> diff --git a/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
> new file mode 100644
> index 0000000000000..e7ab61d71ffbd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
> @@ -0,0 +1,297 @@
[ ... ]
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
[ ... ]
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + camss_csiphy0_ep: endpoint {
> + data-lanes = <0 1 2 3>;
> + remote-endpoint = <&csiphy0_out>;
> + };
> + };
> + };
> + };
> + };
[Severity: Low]
Should data-lanes in the example endpoint be <1 2 3 4> instead of
<0 1 2 3>?
On SM8750, CSIPHY blocks are standalone PHY devices rather than legacy
sub-resources inside the CAMSS node, so camss_detect_legacy_phy() sets
camss->legacy_phy = false and camss_parse_ports() sets lane_base = 1.
camss_parse_endpoint_node() then rejects lane 0 with -EINVAL and fails
probe:
drivers/media/platform/qcom/camss/camss.c:camss_parse_endpoint_node() {
...
if (lane < lane_base || lane - lane_base >= MSM_CSIPHY_MAX_DATA_LANE) {
dev_err(dev, "invalid data-lane %u\n", lane);
return -EINVAL;
}
...
}
The endpoint schema for data-lanes could also constrain items to minimum: 1
and maximum: 4 so 0-based lane indices are caught by schema validation.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261114-add-support-for-camss-on-sm8750-v7-0-8ff2a11835f6@oss.qualcomm.com?part=3
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH v7 03/23] dt-bindings: media: qcom,sm8750-camss: Add SM8750 CAMSS
@ 2026-11-14 11:42 ` sashiko-bot
0 siblings, 0 replies; 56+ messages in thread
From: sashiko-bot @ 2026-11-14 11:42 UTC (permalink / raw)
To: Wenmeng Liu
Cc: linux-phy, devicetree, robh, conor+dt, media-ci, vkoul,
neil.armstrong, olteanv
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] dt-bindings: media: qcom,sm8750-camss: invalid 0-based
data-lanes in example
--
commit cfe5f0b3c8e80533b908dd73b55a048664a6ed2e
Author: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
dt-bindings: media: qcom,sm8750-camss: Add SM8750 CAMSS
This commit adds the Device Tree binding schema for the Qualcomm SM8750
Camera Subsystem (CAMSS).
> diff --git a/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
> new file mode 100644
> index 0000000000000..e7ab61d71ffbd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
> @@ -0,0 +1,297 @@
[ ... ]
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
[ ... ]
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + camss_csiphy0_ep: endpoint {
> + data-lanes = <0 1 2 3>;
> + remote-endpoint = <&csiphy0_out>;
> + };
> + };
> + };
> + };
> + };
[Severity: Low]
Should data-lanes in the example endpoint be <1 2 3 4> instead of
<0 1 2 3>?
On SM8750, CSIPHY blocks are standalone PHY devices rather than legacy
sub-resources inside the CAMSS node, so camss_detect_legacy_phy() sets
camss->legacy_phy = false and camss_parse_ports() sets lane_base = 1.
camss_parse_endpoint_node() then rejects lane 0 with -EINVAL and fails
probe:
drivers/media/platform/qcom/camss/camss.c:camss_parse_endpoint_node() {
...
if (lane < lane_base || lane - lane_base >= MSM_CSIPHY_MAX_DATA_LANE) {
dev_err(dev, "invalid data-lane %u\n", lane);
return -EINVAL;
}
...
}
The endpoint schema for data-lanes could also constrain items to minimum: 1
and maximum: 4 so 0-based lane indices are caught by schema validation.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261114-add-support-for-camss-on-sm8750-v7-0-8ff2a11835f6@oss.qualcomm.com?part=3
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH v7 11/23] media: qcom: camss: vfe: Add support for VFE 980
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:42 ` sashiko-bot
-1 siblings, 0 replies; 56+ messages in thread
From: sashiko-bot @ 2026-11-14 11:42 UTC (permalink / raw)
To: Wenmeng Liu
Cc: linux-phy, devicetree, robh, conor+dt, media-ci, vkoul,
neil.armstrong, olteanv
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] media: qcom: camss: camss-vfe-980.c duplicates camss-vfe-1080.c
--
commit 29195d9029785533829d246888a075efe92d772a
Author: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
media: qcom: camss: vfe: Add support for VFE 980
This commit adds hardware operations and SM8750 subdevice resource definitions
for VFE 980.
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe-980.c b/drivers/media/platform/qcom/camss/camss-vfe-980.c
> new file mode 100644
> index 0000000000000..47f6c18190acf
> --- /dev/null
> +++ b/drivers/media/platform/qcom/camss/camss-vfe-980.c
> @@ -0,0 +1,213 @@
[ ... ]
> +/* VFE-980 Bus Register Base Addresses */
> +#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x200 : 0x800)
[Severity: Low]
Could VFE 980 share the implementation in camss-vfe-1080.c instead of
duplicating the entire file?
Every register offset, client index, and callback in camss-vfe-980.c is
identical to camss-vfe-1080.c except for BUS_REG_BASE, which could be
selected based on vfe->camss->res->version (similar to camss-vfe-gen3.c).
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261114-add-support-for-camss-on-sm8750-v7-0-8ff2a11835f6@oss.qualcomm.com?part=11
--
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^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH v7 11/23] media: qcom: camss: vfe: Add support for VFE 980
@ 2026-11-14 11:42 ` sashiko-bot
0 siblings, 0 replies; 56+ messages in thread
From: sashiko-bot @ 2026-11-14 11:42 UTC (permalink / raw)
To: Wenmeng Liu
Cc: linux-phy, devicetree, robh, conor+dt, media-ci, vkoul,
neil.armstrong, olteanv
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] media: qcom: camss: camss-vfe-980.c duplicates camss-vfe-1080.c
--
commit 29195d9029785533829d246888a075efe92d772a
Author: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
media: qcom: camss: vfe: Add support for VFE 980
This commit adds hardware operations and SM8750 subdevice resource definitions
for VFE 980.
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe-980.c b/drivers/media/platform/qcom/camss/camss-vfe-980.c
> new file mode 100644
> index 0000000000000..47f6c18190acf
> --- /dev/null
> +++ b/drivers/media/platform/qcom/camss/camss-vfe-980.c
> @@ -0,0 +1,213 @@
[ ... ]
> +/* VFE-980 Bus Register Base Addresses */
> +#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x200 : 0x800)
[Severity: Low]
Could VFE 980 share the implementation in camss-vfe-1080.c instead of
duplicating the entire file?
Every register offset, client index, and callback in camss-vfe-980.c is
identical to camss-vfe-1080.c except for BUS_REG_BASE, which could be
selected based on vfe->camss->res->version (similar to camss-vfe-gen3.c).
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261114-add-support-for-camss-on-sm8750-v7-0-8ff2a11835f6@oss.qualcomm.com?part=11
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH v7 04/23] dt-bindings: media: qcom,eliza-camss: Add Eliza CAMSS
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:43 ` sashiko-bot
-1 siblings, 0 replies; 56+ messages in thread
From: sashiko-bot @ 2026-11-14 11:43 UTC (permalink / raw)
To: Wenmeng Liu
Cc: linux-phy, devicetree, robh, conor+dt, media-ci, vkoul,
neil.armstrong, olteanv
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] dt-bindings: media: qcom,eliza-camss: invalid 0-based data-lanes
in example
--
commit bce0133de93b87d5e9e002d47e94f2395d97b15f
Author: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
dt-bindings: media: qcom,eliza-camss: Add Eliza CAMSS
This commit adds the Device Tree binding schema and example for the Camera
Subsystem (CAMSS) on the Qualcomm Eliza platform.
> diff --git a/Documentation/devicetree/bindings/media/qcom,eliza-camss.yaml b/Documentation/devicetree/bindings/media/qcom,eliza-camss.yaml
> new file mode 100644
> index 0000000000000..8775ec6a2f69b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,eliza-camss.yaml
> @@ -0,0 +1,282 @@
[ ... ]
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
[ ... ]
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + camss_csiphy0_ep: endpoint {
> + data-lanes = <0 1 2 3>;
> + remote-endpoint = <&csiphy0_out>;
> + };
[Severity: Low]
Should data-lanes in the example be 1-based (<1 2 3 4>) instead of 0-based
(<0 1 2 3>)?
Because Eliza uses standalone CSIPHY devices without legacy CSIPHY
resources, camss_detect_legacy_phy() sets camss->legacy_phy to false and
camss_parse_ports() sets lane_base to 1. camss_parse_endpoint_node() then
rejects lane 0 with -EINVAL:
drivers/media/platform/qcom/camss/camss.c:camss_parse_endpoint_node() {
...
if (lane < lane_base || lane - lane_base >= MSM_CSIPHY_MAX_DATA_LANE) {
dev_err(dev, "invalid data-lane %u\n", lane);
return -EINVAL;
}
...
}
Any Device Tree modeled after this example will fail to probe. The
endpoint data-lanes schema above also only constrains minItems and
maxItems, so adding items with minimum: 1 and maximum: 4 would allow
dtbs_check to catch 0-based lane indices.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261114-add-support-for-camss-on-sm8750-v7-0-8ff2a11835f6@oss.qualcomm.com?part=4
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH v7 04/23] dt-bindings: media: qcom,eliza-camss: Add Eliza CAMSS
@ 2026-11-14 11:43 ` sashiko-bot
0 siblings, 0 replies; 56+ messages in thread
From: sashiko-bot @ 2026-11-14 11:43 UTC (permalink / raw)
To: Wenmeng Liu
Cc: linux-phy, devicetree, robh, conor+dt, media-ci, vkoul,
neil.armstrong, olteanv
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] dt-bindings: media: qcom,eliza-camss: invalid 0-based data-lanes
in example
--
commit bce0133de93b87d5e9e002d47e94f2395d97b15f
Author: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
dt-bindings: media: qcom,eliza-camss: Add Eliza CAMSS
This commit adds the Device Tree binding schema and example for the Camera
Subsystem (CAMSS) on the Qualcomm Eliza platform.
> diff --git a/Documentation/devicetree/bindings/media/qcom,eliza-camss.yaml b/Documentation/devicetree/bindings/media/qcom,eliza-camss.yaml
> new file mode 100644
> index 0000000000000..8775ec6a2f69b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,eliza-camss.yaml
> @@ -0,0 +1,282 @@
[ ... ]
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
[ ... ]
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + camss_csiphy0_ep: endpoint {
> + data-lanes = <0 1 2 3>;
> + remote-endpoint = <&csiphy0_out>;
> + };
[Severity: Low]
Should data-lanes in the example be 1-based (<1 2 3 4>) instead of 0-based
(<0 1 2 3>)?
Because Eliza uses standalone CSIPHY devices without legacy CSIPHY
resources, camss_detect_legacy_phy() sets camss->legacy_phy to false and
camss_parse_ports() sets lane_base to 1. camss_parse_endpoint_node() then
rejects lane 0 with -EINVAL:
drivers/media/platform/qcom/camss/camss.c:camss_parse_endpoint_node() {
...
if (lane < lane_base || lane - lane_base >= MSM_CSIPHY_MAX_DATA_LANE) {
dev_err(dev, "invalid data-lane %u\n", lane);
return -EINVAL;
}
...
}
Any Device Tree modeled after this example will fail to probe. The
endpoint data-lanes schema above also only constrains minItems and
maxItems, so adding items with minimum: 1 and maximum: 4 would allow
dtbs_check to catch 0-based lane indices.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261114-add-support-for-camss-on-sm8750-v7-0-8ff2a11835f6@oss.qualcomm.com?part=4
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH v7 10/23] media: qcom: camss: csid: Add support for CSID 980
2026-11-14 11:29 ` Wenmeng Liu
@ 2026-11-14 11:55 ` sashiko-bot
-1 siblings, 0 replies; 56+ messages in thread
From: sashiko-bot @ 2026-11-14 11:55 UTC (permalink / raw)
To: Wenmeng Liu
Cc: linux-phy, devicetree, robh, conor+dt, media-ci, vkoul,
neil.armstrong, olteanv
Thank you for your contribution! Sashiko AI review found 3 potential
issues to consider:
- [High] media: qcom: camss: wrong dt_id calculation in
__csid_configure_rdi_stream()
- [Medium] media: qcom: camss: misplaced lane_cnt fallback in
camss-csid-980.c
- [Medium] media: qcom: camss: race on csid->reg_update and addr_update
in csid-980
--
commit ad1ff7fa26120bcd2005c8cf69d816599d94898f
Author: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
media: qcom: camss: csid: Add support for CSID 980
This commit adds the CSID 980 hardware operations driver and populates
the SM8750 CSID subdevice resource definitions.
> diff --git a/drivers/media/platform/qcom/camss/camss-csid-980.c b/drivers/media/platform/qcom/camss/camss-csid-980.c
> new file mode 100644
> index 0000000000000..713db25cd8c65
> --- /dev/null
> +++ b/drivers/media/platform/qcom/camss/camss-csid-980.c
> @@ -0,0 +1,466 @@
[ ... ]
> +static void __csid_configure_rx(struct csid_device *csid,
> + struct csid_phy_config *phy)
> +{
> + int val;
> +
> + val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
> + val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
> + val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX)
> + << CSI2_RX_CFG0_PHY_NUM_SEL;
> + writel(val, csid->base + CSID_CSI2_RX_CFG0);
> +
> + val = CSI2_RX_CFG1_ECC_CORRECTION_EN;
> + writel(val, csid->base + CSID_CSI2_RX_CFG1);
> +}
[ ... ]
> +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 port, u8 vc)
> +{
> + u8 lane_cnt = csid->phy.lane_cnt;
> + u32 val;
> +
> + /* Source pads matching RDI channels on hardware.
> + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc.
> + */
> + struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + port];
> + const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
> + csid->res->formats->nformats,
> + input_format->code);
> +
> + if (!lane_cnt)
> + lane_cnt = 4;
[Severity: Medium]
Was the lane_cnt fallback meant to be in __csid_configure_rx() instead of
__csid_configure_rdi_stream()?
In __csid_configure_rdi_stream(), lane_cnt is never read after being set,
which triggers a -Wunused-but-set-variable warning under W=1 (and precedes
the variable declarations below). Meanwhile, __csid_configure_rx() uses
phy->lane_cnt - 1 directly in signed int arithmetic, so if phy->lane_cnt
is 0 (for instance, when csid_set_stream() disables a stream after
csid_set_power() without an active sink link), val becomes -1 and corrupts
all fields written to CSID_CSI2_RX_CFG0.
> +
> + /*
> + * DT_ID is a two bit bitfield that is concatenated with
> + * the four least significant bits of the five bit VC
> + * bitfield to generate an internal CID value.
> + *
> + * CSID_RDI_CFG0(vc)
> + * DT_ID : 28:27
> + * VC : 26:22
> + * DT : 21:16
> + *
> + * CID : VC 3:0 << 2 | DT_ID 1:0
> + */
> + u8 dt_id = vc & 0x03;
> + u32 rdi_cfg0_offset = CSID_RDI_CFG0(port);
> + u32 rdi_cfg1_offset = CSID_RDI_CFG1(port);
> + u32 rdi_ctrl_offset = CSID_RDI_CTRL(port);
> +
> + val = RDI_CFG0_TIMESTAMP_EN;
> + val |= RDI_CFG0_TIMESTAMP_STB_SEL;
> + val |= RDI_CFG0_RETIME_BS;
> +
> + /* note: for non-RDI path, this should be format->decode_format */
> + val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
> + val |= vc << RDI_CFG0_VC;
> + val |= format->data_type << RDI_CFG0_DT;
> + val |= dt_id << RDI_CFG0_DT_ID;
> + writel(val, csid->base + rdi_cfg0_offset);
[ ... ]
> +static void csid_configure_stream(struct csid_device *csid, u8 enable)
> +{
> + u8 i, k;
> +
> + __csid_configure_rx(csid, &csid->phy);
> +
> + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) {
> + if (csid->phy.en_vc & BIT(i)) {
> + __csid_configure_rdi_stream(csid, enable, i, 0);
[Severity: High]
Should dt_id in __csid_configure_rdi_stream() be derived from port & 0x03
rather than vc & 0x03?
csid_configure_stream() always passes vc = 0 while passing the RDI channel
index i as port. Calculating dt_id from vc sets RDI_CFG0_DT_ID to 0 for
every RDI channel, so RDI1, RDI2, and RDI3 all receive internal CID 0 and
cannot stream properly, matching the issue fixed for CSID GEN3 in commit
ad136e52634d ("media: qcom: camss: Fix RDI streaming for CSID GEN3") and
for CSID GEN2 in commit 618765634cef ("media: qcom: camss: Fix RDI
streaming for CSID GEN2").
[ ... ]
> +static irqreturn_t csid_isr(int irq, void *dev)
> +{
> + struct csid_device *csid = dev;
> + u32 val, buf_done_val;
> + u8 reset_done;
> + int i;
> +
> + val = readl(csid->base + CSID_TOP_IRQ_STATUS);
> + writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
> +
> + reset_done = val & INFO_RST_DONE;
> +
> + buf_done_val = readl(csid->base + CSID_BUF_DONE_IRQ_STATUS);
> + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
> +
> + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) {
> + if (csid->phy.en_vc & BIT(i)) {
> + val = readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i));
> + writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i));
> +
> + if (val & INFO_RUP_DONE) {
> + __csid_addr_update_clear(csid, i);
> + __csid_reg_update_clear(csid, i);
> + }
> +
> + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i))
> + camss_buf_done(csid->camss, csid->id, i);
> + }
> + }
[Severity: Medium]
Can __csid_addr_update_clear() and __csid_reg_update_clear() in csid_isr()
race with concurrent updates to csid->reg_update and csid->addr_update?
In camss-vfe.c, vfe_queue_buffer_v2(), vfe_enable_output_v2(), and
vfe_buf_done() hold vfe->output_lock while calling the CSID addr_update
and reg_update callbacks, which perform non-atomic read-modify-write
updates on csid->reg_update and csid->addr_update. However, csid_isr()
clears bits in csid->addr_update and csid->reg_update before
camss_buf_done() is called and without holding vfe->output_lock:
CPU0 CPU1 (<hardirq>)
vfe_queue_buffer_v2()
spin_lock_irqsave(&vfe->output_lock)
__csid_addr_update(csid, i)
csid->reg_update |= AUP_RDI(i)
writel(csid->reg_update,
CSID_LITE_RUP_AUP_CMD)
csid_isr()
if (val & INFO_RUP_DONE)
__csid_addr_update_clear(csid, i)
csid->reg_update &= ~AUP_RDI(i)
__csid_reg_update(csid, i)
csid->reg_update |= RUP_RDI(i)
writel(csid->reg_update, ...) <-- overwrites CMD with AUP_RDI(i) cleared
On CSID Lite, where RUP and AUP share csid->reg_update and the
CSID_LITE_RUP_AUP_CMD register, this race can clear a newly queued AUP bit
in hardware before it is consumed, and across multiple active RDI ports it
can lose or retain stale update bits in csid->reg_update and
csid->addr_update.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261114-add-support-for-camss-on-sm8750-v7-0-8ff2a11835f6@oss.qualcomm.com?part=10
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH v7 10/23] media: qcom: camss: csid: Add support for CSID 980
@ 2026-11-14 11:55 ` sashiko-bot
0 siblings, 0 replies; 56+ messages in thread
From: sashiko-bot @ 2026-11-14 11:55 UTC (permalink / raw)
To: Wenmeng Liu
Cc: linux-phy, devicetree, robh, conor+dt, media-ci, vkoul,
neil.armstrong, olteanv
Thank you for your contribution! Sashiko AI review found 3 potential
issues to consider:
- [High] media: qcom: camss: wrong dt_id calculation in
__csid_configure_rdi_stream()
- [Medium] media: qcom: camss: misplaced lane_cnt fallback in
camss-csid-980.c
- [Medium] media: qcom: camss: race on csid->reg_update and addr_update
in csid-980
--
commit ad1ff7fa26120bcd2005c8cf69d816599d94898f
Author: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
media: qcom: camss: csid: Add support for CSID 980
This commit adds the CSID 980 hardware operations driver and populates
the SM8750 CSID subdevice resource definitions.
> diff --git a/drivers/media/platform/qcom/camss/camss-csid-980.c b/drivers/media/platform/qcom/camss/camss-csid-980.c
> new file mode 100644
> index 0000000000000..713db25cd8c65
> --- /dev/null
> +++ b/drivers/media/platform/qcom/camss/camss-csid-980.c
> @@ -0,0 +1,466 @@
[ ... ]
> +static void __csid_configure_rx(struct csid_device *csid,
> + struct csid_phy_config *phy)
> +{
> + int val;
> +
> + val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
> + val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
> + val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX)
> + << CSI2_RX_CFG0_PHY_NUM_SEL;
> + writel(val, csid->base + CSID_CSI2_RX_CFG0);
> +
> + val = CSI2_RX_CFG1_ECC_CORRECTION_EN;
> + writel(val, csid->base + CSID_CSI2_RX_CFG1);
> +}
[ ... ]
> +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 port, u8 vc)
> +{
> + u8 lane_cnt = csid->phy.lane_cnt;
> + u32 val;
> +
> + /* Source pads matching RDI channels on hardware.
> + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc.
> + */
> + struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + port];
> + const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
> + csid->res->formats->nformats,
> + input_format->code);
> +
> + if (!lane_cnt)
> + lane_cnt = 4;
[Severity: Medium]
Was the lane_cnt fallback meant to be in __csid_configure_rx() instead of
__csid_configure_rdi_stream()?
In __csid_configure_rdi_stream(), lane_cnt is never read after being set,
which triggers a -Wunused-but-set-variable warning under W=1 (and precedes
the variable declarations below). Meanwhile, __csid_configure_rx() uses
phy->lane_cnt - 1 directly in signed int arithmetic, so if phy->lane_cnt
is 0 (for instance, when csid_set_stream() disables a stream after
csid_set_power() without an active sink link), val becomes -1 and corrupts
all fields written to CSID_CSI2_RX_CFG0.
> +
> + /*
> + * DT_ID is a two bit bitfield that is concatenated with
> + * the four least significant bits of the five bit VC
> + * bitfield to generate an internal CID value.
> + *
> + * CSID_RDI_CFG0(vc)
> + * DT_ID : 28:27
> + * VC : 26:22
> + * DT : 21:16
> + *
> + * CID : VC 3:0 << 2 | DT_ID 1:0
> + */
> + u8 dt_id = vc & 0x03;
> + u32 rdi_cfg0_offset = CSID_RDI_CFG0(port);
> + u32 rdi_cfg1_offset = CSID_RDI_CFG1(port);
> + u32 rdi_ctrl_offset = CSID_RDI_CTRL(port);
> +
> + val = RDI_CFG0_TIMESTAMP_EN;
> + val |= RDI_CFG0_TIMESTAMP_STB_SEL;
> + val |= RDI_CFG0_RETIME_BS;
> +
> + /* note: for non-RDI path, this should be format->decode_format */
> + val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
> + val |= vc << RDI_CFG0_VC;
> + val |= format->data_type << RDI_CFG0_DT;
> + val |= dt_id << RDI_CFG0_DT_ID;
> + writel(val, csid->base + rdi_cfg0_offset);
[ ... ]
> +static void csid_configure_stream(struct csid_device *csid, u8 enable)
> +{
> + u8 i, k;
> +
> + __csid_configure_rx(csid, &csid->phy);
> +
> + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) {
> + if (csid->phy.en_vc & BIT(i)) {
> + __csid_configure_rdi_stream(csid, enable, i, 0);
[Severity: High]
Should dt_id in __csid_configure_rdi_stream() be derived from port & 0x03
rather than vc & 0x03?
csid_configure_stream() always passes vc = 0 while passing the RDI channel
index i as port. Calculating dt_id from vc sets RDI_CFG0_DT_ID to 0 for
every RDI channel, so RDI1, RDI2, and RDI3 all receive internal CID 0 and
cannot stream properly, matching the issue fixed for CSID GEN3 in commit
ad136e52634d ("media: qcom: camss: Fix RDI streaming for CSID GEN3") and
for CSID GEN2 in commit 618765634cef ("media: qcom: camss: Fix RDI
streaming for CSID GEN2").
[ ... ]
> +static irqreturn_t csid_isr(int irq, void *dev)
> +{
> + struct csid_device *csid = dev;
> + u32 val, buf_done_val;
> + u8 reset_done;
> + int i;
> +
> + val = readl(csid->base + CSID_TOP_IRQ_STATUS);
> + writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
> +
> + reset_done = val & INFO_RST_DONE;
> +
> + buf_done_val = readl(csid->base + CSID_BUF_DONE_IRQ_STATUS);
> + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
> +
> + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) {
> + if (csid->phy.en_vc & BIT(i)) {
> + val = readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i));
> + writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i));
> +
> + if (val & INFO_RUP_DONE) {
> + __csid_addr_update_clear(csid, i);
> + __csid_reg_update_clear(csid, i);
> + }
> +
> + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i))
> + camss_buf_done(csid->camss, csid->id, i);
> + }
> + }
[Severity: Medium]
Can __csid_addr_update_clear() and __csid_reg_update_clear() in csid_isr()
race with concurrent updates to csid->reg_update and csid->addr_update?
In camss-vfe.c, vfe_queue_buffer_v2(), vfe_enable_output_v2(), and
vfe_buf_done() hold vfe->output_lock while calling the CSID addr_update
and reg_update callbacks, which perform non-atomic read-modify-write
updates on csid->reg_update and csid->addr_update. However, csid_isr()
clears bits in csid->addr_update and csid->reg_update before
camss_buf_done() is called and without holding vfe->output_lock:
CPU0 CPU1 (<hardirq>)
vfe_queue_buffer_v2()
spin_lock_irqsave(&vfe->output_lock)
__csid_addr_update(csid, i)
csid->reg_update |= AUP_RDI(i)
writel(csid->reg_update,
CSID_LITE_RUP_AUP_CMD)
csid_isr()
if (val & INFO_RUP_DONE)
__csid_addr_update_clear(csid, i)
csid->reg_update &= ~AUP_RDI(i)
__csid_reg_update(csid, i)
csid->reg_update |= RUP_RDI(i)
writel(csid->reg_update, ...) <-- overwrites CMD with AUP_RDI(i) cleared
On CSID Lite, where RUP and AUP share csid->reg_update and the
CSID_LITE_RUP_AUP_CMD register, this race can clear a newly queued AUP bit
in hardware before it is consumed, and across multiple active RDI ports it
can lose or retain stale update bits in csid->reg_update and
csid->addr_update.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261114-add-support-for-camss-on-sm8750-v7-0-8ff2a11835f6@oss.qualcomm.com?part=10
^ permalink raw reply [flat|nested] 56+ messages in thread
end of thread, other threads:[~2026-11-14 11:55 UTC | newest]
Thread overview: 56+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-11-14 11:29 [PATCH v7 00/23] Add CAMSS support for SM8750 and Eliza Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:29 ` [PATCH v7 01/23] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add SM8750 CSI2 PHY Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:29 ` [PATCH v7 02/23] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add Eliza " Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:29 ` [PATCH v7 03/23] dt-bindings: media: qcom,sm8750-camss: Add SM8750 CAMSS Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:42 ` sashiko-bot
2026-11-14 11:42 ` sashiko-bot
2026-11-14 11:29 ` [PATCH v7 04/23] dt-bindings: media: qcom,eliza-camss: Add Eliza CAMSS Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:43 ` sashiko-bot
2026-11-14 11:43 ` sashiko-bot
2026-11-14 11:29 ` [PATCH v7 05/23] dt-bindings: i2c: qcom-cci: Document Eliza compatible Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:29 ` [PATCH v7 06/23] phy: qcom-mipi-csi2: Add SM8750 support Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:29 ` [PATCH v7 07/23] media: qcom: camss: Add SM8750 compatible Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:29 ` [PATCH v7 08/23] media: qcom: camss: Add PM clock definitions for SM8750 Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:29 ` [PATCH v7 09/23] media: qcom: camss: csid: Scale the clocks with the CSI-2 link rate Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:29 ` [PATCH v7 10/23] media: qcom: camss: csid: Add support for CSID 980 Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:55 ` sashiko-bot
2026-11-14 11:55 ` sashiko-bot
2026-11-14 11:29 ` [PATCH v7 11/23] media: qcom: camss: vfe: Add support for VFE 980 Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:42 ` sashiko-bot
2026-11-14 11:42 ` sashiko-bot
2026-11-14 11:29 ` [PATCH v7 12/23] media: qcom: camss: tpg: Add support for v2.3.0 TPG Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:29 ` [PATCH v7 13/23] media: qcom: camss: Add Eliza compatible Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:29 ` [PATCH v7 14/23] arm64: dts: qcom: sm8750: Add CAMSS and CSIPHY block definitions Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:29 ` [PATCH v7 15/23] arm64: dts: qcom: sm8750: Add CCI definitions Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:29 ` [PATCH v7 16/23] arm64: dts: qcom: sm8750: Add camera MCLK pinctrl Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:29 ` [PATCH v7 17/23] arm64: dts: qcom: sm8750-qrd: Enable S5KJN1 camera sensor Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:29 ` [PATCH v7 18/23] arm64: dts: qcom: eliza: Add CAMSS and CSIPHY block definitions Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:29 ` [PATCH v7 19/23] arm64: dts: qcom: eliza: Add CCI definitions Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:29 ` [PATCH v7 20/23] arm64: dts: qcom: eliza: Add camera MCLK pinctrl Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:29 ` [PATCH v7 21/23] arm64: dts: qcom: eliza-mtp: Add PM8010 PMICs Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:29 ` [PATCH v7 22/23] arm64: dts: qcom: eliza-mtp: Enable rear camera Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
2026-11-14 11:29 ` [PATCH v7 23/23] arm64: dts: qcom: eliza-evk-imx577-camera: Add DT overlay Wenmeng Liu
2026-11-14 11:29 ` Wenmeng Liu
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