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From: <sunpeng.li-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Chris Park <Chris.Park-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 12/26] drm/amd/display: Move link functions from dc to dc_link
Date: Mon, 27 May 2019 15:50:51 -0400	[thread overview]
Message-ID: <1558986665-12964-13-git-send-email-sunpeng.li@amd.com> (raw)
In-Reply-To: <1558986665-12964-1-git-send-email-sunpeng.li-5C7GfCeVMHo@public.gmane.org>

From: Chris Park <Chris.Park@amd.com>

[Why]
link-specific functions should reside in dc_link.c

[How]
Move them there.

Signed-off-by: Chris Park <Chris.Park@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c      | 122 -------------------------
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 127 +++++++++++++++++++++++++-
 2 files changed, 126 insertions(+), 123 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 5012b675..49be328 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -490,128 +490,6 @@ void dc_stream_set_static_screen_events(struct dc *dc,
 	dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
 }
 
-void dc_link_set_drive_settings(struct dc *dc,
-				struct link_training_settings *lt_settings,
-				const struct dc_link *link)
-{
-
-	int i;
-
-	for (i = 0; i < dc->link_count; i++) {
-		if (dc->links[i] == link)
-			break;
-	}
-
-	if (i >= dc->link_count)
-		ASSERT_CRITICAL(false);
-
-	dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
-}
-
-void dc_link_perform_link_training(struct dc *dc,
-				   struct dc_link_settings *link_setting,
-				   bool skip_video_pattern)
-{
-	int i;
-
-	for (i = 0; i < dc->link_count; i++)
-		dc_link_dp_perform_link_training(
-			dc->links[i],
-			link_setting,
-			skip_video_pattern);
-}
-
-void dc_link_set_preferred_link_settings(struct dc *dc,
-					 struct dc_link_settings *link_setting,
-					 struct dc_link *link)
-{
-	int i;
-	struct pipe_ctx *pipe;
-	struct dc_stream_state *link_stream;
-	struct dc_link_settings store_settings = *link_setting;
-
-	link->preferred_link_setting = store_settings;
-
-	/* Retrain with preferred link settings only relevant for
-	 * DP signal type
-	 */
-	if (!dc_is_dp_signal(link->connector_signal))
-		return;
-
-	for (i = 0; i < MAX_PIPES; i++) {
-		pipe = &dc->current_state->res_ctx.pipe_ctx[i];
-		if (pipe->stream && pipe->stream->link) {
-			if (pipe->stream->link == link)
-				break;
-		}
-	}
-
-	/* Stream not found */
-	if (i == MAX_PIPES)
-		return;
-
-	link_stream = link->dc->current_state->res_ctx.pipe_ctx[i].stream;
-
-	/* Cannot retrain link if backend is off */
-	if (link_stream->dpms_off)
-		return;
-
-	if (link_stream)
-		decide_link_settings(link_stream, &store_settings);
-
-	if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
-		(store_settings.link_rate != LINK_RATE_UNKNOWN))
-		dp_retrain_link_dp_test(link, &store_settings, false);
-}
-
-void dc_link_enable_hpd(const struct dc_link *link)
-{
-	dc_link_dp_enable_hpd(link);
-}
-
-void dc_link_disable_hpd(const struct dc_link *link)
-{
-	dc_link_dp_disable_hpd(link);
-}
-
-
-void dc_link_set_test_pattern(struct dc_link *link,
-			      enum dp_test_pattern test_pattern,
-			      const struct link_training_settings *p_link_settings,
-			      const unsigned char *p_custom_pattern,
-			      unsigned int cust_pattern_size)
-{
-	if (link != NULL)
-		dc_link_dp_set_test_pattern(
-			link,
-			test_pattern,
-			p_link_settings,
-			p_custom_pattern,
-			cust_pattern_size);
-}
-
-uint32_t dc_link_bandwidth_kbps(
-	const struct dc_link *link,
-	const struct dc_link_settings *link_setting)
-{
-	uint32_t link_bw_kbps = link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
-
-	link_bw_kbps *= 8;   /* 8 bits per byte*/
-	link_bw_kbps *= link_setting->lane_count;
-
-	return link_bw_kbps;
-
-}
-
-const struct dc_link_settings *dc_link_get_link_cap(
-		const struct dc_link *link)
-{
-	if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
-			link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
-		return &link->preferred_link_setting;
-	return &link->verified_link_cap;
-}
-
 static void destruct(struct dc *dc)
 {
 	dc_release_state(dc->current_state);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 90a1cdc..c9e0b12 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2339,7 +2339,8 @@ void core_link_resume(struct dc_link *link)
 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
 {
 	struct fixed31_32 mbytes_per_sec;
-	uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link, &stream->link->cur_link_settings);
+	uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
+			&stream->link->cur_link_settings);
 	link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
 
 	mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
@@ -2858,3 +2859,127 @@ uint32_t dc_bandwidth_in_kbps_from_timing(
 	return kbps;
 
 }
+
+void dc_link_set_drive_settings(struct dc *dc,
+				struct link_training_settings *lt_settings,
+				const struct dc_link *link)
+{
+
+	int i;
+
+	for (i = 0; i < dc->link_count; i++) {
+		if (dc->links[i] == link)
+			break;
+	}
+
+	if (i >= dc->link_count)
+		ASSERT_CRITICAL(false);
+
+	dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
+}
+
+void dc_link_perform_link_training(struct dc *dc,
+				   struct dc_link_settings *link_setting,
+				   bool skip_video_pattern)
+{
+	int i;
+
+	for (i = 0; i < dc->link_count; i++)
+		dc_link_dp_perform_link_training(
+			dc->links[i],
+			link_setting,
+			skip_video_pattern);
+}
+
+void dc_link_set_preferred_link_settings(struct dc *dc,
+					 struct dc_link_settings *link_setting,
+					 struct dc_link *link)
+{
+	int i;
+	struct pipe_ctx *pipe;
+	struct dc_stream_state *link_stream;
+	struct dc_link_settings store_settings = *link_setting;
+
+	link->preferred_link_setting = store_settings;
+
+	/* Retrain with preferred link settings only relevant for
+	 * DP signal type
+	 */
+	if (!dc_is_dp_signal(link->connector_signal))
+		return;
+
+	for (i = 0; i < MAX_PIPES; i++) {
+		pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+		if (pipe->stream && pipe->stream->link) {
+			if (pipe->stream->link == link)
+				break;
+		}
+	}
+
+	/* Stream not found */
+	if (i == MAX_PIPES)
+		return;
+
+	link_stream = link->dc->current_state->res_ctx.pipe_ctx[i].stream;
+
+	/* Cannot retrain link if backend is off */
+	if (link_stream->dpms_off)
+		return;
+
+	if (link_stream)
+		decide_link_settings(link_stream, &store_settings);
+
+	if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
+		(store_settings.link_rate != LINK_RATE_UNKNOWN))
+		dp_retrain_link_dp_test(link, &store_settings, false);
+}
+
+void dc_link_enable_hpd(const struct dc_link *link)
+{
+	dc_link_dp_enable_hpd(link);
+}
+
+void dc_link_disable_hpd(const struct dc_link *link)
+{
+	dc_link_dp_disable_hpd(link);
+}
+
+
+void dc_link_set_test_pattern(struct dc_link *link,
+			      enum dp_test_pattern test_pattern,
+			      const struct link_training_settings *p_link_settings,
+			      const unsigned char *p_custom_pattern,
+			      unsigned int cust_pattern_size)
+{
+	if (link != NULL)
+		dc_link_dp_set_test_pattern(
+			link,
+			test_pattern,
+			p_link_settings,
+			p_custom_pattern,
+			cust_pattern_size);
+}
+
+uint32_t dc_link_bandwidth_kbps(
+	const struct dc_link *link,
+	const struct dc_link_settings *link_setting)
+{
+	uint32_t link_bw_kbps =
+		link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
+
+	link_bw_kbps *= 8;   /* 8 bits per byte*/
+	link_bw_kbps *= link_setting->lane_count;
+
+	return link_bw_kbps;
+
+}
+
+const struct dc_link_settings *dc_link_get_link_cap(
+		const struct dc_link *link)
+{
+	if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
+			link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
+		return &link->preferred_link_setting;
+	return &link->verified_link_cap;
+}
+
-- 
2.7.4

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  parent reply	other threads:[~2019-05-27 19:50 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-27 19:50 [PATCH 00/26] DC Patches 27 May 2019 sunpeng.li-5C7GfCeVMHo
     [not found] ` <1558986665-12964-1-git-send-email-sunpeng.li-5C7GfCeVMHo@public.gmane.org>
2019-05-27 19:50   ` [PATCH 01/26] drm/amd/display: make clk mgr soc specific sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 02/26] drm/amd/display: Don't use ROM for output TF if GAMMA_CS_TFM_1D sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 03/26] drm/amd/display: Implement CM dealpha and bias interfaces sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 04/26] drm/amd/display: Move CLK_BASE_INNER macro sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 05/26] drm/amd/display: assign new stream id in dc_copy_stream sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 06/26] drm/amd/display: Disable audio stream only if it's currently enabled sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 07/26] drm/amd/display: Add GSL source select registers sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 08/26] drm/amd/display: Ensure DRR triggers in BP sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 09/26] drm/amd/display: disable PSR/ABM before destroy DMCU struct sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 10/26] drm/amd/display: move clk_mgr files to right place sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 11/26] drm/amd/display: Add min_dcfclk_mhz field to bb overrides sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` sunpeng.li-5C7GfCeVMHo [this message]
2019-05-27 19:50   ` [PATCH 13/26] drm/amd/display: 3.2.32 sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 14/26] drm/amd/display: fix calculation of total_data_read_bandwidth sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 15/26] drm/amd/display: fix crash on setmode when mode is close to bw limit sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 16/26] drm/amd/display: do not power on eDP power rail early sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 17/26] drm/amd/display: Fix type of pp_smu_wm_set_range struct sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 18/26] drm/amd/display: Refactor clk_mgr functions sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 19/26] drm/amd/display: Add writeback_config to VBA vars sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 20/26] drm/amd/display: Modified AUX_DPHY_RX_CONTROL0 sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 21/26] drm/amd/display: Refactor DIO stream encoder sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 22/26] drm/amd/display: fix issues with bad AUX reply on some displays sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 23/26] drm/amd/display: Increase Backlight Gain Step Size sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 24/26] drm/amd/display: Reset planes for color management changes sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 25/26] drm/amd/display: CS_TFM_1D only applied post EOTF sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 26/26] drm/amd/display: program manual trigger only for bottom most pipe sunpeng.li-5C7GfCeVMHo

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