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From: <sunpeng.li-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Krunoslav Kovac <Krunoslav.Kovac-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 07/26] drm/amd/display: Add GSL source select registers
Date: Mon, 27 May 2019 15:50:46 -0400	[thread overview]
Message-ID: <1558986665-12964-8-git-send-email-sunpeng.li@amd.com> (raw)
In-Reply-To: <1558986665-12964-1-git-send-email-sunpeng.li-5C7GfCeVMHo@public.gmane.org>

From: Krunoslav Kovac <Krunoslav.Kovac@amd.com>

GSL is a form of locking that can be used to synchronize pipes in a
pipe-split configurations when async flip is used. Add the registers
here.

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index 651b8ca..70fd56f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -84,7 +84,8 @@
 	SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
 	SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
 	SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
-	SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst)
+	SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
+	SR(GSL_SOURCE_SELECT)
 
 #define TG_COMMON_REG_LIST_DCN1_0(inst) \
 	TG_COMMON_REG_LIST_DCN(inst),\
@@ -156,6 +157,7 @@ struct dcn_optc_registers {
 	uint32_t OTG_CRC0_WINDOWA_Y_CONTROL;
 	uint32_t OTG_CRC0_WINDOWB_X_CONTROL;
 	uint32_t OTG_CRC0_WINDOWB_Y_CONTROL;
+	uint32_t GSL_SOURCE_SELECT;
 };
 
 #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
@@ -266,7 +268,10 @@ struct dcn_optc_registers {
 	SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
 	SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
 	SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
-	SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh)
+	SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
+	SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
+	SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
+	SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh)
 
 
 #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
@@ -413,7 +418,10 @@ struct dcn_optc_registers {
 	type OTG_CRC0_WINDOWB_X_START;\
 	type OTG_CRC0_WINDOWB_X_END;\
 	type OTG_CRC0_WINDOWB_Y_START;\
-	type OTG_CRC0_WINDOWB_Y_END;
+	type OTG_CRC0_WINDOWB_Y_END;\
+	type GSL0_READY_SOURCE_SEL;\
+	type GSL1_READY_SOURCE_SEL;\
+	type GSL2_READY_SOURCE_SEL;
 
 
 #define TG_REG_FIELD_LIST(type) \
-- 
2.7.4

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  parent reply	other threads:[~2019-05-27 19:50 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-27 19:50 [PATCH 00/26] DC Patches 27 May 2019 sunpeng.li-5C7GfCeVMHo
     [not found] ` <1558986665-12964-1-git-send-email-sunpeng.li-5C7GfCeVMHo@public.gmane.org>
2019-05-27 19:50   ` [PATCH 01/26] drm/amd/display: make clk mgr soc specific sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 02/26] drm/amd/display: Don't use ROM for output TF if GAMMA_CS_TFM_1D sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 03/26] drm/amd/display: Implement CM dealpha and bias interfaces sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 04/26] drm/amd/display: Move CLK_BASE_INNER macro sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 05/26] drm/amd/display: assign new stream id in dc_copy_stream sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 06/26] drm/amd/display: Disable audio stream only if it's currently enabled sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` sunpeng.li-5C7GfCeVMHo [this message]
2019-05-27 19:50   ` [PATCH 08/26] drm/amd/display: Ensure DRR triggers in BP sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 09/26] drm/amd/display: disable PSR/ABM before destroy DMCU struct sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 10/26] drm/amd/display: move clk_mgr files to right place sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 11/26] drm/amd/display: Add min_dcfclk_mhz field to bb overrides sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 12/26] drm/amd/display: Move link functions from dc to dc_link sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 13/26] drm/amd/display: 3.2.32 sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 14/26] drm/amd/display: fix calculation of total_data_read_bandwidth sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 15/26] drm/amd/display: fix crash on setmode when mode is close to bw limit sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 16/26] drm/amd/display: do not power on eDP power rail early sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 17/26] drm/amd/display: Fix type of pp_smu_wm_set_range struct sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 18/26] drm/amd/display: Refactor clk_mgr functions sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 19/26] drm/amd/display: Add writeback_config to VBA vars sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 20/26] drm/amd/display: Modified AUX_DPHY_RX_CONTROL0 sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 21/26] drm/amd/display: Refactor DIO stream encoder sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 22/26] drm/amd/display: fix issues with bad AUX reply on some displays sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 23/26] drm/amd/display: Increase Backlight Gain Step Size sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 24/26] drm/amd/display: Reset planes for color management changes sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 25/26] drm/amd/display: CS_TFM_1D only applied post EOTF sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 26/26] drm/amd/display: program manual trigger only for bottom most pipe sunpeng.li-5C7GfCeVMHo

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