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From: <sunpeng.li-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Anthony Koo <Anthony.Koo-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 16/26] drm/amd/display: do not power on eDP power rail early
Date: Mon, 27 May 2019 15:50:55 -0400	[thread overview]
Message-ID: <1558986665-12964-17-git-send-email-sunpeng.li@amd.com> (raw)
In-Reply-To: <1558986665-12964-1-git-send-email-sunpeng.li-5C7GfCeVMHo@public.gmane.org>

From: Anthony Koo <Anthony.Koo@amd.com>

[Why]
Modern Standby may toggle display adapter state between D0
and D3 state unpredictably.
But events that cause transition to D0 are not always resulting
in a display light up scenario.

Modern eDP panels should be able to power on panel logic
quickly upon VDD going high. Based on spec, the T3 time
between VDD on and HPD high can be between 0 and 80 ms.

Doing any tricky sorts of optimization by powering on panel
VDD early during D0 transition on can negatively impact other
features due to unnecessary power drain and toggling when
final system state does not intend for the panel to be lit up.

We need OEMs to source higher end panels that have T3 time
close to 0 if they want quick S3/Modern Standby resume times.

[How]
Remove panel VDD power on in init_hw

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 ---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c   | 3 ---
 2 files changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index f3dd117..3042741 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2352,9 +2352,6 @@ static void init_hw(struct dc *dc)
 		 * default signal on connector). */
 		struct dc_link *link = dc->links[i];
 
-		if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
-			dc->hwss.edp_power_control(link, true);
-
 		link->link_enc->funcs->hw_init(link->link_enc);
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index c2207df..821a280 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1102,9 +1102,6 @@ static void dcn10_init_hw(struct dc *dc)
 		 */
 		struct dc_link *link = dc->links[i];
 
-		if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
-			dc->hwss.edp_power_control(link, true);
-
 		link->link_enc->funcs->hw_init(link->link_enc);
 
 		/* Check for enabled DIG to identify enabled display */
-- 
2.7.4

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amd-gfx@lists.freedesktop.org
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  parent reply	other threads:[~2019-05-27 19:50 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-27 19:50 [PATCH 00/26] DC Patches 27 May 2019 sunpeng.li-5C7GfCeVMHo
     [not found] ` <1558986665-12964-1-git-send-email-sunpeng.li-5C7GfCeVMHo@public.gmane.org>
2019-05-27 19:50   ` [PATCH 01/26] drm/amd/display: make clk mgr soc specific sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 02/26] drm/amd/display: Don't use ROM for output TF if GAMMA_CS_TFM_1D sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 03/26] drm/amd/display: Implement CM dealpha and bias interfaces sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 04/26] drm/amd/display: Move CLK_BASE_INNER macro sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 05/26] drm/amd/display: assign new stream id in dc_copy_stream sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 06/26] drm/amd/display: Disable audio stream only if it's currently enabled sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 07/26] drm/amd/display: Add GSL source select registers sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 08/26] drm/amd/display: Ensure DRR triggers in BP sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 09/26] drm/amd/display: disable PSR/ABM before destroy DMCU struct sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 10/26] drm/amd/display: move clk_mgr files to right place sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 11/26] drm/amd/display: Add min_dcfclk_mhz field to bb overrides sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 12/26] drm/amd/display: Move link functions from dc to dc_link sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 13/26] drm/amd/display: 3.2.32 sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 14/26] drm/amd/display: fix calculation of total_data_read_bandwidth sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 15/26] drm/amd/display: fix crash on setmode when mode is close to bw limit sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` sunpeng.li-5C7GfCeVMHo [this message]
2019-05-27 19:50   ` [PATCH 17/26] drm/amd/display: Fix type of pp_smu_wm_set_range struct sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 18/26] drm/amd/display: Refactor clk_mgr functions sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 19/26] drm/amd/display: Add writeback_config to VBA vars sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 20/26] drm/amd/display: Modified AUX_DPHY_RX_CONTROL0 sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 21/26] drm/amd/display: Refactor DIO stream encoder sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 22/26] drm/amd/display: fix issues with bad AUX reply on some displays sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 23/26] drm/amd/display: Increase Backlight Gain Step Size sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 24/26] drm/amd/display: Reset planes for color management changes sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 25/26] drm/amd/display: CS_TFM_1D only applied post EOTF sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 26/26] drm/amd/display: program manual trigger only for bottom most pipe sunpeng.li-5C7GfCeVMHo

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