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From: <sunpeng.li-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Eric Yang <Eric.Yang2-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 18/26] drm/amd/display: Refactor clk_mgr functions
Date: Mon, 27 May 2019 15:50:57 -0400	[thread overview]
Message-ID: <1558986665-12964-19-git-send-email-sunpeng.li@amd.com> (raw)
In-Reply-To: <1558986665-12964-1-git-send-email-sunpeng.li-5C7GfCeVMHo@public.gmane.org>

From: Eric Yang <Eric.Yang2@amd.com>

[Why]
Some HW specific implementations can be pulled out into clk_mgr.c.

[How]
* Pull get_active_display_cnt out to clk_mgr.
* Pull out shared logic in set_dispclk and set_dprefclk

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c   | 25 ++++++++++
 .../drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 25 +---------
 .../dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c       | 58 +++++++++++-----------
 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h    |  5 ++
 .../drm/amd/display/dc/inc/hw/clk_mgr_internal.h   |  4 ++
 5 files changed, 65 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index ce24614..08b27c7 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -35,6 +35,31 @@
 #include "dcn10/rv1_clk_mgr.h"
 #include "dcn10/rv2_clk_mgr.h"
 
+
+int clk_mgr_helper_get_active_display_cnt(
+		struct dc *dc,
+		struct dc_state *context)
+{
+	int i, display_count;
+
+	display_count = 0;
+	for (i = 0; i < context->stream_count; i++) {
+		const struct dc_stream_state *stream = context->streams[i];
+
+		/*
+		 * Only notify active stream or virtual stream.
+		 * Need to notify virtual stream to work around
+		 * headless case. HPD does not fire when system is in
+		 * S0i2.
+		 */
+		if (!stream->dpms_off || stream->signal == SIGNAL_TYPE_VIRTUAL)
+			display_count++;
+	}
+
+	return display_count;
+}
+
+
 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg)
 {
 	struct hw_asic_id asic_id = ctx->asic_id;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
index a3f953c..31db9b55 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
@@ -114,29 +114,6 @@ static void ramp_up_dispclk_with_dpp(struct clk_mgr_internal *clk_mgr, struct dc
 	clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz;
 }
 
-static int get_active_display_cnt(
-		struct dc *dc,
-		struct dc_state *context)
-{
-	int i, display_count;
-
-	display_count = 0;
-	for (i = 0; i < context->stream_count; i++) {
-		const struct dc_stream_state *stream = context->streams[i];
-
-		/*
-		 * Only notify active stream or virtual stream.
-		 * Need to notify virtual stream to work around
-		 * headless case. HPD does not fire when system is in
-		 * S0i2.
-		 */
-		if (!stream->dpms_off || stream->signal == SIGNAL_TYPE_VIRTUAL)
-			display_count++;
-	}
-
-	return display_count;
-}
-
 static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
 			struct dc_state *context,
 			bool safe_to_lower)
@@ -156,7 +133,7 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
 
 	pp_smu = &clk_mgr->pp_smu->rv_funcs;
 
-	display_count = get_active_display_cnt(dc, context);
+	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
 
 	if (display_count == 0)
 		enter_display_off = true;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
index 1960870..1897e91 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
@@ -68,57 +68,59 @@ static const struct IP_BASE MP1_BASE  = { { { { 0x00016000, 0, 0, 0, 0 } },
 #define VBIOSSMC_MSG_SetDispclkFreq           0x4
 #define VBIOSSMC_MSG_SetDprefclkFreq          0x5
 
-int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
+int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param)
 {
-
-	int actual_dispclk_set_khz = -1;
-	struct dc *core_dc = clk_mgr->base.ctx->dc;
-	struct dmcu *dmcu = core_dc->res_pool->dmcu;
-
 	/* First clear response register */
-	//dm_write_reg(ctx, mmMP1_SMN_C2PMSG_91, 0);
 	REG_WRITE(MP1_SMN_C2PMSG_91, 0);
 
 	/* Set the parameter register for the SMU message, unit is Mhz */
-	//dm_write_reg(ctx, mmMP1_SMN_C2PMSG_83, requested_dispclk_khz / 1000);
-	REG_WRITE(MP1_SMN_C2PMSG_83, requested_dispclk_khz / 1000);
+	REG_WRITE(MP1_SMN_C2PMSG_83, param);
 
 	/* Trigger the message transaction by writing the message ID */
-	//dm_write_reg(ctx, mmMP1_SMN_C2PMSG_67, VBIOSSMC_MSG_SetDispclkFreq);
-	REG_WRITE(MP1_SMN_C2PMSG_67, VBIOSSMC_MSG_SetDispclkFreq);
+	REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
 
 	REG_WAIT(MP1_SMN_C2PMSG_91, CONTENT, 1, 10, 200000);
 
 	/* Actual dispclk set is returned in the parameter register */
-	actual_dispclk_set_khz = REG_READ(MP1_SMN_C2PMSG_83) * 1000;
+	return REG_READ(MP1_SMN_C2PMSG_83);
+}
+
+int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
+{
+	int actual_dispclk_set_mhz = -1;
+	struct dc *core_dc = clk_mgr->base.ctx->dc;
+	struct dmcu *dmcu = core_dc->res_pool->dmcu;
+
+	/*  Unit of SMU msg parameter is Mhz */
+	actual_dispclk_set_mhz = rv1_vbios_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetDispclkFreq,
+			requested_dispclk_khz / 1000);
+
+	/* Actual dispclk set is returned in the parameter register */
+	actual_dispclk_set_mhz = REG_READ(MP1_SMN_C2PMSG_83) * 1000;
 
 	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
 		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
-			if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_khz)
+			if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)
 				dmcu->funcs->set_psr_wait_loop(dmcu,
-						actual_dispclk_set_khz / 1000 / 7);
+						actual_dispclk_set_mhz / 7);
 		}
 	}
 
-	return actual_dispclk_set_khz;
+	return actual_dispclk_set_mhz * 1000;
 }
 
 int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
 {
-	int actual_dprefclk_set_khz = -1;
-
-	REG_WRITE(MP1_SMN_C2PMSG_91, 0);
-
-	/* Set the parameter register for the SMU message */
-	REG_WRITE(MP1_SMN_C2PMSG_83, clk_mgr->base.dprefclk_khz / 1000);
+	int actual_dprefclk_set_mhz = -1;
 
-	/* Trigger the message transaction by writing the message ID */
-	REG_WRITE(MP1_SMN_C2PMSG_67, VBIOSSMC_MSG_SetDprefclkFreq);
-
-	/* Wait for SMU response */
-	REG_WAIT(MP1_SMN_C2PMSG_91, CONTENT, 1, 10, 200000);
+	actual_dprefclk_set_mhz = rv1_vbios_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetDprefclkFreq,
+			clk_mgr->base.dprefclk_khz / 1000);
 
-	actual_dprefclk_set_khz = REG_READ(MP1_SMN_C2PMSG_83) * 1000;
+	/* TODO: add code for programing DP DTO, currently this is down by command table */
 
-	return actual_dprefclk_set_khz;
+	return actual_dprefclk_set_mhz * 1000;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index 0a2346a..721e131 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -30,6 +30,10 @@
 
 /* Public interfaces */
 
+struct clk_states {
+	uint32_t dprefclk_khz;
+};
+
 struct clk_mgr_funcs {
 	/*
 	 * This function should set new clocks based on the input "safe_to_lower".
@@ -46,6 +50,7 @@ struct clk_mgr_funcs {
 
 	void (*init_clocks)(struct clk_mgr *clk_mgr);
 
+	void (*enable_pme_wa) (struct clk_mgr *clk_mgr);
 };
 
 void dce121_clock_patch_xgmi_ss_info(struct clk_mgr *clk_mgr_base);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index 53f6286..6e189b1 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -202,6 +202,10 @@ static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_cl
 	return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk);
 }
 
+int clk_mgr_helper_get_active_display_cnt(
+		struct dc *dc,
+		struct dc_state *context);
+
 
 
 #endif //__DAL_CLK_MGR_INTERNAL_H__
-- 
2.7.4

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  parent reply	other threads:[~2019-05-27 19:50 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-27 19:50 [PATCH 00/26] DC Patches 27 May 2019 sunpeng.li-5C7GfCeVMHo
     [not found] ` <1558986665-12964-1-git-send-email-sunpeng.li-5C7GfCeVMHo@public.gmane.org>
2019-05-27 19:50   ` [PATCH 01/26] drm/amd/display: make clk mgr soc specific sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 02/26] drm/amd/display: Don't use ROM for output TF if GAMMA_CS_TFM_1D sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 03/26] drm/amd/display: Implement CM dealpha and bias interfaces sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 04/26] drm/amd/display: Move CLK_BASE_INNER macro sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 05/26] drm/amd/display: assign new stream id in dc_copy_stream sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 06/26] drm/amd/display: Disable audio stream only if it's currently enabled sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 07/26] drm/amd/display: Add GSL source select registers sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 08/26] drm/amd/display: Ensure DRR triggers in BP sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 09/26] drm/amd/display: disable PSR/ABM before destroy DMCU struct sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 10/26] drm/amd/display: move clk_mgr files to right place sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 11/26] drm/amd/display: Add min_dcfclk_mhz field to bb overrides sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 12/26] drm/amd/display: Move link functions from dc to dc_link sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 13/26] drm/amd/display: 3.2.32 sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 14/26] drm/amd/display: fix calculation of total_data_read_bandwidth sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 15/26] drm/amd/display: fix crash on setmode when mode is close to bw limit sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 16/26] drm/amd/display: do not power on eDP power rail early sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 17/26] drm/amd/display: Fix type of pp_smu_wm_set_range struct sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` sunpeng.li-5C7GfCeVMHo [this message]
2019-05-27 19:50   ` [PATCH 19/26] drm/amd/display: Add writeback_config to VBA vars sunpeng.li-5C7GfCeVMHo
2019-05-27 19:50   ` [PATCH 20/26] drm/amd/display: Modified AUX_DPHY_RX_CONTROL0 sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 21/26] drm/amd/display: Refactor DIO stream encoder sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 22/26] drm/amd/display: fix issues with bad AUX reply on some displays sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 23/26] drm/amd/display: Increase Backlight Gain Step Size sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 24/26] drm/amd/display: Reset planes for color management changes sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 25/26] drm/amd/display: CS_TFM_1D only applied post EOTF sunpeng.li-5C7GfCeVMHo
2019-05-27 19:51   ` [PATCH 26/26] drm/amd/display: program manual trigger only for bottom most pipe sunpeng.li-5C7GfCeVMHo

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