* [PATCH 00/16] Add support for Raven2
@ 2018-09-12 19:29 Alex Deucher
[not found] ` <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 20+ messages in thread
From: Alex Deucher @ 2018-09-12 19:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
Raven2 is a new Raven APU.
Alex Deucher (1):
drm/amdgpu: set external rev id for raven2
Bhawanpreet Lakha (2):
drm/amd/display: Add Raven2 definitions in dc
drm/amd/display: Add DC config flag for Raven2 (v2)
Evan Quan (3):
drm/amd/powerplay: update smu10_verify_smc_interface() to be raven2
compatible
drm/amd/powerplay: round up the Mhz convertion (v2)
drm/amd/powerplay: disable raven2 force dpm level support (v2)
Feifei Xu (6):
drm/amdgpu: add raven2 to gpu_info firmware
drm/amdgpu: add raven2 vcn firmware support
drm/amdgpu/sdma4: specify raven2 firmware.
drm/amdgpu/sdma4: Add raven2 golden setting
drm/amdgpu/gfx9: add support for raven2 gfx firmware
drm/amdgpu/gfx9: add raven2 golden setting
Huang Rui (3):
drm/amdgpu: move get_rev_id at first before load gpu_info firmware
drm/amdgpu: fix the VM fault while write at the top of the invisible
vram
drm/amdgpu: set CG flags for raven2 (v2)
Likun Gao (1):
drm/amdgpu: add psp support for raven2
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 52 ++++++++++++++-
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 15 ++++-
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 15 ++++-
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 27 ++++++--
drivers/gpu/drm/amd/amdgpu/soc15.c | 75 ++++++++++++++--------
drivers/gpu/drm/amd/display/Kconfig | 6 ++
.../amd/display/dc/bios/command_table_helper2.c | 5 ++
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 ++
.../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 ++
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 36 ++++++++++-
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 5 ++
drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 5 ++
drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 4 ++
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 7 ++
drivers/gpu/drm/amd/display/include/dal_types.h | 3 +
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 16 ++++-
.../gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c | 3 +-
20 files changed, 261 insertions(+), 46 deletions(-)
--
2.13.6
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 01/16] drm/amdgpu: move get_rev_id at first before load gpu_info firmware
[not found] ` <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
@ 2018-09-12 19:29 ` Alex Deucher
2018-09-12 19:29 ` [PATCH 02/16] drm/amdgpu: set external rev id for raven2 Alex Deucher
` (14 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Alex Deucher @ 2018-09-12 19:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Rev id is used for identifying Raven2 series of chips. So we would better to
initialize it at first.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index e338ad6d0d20..794cfe4a52d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -479,6 +479,11 @@ static const struct amdgpu_ip_block_version vega10_common_ip_block =
.funcs = &soc15_common_ip_funcs,
};
+static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
+{
+ return adev->nbio_funcs->get_rev_id(adev);
+}
+
int soc15_set_ip_blocks(struct amdgpu_device *adev)
{
/* Set IP register base before any HW register access */
@@ -507,6 +512,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
adev->df_funcs = &df_v3_6_funcs;
else
adev->df_funcs = &df_v1_7_funcs;
+
+ adev->rev_id = soc15_get_rev_id(adev);
adev->nbio_funcs->detect_hw_virt(adev);
if (amdgpu_sriov_vf(adev))
@@ -581,11 +588,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
return 0;
}
-static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
-{
- return adev->nbio_funcs->get_rev_id(adev);
-}
-
static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
{
adev->nbio_funcs->hdp_flush(adev, ring);
@@ -642,7 +644,6 @@ static int soc15_common_early_init(void *handle)
adev->asic_funcs = &soc15_asic_funcs;
- adev->rev_id = soc15_get_rev_id(adev);
adev->external_rev_id = 0xFF;
switch (adev->asic_type) {
case CHIP_VEGA10:
--
2.13.6
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 02/16] drm/amdgpu: set external rev id for raven2
[not found] ` <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2018-09-12 19:29 ` [PATCH 01/16] drm/amdgpu: move get_rev_id at first before load gpu_info firmware Alex Deucher
@ 2018-09-12 19:29 ` Alex Deucher
2018-09-12 19:29 ` [PATCH 03/16] drm/amdgpu: add raven2 to gpu_info firmware Alex Deucher
` (13 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Alex Deucher @ 2018-09-12 19:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
It's different from raven1.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 794cfe4a52d1..0a935604ec9e 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -742,7 +742,10 @@ static int soc15_common_early_init(void *handle)
AMD_PG_SUPPORT_CP |
AMD_PG_SUPPORT_RLC_SMU_HS;
- adev->external_rev_id = 0x1;
+ if (adev->rev_id >= 0x8)
+ adev->external_rev_id = adev->rev_id + 0x81;
+ else
+ adev->external_rev_id = 0x1;
break;
case CHIP_PICASSO:
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS |
--
2.13.6
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 03/16] drm/amdgpu: add raven2 to gpu_info firmware
[not found] ` <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2018-09-12 19:29 ` [PATCH 01/16] drm/amdgpu: move get_rev_id at first before load gpu_info firmware Alex Deucher
2018-09-12 19:29 ` [PATCH 02/16] drm/amdgpu: set external rev id for raven2 Alex Deucher
@ 2018-09-12 19:29 ` Alex Deucher
2018-09-12 19:29 ` [PATCH 04/16] drm/amdgpu: add raven2 vcn firmware support Alex Deucher
` (12 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Alex Deucher @ 2018-09-12 19:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Feifei Xu
From: Feifei Xu <Feifei.Xu@amd.com>
Add gpu_info firmware for raven2.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 39fe66810d53..762dc5f886cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -63,6 +63,7 @@ MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
+MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
#define AMDGPU_RESUME_MS 2000
@@ -1334,7 +1335,10 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
chip_name = "vega12";
break;
case CHIP_RAVEN:
- chip_name = "raven";
+ if (adev->rev_id >= 8)
+ chip_name = "raven2";
+ else
+ chip_name = "raven";
break;
case CHIP_PICASSO:
chip_name = "picasso";
--
2.13.6
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 04/16] drm/amdgpu: add raven2 vcn firmware support
[not found] ` <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2018-09-12 19:29 ` [PATCH 03/16] drm/amdgpu: add raven2 to gpu_info firmware Alex Deucher
@ 2018-09-12 19:29 ` Alex Deucher
2018-09-12 19:29 ` [PATCH 05/16] drm/amdgpu: add psp support for raven2 Alex Deucher
` (11 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Alex Deucher @ 2018-09-12 19:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Feifei Xu
From: Feifei Xu <Feifei.Xu@amd.com>
Specify raven2 vcn firmware on amdgpu_vce_sw_init.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 93ffba2cbec4..a74498ce87ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -43,9 +43,11 @@
/* Firmware Names */
#define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin"
#define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin"
+#define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin"
MODULE_FIRMWARE(FIRMWARE_RAVEN);
MODULE_FIRMWARE(FIRMWARE_PICASSO);
+MODULE_FIRMWARE(FIRMWARE_RAVEN2);
static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
@@ -61,7 +63,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_RAVEN:
- fw_name = FIRMWARE_RAVEN;
+ if (adev->rev_id >= 8)
+ fw_name = FIRMWARE_RAVEN2;
+ else
+ fw_name = FIRMWARE_RAVEN;
break;
case CHIP_PICASSO:
fw_name = FIRMWARE_PICASSO;
--
2.13.6
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 05/16] drm/amdgpu: add psp support for raven2
[not found] ` <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2018-09-12 19:29 ` [PATCH 04/16] drm/amdgpu: add raven2 vcn firmware support Alex Deucher
@ 2018-09-12 19:29 ` Alex Deucher
2018-09-12 19:29 ` [PATCH 06/16] drm/amdgpu/sdma4: specify raven2 firmware Alex Deucher
` (10 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Alex Deucher @ 2018-09-12 19:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Likun Gao
From: Likun Gao <Likun.Gao@amd.com>
Modified for using raven2_asd.bin to replace raven_asd.bin for raven2
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 73a1ca833292..4edeb0496a12 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -36,6 +36,7 @@
MODULE_FIRMWARE("amdgpu/raven_asd.bin");
MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
+MODULE_FIRMWARE("amdgpu/raven2_asd.bin");
static int
psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
@@ -112,7 +113,10 @@ static int psp_v10_0_init_microcode(struct psp_context *psp)
switch (adev->asic_type) {
case CHIP_RAVEN:
- chip_name = "raven";
+ if (adev->rev_id >= 0x8)
+ chip_name = "raven2";
+ else
+ chip_name = "raven";
break;
case CHIP_PICASSO:
chip_name = "picasso";
--
2.13.6
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 06/16] drm/amdgpu/sdma4: specify raven2 firmware.
[not found] ` <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2018-09-12 19:29 ` [PATCH 05/16] drm/amdgpu: add psp support for raven2 Alex Deucher
@ 2018-09-12 19:29 ` Alex Deucher
2018-09-12 19:29 ` [PATCH 07/16] drm/amdgpu/sdma4: Add raven2 golden setting Alex Deucher
` (9 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Alex Deucher @ 2018-09-12 19:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Feifei Xu
From: Feifei Xu <Feifei.Xu@amd.com>
use raven2 sdma firmware.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index ca8a26178e2f..7ef140aaca3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -49,6 +49,7 @@ MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
+MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
@@ -269,7 +270,10 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
chip_name = "vega20";
break;
case CHIP_RAVEN:
- chip_name = "raven";
+ if (adev->rev_id >= 8)
+ chip_name = "raven2";
+ else
+ chip_name = "raven";
break;
case CHIP_PICASSO:
chip_name = "picasso";
--
2.13.6
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 07/16] drm/amdgpu/sdma4: Add raven2 golden setting
[not found] ` <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (5 preceding siblings ...)
2018-09-12 19:29 ` [PATCH 06/16] drm/amdgpu/sdma4: specify raven2 firmware Alex Deucher
@ 2018-09-12 19:29 ` Alex Deucher
2018-09-12 19:29 ` [PATCH 08/16] drm/amdgpu/gfx9: add support for raven2 gfx firmware Alex Deucher
` (8 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Alex Deucher @ 2018-09-12 19:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Feifei Xu
From: Feifei Xu <Feifei.Xu@amd.com>
Golden register settings from the hw team.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 21 ++++++++++++++++-----
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 7ef140aaca3c..75be0b9ed2c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -185,6 +185,12 @@ static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
};
+static const struct soc15_reg_golden golden_settings_sdma_rv2[] =
+{
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)
+};
+
static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
u32 instance, u32 offset)
{
@@ -225,11 +231,16 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
case CHIP_RAVEN:
case CHIP_PICASSO:
soc15_program_register_sequence(adev,
- golden_settings_sdma_4_1,
- ARRAY_SIZE(golden_settings_sdma_4_1));
- soc15_program_register_sequence(adev,
- golden_settings_sdma_rv1,
- ARRAY_SIZE(golden_settings_sdma_rv1));
+ golden_settings_sdma_4_1,
+ ARRAY_SIZE(golden_settings_sdma_4_1));
+ if (adev->rev_id >= 8)
+ soc15_program_register_sequence(adev,
+ golden_settings_sdma_rv2,
+ ARRAY_SIZE(golden_settings_sdma_rv2));
+ else
+ soc15_program_register_sequence(adev,
+ golden_settings_sdma_rv1,
+ ARRAY_SIZE(golden_settings_sdma_rv1));
break;
default:
break;
--
2.13.6
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 08/16] drm/amdgpu/gfx9: add support for raven2 gfx firmware
[not found] ` <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (6 preceding siblings ...)
2018-09-12 19:29 ` [PATCH 07/16] drm/amdgpu/sdma4: Add raven2 golden setting Alex Deucher
@ 2018-09-12 19:29 ` Alex Deucher
2018-09-12 19:29 ` [PATCH 09/16] drm/amdgpu/gfx9: add raven2 golden setting Alex Deucher
` (7 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Alex Deucher @ 2018-09-12 19:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Feifei Xu
From: Feifei Xu <Feifei.Xu@amd.com>
use raven2 gfx firmware.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ad20747bace8..7b9e1c274c59 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -87,6 +87,13 @@ MODULE_FIRMWARE("amdgpu/picasso_mec.bin");
MODULE_FIRMWARE("amdgpu/picasso_mec2.bin");
MODULE_FIRMWARE("amdgpu/picasso_rlc.bin");
+MODULE_FIRMWARE("amdgpu/raven2_ce.bin");
+MODULE_FIRMWARE("amdgpu/raven2_pfp.bin");
+MODULE_FIRMWARE("amdgpu/raven2_me.bin");
+MODULE_FIRMWARE("amdgpu/raven2_mec.bin");
+MODULE_FIRMWARE("amdgpu/raven2_mec2.bin");
+MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
+
static const struct soc15_reg_golden golden_settings_gc_9_0[] =
{
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
@@ -573,7 +580,10 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
chip_name = "vega20";
break;
case CHIP_RAVEN:
- chip_name = "raven";
+ if (adev->rev_id >= 8)
+ chip_name = "raven2";
+ else
+ chip_name = "raven";
break;
case CHIP_PICASSO:
chip_name = "picasso";
--
2.13.6
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 09/16] drm/amdgpu/gfx9: add raven2 golden setting
[not found] ` <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (7 preceding siblings ...)
2018-09-12 19:29 ` [PATCH 08/16] drm/amdgpu/gfx9: add support for raven2 gfx firmware Alex Deucher
@ 2018-09-12 19:29 ` Alex Deucher
2018-09-12 19:29 ` [PATCH 10/16] drm/amdgpu: fix the VM fault while write at the top of the invisible vram Alex Deucher
` (6 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Alex Deucher @ 2018-09-12 19:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Feifei Xu
From: Feifei Xu <Feifei.Xu@amd.com>
Golden register settings from the hw team.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 40 ++++++++++++++++++++++++++++++++++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 7b9e1c274c59..4991ae00a4ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -187,6 +187,29 @@ static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800)
};
+static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] =
+{
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
+};
+
static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
{
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),
@@ -255,6 +278,7 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
#define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
#define PICASSO_GB_ADDR_CONFIG_GOLDEN 0x24000042
+#define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041
static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -294,6 +318,17 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
ARRAY_SIZE(golden_settings_gc_9_0_vg20));
break;
case CHIP_RAVEN:
+ soc15_program_register_sequence(adev, golden_settings_gc_9_1,
+ ARRAY_SIZE(golden_settings_gc_9_1));
+ if (adev->rev_id >= 8)
+ soc15_program_register_sequence(adev,
+ golden_settings_gc_9_1_rv2,
+ ARRAY_SIZE(golden_settings_gc_9_1_rv2));
+ else
+ soc15_program_register_sequence(adev,
+ golden_settings_gc_9_1_rv1,
+ ARRAY_SIZE(golden_settings_gc_9_1_rv1));
+ break;
case CHIP_PICASSO:
soc15_program_register_sequence(adev,
golden_settings_gc_9_1,
@@ -1288,7 +1323,10 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
- gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
+ if (adev->rev_id >= 8)
+ gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN;
+ else
+ gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
break;
case CHIP_PICASSO:
adev->gfx.config.max_hw_contexts = 8;
--
2.13.6
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 10/16] drm/amdgpu: fix the VM fault while write at the top of the invisible vram
[not found] ` <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (8 preceding siblings ...)
2018-09-12 19:29 ` [PATCH 09/16] drm/amdgpu/gfx9: add raven2 golden setting Alex Deucher
@ 2018-09-12 19:29 ` Alex Deucher
2018-09-12 19:29 ` [PATCH 11/16] drm/amd/display: Add Raven2 definitions in dc Alex Deucher
` (5 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Alex Deucher @ 2018-09-12 19:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Raven2 has a HW issue that it is unable to use the vram which is out of
MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the workaround that increase system
aperture high address to get rid of the VM fault and hardware hang.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 15 +++++++++++++--
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 15 +++++++++++++--
2 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index ffd0ec9586d1..65f58ebcf835 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -73,8 +73,19 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
/* Program the system aperture low logical page number. */
WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
min(adev->gmc.vram_start, adev->gmc.agp_start) >> 18);
- WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
- max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);
+
+ if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
+ /*
+ * Raven2 has a HW issue that it is unable to use the vram which
+ * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
+ * workaround that increase system aperture high address (add 1)
+ * to get rid of the VM fault and hardware hang.
+ */
+ WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+ (max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18) + 0x1);
+ else
+ WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+ max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);
/* Set default page address. */
value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index b121eb6a0ad4..2a126c6950c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -91,8 +91,19 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
/* Program the system aperture low logical page number. */
WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
min(adev->gmc.vram_start, adev->gmc.agp_start) >> 18);
- WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
- max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);
+
+ if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
+ /*
+ * Raven2 has a HW issue that it is unable to use the vram which
+ * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
+ * workaround that increase system aperture high address (add 1)
+ * to get rid of the VM fault and hardware hang.
+ */
+ WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+ (max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18) + 0x1);
+ else
+ WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+ max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);
/* Set default page address. */
value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
--
2.13.6
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 11/16] drm/amd/display: Add Raven2 definitions in dc
[not found] ` <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (9 preceding siblings ...)
2018-09-12 19:29 ` [PATCH 10/16] drm/amdgpu: fix the VM fault while write at the top of the invisible vram Alex Deucher
@ 2018-09-12 19:29 ` Alex Deucher
[not found] ` <20180912192933.28712-12-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2018-09-12 19:29 ` [PATCH 12/16] drm/amd/display: Add DC config flag for Raven2 (v2) Alex Deucher
` (4 subsequent siblings)
15 siblings, 1 reply; 20+ messages in thread
From: Alex Deucher @ 2018-09-12 19:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Bhawanpreet Lakha
From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Add Raven2 definitions in the dc code
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../amd/display/dc/bios/command_table_helper2.c | 5 +++
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 +++++
.../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 +++++
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 36 +++++++++++++++++++++-
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 5 +++
drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 5 +++
drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 4 +++
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 7 +++++
drivers/gpu/drm/amd/display/include/dal_types.h | 3 ++
9 files changed, 78 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index bbbcef566c55..65b006ad372e 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -61,6 +61,11 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
return true;
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ case DCN_VERSION_1_01:
+ *h = dal_cmd_tbl_helper_dce112_get_table2();
+ return true;
+#endif
case DCE_VERSION_12_0:
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index d981755d1e4d..721dd13d2ed2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -88,6 +88,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case FAMILY_RV:
dc_version = DCN_VERSION_1_0;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
+ dc_version = DCN_VERSION_1_01;
+#endif
break;
#endif
default:
@@ -138,6 +142,9 @@ struct resource_pool *dc_create_resource_pool(
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case DCN_VERSION_1_0:
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ case DCN_VERSION_1_01:
+#endif
res_pool = dcn10_create_resource_pool(
num_virtual_links, dc);
break;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 5a9f3601ffb6..ae3c44aff1c8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -601,6 +601,9 @@ static uint32_t dce110_get_pix_clk_dividers(
case DCN_VERSION_1_0:
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ case DCN_VERSION_1_01:
+#endif
dce112_get_pix_clk_dividers_helper(clk_src,
pll_settings, pix_clk_params);
break;
@@ -907,6 +910,10 @@ static bool dce110_program_pix_clk(
case DCN_VERSION_1_0:
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ case DCN_VERSION_1_01:
+#endif
+
if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
pll_settings->use_external_clk;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 1b519f8f044f..65a596ffa02a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -152,7 +152,10 @@ enum dcn10_clk_src_array_id {
DCN10_CLK_SRC_PLL1,
DCN10_CLK_SRC_PLL2,
DCN10_CLK_SRC_PLL3,
- DCN10_CLK_SRC_TOTAL
+ DCN10_CLK_SRC_TOTAL,
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
+#endif
};
/* begin *********************
@@ -1163,6 +1166,10 @@ static bool construct(
/* max pipe num for ASIC before check pipe fuses */
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ if (dc->ctx->dce_version == DCN_VERSION_1_01)
+ pool->base.pipe_count = 3;
+#endif
dc->caps.max_video_width = 3840;
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 100;
@@ -1194,13 +1201,28 @@ static bool construct(
dcn10_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_COMBO_PHY_PLL2,
&clk_src_regs[2], false);
+
+#ifdef CONFIG_DRM_AMD_DC_DCN1_01
+ if (dc->ctx->dce_version == DCN_VERSION_1_0) {
+ pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
+ dcn10_clock_source_create(ctx, ctx->dc_bios,
+ CLOCK_SOURCE_COMBO_PHY_PLL3,
+ &clk_src_regs[3], false);
+ }
+#else
pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
dcn10_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_COMBO_PHY_PLL3,
&clk_src_regs[3], false);
+#endif
pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ if (dc->ctx->dce_version == DCN_VERSION_1_01)
+ pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;
+#endif
+
pool->base.dp_clock_source =
dcn10_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_ID_DP_DTO,
@@ -1246,6 +1268,18 @@ static bool construct(
memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ if (dc->ctx->dce_version == DCN_VERSION_1_01) {
+ struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;
+ struct dcn_ip_params *dcn_ip = dc->dcn_ip;
+ struct display_mode_lib *dml = &dc->dml;
+
+ dml->ip.max_num_dpp = 3;
+ /* TODO how to handle 23.84? */
+ dcn_soc->dram_clock_change_latency = 23;
+ dcn_ip->max_num_dpp = 3;
+ }
+#endif
if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
dc->dcn_soc->urgent_latency = 3;
dc->debug.disable_dmcu = true;
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
index 0caee3523017..a683f4102e65 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
@@ -86,6 +86,11 @@ bool dal_hw_factory_init(
dal_hw_factory_dcn10_init(factory);
return true;
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ case DCN_VERSION_1_01:
+ dal_hw_factory_dcn10_init(factory);
+ return true;
+#endif
default:
ASSERT_CRITICAL(false);
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
index 55c707488541..096f45628630 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
@@ -83,6 +83,11 @@ bool dal_hw_translate_init(
dal_hw_translate_dcn10_init(translate);
return true;
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ case DCN_VERSION_1_01:
+ dal_hw_translate_dcn10_init(translate);
+ return true;
+#endif
default:
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
index 9b0bcc6b769b..e56093f26eed 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
@@ -96,6 +96,10 @@ struct i2caux *dal_i2caux_create(
return dal_i2caux_dcn10_create(ctx);
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ case DCN_VERSION_1_01:
+ return dal_i2caux_dcn10_create(ctx);
+#endif
default:
BREAK_TO_DEBUGGER();
return NULL;
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 25029ed42d89..4f501ddcfb8d 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -131,8 +131,15 @@
#define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */
#define RAVEN_A0 0x01
#define RAVEN_B0 0x21
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+/* DCN1_01 */
+#define RAVEN2_A0 0x81
+#endif
#define RAVEN_UNKNOWN 0xFF
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < 0xF0))
+#endif /* DCN1_01 */
#define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
#define RAVEN1_F0 0xF0
#define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
index 840142b65f8b..89627133e188 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -44,6 +44,9 @@ enum dce_version {
DCE_VERSION_12_0,
DCE_VERSION_MAX,
DCN_VERSION_1_0,
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ DCN_VERSION_1_01,
+#endif /* DCN1_01 */
DCN_VERSION_MAX
};
--
2.13.6
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 12/16] drm/amd/display: Add DC config flag for Raven2 (v2)
[not found] ` <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (10 preceding siblings ...)
2018-09-12 19:29 ` [PATCH 11/16] drm/amd/display: Add Raven2 definitions in dc Alex Deucher
@ 2018-09-12 19:29 ` Alex Deucher
2018-09-12 19:29 ` [PATCH 13/16] drm/amd/powerplay: update smu10_verify_smc_interface() to be raven2 compatible Alex Deucher
` (3 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Alex Deucher @ 2018-09-12 19:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Bhawanpreet Lakha
From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Add DRM_AMD_DC_DCN1_01 config flag for Raven2
v2: Make DC select DRM_AMD_DC_DCN1_01 (Alex)
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/Kconfig | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
index ed654a76c76a..13a6ce9c8e94 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -5,6 +5,7 @@ config DRM_AMD_DC
bool "AMD DC - Enable new display engine"
default y
select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
+ select DRM_AMD_DC_DCN1_01 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
help
Choose this option if you want to use the new display engine
support for AMDGPU. This adds required support for Vega and
@@ -15,6 +16,11 @@ config DRM_AMD_DC_DCN1_0
help
RV family support for display engine
+config DRM_AMD_DC_DCN1_01
+ def_bool n
+ help
+ RV2 family for display engine
+
config DEBUG_KERNEL_DC
bool "Enable kgdb break in DC"
depends on DRM_AMD_DC
--
2.13.6
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 13/16] drm/amd/powerplay: update smu10_verify_smc_interface() to be raven2 compatible
[not found] ` <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (11 preceding siblings ...)
2018-09-12 19:29 ` [PATCH 12/16] drm/amd/display: Add DC config flag for Raven2 (v2) Alex Deucher
@ 2018-09-12 19:29 ` Alex Deucher
2018-09-12 19:29 ` [PATCH 14/16] drm/amd/powerplay: round up the Mhz convertion (v2) Alex Deucher
` (2 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Alex Deucher @ 2018-09-12 19:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Evan Quan
From: Evan Quan <evan.quan@amd.com>
Check the raven2 version number as well.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
index bb07d43f3874..6f961dec2088 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
@@ -177,7 +177,8 @@ static int smu10_verify_smc_interface(struct pp_hwmgr *hwmgr)
PPSMC_MSG_GetDriverIfVersion);
smc_driver_if_version = smu10_read_arg_from_smc(hwmgr);
- if (smc_driver_if_version != SMU10_DRIVER_IF_VERSION) {
+ if ((smc_driver_if_version != SMU10_DRIVER_IF_VERSION) &&
+ (smc_driver_if_version != SMU10_DRIVER_IF_VERSION + 1)) {
pr_err("Attempt to read SMC IF Version Number Failed!\n");
return -EINVAL;
}
--
2.13.6
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 14/16] drm/amd/powerplay: round up the Mhz convertion (v2)
[not found] ` <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (12 preceding siblings ...)
2018-09-12 19:29 ` [PATCH 13/16] drm/amd/powerplay: update smu10_verify_smc_interface() to be raven2 compatible Alex Deucher
@ 2018-09-12 19:29 ` Alex Deucher
2018-09-12 19:29 ` [PATCH 15/16] drm/amd/powerplay: disable raven2 force dpm level support (v2) Alex Deucher
2018-09-12 19:29 ` [PATCH 16/16] drm/amdgpu: set CG flags for raven2 (v2) Alex Deucher
15 siblings, 0 replies; 20+ messages in thread
From: Alex Deucher @ 2018-09-12 19:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Evan Quan
From: Evan Quan <evan.quan@amd.com>
Since the clock value there may be like 29999 10Khz.
v2: rebase (Alex)
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 26d130a91725..5b55c709fb1c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -211,12 +211,18 @@ static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
return 0;
}
+static inline uint32_t convert_10k_to_mhz(uint32_t clock)
+{
+ return (clock + 99) / 100;
+}
+
static int smu10_set_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
{
struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
- if (smu10_data->need_min_deep_sleep_dcefclk && smu10_data->deep_sleep_dcefclk != clock/100) {
- smu10_data->deep_sleep_dcefclk = clock/100;
+ if (smu10_data->need_min_deep_sleep_dcefclk &&
+ smu10_data->deep_sleep_dcefclk != convert_10k_to_mhz(clock)) {
+ smu10_data->deep_sleep_dcefclk = convert_10k_to_mhz(clock);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetMinDeepSleepDcefclk,
smu10_data->deep_sleep_dcefclk);
--
2.13.6
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 15/16] drm/amd/powerplay: disable raven2 force dpm level support (v2)
[not found] ` <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (13 preceding siblings ...)
2018-09-12 19:29 ` [PATCH 14/16] drm/amd/powerplay: round up the Mhz convertion (v2) Alex Deucher
@ 2018-09-12 19:29 ` Alex Deucher
2018-09-12 19:29 ` [PATCH 16/16] drm/amdgpu: set CG flags for raven2 (v2) Alex Deucher
15 siblings, 0 replies; 20+ messages in thread
From: Alex Deucher @ 2018-09-12 19:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Evan Quan
From: Evan Quan <evan.quan@amd.com>
It's not supported yet.
v2: rebase (Alex)
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 5b55c709fb1c..9808bd48b386 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -551,12 +551,18 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
enum amd_dpm_forced_level level)
{
struct smu10_hwmgr *data = hwmgr->backend;
+ struct amdgpu_device *adev = hwmgr->adev;
if (hwmgr->smu_version < 0x1E3700) {
pr_info("smu firmware version too old, can not set dpm level\n");
return 0;
}
+ /* Disable UMDPSTATE support on rv2 temporarily */
+ if ((adev->asic_type == CHIP_RAVEN) &&
+ (adev->rev_id >= 8))
+ return 0;
+
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
--
2.13.6
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 16/16] drm/amdgpu: set CG flags for raven2 (v2)
[not found] ` <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (14 preceding siblings ...)
2018-09-12 19:29 ` [PATCH 15/16] drm/amd/powerplay: disable raven2 force dpm level support (v2) Alex Deucher
@ 2018-09-12 19:29 ` Alex Deucher
15 siblings, 0 replies; 20+ messages in thread
From: Alex Deucher @ 2018-09-12 19:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Raven2 does not enable all of the CG flags that raven1 does.
v2: rebase (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 57 +++++++++++++++++++++++++-------------
1 file changed, 37 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 0a935604ec9e..f5a44d1fe5da 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -714,26 +714,43 @@ static int soc15_common_early_init(void *handle)
adev->external_rev_id = adev->rev_id + 0x28;
break;
case CHIP_RAVEN:
- adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
- AMD_CG_SUPPORT_GFX_MGLS |
- AMD_CG_SUPPORT_GFX_RLC_LS |
- AMD_CG_SUPPORT_GFX_CP_LS |
- AMD_CG_SUPPORT_GFX_3D_CGCG |
- AMD_CG_SUPPORT_GFX_3D_CGLS |
- AMD_CG_SUPPORT_GFX_CGCG |
- AMD_CG_SUPPORT_GFX_CGLS |
- AMD_CG_SUPPORT_BIF_MGCG |
- AMD_CG_SUPPORT_BIF_LS |
- AMD_CG_SUPPORT_HDP_MGCG |
- AMD_CG_SUPPORT_HDP_LS |
- AMD_CG_SUPPORT_DRM_MGCG |
- AMD_CG_SUPPORT_DRM_LS |
- AMD_CG_SUPPORT_ROM_MGCG |
- AMD_CG_SUPPORT_MC_MGCG |
- AMD_CG_SUPPORT_MC_LS |
- AMD_CG_SUPPORT_SDMA_MGCG |
- AMD_CG_SUPPORT_SDMA_LS |
- AMD_CG_SUPPORT_VCN_MGCG;
+ if (adev->rev_id >= 0x8)
+ adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+ AMD_CG_SUPPORT_GFX_MGLS |
+ AMD_CG_SUPPORT_GFX_CP_LS |
+ AMD_CG_SUPPORT_GFX_3D_CGCG |
+ AMD_CG_SUPPORT_GFX_3D_CGLS |
+ AMD_CG_SUPPORT_GFX_CGCG |
+ AMD_CG_SUPPORT_GFX_CGLS |
+ AMD_CG_SUPPORT_BIF_LS |
+ AMD_CG_SUPPORT_HDP_LS |
+ AMD_CG_SUPPORT_ROM_MGCG |
+ AMD_CG_SUPPORT_MC_MGCG |
+ AMD_CG_SUPPORT_MC_LS |
+ AMD_CG_SUPPORT_SDMA_MGCG |
+ AMD_CG_SUPPORT_SDMA_LS |
+ AMD_CG_SUPPORT_VCN_MGCG;
+ else
+ adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+ AMD_CG_SUPPORT_GFX_MGLS |
+ AMD_CG_SUPPORT_GFX_RLC_LS |
+ AMD_CG_SUPPORT_GFX_CP_LS |
+ AMD_CG_SUPPORT_GFX_3D_CGCG |
+ AMD_CG_SUPPORT_GFX_3D_CGLS |
+ AMD_CG_SUPPORT_GFX_CGCG |
+ AMD_CG_SUPPORT_GFX_CGLS |
+ AMD_CG_SUPPORT_BIF_MGCG |
+ AMD_CG_SUPPORT_BIF_LS |
+ AMD_CG_SUPPORT_HDP_MGCG |
+ AMD_CG_SUPPORT_HDP_LS |
+ AMD_CG_SUPPORT_DRM_MGCG |
+ AMD_CG_SUPPORT_DRM_LS |
+ AMD_CG_SUPPORT_ROM_MGCG |
+ AMD_CG_SUPPORT_MC_MGCG |
+ AMD_CG_SUPPORT_MC_LS |
+ AMD_CG_SUPPORT_SDMA_MGCG |
+ AMD_CG_SUPPORT_SDMA_LS |
+ AMD_CG_SUPPORT_VCN_MGCG;
adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
--
2.13.6
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 11/16] drm/amd/display: Add Raven2 definitions in dc
[not found] ` <20180912192933.28712-12-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
@ 2018-09-12 20:10 ` Alex Deucher
[not found] ` <CADnq5_PsBONPZyirw5BVGNb=sf5_9njE6=jXBm0d7RjqC8=i+g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 20+ messages in thread
From: Alex Deucher @ 2018-09-12 20:10 UTC (permalink / raw)
To: amd-gfx list; +Cc: Deucher, Alexander, Bhawanpreet Lakha
On Wed, Sep 12, 2018 at 3:29 PM Alex Deucher <alexdeucher@gmail.com> wrote:
>
> From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
>
> Add Raven2 definitions in the dc code
>
> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
> Reviewed-by: Huang Rui <ray.huang@amd.com>
> Acked-by: Alex Deucher <alexander.deucher@amd.com
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> .../amd/display/dc/bios/command_table_helper2.c | 5 +++
> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 +++++
> .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 +++++
Some of the clock source changes look suspect. See comments below.
Alex
> .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 36 +++++++++++++++++++++-
> drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 5 +++
> drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 5 +++
> drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 4 +++
> drivers/gpu/drm/amd/display/include/dal_asic_id.h | 7 +++++
> drivers/gpu/drm/amd/display/include/dal_types.h | 3 ++
> 9 files changed, 78 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> index bbbcef566c55..65b006ad372e 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> @@ -61,6 +61,11 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
> return true;
> #endif
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + case DCN_VERSION_1_01:
> + *h = dal_cmd_tbl_helper_dce112_get_table2();
> + return true;
> +#endif
> case DCE_VERSION_12_0:
> *h = dal_cmd_tbl_helper_dce112_get_table2();
> return true;
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> index d981755d1e4d..721dd13d2ed2 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> @@ -88,6 +88,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
> case FAMILY_RV:
> dc_version = DCN_VERSION_1_0;
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
> + dc_version = DCN_VERSION_1_01;
> +#endif
> break;
> #endif
> default:
> @@ -138,6 +142,9 @@ struct resource_pool *dc_create_resource_pool(
>
> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
> case DCN_VERSION_1_0:
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + case DCN_VERSION_1_01:
> +#endif
> res_pool = dcn10_create_resource_pool(
> num_virtual_links, dc);
> break;
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> index 5a9f3601ffb6..ae3c44aff1c8 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> @@ -601,6 +601,9 @@ static uint32_t dce110_get_pix_clk_dividers(
> case DCN_VERSION_1_0:
> #endif
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + case DCN_VERSION_1_01:
> +#endif
> dce112_get_pix_clk_dividers_helper(clk_src,
> pll_settings, pix_clk_params);
> break;
> @@ -907,6 +910,10 @@ static bool dce110_program_pix_clk(
> case DCN_VERSION_1_0:
> #endif
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + case DCN_VERSION_1_01:
> +#endif
> +
> if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
> bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
> pll_settings->use_external_clk;
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> index 1b519f8f044f..65a596ffa02a 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> @@ -152,7 +152,10 @@ enum dcn10_clk_src_array_id {
> DCN10_CLK_SRC_PLL1,
> DCN10_CLK_SRC_PLL2,
> DCN10_CLK_SRC_PLL3,
> - DCN10_CLK_SRC_TOTAL
> + DCN10_CLK_SRC_TOTAL,
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
> +#endif
This change looks suspect.
Alex
> };
>
> /* begin *********************
> @@ -1163,6 +1166,10 @@ static bool construct(
> /* max pipe num for ASIC before check pipe fuses */
> pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + if (dc->ctx->dce_version == DCN_VERSION_1_01)
> + pool->base.pipe_count = 3;
> +#endif
> dc->caps.max_video_width = 3840;
> dc->caps.max_downscale_ratio = 200;
> dc->caps.i2c_speed_in_khz = 100;
> @@ -1194,13 +1201,28 @@ static bool construct(
> dcn10_clock_source_create(ctx, ctx->dc_bios,
> CLOCK_SOURCE_COMBO_PHY_PLL2,
> &clk_src_regs[2], false);
> +
> +#ifdef CONFIG_DRM_AMD_DC_DCN1_01
> + if (dc->ctx->dce_version == DCN_VERSION_1_0) {
> + pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
> + dcn10_clock_source_create(ctx, ctx->dc_bios,
> + CLOCK_SOURCE_COMBO_PHY_PLL3,
> + &clk_src_regs[3], false);
> + }
> +#else
> pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
> dcn10_clock_source_create(ctx, ctx->dc_bios,
> CLOCK_SOURCE_COMBO_PHY_PLL3,
> &clk_src_regs[3], false);
> +#endif
This one too.
>
> pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + if (dc->ctx->dce_version == DCN_VERSION_1_01)
> + pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;
> +#endif
Here too.
> +
> pool->base.dp_clock_source =
> dcn10_clock_source_create(ctx, ctx->dc_bios,
> CLOCK_SOURCE_ID_DP_DTO,
> @@ -1246,6 +1268,18 @@ static bool construct(
> memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
> memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + if (dc->ctx->dce_version == DCN_VERSION_1_01) {
> + struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;
> + struct dcn_ip_params *dcn_ip = dc->dcn_ip;
> + struct display_mode_lib *dml = &dc->dml;
> +
> + dml->ip.max_num_dpp = 3;
> + /* TODO how to handle 23.84? */
> + dcn_soc->dram_clock_change_latency = 23;
> + dcn_ip->max_num_dpp = 3;
> + }
> +#endif
> if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
> dc->dcn_soc->urgent_latency = 3;
> dc->debug.disable_dmcu = true;
> diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
> index 0caee3523017..a683f4102e65 100644
> --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
> +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
> @@ -86,6 +86,11 @@ bool dal_hw_factory_init(
> dal_hw_factory_dcn10_init(factory);
> return true;
> #endif
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + case DCN_VERSION_1_01:
> + dal_hw_factory_dcn10_init(factory);
> + return true;
> +#endif
>
> default:
> ASSERT_CRITICAL(false);
> diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
> index 55c707488541..096f45628630 100644
> --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
> +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
> @@ -83,6 +83,11 @@ bool dal_hw_translate_init(
> dal_hw_translate_dcn10_init(translate);
> return true;
> #endif
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + case DCN_VERSION_1_01:
> + dal_hw_translate_dcn10_init(translate);
> + return true;
> +#endif
>
> default:
> BREAK_TO_DEBUGGER();
> diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
> index 9b0bcc6b769b..e56093f26eed 100644
> --- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
> +++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
> @@ -96,6 +96,10 @@ struct i2caux *dal_i2caux_create(
> return dal_i2caux_dcn10_create(ctx);
> #endif
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + case DCN_VERSION_1_01:
> + return dal_i2caux_dcn10_create(ctx);
> +#endif
> default:
> BREAK_TO_DEBUGGER();
> return NULL;
> diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
> index 25029ed42d89..4f501ddcfb8d 100644
> --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
> +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
> @@ -131,8 +131,15 @@
> #define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */
> #define RAVEN_A0 0x01
> #define RAVEN_B0 0x21
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> +/* DCN1_01 */
> +#define RAVEN2_A0 0x81
> +#endif
> #define RAVEN_UNKNOWN 0xFF
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> +#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < 0xF0))
> +#endif /* DCN1_01 */
> #define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
> #define RAVEN1_F0 0xF0
> #define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
> diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
> index 840142b65f8b..89627133e188 100644
> --- a/drivers/gpu/drm/amd/display/include/dal_types.h
> +++ b/drivers/gpu/drm/amd/display/include/dal_types.h
> @@ -44,6 +44,9 @@ enum dce_version {
> DCE_VERSION_12_0,
> DCE_VERSION_MAX,
> DCN_VERSION_1_0,
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + DCN_VERSION_1_01,
> +#endif /* DCN1_01 */
> DCN_VERSION_MAX
> };
>
> --
> 2.13.6
>
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 11/16] drm/amd/display: Add Raven2 definitions in dc
[not found] ` <CADnq5_PsBONPZyirw5BVGNb=sf5_9njE6=jXBm0d7RjqC8=i+g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2018-09-12 20:43 ` Harry Wentland
[not found] ` <4a0826ff-d3a2-4f6f-2c74-d262e6ec70b3-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 20+ messages in thread
From: Harry Wentland @ 2018-09-12 20:43 UTC (permalink / raw)
To: Alex Deucher, amd-gfx list
Cc: Deucher, Alexander, Wu, Hersen, Bhawanpreet Lakha
On 2018-09-12 04:10 PM, Alex Deucher wrote:
> On Wed, Sep 12, 2018 at 3:29 PM Alex Deucher <alexdeucher@gmail.com> wrote:
>>
>> From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
>>
>> Add Raven2 definitions in the dc code
>>
>> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
>> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
>> Reviewed-by: Huang Rui <ray.huang@amd.com>
>> Acked-by: Alex Deucher <alexander.deucher@amd.com
>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>> ---
>> .../amd/display/dc/bios/command_table_helper2.c | 5 +++
>> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 +++++
>> .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 +++++
>
> Some of the clock source changes look suspect. See comments below.
>
> Alex
>
>> .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 36 +++++++++++++++++++++-
>> drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 5 +++
>> drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 5 +++
>> drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 4 +++
>> drivers/gpu/drm/amd/display/include/dal_asic_id.h | 7 +++++
>> drivers/gpu/drm/amd/display/include/dal_types.h | 3 ++
>> 9 files changed, 78 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>> index bbbcef566c55..65b006ad372e 100644
>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>> @@ -61,6 +61,11 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
>> return true;
>> #endif
>>
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> + case DCN_VERSION_1_01:
>> + *h = dal_cmd_tbl_helper_dce112_get_table2();
>> + return true;
>> +#endif
>> case DCE_VERSION_12_0:
>> *h = dal_cmd_tbl_helper_dce112_get_table2();
>> return true;
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> index d981755d1e4d..721dd13d2ed2 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> @@ -88,6 +88,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
>> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
>> case FAMILY_RV:
>> dc_version = DCN_VERSION_1_0;
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> + if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
>> + dc_version = DCN_VERSION_1_01;
>> +#endif
>> break;
>> #endif
>> default:
>> @@ -138,6 +142,9 @@ struct resource_pool *dc_create_resource_pool(
>>
>> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
>> case DCN_VERSION_1_0:
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> + case DCN_VERSION_1_01:
>> +#endif
>> res_pool = dcn10_create_resource_pool(
>> num_virtual_links, dc);
>> break;
>> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>> index 5a9f3601ffb6..ae3c44aff1c8 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>> @@ -601,6 +601,9 @@ static uint32_t dce110_get_pix_clk_dividers(
>> case DCN_VERSION_1_0:
>> #endif
>>
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> + case DCN_VERSION_1_01:
>> +#endif
>> dce112_get_pix_clk_dividers_helper(clk_src,
>> pll_settings, pix_clk_params);
>> break;
>> @@ -907,6 +910,10 @@ static bool dce110_program_pix_clk(
>> case DCN_VERSION_1_0:
>> #endif
>>
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> + case DCN_VERSION_1_01:
>> +#endif
>> +
>> if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
>> bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
>> pll_settings->use_external_clk;
>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
>> index 1b519f8f044f..65a596ffa02a 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
>> @@ -152,7 +152,10 @@ enum dcn10_clk_src_array_id {
>> DCN10_CLK_SRC_PLL1,
>> DCN10_CLK_SRC_PLL2,
>> DCN10_CLK_SRC_PLL3,
>> - DCN10_CLK_SRC_TOTAL
>> + DCN10_CLK_SRC_TOTAL,
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> + DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
>> +#endif
>
> This change looks suspect.
+Hersen who did some of the original work.
AFAIK DCN 10.1 has one less PLL.
We can drop all the DCN1_01 ifdefs to help simplify this code a bit.
Or do you mean something else here?
Harry
>
> Alex
>
>> };
>>
>> /* begin *********************
>> @@ -1163,6 +1166,10 @@ static bool construct(
>> /* max pipe num for ASIC before check pipe fuses */
>> pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
>>
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> + if (dc->ctx->dce_version == DCN_VERSION_1_01)
>> + pool->base.pipe_count = 3;
>> +#endif
>> dc->caps.max_video_width = 3840;
>> dc->caps.max_downscale_ratio = 200;
>> dc->caps.i2c_speed_in_khz = 100;
>> @@ -1194,13 +1201,28 @@ static bool construct(
>> dcn10_clock_source_create(ctx, ctx->dc_bios,
>> CLOCK_SOURCE_COMBO_PHY_PLL2,
>> &clk_src_regs[2], false);
>> +
>> +#ifdef CONFIG_DRM_AMD_DC_DCN1_01
>> + if (dc->ctx->dce_version == DCN_VERSION_1_0) {
>> + pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
>> + dcn10_clock_source_create(ctx, ctx->dc_bios,
>> + CLOCK_SOURCE_COMBO_PHY_PLL3,
>> + &clk_src_regs[3], false);
>> + }
>> +#else
>> pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
>> dcn10_clock_source_create(ctx, ctx->dc_bios,
>> CLOCK_SOURCE_COMBO_PHY_PLL3,
>> &clk_src_regs[3], false);
>> +#endif
>
> This one too.
>
>>
>> pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
>>
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> + if (dc->ctx->dce_version == DCN_VERSION_1_01)
>> + pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;
>> +#endif
>
> Here too.
>
>> +
>> pool->base.dp_clock_source =
>> dcn10_clock_source_create(ctx, ctx->dc_bios,
>> CLOCK_SOURCE_ID_DP_DTO,
>> @@ -1246,6 +1268,18 @@ static bool construct(
>> memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
>> memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
>>
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> + if (dc->ctx->dce_version == DCN_VERSION_1_01) {
>> + struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;
>> + struct dcn_ip_params *dcn_ip = dc->dcn_ip;
>> + struct display_mode_lib *dml = &dc->dml;
>> +
>> + dml->ip.max_num_dpp = 3;
>> + /* TODO how to handle 23.84? */
>> + dcn_soc->dram_clock_change_latency = 23;
>> + dcn_ip->max_num_dpp = 3;
>> + }
>> +#endif
>> if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
>> dc->dcn_soc->urgent_latency = 3;
>> dc->debug.disable_dmcu = true;
>> diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
>> index 0caee3523017..a683f4102e65 100644
>> --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
>> +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
>> @@ -86,6 +86,11 @@ bool dal_hw_factory_init(
>> dal_hw_factory_dcn10_init(factory);
>> return true;
>> #endif
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> + case DCN_VERSION_1_01:
>> + dal_hw_factory_dcn10_init(factory);
>> + return true;
>> +#endif
>>
>> default:
>> ASSERT_CRITICAL(false);
>> diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
>> index 55c707488541..096f45628630 100644
>> --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
>> +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
>> @@ -83,6 +83,11 @@ bool dal_hw_translate_init(
>> dal_hw_translate_dcn10_init(translate);
>> return true;
>> #endif
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> + case DCN_VERSION_1_01:
>> + dal_hw_translate_dcn10_init(translate);
>> + return true;
>> +#endif
>>
>> default:
>> BREAK_TO_DEBUGGER();
>> diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
>> index 9b0bcc6b769b..e56093f26eed 100644
>> --- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
>> +++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
>> @@ -96,6 +96,10 @@ struct i2caux *dal_i2caux_create(
>> return dal_i2caux_dcn10_create(ctx);
>> #endif
>>
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> + case DCN_VERSION_1_01:
>> + return dal_i2caux_dcn10_create(ctx);
>> +#endif
>> default:
>> BREAK_TO_DEBUGGER();
>> return NULL;
>> diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
>> index 25029ed42d89..4f501ddcfb8d 100644
>> --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
>> +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
>> @@ -131,8 +131,15 @@
>> #define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */
>> #define RAVEN_A0 0x01
>> #define RAVEN_B0 0x21
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> +/* DCN1_01 */
>> +#define RAVEN2_A0 0x81
>> +#endif
>> #define RAVEN_UNKNOWN 0xFF
>>
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> +#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < 0xF0))
>> +#endif /* DCN1_01 */
>> #define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
>> #define RAVEN1_F0 0xF0
>> #define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
>> diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
>> index 840142b65f8b..89627133e188 100644
>> --- a/drivers/gpu/drm/amd/display/include/dal_types.h
>> +++ b/drivers/gpu/drm/amd/display/include/dal_types.h
>> @@ -44,6 +44,9 @@ enum dce_version {
>> DCE_VERSION_12_0,
>> DCE_VERSION_MAX,
>> DCN_VERSION_1_0,
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> + DCN_VERSION_1_01,
>> +#endif /* DCN1_01 */
>> DCN_VERSION_MAX
>> };
>>
>> --
>> 2.13.6
>>
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* Re: [PATCH 11/16] drm/amd/display: Add Raven2 definitions in dc
[not found] ` <4a0826ff-d3a2-4f6f-2c74-d262e6ec70b3-5C7GfCeVMHo@public.gmane.org>
@ 2018-09-12 20:56 ` Alex Deucher
0 siblings, 0 replies; 20+ messages in thread
From: Alex Deucher @ 2018-09-12 20:56 UTC (permalink / raw)
To: Wentland, Harry
Cc: Deucher, Alexander, Hersen Wu, Bhawanpreet Lakha, amd-gfx list
On Wed, Sep 12, 2018 at 4:44 PM Harry Wentland <harry.wentland@amd.com> wrote:
>
>
>
> On 2018-09-12 04:10 PM, Alex Deucher wrote:
> > On Wed, Sep 12, 2018 at 3:29 PM Alex Deucher <alexdeucher@gmail.com> wrote:
> >>
> >> From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
> >>
> >> Add Raven2 definitions in the dc code
> >>
> >> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
> >> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
> >> Reviewed-by: Huang Rui <ray.huang@amd.com>
> >> Acked-by: Alex Deucher <alexander.deucher@amd.com
> >> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> >> ---
> >> .../amd/display/dc/bios/command_table_helper2.c | 5 +++
> >> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 +++++
> >> .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 +++++
> >
> > Some of the clock source changes look suspect. See comments below.
> >
> > Alex
> >
> >> .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 36 +++++++++++++++++++++-
> >> drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 5 +++
> >> drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 5 +++
> >> drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 4 +++
> >> drivers/gpu/drm/amd/display/include/dal_asic_id.h | 7 +++++
> >> drivers/gpu/drm/amd/display/include/dal_types.h | 3 ++
> >> 9 files changed, 78 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> >> index bbbcef566c55..65b006ad372e 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> >> @@ -61,6 +61,11 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
> >> return true;
> >> #endif
> >>
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> + case DCN_VERSION_1_01:
> >> + *h = dal_cmd_tbl_helper_dce112_get_table2();
> >> + return true;
> >> +#endif
> >> case DCE_VERSION_12_0:
> >> *h = dal_cmd_tbl_helper_dce112_get_table2();
> >> return true;
> >> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >> index d981755d1e4d..721dd13d2ed2 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >> @@ -88,6 +88,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
> >> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
> >> case FAMILY_RV:
> >> dc_version = DCN_VERSION_1_0;
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> + if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
> >> + dc_version = DCN_VERSION_1_01;
> >> +#endif
> >> break;
> >> #endif
> >> default:
> >> @@ -138,6 +142,9 @@ struct resource_pool *dc_create_resource_pool(
> >>
> >> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
> >> case DCN_VERSION_1_0:
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> + case DCN_VERSION_1_01:
> >> +#endif
> >> res_pool = dcn10_create_resource_pool(
> >> num_virtual_links, dc);
> >> break;
> >> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> >> index 5a9f3601ffb6..ae3c44aff1c8 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> >> @@ -601,6 +601,9 @@ static uint32_t dce110_get_pix_clk_dividers(
> >> case DCN_VERSION_1_0:
> >> #endif
> >>
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> + case DCN_VERSION_1_01:
> >> +#endif
> >> dce112_get_pix_clk_dividers_helper(clk_src,
> >> pll_settings, pix_clk_params);
> >> break;
> >> @@ -907,6 +910,10 @@ static bool dce110_program_pix_clk(
> >> case DCN_VERSION_1_0:
> >> #endif
> >>
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> + case DCN_VERSION_1_01:
> >> +#endif
> >> +
> >> if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
> >> bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
> >> pll_settings->use_external_clk;
> >> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> >> index 1b519f8f044f..65a596ffa02a 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> >> @@ -152,7 +152,10 @@ enum dcn10_clk_src_array_id {
> >> DCN10_CLK_SRC_PLL1,
> >> DCN10_CLK_SRC_PLL2,
> >> DCN10_CLK_SRC_PLL3,
> >> - DCN10_CLK_SRC_TOTAL
> >> + DCN10_CLK_SRC_TOTAL,
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> + DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
> >> +#endif
> >
> > This change looks suspect.
>
> +Hersen who did some of the original work.
>
> AFAIK DCN 10.1 has one less PLL.
>
> We can drop all the DCN1_01 ifdefs to help simplify this code a bit.
>
> Or do you mean something else here?
It looks like setting CONFIG_DRM_AMD_DC_DCN1_01 may break some other
asics that rely on dcn10_clk_src_array_id, specifically
DCN101_CLK_SRC_TOTAL.
>
> Harry
>
> >
> > Alex
> >
> >> };
> >>
> >> /* begin *********************
> >> @@ -1163,6 +1166,10 @@ static bool construct(
> >> /* max pipe num for ASIC before check pipe fuses */
> >> pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
> >>
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> + if (dc->ctx->dce_version == DCN_VERSION_1_01)
> >> + pool->base.pipe_count = 3;
> >> +#endif
> >> dc->caps.max_video_width = 3840;
> >> dc->caps.max_downscale_ratio = 200;
> >> dc->caps.i2c_speed_in_khz = 100;
> >> @@ -1194,13 +1201,28 @@ static bool construct(
> >> dcn10_clock_source_create(ctx, ctx->dc_bios,
> >> CLOCK_SOURCE_COMBO_PHY_PLL2,
> >> &clk_src_regs[2], false);
> >> +
> >> +#ifdef CONFIG_DRM_AMD_DC_DCN1_01
> >> + if (dc->ctx->dce_version == DCN_VERSION_1_0) {
> >> + pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
> >> + dcn10_clock_source_create(ctx, ctx->dc_bios,
> >> + CLOCK_SOURCE_COMBO_PHY_PLL3,
> >> + &clk_src_regs[3], false);
> >> + }
> >> +#else
> >> pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
> >> dcn10_clock_source_create(ctx, ctx->dc_bios,
> >> CLOCK_SOURCE_COMBO_PHY_PLL3,
> >> &clk_src_regs[3], false);
> >> +#endif
> >
> > This one too.
> >
> >>
> >> pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
> >>
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> + if (dc->ctx->dce_version == DCN_VERSION_1_01)
> >> + pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;
> >> +#endif
> >
> > Here too.
Seems like it would be better to drop the change to the enum and just
set pool->base.clk_src_count = DCN10_CLK_SRC_PLL3 otherwise the count
will be different for DCN1.
Alex
> >
> >> +
> >> pool->base.dp_clock_source =
> >> dcn10_clock_source_create(ctx, ctx->dc_bios,
> >> CLOCK_SOURCE_ID_DP_DTO,
> >> @@ -1246,6 +1268,18 @@ static bool construct(
> >> memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
> >> memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
> >>
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> + if (dc->ctx->dce_version == DCN_VERSION_1_01) {
> >> + struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;
> >> + struct dcn_ip_params *dcn_ip = dc->dcn_ip;
> >> + struct display_mode_lib *dml = &dc->dml;
> >> +
> >> + dml->ip.max_num_dpp = 3;
> >> + /* TODO how to handle 23.84? */
> >> + dcn_soc->dram_clock_change_latency = 23;
> >> + dcn_ip->max_num_dpp = 3;
> >> + }
> >> +#endif
> >> if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
> >> dc->dcn_soc->urgent_latency = 3;
> >> dc->debug.disable_dmcu = true;
> >> diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
> >> index 0caee3523017..a683f4102e65 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
> >> @@ -86,6 +86,11 @@ bool dal_hw_factory_init(
> >> dal_hw_factory_dcn10_init(factory);
> >> return true;
> >> #endif
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> + case DCN_VERSION_1_01:
> >> + dal_hw_factory_dcn10_init(factory);
> >> + return true;
> >> +#endif
> >>
> >> default:
> >> ASSERT_CRITICAL(false);
> >> diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
> >> index 55c707488541..096f45628630 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
> >> @@ -83,6 +83,11 @@ bool dal_hw_translate_init(
> >> dal_hw_translate_dcn10_init(translate);
> >> return true;
> >> #endif
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> + case DCN_VERSION_1_01:
> >> + dal_hw_translate_dcn10_init(translate);
> >> + return true;
> >> +#endif
> >>
> >> default:
> >> BREAK_TO_DEBUGGER();
> >> diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
> >> index 9b0bcc6b769b..e56093f26eed 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
> >> @@ -96,6 +96,10 @@ struct i2caux *dal_i2caux_create(
> >> return dal_i2caux_dcn10_create(ctx);
> >> #endif
> >>
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> + case DCN_VERSION_1_01:
> >> + return dal_i2caux_dcn10_create(ctx);
> >> +#endif
> >> default:
> >> BREAK_TO_DEBUGGER();
> >> return NULL;
> >> diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
> >> index 25029ed42d89..4f501ddcfb8d 100644
> >> --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
> >> +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
> >> @@ -131,8 +131,15 @@
> >> #define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */
> >> #define RAVEN_A0 0x01
> >> #define RAVEN_B0 0x21
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> +/* DCN1_01 */
> >> +#define RAVEN2_A0 0x81
> >> +#endif
> >> #define RAVEN_UNKNOWN 0xFF
> >>
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> +#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < 0xF0))
> >> +#endif /* DCN1_01 */
> >> #define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
> >> #define RAVEN1_F0 0xF0
> >> #define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
> >> diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
> >> index 840142b65f8b..89627133e188 100644
> >> --- a/drivers/gpu/drm/amd/display/include/dal_types.h
> >> +++ b/drivers/gpu/drm/amd/display/include/dal_types.h
> >> @@ -44,6 +44,9 @@ enum dce_version {
> >> DCE_VERSION_12_0,
> >> DCE_VERSION_MAX,
> >> DCN_VERSION_1_0,
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> + DCN_VERSION_1_01,
> >> +#endif /* DCN1_01 */
> >> DCN_VERSION_MAX
> >> };
> >>
> >> --
> >> 2.13.6
> >>
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> >
_______________________________________________
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^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2018-09-12 20:56 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-09-12 19:29 [PATCH 00/16] Add support for Raven2 Alex Deucher
[not found] ` <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2018-09-12 19:29 ` [PATCH 01/16] drm/amdgpu: move get_rev_id at first before load gpu_info firmware Alex Deucher
2018-09-12 19:29 ` [PATCH 02/16] drm/amdgpu: set external rev id for raven2 Alex Deucher
2018-09-12 19:29 ` [PATCH 03/16] drm/amdgpu: add raven2 to gpu_info firmware Alex Deucher
2018-09-12 19:29 ` [PATCH 04/16] drm/amdgpu: add raven2 vcn firmware support Alex Deucher
2018-09-12 19:29 ` [PATCH 05/16] drm/amdgpu: add psp support for raven2 Alex Deucher
2018-09-12 19:29 ` [PATCH 06/16] drm/amdgpu/sdma4: specify raven2 firmware Alex Deucher
2018-09-12 19:29 ` [PATCH 07/16] drm/amdgpu/sdma4: Add raven2 golden setting Alex Deucher
2018-09-12 19:29 ` [PATCH 08/16] drm/amdgpu/gfx9: add support for raven2 gfx firmware Alex Deucher
2018-09-12 19:29 ` [PATCH 09/16] drm/amdgpu/gfx9: add raven2 golden setting Alex Deucher
2018-09-12 19:29 ` [PATCH 10/16] drm/amdgpu: fix the VM fault while write at the top of the invisible vram Alex Deucher
2018-09-12 19:29 ` [PATCH 11/16] drm/amd/display: Add Raven2 definitions in dc Alex Deucher
[not found] ` <20180912192933.28712-12-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2018-09-12 20:10 ` Alex Deucher
[not found] ` <CADnq5_PsBONPZyirw5BVGNb=sf5_9njE6=jXBm0d7RjqC8=i+g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-09-12 20:43 ` Harry Wentland
[not found] ` <4a0826ff-d3a2-4f6f-2c74-d262e6ec70b3-5C7GfCeVMHo@public.gmane.org>
2018-09-12 20:56 ` Alex Deucher
2018-09-12 19:29 ` [PATCH 12/16] drm/amd/display: Add DC config flag for Raven2 (v2) Alex Deucher
2018-09-12 19:29 ` [PATCH 13/16] drm/amd/powerplay: update smu10_verify_smc_interface() to be raven2 compatible Alex Deucher
2018-09-12 19:29 ` [PATCH 14/16] drm/amd/powerplay: round up the Mhz convertion (v2) Alex Deucher
2018-09-12 19:29 ` [PATCH 15/16] drm/amd/powerplay: disable raven2 force dpm level support (v2) Alex Deucher
2018-09-12 19:29 ` [PATCH 16/16] drm/amdgpu: set CG flags for raven2 (v2) Alex Deucher
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